Transistor with asymmetrically arranged source / drain regions

Abstract

The present invention relates to a transistor with asymmetrically arranged source / drain regions, and discloses the structure of a field effect transistor and a method for forming the structure of a field effect transistor. A first and a second gate structure extend above a semiconductor body. The first gate structure includes a first sidewall and a second sidewall opposite to the first sidewall, and the second gate structure includes a sidewall adjacent to the first sidewall of the first gate structure. The first source / drain region includes a first epitaxial semiconductor layer located between the first sidewall of the first gate structure and the sidewall of the second gate structure. The second source / drain region includes a second epitaxial semiconductor layer arranged adjacent to the second sidewall of the first gate structure. The first sidewall of the first gate structure and the sidewall of the second gate structure are separated by a distance greater than the width of the first epitaxial semiconductor layer.

Description

Technical Field

[0001] The present invention relates to semiconductor device manufacturing and integrated circuits, and more particularly to a structure of a field effect transistor and a method for forming the structure of a field effect transistor. Background Art

[0002] A complementary metal oxide semiconductor (CMOS) process can be used to create a combination of p-type and n-type field effect transistors, which are used as devices to construct, for example, logic cells. A field effect transistor typically includes a source, a drain, a channel region between the source and the drain, and a gate electrode superimposed on the channel region. When a control voltage exceeding a characteristic threshold voltage is applied to the gate electrode, carrier flow occurs in the channel region between the source and the drain, thereby generating a device output current. A field effect transistor may include multiple gates superimposed on multiple channel regions.

[0003] The source and drain of a field effect transistor are formed simultaneously. One method is to implant ions containing p-type dopants or n-type dopants into a region of the semiconductor body to provide the source and drain. Another method is to epitaxially grow a section of semiconductor material from the semiconductor body to form the source and drain. The semiconductor material may be doped in situ with p-type dopants or n-type dopants during epitaxial growth.

[0004] A problem associated with wide gate spacing in multi-gate field effect transistors is underfilling of the semiconductor material epitaxially grown in the cavity to form the source and drain. This underfilling may degrade device performance, for example, by reducing radio frequency performance indicators such as power gain. This underfilling may also degrade other performance indicators. For example, it may reduce the drain current (Idsat) when the transistor is biased in the saturation region and may increase contact resistance.

[0005] There is a need for improved field effect transistor structures and methods of forming field effect transistor structures. Summary of the invention

[0006] In one embodiment of the present invention, a structure of a field effect transistor is provided. The structure includes first and second gate structures extending above a semiconductor body. The first gate structure includes a first sidewall and a second sidewall opposite to the first sidewall, and the second gate structure includes a sidewall disposed adjacent to the first sidewall of the first gate structure. A first source / drain region includes a first epitaxial semiconductor layer located between the first sidewall of the first gate structure and the sidewall of the second gate structure. A second source / drain region includes a second epitaxial semiconductor layer disposed adjacent to the second sidewall of the first gate structure. The first epitaxial semiconductor layer has a width, and the first sidewall of the first gate structure is separated from the sidewall of the second gate structure by a distance greater than the width of the first epitaxial semiconductor layer.

[0007] In one embodiment of the present invention, a method for forming a structure of a field effect transistor is provided. The method includes: forming a first gate structure extending above a semiconductor body, forming a second gate structure extending above the semiconductor body, forming a first epitaxial semiconductor layer of a first source / drain region on the semiconductor body, and forming a second epitaxial semiconductor layer of a second source / drain region on the semiconductor body. The first gate structure includes a first sidewall and a second sidewall opposite to the first sidewall, and the second gate structure includes a sidewall adjacent to the first sidewall of the first gate structure. The first source / drain region is located between the first sidewall of the first gate structure and the sidewall of the second gate structure, and the second source / drain region is disposed adjacent to the second sidewall of the first gate structure. The first epitaxial semiconductor layer has a width, and the first sidewall of the first gate structure is separated from the sidewall of the second gate structure by a distance greater than the width of the first epitaxial semiconductor layer. BRIEF DESCRIPTION OF THE DRAWINGS

[0008] The accompanying drawings, which are included in and constitute a part of this specification, illustrate various embodiments of the present invention and, together with the general description of the present invention made above and the detailed description of these embodiments made below, are used to explain these embodiments of the present invention. In the accompanying drawings, like reference numerals represent similar features in different views.

[0009] Figure 1-10 Cross-sectional views showing the structure of a FinFET at successive stages of a manufacturing process according to an embodiment of the present invention. DETAILED DESCRIPTION

[0010] Please refer to Figure 1According to an embodiment of the present invention, the structure 10 of the field effect transistor includes a fin 12 disposed above a substrate 14 and protruding upward from the substrate. The fin 12 and the substrate 14 may be composed of a single crystal semiconductor material, such as single crystal silicon. The fin 12 may be formed by patterning the substrate 14 using a photolithography and etching process, or by a self-aligned multi-patterning process. A shallow trench isolation (not shown) may surround the lower portion of the fin 12.

[0011] A material layer 16 such as polysilicon and a dielectric material layer 17 such as silicon dioxide are successively formed over the fin 12 and the shallow trench isolation. Layer 17 is disposed between layer 16 and the fin 12. Layer 16 may be deposited by chemical vapor deposition, and layer 17 may be formed by an oxidation process. A hard mask portion 18 is formed, which is disposed over the top surface 11 of the fin 12 and may extend through the shallow trench isolation. Hard mask portion 18 may be formed by patterning a dielectric material layer such as silicon nitride using a photolithography and etching process. Hard mask portion 18 may be a strip having a parallel arrangement and a given uniform spacing.

[0012] Please refer to Figure 2 , wherein similar reference numerals denote Figure 1 , and in the next manufacturing stage, one or more of the hard mask portions 18 are removed by a photolithography and etching process. In the representative embodiment, one of the hard mask portions 18 is removed from the top surface 11 of the fin 12. The photolithography process can form an etch mask 20 that masks the retained hard mask portions 18 and exposes the hard mask portions 18 to be removed by etching. The etch mask 20 may include a layer of photosensitive material, such as a photoresist, which is applied by a spin coating process, pre-baked, exposed to light projected through a photomask, post-exposure baked, and developed with a chemical developer. The etching process may be a reactive ion etching process that selectively removes the material of the hard mask portion 18 relative to the material of the layer 16. The term "selective" as used herein in reference to a material removal process (e.g., etching) means that the material removal rate (i.e., etching rate) of the target material is higher than the material removal rate (i.e., etching rate) of at least another material exposed to the material removal process. The etch mask 20 is stripped after patterning.

[0013] The removal of the hard mask portions 18 locally increases the pitch of the hard mask portions 18 in the region 60. The initial pitch is maintained in the adjacent region 62. In particular, the pitch is locally doubled by the removal of the hard mask portions 18. In an alternative embodiment, a plurality of adjacent hard mask portions 18 may be removed in the region 60 to additionally increase the local pitch. For example, a pair of adjacent hard mask portions 18 may be removed to locally triple the pitch of the hard mask portions 18 in the region 60.

[0014] Please refer to Figure 3, wherein similar reference numerals denote Figure 2 and, in a next manufacturing stage, patterning layers 16, 17 to define gate structures 22, 23, 24, which extend laterally along corresponding longitudinal axes above fin 12 and through the fin and the trench isolation. Each gate structure 22, 23, 24 is arranged perpendicular to fin 12, overlaps and covers fin 12. Each gate structure 22, 23, 24 has a sidewall 25 and a sidewall 27 opposite to sidewall 25. Layer 16 can be patterned by an etching process, such as a reactive ion etching process, which is selective to the material of fin 12 and relies on hard mask portion 18 as an etching mask. Each gate structure 22, 23, 24 may include a dummy gate composed of the material of layer 16 and a dielectric layer composed of the material of layer 17 in the form of a layer stack. The hard mask portion 18 is provided in the form of a gate cap above the gate structures 22, 23, 24.

[0015] The gate structures 22, 23, 24 (which are dummy gate elements) adopt the pattern of the hard mask portion 18, including the plurality of pitches. As a result, the sidewall 25 of the gate structure 22 is spaced apart from the sidewall 25 of the gate structure 23 by a pitch s1, and the sidewall 25 of the gate structure 23 is spaced apart from the sidewall 25 of the gate structure 24 by a pitch s2 that is greater than the pitch s1. In one embodiment, the pitch s2 may be equal to or substantially equal to twice the pitch s1. In such an embodiment, the gate structures 22, 23 may have a 1CPP (contacted (poly) pitch) gate pitch, and the gate structures 23, 24 may have a 2CPP gate pitch. In other embodiments, the pitch s2 may be equal to or substantially equal to an integer multiple of the pitch s1, depending on the number of hard mask portions 18 removed from the region 60. In an embodiment where the integer is three (3) and the gate structure 24 is removed, the gate structure 23 and a gate structure (not shown) adjacent to the removed gate structure 24 may have a 3CPP gate pitch.

[0016] Please refer to Figure 4 , wherein similar reference numerals denote Figure 3 In the next manufacturing stage, a conformal layer 26 composed of, for example, a low-k dielectric material is deposited as a liner over the gate structures 22, 23, 24 and the fins 12 by, for example, atomic layer deposition. The conformal layer 26 may have a uniform thickness that is independent of or substantially independent of position.

[0017] A layer 28 composed of, for example, silicon dioxide is deposited over the conformal layer 26 on the gate structures 22, 23, 24 and the fins 12. The layer 28 may be sandwiched in the space between the gate structures 22 and 23 so that the space is completely filled. The layer 28 is not sandwiched in the space between the gate structures 23 and 24 so that the space is only partially filled. In particular, the layer 28 reduces the width of the space between the gate structures 23, 24 and effectively defines the trench 30. The opposing sidewalls of the trench 30 may be disposed equidistantly or substantially equidistantly from the gate structures 23 and 24.

[0018] Please refer to Figure 5 , wherein similar reference numerals denote Figure 4 1 and 12. In the next manufacturing stage, trench 30 is extended by an anisotropic etching process, such as reactive ion etching, so that it passes through layer 28 to conformal layer 26. Spacers 32 are effectively formed from layer 28 in the space between trench 30 and gate structure 23 and in the space between trench 30 and gate structure 24. Two spacers 32 are arranged in a lateral direction between gate structure 23 and gate structure 24. Trench 30 extends through the etching process in a direction perpendicular to conformal layer 26 on top surface 11 of fin 12.

[0019] Next, the conformal layer 26 is etched using an anisotropic etching process such as reactive ion etching by using the spacer 32 as an etching mask to define an opening 35 in the conformal layer 26, thereby exposing an area located on the top surface 11 of the fin 12. The etched conformal layer 26 defines L-shaped spacers 33, 34. The spacer 33 includes a portion 70 located on the gate structure 23 and a portion 72 extending from the portion 70 on the gate structure 23 to the opening 35 in a lateral direction. The spacer 34 includes a portion 74 located on the gate structure 24 and a portion 76 extending from the portion 74 on the gate structure 24 to the opening 35 in a lateral direction. The portions 72, 76 are located on the top surface 11 of the fin 12, and the opening 35 is laterally located between the portion 72 of the spacer 33 and the portion 76 of the spacer 34. The portion 72 of the spacer 33 is adjacent to and continues the portion 70 of the spacer 33, and the portion 76 of the spacer 34 is adjacent to and continues the portion 74 of the spacer 34.

[0020] Please refer to Figure 6 , wherein similar reference numerals denote Figure 5, and in the next manufacturing stage, a cavity 36 is formed in a portion of the fin 12 laterally located between the gate structure 23 and the gate structure 24 by an etching process such as an anisotropic etching process (e.g., reactive ion etching). The cavity 36 is formed at the location of the opening 35 between the portion 72 of the spacer 33 and the portion 76 of the spacer 34 ( Figure 5 ), and the spacer 32 again acts as an etching mask. The opposite sidewalls of the cavity 36 may be disposed equidistant from the gate structure 23 and the gate structure 24 (ie, symmetrically located between the gate structure 23 and the gate structure 24).

[0021] Please refer to Figure 7 , wherein similar reference numerals denote Figure 6 1 and 12. In the next manufacturing stage, the layer 28 and the spacer 32 are removed by an etching process, which may be a wet chemical etching process, which selectively removes silicon dioxide relative to the material of the conformal layer 26 and the hard mask portion 18. A blocking mask 37 is formed, which covers the portion of the fin 12 located between the gate structure 23 and the gate structure 24. The blocking mask 37 may be a spin-on hard mask composed of an organic material patterned by a photolithography and etching process. The portion of the conformal layer 26 located between the gate structure 22 and the gate structure 23 is exposed through the patterned blocking mask 37.

[0022] Please refer to Figure 8 , wherein similar reference numerals denote Figure 7 , and in the next manufacturing stage, an anisotropic etching process such as reactive ion etching is used to etch the conformal layer 26, thereby forming a spacer 38 in the space between the gate structure 22 and the gate structure 23. A portion of the fin 12 is laterally exposed between the spacers 38. A cavity 40 is formed in the exposed portion of the fin 12 laterally located between the gate structure 22 and the gate structure 23 by an etching process such as an anisotropic etching process (e.g., reactive ion etching). The blocking mask 37 acts as an etching mask to protect the spacers 33, 34 and the fin 12 located between the gate structures 23, 24 during the etching process to form the cavity 40. After the cavity 40 is formed, the blocking mask 37 can be stripped by, for example, an ashing process. In one embodiment, the cavity 40 can have the same size (dimensions) as the cavity 36.

[0023] Please refer to Fig. 9 , wherein similar reference numerals denote Figure 8, and in the next manufacturing stage, a semiconductor material layer 42 is grown from the surface of the fin 12 surrounding the cavity 36 by an epitaxial growth process, and a semiconductor material layer 44 is grown from the surface of the fin 12 surrounding the cavity 40 by an epitaxial growth process. Layers 42 and 44 can be formed simultaneously by the same epitaxial growth process. Layer 42 can extend laterally outward from the space between the gate structures 22 and 23 and have a small faceted shape, and layer 44 can also extend laterally outward from the space between the gate structures 23 and 24 and have a small faceted shape.

[0024] The epitaxial growth process to form layers 42, 44 may be selective in that the semiconductor material is not grown from dielectric surfaces such as hard mask portion 18, spacers 33, 34, and spacers 38. Layers 42, 44 may be doped in situ during epitaxial growth with a concentration of dopant. In one embodiment, layers 42, 44 may be doped in situ during epitaxial growth with a p-type dopant (e.g., boron) that provides p-type conductivity. In an alternative embodiment, layers 42, 44 may be doped in situ during epitaxial growth with an n-type dopant (e.g., phosphorus and / or arsenic) that provides n-type conductivity. Layers 42, 44 may have a composition including germanium and silicon, and in one embodiment, layers 42, 44 may be composed of silicon-germanium. In one embodiment, layers 42, 44 may be composed of silicon-germanium and may include p-type dopant. In one embodiment, layers 42, 44 may be composed of silicon. In one embodiment, layers 42, 44 may be composed of silicon and may include n-type dopant.

[0025] Layer 44 is constrained by spacers 33, 34 located at the entrance of cavity 36 during epitaxial growth. Due to the constraint provided by spacers 33, 34, layer 44 grows only from the portion of fin 12 exposed by opening 35 between portion 72 of spacer 33 and portion 76 of spacer 34. Portion 72 of spacer 33 and portion 76 of spacer 34 effectively reduce the portion of fin 12 that allows epitaxial growth of layer 44. Layer 42 has a width w1, and layer 44 has a width w2. In one embodiment, the width w2 of layer 42 may be equal to the width w1 of layer 44. Due to the presence of portion 72 of spacer 33 and portion 76 of spacer 34 in region 60 having a larger gate pitch than region 62, the width of layer 44 is reduced. Cavity 36 and layer 44 are laterally spaced from gate structure 23 by a distance d1, and cavity 36 and layer 44 are laterally spaced from gate structure 24 by a distance d2. Distances d1 and d2 may be equal.

[0026] Please refer to Fig.10 , wherein similar reference numerals denote Fig. 9, and at the next manufacturing stage, a replacement gate process is performed to replace the gate structures 22, 23, 24 with gate structures 46, 48, 50 and complete the structure 10 of the field effect transistor. The gate structures 46, 48, 50 may include a layer 64 composed of one or more metal gate materials, such as work function metals, and a layer 66 composed of a dielectric material, such as a high-k dielectric material such as hafnium oxide. Each gate structure 46, 48, 50 has opposing side surfaces or sidewalls 47, 49. A gate cap layer 58 composed of, for example, silicon nitride may be disposed over each gate structure 46, 48, 50.

[0027] As a result of the replacement gate process, gate structures 46, 48, 50 adopt the pattern of gate structures 22, 23, 24, including the plurality of pitches. As a result, sidewalls 47 of gate structure 46 are spaced apart from sidewalls 47 of gate structure 48 by a pitch s3, and sidewalls 47 of gate structure 48 are spaced apart from sidewalls 47 of gate structure 50 by a pitch s4 that is greater than pitch s3. In one embodiment, pitch s4 may be equal to or substantially equal to twice the pitch s3. In this embodiment, gate structures 46, 48 may have a 1CPP (contact (poly) pitch) gate pitch, and gate structures 48, 50 may have a 2CPP gate pitch. In other embodiments, pitch s4 may be equal to or substantially equal to an integer multiple of pitch s3, depending on the number of adjacent hard mask portions 18 previously removed. In an embodiment where the integer is three (3), gate structure 50 is not present, and gate structure 48 and a gate structure (not shown) adjacent to gate structure 48 may have a 3CPP gate pitch.

[0028] The sidewall 49 of the gate structure 48 is separated from the sidewall 47 of the gate structure 50 by a distance d3. The distance d3 is greater than the width w2 of the layer 44. The portion 72 of the spacer 33 and the portion 76 of the spacer 34 facilitate the width difference by constraining the epitaxial growth of the layer 44. The portion 70 of the spacer 33 is disposed on the sidewall 49 of the gate structure 48, and the portion 74 of the spacer 34 is disposed on the sidewall 47 of the gate structure 50. The portion 72 of the spacer 33 is disposed between the layer 44 and the sidewall 49 of the gate structure 48. The portion 76 of the spacer 34 is disposed between the layer 44 and the sidewall 47 of the gate structure 50.

[0029] The structure 10 includes a buried source / drain region 52 provided by layer 42 and a buried source / drain region 54 provided by layer 44. The term "source / drain region" as used herein refers to a doped region of a semiconductor material that can act as a source or drain of a field effect transistor. The source / drain region 52 is laterally located between the gate structure 46 and the gate structure 48, and the source / drain region 54 is laterally located between the gate structure 48 and the gate structure 50. The fin 12 provides a semiconductor body for forming the source / drain regions 52, 54, and the source / drain regions have an asymmetric arrangement relative to the gate structure 48. The channel region 56 is provided in the fin 12 laterally located between the source / drain region 52 and the source / drain region 54 and vertically located below the overlying gate structure 48. Portions of the interlayer dielectric layer 68 may be located in the space between the gate structures 46, 48, 50 above the source / drain regions 52, 54.

[0030] In one embodiment, source / drain region 52 may provide a source in structure 10 of the field effect transistor, and source / drain region 54 may provide a drain in structure 10 of the field effect transistor. In an alternative embodiment, source / drain region 52 may provide a drain in structure 10 of the field effect transistor, and source / drain region 54 may provide a source in structure 10 of the field effect transistor. Source / drain regions 52, 54 are doped to have a conductivity type of the same polarity (i.e., the same conductivity type). Layer 44 located on the drain side of the field effect transistor and layer 42 located on the source side of the field effect transistor provide the same epitaxial semiconductor geometry.

[0031] Then, an intermediate process and a back-end process are performed, including forming contacts, vias, and interconnection structure lines coupled to the field effect transistor.

[0032] Since the spacers 33, 34 compensate for the larger gate pitch on the drain side compared to the source side, the field effect transistor having the source / drain region 52 providing the source and the source / drain region 54 providing the drain can show an improvement in filling of the epitaxial semiconductor material. Compared with a conventional field effect transistor having a gate structure with a 1CPP gate pitch on the source side and on the drain side, the larger gate pitch on the drain side can improve the radio frequency performance (e.g., in terms of power gain, cutoff frequency (f T ), and the maximum oscillation frequency (f Max ) Improvements in aspects of the present invention. The structure 10 may include additional gate structures having different gate pitches, and the buried source / drain regions 52, 54 may be repeated for pairs of gate structures to form a multi-gate field effect transistor for a radio frequency integrated circuit.

[0033] The above method is used for the manufacture of integrated circuit chips. The manufacturer can distribute the resulting integrated circuit chips in raw wafer form (e.g., as a single wafer with multiple unpackaged chips), as a bare chip, or in a packaged form. In the latter case, the chip is provided in a single-chip package (e.g., a plastic carrier with pins attached to a motherboard or other higher-level carrier) or in a multi-chip package (e.g., a ceramic carrier with single-sided or double-sided interconnects or embedded interconnects). In any case, the chip can be integrated with other chips, discrete circuit elements and / or other signal processing devices as part of an intermediate product or a final product.

[0034] Terms such as "vertical", "horizontal", etc. are cited herein as examples to establish a reference frame and are not limiting. The term "horizontal" as used herein is defined as a plane parallel to the conventional plane of the semiconductor substrate, regardless of its actual three-dimensional spatial orientation. The terms "vertical" and "orthogonal" refer to directions perpendicular to the horizontal plane as just defined. The term "lateral" refers to a direction within the horizontal plane.

[0035] Terms modified by approximate language such as "about," "approximately," and "substantially" cited herein are not limited to the exact value specified. The approximate language may correspond to the precision of the instrument used to measure the value, and may represent + / -10% of the value unless otherwise dependent on the precision of the instrument.

[0036] A feature that is "connected" or "coupled" to another feature may be directly connected or coupled to the other feature, or one or more intermediate features may be present. A feature may be "directly connected" or "directly coupled" to another feature if there are no intermediate features. A feature may be "not directly connected" or "not directly coupled" to another feature if there are at least one intermediate feature. A feature that is "on" or "in contact with" another feature may be directly on or in direct contact with the other feature, or one or more intermediate features may be present. A feature may be directly "on" or "in direct contact with" another feature if there are no intermediate features. A feature may not be "directly" "on" or "not directly in contact with" another feature if there are at least one intermediate feature.

[0037] The description of various embodiments of the present invention is for illustrative purposes and is not intended to be exhaustive or limited to the disclosed embodiments. Many modifications and variations will be apparent to those of ordinary skill in the art without departing from the scope and spirit of the described embodiments. The terms used herein are selected to best explain the principles of the embodiments, practical applications, or technical improvements over commercially known technologies, or to enable those of ordinary skill in the art to understand the embodiments disclosed herein.

Claims

1. A structure of a field effect transistor, comprising: Semiconductor fins; A first gate structure extending above the semiconductor fin, the first gate structure comprising a first sidewall and a second sidewall opposite to the first sidewall; A second gate structure extending above the semiconductor fin, the second gate structure comprising a first sidewall and a second sidewall opposite to the first sidewall, the second sidewall of the second gate structure being adjacent to the first sidewall of the first gate structure; A third gate structure extending above the semiconductor fin, the third gate structure comprising a first sidewall and a second sidewall opposite to the first sidewall, the first sidewall of the third gate structure being adjacent to the second sidewall of the first gate structure; A first source / drain region includes a first epitaxial semiconductor layer located between the first sidewall of the first gate structure and the second sidewall of the second gate structure; A second source / drain region includes a second epitaxial semiconductor layer, wherein the second epitaxial semiconductor layer is located between the second sidewall of the first gate structure and the first sidewall of the third gate structure; as well as an interlayer dielectric layer, located on the top surface of the first source / drain region and the top surface of the second source / drain region, The first epitaxial semiconductor layer has a first width, and the first sidewall of the first gate structure is separated from the second sidewall of the second gate structure by a distance greater than the first width of the first epitaxial semiconductor layer. The second side wall of the first gate structure is separated from the second side wall of the second gate structure by a first spacing, the second side wall of the third gate structure is separated from the second side wall of the first gate structure by a second spacing, the first spacing is equal to an integer multiple of the second spacing, and the first spacing and the second spacing are gate spacings.

2. The structure of claim 1, further comprising: A first spacer wall including a first portion extending laterally above the fin; as well as A second spacer includes a first portion extending laterally above the fin toward the first portion of the first spacer, The first epitaxial semiconductor layer is located between the first portion of the first spacer and the first portion of the second spacer.

3. The structure of claim 2, wherein: The first spacer includes a second portion located on the first sidewall of the first gate structure, the first portion of the first spacer is adjacent to the second portion of the first spacer, the second spacer includes a second portion located on the second sidewall of the second gate structure, and the first portion of the second spacer is adjacent to the second portion of the second spacer.

4. The structure of claim 2, wherein: The first epitaxial semiconductor layer is formed in a first cavity in the fin, and the first cavity and the first epitaxial semiconductor layer are located between the first portion of the first spacer and the first portion of the second spacer.

5. The structure of claim 4, wherein: The second epitaxial semiconductor layer of the second source / drain region is formed in a second cavity in the fin, the second epitaxial semiconductor layer has a second width, and the first width of the first epitaxial semiconductor layer is substantially equal to the second width of the second epitaxial semiconductor layer.

6. The structure of claim 1, wherein: The third gate structure is disposed adjacent to the second sidewall of the first gate structure, The second source / drain region is laterally located between the second sidewall of the first gate structure and the first sidewall of the third gate structure.

7. The structure of claim 6, wherein: The first interval is greater than the second interval.

8. The structure of claim 7, wherein: The first spacing is equal to an integer multiple of the second spacing.

9. The structure of claim 7, wherein: The first spacing is equal to twice the second spacing.

10. The structure of claim 1, wherein: The second epitaxial semiconductor layer has a second width, and the first width of the first epitaxial semiconductor layer is substantially equal to the second width of the second epitaxial semiconductor layer.

11. The structure of claim 1, wherein: The first source / drain region is the drain of the field effect transistor, and the second source / drain region is the source of the field effect transistor.

12. A method for forming a structure of a field effect transistor, the method comprising: forming a first gate structure extending above the semiconductor fin; forming a second gate structure extending above the semiconductor fin; forming a third gate structure extending above the semiconductor fin; forming a first epitaxial semiconductor layer of a first source / drain region on the semiconductor fin; forming a second epitaxial semiconductor layer of a second source / drain region on the semiconductor fin; as well as forming an interlayer dielectric layer on the top surface of the first source / drain region and the top surface of the second source / drain region, wherein the first gate structure includes a first sidewall and a second sidewall opposite to the first sidewall, the second gate structure includes a first sidewall and a second sidewall opposite to the first sidewall, the second sidewall of the second gate structure is adjacent to the first sidewall of the first gate structure, the third gate structure includes a first sidewall and a second sidewall opposite to the first sidewall, the first sidewall of the third gate structure is adjacent to the second sidewall of the first gate structure, the first source / drain region is located between the first sidewall of the first gate structure and the second sidewall of the second gate structure, the second source / drain region is located between the second sidewall of the first gate structure and the first sidewall of the third gate structure, the first epitaxial semiconductor layer has a first width, and the first sidewall of the first gate structure is separated from the sidewall of the second gate structure by a distance greater than the first width of the first epitaxial semiconductor layer, The second side wall of the first gate structure is separated from the second side wall of the second gate structure by a first spacing, the second side wall of the third gate structure is separated from the second side wall of the first gate structure by a second spacing, the first spacing is equal to an integer multiple of the second spacing, and the first spacing and the second spacing are gate spacings.

13. The method of claim 12, further comprising: forming a first spacer including a first portion extending laterally above the fin; as well as forming a second spacer including a first portion extending laterally above the fin toward the first portion of the first spacer, The first epitaxial semiconductor layer is located between the first portion of the first spacer and the first portion of the second spacer.

14. The method of claim 13, wherein: The first spacer includes a second portion located on the first sidewall of the first gate structure, the first portion of the first spacer is adjacent to the second portion of the first spacer, the second spacer includes a second portion located on the second sidewall of the second gate structure, and the first portion of the second spacer is adjacent to the second portion of the second spacer.

15. The method of claim 13, wherein: The first epitaxial semiconductor layer is formed in a first cavity in the fin, and the first cavity and the first epitaxial semiconductor layer are located between the first portion of the first spacer and the first portion of the second spacer.

16. The method of claim 12, in, The third gate structure is disposed adjacent to the second sidewall of the first gate structure, and the second source / drain region is laterally located between the second sidewall of the first gate structure and the first sidewall of the third gate structure.

17. The method of claim 16, wherein: The first interval is greater than the second interval.

18. The method of claim 17, wherein: The first spacing is equal to an integer multiple of the second spacing.

19. The method of claim 12, wherein: The second epitaxial semiconductor layer has a second width, and the first width of the first epitaxial semiconductor layer is substantially equal to the second width of the second epitaxial semiconductor layer.

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