Pulse Width Modulation Circuit with Constant Power Output and Pulse Width Modulation Method

Abstract

The present invention discloses a pulse width modulation circuit with constant power output and a pulse width modulation method. A power switch and a sampling circuit generate a feedback voltage according to the output power and output the feedback voltage to a comparator. The comparator generates a comparison result based on the feedback voltage and one output signal of a triangular wave generator, and sends the comparison result to a logic control circuit. The logic control circuit generates a pulse width modulation signal according to the comparison signal and another output signal of the triangular wave generator, and sends the pulse width modulation signal to the power switch and the sampling circuit through a buffer. The pulse width modulation signal is used to control the output power and output duty cycle of the power switch and the sampling circuit. Among them, the pulse width modulation circuit with constant power output controls the output duty cycle to make the output power constant. This circuit has the advantages of stable output power, high detection accuracy, and low power consumption, etc.

Description

Technical Field

[0001] The present invention relates to power driving technology, and particularly to a pulse width modulation circuit with constant power output and a pulse width modulation method, belonging to the field of integrated circuit technology. Background Art

[0002] Power driving technology can be applied to heating devices. The load in heating devices is generally a resistive load. In this way, the output power can be controlled by controlling the output current and output voltage of the load, so as to generate different heating effects through different output powers. The output power of traditional driving circuits changes with the change of output voltage. In a resistive load driving circuit, generally, the output power has a square-law relationship with the output voltage, and the output voltage is generally positively correlated with the power supply voltage. Therefore, when the power supply voltage decreases, the output power will also decrease rapidly, which will lead to very unsatisfactory experiences and effects in practical applications. For example, the temperature of the heating device rises too fast, and the temperature rise time is different under different power supply voltages, resulting in a poor user experience of the product.

[0003] To solve the above problems, two constant-power pulse width modulation circuits are provided in the prior art, as Figure 1 shown. One pulse width modulation circuit includes a detection circuit, an analog-to-digital conversion circuit, and other digital logic operation circuits, and drives a power switch device through the generated pulse width modulation signal (Pulse Width Modulation, PWM), and the duty cycle of the pulse width modulation signal changes dynamically with the output voltage to achieve approximate constancy of the output power within a certain voltage range. As Figure 2 shown, another pulse width modulation circuit includes an analog circuit and several logic control circuits, which generate pulse width modulation signals (PWM) with different duty cycles under different power supply voltages to control the switch device to obtain a stable average output voltage.

[0004] Both of the above two pulse width modulation circuits have their own disadvantages. In the first pulse width modulation circuit, the structure of the analog-to-digital conversion circuit is complex, the power consumption is high, and the layout area is larger with higher precision. In the second pulse width modulation circuit, the detection circuit detects the power supply voltage instead of the output voltage, and the existence of the voltage drop when the power switch device is turned on will reduce the detection accuracy, thereby reducing the accuracy of PWM modulation. Summary of the Invention

[0005] The present invention provides a pulse width modulation circuit with constant power output and a pulse width modulation method, which have the advantages of stable output power, high detection accuracy, and low power consumption, thereby solving the technical problems of unstable output power, low detection accuracy, and high power consumption of the pulse width modulation circuit in the related art.

[0006] The present invention specifically adopts the following technical solutions to solve the above technical problems:

[0007] A pulse width modulation circuit with constant power output, wherein the pulse width modulation circuit with constant power output includes a triangular wave generator, a comparator, a logic control circuit, a buffer, a power switch and a sampling circuit;

[0008] The first output end of the triangular wave generator is connected to the first input end of the logic control circuit, and the second output end of the triangular wave generator is connected to the first input end of the comparator;

[0009] The second input end of the comparator is connected to the second output end of the power switch and the sampling circuit, and the output end of the comparator is connected to the second input end of the logic control circuit;

[0010] The output end of the logic control circuit is connected to the input end of the buffer, the output end of the buffer is connected to the input end of the power switch and the sampling circuit, and the first output end of the power switch and the sampling circuit is used as the output end of the pulse width modulation circuit with constant power output and is connected to the load;

[0011] Wherein, the pulse width modulation signal of the pulse width modulation circuit with constant power output is used to control the output duty cycle, and the output duty cycle is used to adjust the output power of the pulse width modulation circuit with constant power output so that the output power is constant.

[0012] In a possible implementation manner, the power switch and the sampling circuit include a power switch device, a current sampling circuit, a voltage sampling circuit and an arithmetic circuit; the input end of the power switch device is respectively connected to the output end of the buffer and the input end of the current sampling circuit, and the output end of the power switch device is respectively connected to the input end of the voltage sampling circuit and the load; the output end of the current sampling circuit is connected to the first input end of the arithmetic circuit; the output end of the voltage sampling circuit is connected to the second input end of the arithmetic circuit; the output end of the arithmetic circuit is connected to the second input end of the comparator;

[0013] The current sampling circuit is used to sample the output current of the power switch device and output a first output voltage generated according to the output current to the arithmetic circuit, and the first output voltage has a linear relationship or a piecewise linear relationship with the output current;

[0014] The voltage sampling circuit is used to sample the second output voltage of the power switch device and output a third output voltage generated according to the second output voltage to the arithmetic circuit, and the third output voltage has a linear relationship or a piecewise linear relationship with the second output voltage;

[0015] The arithmetic circuit is used to perform arithmetic operations on the first output voltage and the third output voltage, and determine the obtained fourth output voltage as the feedback voltage output to the comparator. The feedback voltage is in a proportional relationship with the arithmetic product or arithmetic sum of the first output voltage and the third output voltage.

[0016] In a possible implementation, the second output voltage of the triangular wave generator is a triangular wave or a sawtooth wave.

[0017] In a possible implementation, the power switch and the sampling circuit include a power switch device and a current sampling circuit; the input end of the power switch device is respectively connected to the output end of the buffer and the input end of the current sampling circuit, and the output end of the power switch device is connected to the load; the output end of the current sampling circuit is connected to the second input end of the comparator;

[0018] The current sampling circuit is used to sample the output current of the power switch device, and determine the first output voltage generated according to the output current as the feedback voltage output to the comparator. The feedback voltage is in a linear relationship or a piecewise linear relationship with the output current.

[0019] In a possible implementation, the power switch and the sampling circuit include a power switch device and a voltage sampling circuit; the input end of the power switch device is connected to the output end of the buffer, and the output end of the power switch device is respectively connected to the input end of the voltage sampling circuit and the load; the output end of the voltage sampling circuit is connected to the second input end of the comparator;

[0020] The voltage sampling circuit is used to sample the second output voltage of the power switch device, and determine the third output voltage generated according to the second output voltage as the feedback voltage output to the comparator. The feedback voltage is in a linear relationship or a piecewise linear relationship with the second output voltage.

[0021] In a possible implementation, the pulse width modulation circuit for constant power output further includes a segmentation controller;

[0022] The segmentation controller is used to compare the output current with a reference current, and adjust the proportional relationship between the feedback voltage and different output currents according to the comparison result; and / or;

[0023] The segmentation controller is used to compare the second output voltage with a reference voltage, and adjust the proportional relationship between the feedback voltage and different second output voltages according to the comparison result.

[0024] In a possible implementation, the power switch device is an N-channel metal oxide semiconductor field effect transistor or a P-channel metal oxide semiconductor field effect transistor.

[0025] In a possible implementation, when the output of the buffer changes from high level to low level, the logic control circuit is used to control the power switch device to turn on; when the output of the buffer changes from low level to high level, the logic control circuit is used to control the power switch device to turn off.

[0026] In a possible implementation, the output signal of the first output terminal in the triangular wave generator is a square wave signal; the output signal of the second output terminal is a triangular wave signal, and the output frequencies of the second output terminal and the first output terminal are the same.

[0027] A pulse width modulation method is used in the pulse width modulation circuit for constant power output as described above. The method includes:

[0028] The power switch and the sampling circuit generate a feedback voltage according to the output power and output the feedback voltage to the comparator;

[0029] The comparator generates a comparison result according to the feedback voltage and an output signal of one path of the triangular wave generator, and sends the comparison result to the logic control circuit;

[0030] The logic control circuit generates a pulse width modulation signal according to the comparison signal and an output signal of the other path of the triangular wave generator, and sends the pulse width modulation signal to the power switch and the sampling circuit through the buffer. The pulse width modulation signal is used to control the output duty cycle of the power switch and the sampling circuit, and the output duty cycle is used to adjust the output power of the pulse width modulation circuit for constant power output so that the output power is constant.

[0031] Compared with the prior art, the technical solution adopted by the present invention has the following advantages and remarkable effects:

[0032] (1) High detection accuracy of output voltage or current;

[0033] (2) Have a more stable output power;

[0034] (3) Low power consumption. Description of the Drawings

[0035] Figure 1 is a pulse width modulation circuit for constant power output implemented by a digital method in the prior art;

[0036] Figure 2 is a pulse width modulation circuit for constant voltage output in the prior art;

[0037] Figure 3 is a pulse width modulation circuit for constant power output proposed by the present invention;

[0038] Figure 4 is the first structure of the power switch and the sampling circuit;

[0039] Figure 5 is the second structure of the power switch and the sampling circuit;

[0040] Figure 6 is the third structure of the power switch and the sampling circuit;

[0041] Figure 7 is the first structure of the voltage sampling circuit;

[0042] Figure 8 is the relationship between the output duty cycle and the output power and the second output voltage VO (or the output current IO);

[0043] Figure 9 is the second structure of the voltage sampling circuit;

[0044] Figure 10 is the relationship between the output duty cycle and the output power and the second output voltage VO (or the output current IO);

[0045] Figure 11 is the first structure of the current sampling circuit;

[0046] Figure 12 is the second structure of the current sampling circuit;

[0047] Figure 13 is a structure of the logic control circuit;

[0048] Figure 14 is the working waveform of the pulse width modulation circuit for constant power output;

[0049] Figure 15 is the flow schematic diagram of the pulse width modulation method. Specific embodiments

[0050] Such as Figure 3As shown in the figure, the present invention discloses a pulse width modulation circuit with constant power output. The pulse width modulation circuit with constant power output includes a triangular wave generator 310, a comparator 320, a logic control circuit 330, a buffer 340, and a power switch and sampling circuit 350. Among them, the first output terminal of the triangular wave generator 310 is connected to the first input terminal of the logic control circuit 330, the second output terminal of the triangular wave generator 310 is connected to the first input terminal of the comparator 320, the second input terminal of the comparator 320 is connected to the second output terminal of the power switch and sampling circuit 350 (i.e., the feedback voltage VF), the output terminal of the comparator 320 is connected to the second input terminal of the logic control circuit 330, the output terminal of the logic control circuit 330 is connected to the input terminal of the buffer 340, the output terminal of the buffer 340 is connected to the input terminal of the power switch and sampling circuit 350, and the first output terminal of the power switch and sampling circuit 350 is connected to the load 360 as the output terminal of the pulse width modulation circuit with constant power output. Among them, the pulse width modulation signal of the pulse width modulation circuit with constant power output is used to control the output duty cycle, and the output duty cycle is used to adjust the output power of the pulse width modulation circuit with constant power output to make the output power constant.

[0051] Among them, the output signal of the first output terminal in the triangular wave generator 310 is a square wave signal; the output signal of the second output terminal is a triangular wave signal, and the output frequencies of the second output terminal and the first output terminal are the same.

[0052] In this embodiment, there are three implementation manners for the power switch and sampling circuit 350, and the following will introduce these three implementation manners respectively.

[0053] Figure 4The first implementation of the power switch and the sampling circuit 350 is shown. In this implementation, the output current and the output voltage are sampled simultaneously, and the output current and the output voltage are operated on to obtain the feedback voltage (VF) output to the comparator 320. Specifically, the power switch and the sampling circuit 350 include a power switch device 351, a current sampling circuit 352, a voltage sampling circuit 353, and an operation circuit 354. The input end of the power switch device 351 is respectively connected to the output end of the buffer 340 and the input end of the current sampling circuit 352; the output end of the power switch device 351 is respectively connected to the input end of the voltage sampling circuit 353 and the load 360; the output end of the current sampling circuit 352 is connected to the first input end of the operation circuit 354; the output end of the voltage sampling circuit 353 is connected to the second input end of the operation circuit 354; the output end of the operation circuit 354 is connected to the second input end of the comparator 320. Among them, the current sampling circuit 352 is used to sample the output current (IO) of the power switch device 351, and generate a first output voltage (V1) according to the output current (IO), and output the first output voltage (V1) to the operation circuit 354. The first output voltage (V1) has a linear relationship or a piecewise linear relationship with the output current. The voltage sampling circuit 353 is used to sample the second output voltage (VO) of the power device 351, and generate a third output voltage (V2) according to the second output voltage (VO), and output the third output voltage (V2) to the operation circuit 354. The third output voltage V2 has a linear relationship or a piecewise linear relationship with the second output voltage (VO). The operation circuit 354 is used to perform a multiplication operation or an addition operation on the first output voltage (V1) and the third output voltage (V2), and determine the obtained fourth output voltage as the feedback voltage (VF) output to the comparator 320. The feedback voltage (VF) is in direct proportion to the operation product or the operation sum of the first output voltage (V1) and the third output voltage (V2).

[0054] Figure 5Shows a second implementation of the power switch and the sampling circuit 350. This implementation samples the output current and calculates the output current to obtain the feedback voltage (VF) output to the comparator 320. Specifically, the power switch and the sampling circuit 350 include a power switch device 351 and a current sampling circuit 352. The input end of the power switch device 351 is respectively connected to the output end of the buffer 340 and the input end of the current sampling circuit 352. The output end of the power switch device 351 is connected to the load 360. The output end of the current sampling circuit 352 is connected to the second input end of the comparator 320. The current sampling circuit 352 is used to sample the output current (IO) of the power switch device 351 and generate a first output voltage (V1) according to the output current (IO), and determine the first output voltage (V1) as the feedback voltage (VF) output to the comparator 320. The feedback voltage (VF) has a linear relationship or a piecewise linear relationship with the output current (IO), where the piecewise linear relationship means that in different output current ranges, the feedback voltage (VF) and the output current (IO) have different proportionality coefficients.

[0055] Figure 6 Shows a third implementation of the power switch and the sampling circuit 350. This implementation samples the output voltage and calculates the output voltage to obtain the feedback voltage (VF) output to the comparator 320. Specifically, the power switch and the sampling circuit 350 include a power switch device 351 and a voltage sampling circuit 353. The input end of the power switch device 351 is connected to the output end of the buffer 340. The output end of the power switch device 351 is respectively connected to the input end of the voltage sampling circuit 353 and the load 360. The output end of the voltage sampling circuit 353 is connected to the second input end of the comparator 320. The voltage sampling circuit 353 is used to sample the second output voltage (VO) of the power switch device 351 and determine the third output voltage generated according to the second output voltage (VO) as the feedback voltage (VF) output to the comparator 320. The feedback voltage (VF) has a linear relationship or a piecewise linear relationship with the second output voltage (VO), where the piecewise linear relationship means that in different output voltage ranges, the feedback voltage (VF) and the second output voltage (VO) have different proportionality coefficients.

[0056] The first point to note is that the input and output of the buffer 340 are in a common-phase relationship, and the buffer 340 is composed of an even number of inverter chains and is used to drive the power switch device 351.

[0057] The second point to note is that the power switch device 352 can be an NMOSFET device, a PMOSFET device, or other types of switch devices.

[0058] The third point to be noted is that the second output voltage of the triangular wave generator 310 is a triangular wave or a sawtooth wave.

[0059] In this embodiment, the pulse width modulation circuit with constant power output may further include a segmentation controller (not shown in the figure); the segmentation controller is used to compare the output current with a reference current and adjust the proportional relationship between the feedback voltage and different output currents according to the comparison result; and / or; the segmentation controller is used to compare the second output voltage with a reference voltage and adjust the proportional relationship between the feedback voltage and different second output voltages according to the comparison result.

[0060] Specifically, the segmentation controller includes at least one comparator and one switching device. The comparator is used to compare the output current (IO) or the second output voltage (VO) with a certain reference current or voltage to determine the range in which the output current or the second output voltage is located, and then generate a control signal through a logic circuit. The switching device is controlled by this control signal to adjust the proportional relationship between the feedback voltage VF and IO (or VO) in different current or voltage ranges, so as to keep the output power approximately constant.

[0061] In this embodiment, when the output of the buffer 340 changes from high level to low level, the logic control circuit 330 is used to control the power switch device 351 to conduct; when the output of the buffer 340 changes from low level to high level, the logic control circuit 330 is used to control the power switch device 351 to turn off. That is, at the rising edge of the first input signal (ST), the output of the logic control circuit 330 changes, the output of the buffer 340 becomes low, and the power switch device 351 conducts. In the low level interval of the first input signal (ST), that is, in the interval where the SAW voltage of the triangular wave generator drops, at the falling edge of the second input signal, the output of the buffer 340 becomes high, and the power switch device 351 turns off.

[0062] In this embodiment, there are two implementation manners for the voltage sampling circuit 353, and the following will introduce these two implementation manners respectively.

[0063] Figure 7The first embodiment of the voltage sampling circuit 353 is shown. The voltage sampling circuit 353 includes a first resistor R1 and a second resistor R2, and the power switch device 351 is a PMOS (P-Channel Metal Oxide Semiconductor) transistor M0, and the load 360 is RO. Among them, the gate of the PMOS transistor M0 is connected to the output terminal of the buffer 340, the source is connected to the power supply voltage VDD, the drain is respectively connected to one end of the first resistor R1 and one end of the load RO at the VO point, the other end of the first resistor R1 is connected to one end of the second resistor R2 at the VF point, and the other end of the second resistor R2 and the other end of the load RO are connected to the GND point. At this time, the series resistance voltage division mode can be used to obtain the feedback voltage (VF), let VF = k0 × VO, the output duty cycle D = m - k1 × VF, where m, k0 = R2 / (R1 + R2), and k1 are constants. Then the output power PO is:

[0064]

[0065] In this case, the relationship diagram of the output duty cycle and the output power changing with the output voltage is as Figure 8 shown. According to Formula 1, the point where the slope of the output power PO is 0 is That is, the value of the output power PO near this point is approximately constant.

[0066] Figure 9The second implementation of the voltage sampling circuit 353 is shown. The voltage sampling circuit 353 includes a third resistor R3 to an eleventh resistor R11, a first comparator CMP1 to a third comparator CMP3, a logic circuit, a first switch S1 to a third switch S3. And the power switch device 351 is a PMOS transistor M0, and the load 360 is RO. The gate of the PMOS transistor M0 is connected to the output terminal of the buffer 340, the source is connected to the power supply voltage VDD, and the drain is connected to one end of the third resistor R3, one end of the seventh resistor R7, and one end of the load RO at the VO point. The other end of the third resistor R3 is connected to one end of the fourth resistor R4 and the non-inverting input terminal of the first comparator CMP1. The other end of the fourth resistor R4 is connected to one end of the fifth resistor R5 and the non-inverting input terminal of the second comparator CMP2. The other end of the fifth resistor R5 is connected to one end of the sixth resistor R6 and the non-inverting input terminal of the third comparator CMP3. The inverting input terminals of the first comparator CMP1 to the third comparator CMP3 are all connected to the reference voltage Vref. The output terminals of the first comparator CMP1 to the third comparator CMP3 are respectively connected to three input terminals of the logic circuit. The other end of the seventh resistor R7 is connected to one end of the eighth resistor R8 at the VF point. The VF point is connected to the second input terminal of the comparator 320. The other end of the eighth resistor R8 is respectively connected to one end of the ninth resistor R9 to the eleventh resistor R11. The other end of the ninth resistor R9 is connected to one end of the first switch S1. The other end of the tenth resistor R10 is connected to one end of the second switch S2. The other end of the eleventh resistor R11 is connected to one end of the third switch S3. The other end of the sixth resistor R6 is connected to the other ends of the first switch S1 to the third switch S3 and the other end of the load RO at the GND point. The three output terminals of the logic circuit are respectively used to control the on and off of the first switch S1 to the third switch S3. In this implementation, a segmented control technique can be adopted. The range of the second output voltage (VO) is obtained through the comparator 320, and then a control signal for controlling the first switch S1 to the third switch S3 is output through the logic circuit. Thus, the output power PO can be adjusted by adjusting the voltage ratio of the feedback voltage (VF) to the second output voltage (VO), and the approximate constancy of the output power PO can be maintained. The point where the slope of the known output power PO is 0 is where k1 is the proportionality coefficient between the feedback voltage VF and the second output voltage VO, and VO’ is inversely proportional to k1. Therefore, when the second output voltage VO increases, as long as k1 is correspondingly reduced, the constancy of the output power PO can be maintained, as Figure 10 shown.

[0067] If VO’ is substituted into Formula 1, the maximum value of the output power PO can be obtained as If the output power PO is to be maintained unchanged, reducing k1 can increase VO’. At the same time, if the output power PO is to be maintained unchanged, then

[0068] Among them, there are many ways to control the on / off of the first switch S1 to the third switch S3. In this embodiment, one of them is taken as an example for illustration, and other control methods are not limited. Specifically, assume V1 < V2 < V3. If VO < V1, the first switch S1 is turned off, and the second switch S2 and the third switch S3 are turned on; if V1 < VO < V2, the second switch S2 is turned off, and the first switch S1 and the third switch S3 are turned on; if V2 < VO < V3, the third switch S3 is turned off, and the first switch S1 and the second switch S2 are turned on; if V3 < VO, the third switch S3 and the first switch S1 are turned off, and the second switch S is turned on.

[0069] In this embodiment, the current sampling circuit 352 has two implementation manners, and the following will introduce these two implementation manners respectively.

[0070] Figure 11 The first implementation manner of the current sampling circuit 352 is shown. The current sampling circuit 352 includes a PMOS transistor M1, a twelfth resistor R12, and a thirteenth resistor R13. The power switch device 351 is a PMOS transistor M0, and the load 360 is RO. The gates of the PMOS transistors M0 and M1 are respectively connected to the output terminal of the buffer 340. The sources of the PMOS transistors M0 and M1 are both connected to the power supply voltage VDD. The drain of the PMOS transistor M0 is connected to one end of the load RO at the VO point. The drain of the PMOS transistor M1 is connected to one end of the twelfth resistor R12. The other end of the twelfth resistor R12 is connected to one end of the thirteenth resistor R13 at the VF point. The VF point is connected to the second input terminal of the comparator 320. The other end of the thirteenth resistor R13 and the other end of the load RO are connected to the GND point. The operating conditions of the PMOS transistors M1 and M0 are the same, and they can form a current mirror. The currents in the PMOS transistors M1 and M0 are proportional to their aspect ratios.

[0071] Figure 12It represents the second implementation of the current sampling circuit 352. The current sampling circuit 352 includes PMOS transistor M2, the fourteenth resistor R14 to the twenty-second resistor R22, the fourth comparator CMP4 to the sixth comparator CMP6, a logic circuit, the fourth switch S4 to the sixth switch S6, and the power switch device 351 is PMOS transistor M0, and the load 360 is RO. The gates of PMOS transistors M0 and M1 are respectively connected to the output terminal of the buffer 340. The sources of PMOS transistors M0 and M1 are both connected to the power supply voltage VDD. The drain of PMOS transistor M0 is connected to one end of the load RO at the VO point. The drain of PMOS transistor M1 is respectively connected to one end of the fourteenth resistor R14 and one end of the eighteenth resistor R18. The other end of the fourteenth resistor R14 is respectively connected to one end of the fifteenth resistor R15 and the non-inverting input terminal of the fourth comparator CMP4. The other end of the fifteenth resistor R15 is respectively connected to one end of the sixteenth resistor R16 and the non-inverting input terminal of the fifth comparator CMP5. The other end of the sixteenth resistor R16 is respectively connected to one end of the seventeenth resistor R17 and the non-inverting input terminal of the sixth comparator CMP6. The inverting input terminals of the fourth comparator CMP4 to the sixth comparator CMP6 are all connected to the reference voltage Vref. The output terminals of the fourth comparator CMP4 to the sixth comparator CMP6 are respectively connected to three input terminals of the logic circuit. The other end of the eighteenth resistor R18 is connected to one end of the nineteenth resistor R19 at the VF point. The VF point is connected to the second input terminal of the comparator 320. The other end of the nineteenth resistor R19 is connected to one end of the twentieth resistor R20 to the twenty-second resistor R22. The other end of the twentieth resistor R20 is connected to one end of the fourth switch S4. The other end of the twenty-first resistor R21 is connected to one end of the fifth switch S5. The other end of the twenty-second resistor R22 is connected to one end of the sixth switch S6. The other end of the seventeenth resistor R17 is connected to the other ends of the fourth switch S4 to the sixth switch S6 and the other end of the load RO and are interconnected at the GND point. Among them, the three output terminals of the logic circuit are respectively used to control the on and off of the fourth switch S4 to the sixth switch S6. The specific control method can be similar to the control method in the above text. PMOS transistors M1 and M0 have the same operating conditions and can form a current mirror, and the currents in PMOS transistors M1 and M0 are proportional to their width-to-length ratios.

[0072] Both of these two implementation methods convert the sampled output current into the first output voltage, and then obtain the feedback voltage VF through resistor voltage division. The conclusion is similar to that of the voltage sampling circuit 353, as Figure 8 and Figure 10 shown.

[0073] Figure 13An implementation of the logic control circuit 330 is shown. The logic control circuit 330 includes a NOR gate and an RS flip-flop. The reset terminal (R) of the RS flip-flop is respectively connected to an input terminal of the NOR gate and the first output terminal of the triangular wave generator 310. The other input terminal of the NOR gate is connected to the output terminal of the comparator 320. The output terminal of the NOR gate is connected to the set terminal (S) of the RS flip-flop. The inverted output terminal of the RS flip-flop is connected to the input terminal of the buffer 340.

[0074] Figure 14 The working waveform of the pulse width modulation circuit with constant power output is shown. As the power supply voltage decreases, the duty cycle of the output voltage gradually increases, so as to achieve the purpose of constant power output.

[0075] As Figure 15 shown, the present invention discloses a pulse width modulation method, which is applied to the pulse width modulation circuit with constant power output described above. The pulse width modulation method includes:

[0076] Step 1501, the power switch and the sampling circuit generate a feedback voltage according to the output power and output the feedback voltage to the comparator.

[0077] Step 1502, the comparator generates a comparison result according to the feedback voltage and an output signal of the triangular wave generator and sends the comparison result to the logic control circuit.

[0078] Step 1503, the logic control circuit generates a pulse width modulation signal according to the comparison signal and another output signal of the triangular wave generator, and sends the pulse width modulation signal to the power switch and the sampling circuit through the buffer. The pulse width modulation signal is used to control the output duty cycle of the power switch and the sampling circuit, and the output duty cycle is used to adjust the output power of the pulse width modulation circuit with constant power output to make the output power constant.

[0079] The above are only the preferred examples of the present invention and are not limited to the present invention. For those skilled in the art, various changes and modifications can be made to the present invention. Any modification, equivalent replacement, improvement, etc. made within the spirit and principle of the present invention shall be included in the protection scope of the present invention.

Claims

1. A pulse width modulation circuit with constant power output, characterized in that The pulse width modulation circuit with constant power output includes a triangular wave generator, a comparator, a logic control circuit, a buffer, a power switch, and a sampling circuit; The first output terminal of the triangular wave generator is connected to the first input terminal of the logic control circuit, and the second output terminal of the triangular wave generator is connected to the first input terminal of the comparator; The second input terminal of the comparator is connected to the second output terminal of the power switch and sampling circuit, and the output terminal of the comparator is connected to the second input terminal of the logic control circuit; The output terminal of the logic control circuit is connected to the input terminal of the buffer, the output terminal of the buffer is connected to the input terminal of the power switch and sampling circuit, and the first output terminal of the power switch and sampling circuit serves as the output terminal of the pulse width modulation circuit with constant power output and is connected to the load; Among them, the pulse width modulation signal of the pulse width modulation circuit with constant power output is used to control the output duty cycle, and the output duty cycle is used to adjust the output power of the pulse width modulation circuit with constant power output to make the output power constant; The power switch and sampling circuit includes a power switch device, a current sampling circuit, a voltage sampling circuit, and an arithmetic circuit; the input terminal of the power switch device is respectively connected to the output terminal of the buffer and the input terminal of the current sampling circuit, and the output terminal of the power switch device is respectively connected to the input terminal of the voltage sampling circuit and the load; the output terminal of the current sampling circuit is connected to the first input terminal of the arithmetic circuit; the output terminal of the voltage sampling circuit is connected to the second input terminal of the arithmetic circuit; the output terminal of the arithmetic circuit is connected to the second input terminal of the comparator; The current sampling circuit is used to sample the output current of the power switch device and output the first output voltage generated according to the output current to the arithmetic circuit, and the first output voltage is linearly related or piecewise linearly related to the output current; The voltage sampling circuit is used to sample the second output voltage of the power switch device and output the third output voltage generated according to the second output voltage to the arithmetic circuit, and the third output voltage is linearly related or piecewise linearly related to the second output voltage; The arithmetic circuit is used to perform arithmetic operations on the first output voltage and the third output voltage, and determine the obtained fourth output voltage as the feedback voltage output to the comparator, and the feedback voltage is directly proportional to the arithmetic product or arithmetic sum of the first output voltage and the third output voltage; The pulse width modulation circuit with constant power output further includes a segmentation controller; The segmentation controller is used to compare the output current with a reference current and adjust the proportional relationship between the feedback voltage and different output currents according to the comparison result; and / or; The segmentation controller is used to compare the second output voltage with a reference voltage and adjust the proportional relationship between the feedback voltage and different second output voltages according to the comparison result.

2. The pulse width modulation circuit with constant power output according to claim 1, characterized in that, The second output voltage of the triangular wave generator is a triangular wave or a sawtooth wave.

3. The pulse width modulation circuit with constant power output according to claim 1, wherein The power switch and sampling circuit includes a power switch device and a current sampling circuit; the input ends of the power switch device are respectively connected to the output end of the buffer and the input end of the current sampling circuit, and the output end of the power switch device is connected to the load; the output end of the current sampling circuit is connected to the second input end of the comparator; The current sampling circuit is used to sample the output current of the power switch device, and determine the first output voltage generated according to the output current as the feedback voltage output to the comparator, and the feedback voltage has a linear relationship or a piecewise linear relationship with the output current.

4. The pulse width modulation circuit with constant power output according to claim 1, characterized in that The power switch and sampling circuit includes a power switch device and a voltage sampling circuit; the input end of the power switch device is connected to the output end of the buffer, and the output end of the power switch device is respectively connected to the input end of the voltage sampling circuit and the load; the output end of the voltage sampling circuit is connected to the second input end of the comparator; The voltage sampling circuit is used to sample the second output voltage of the power switch device, and determine the third output voltage generated according to the second output voltage as the feedback voltage output to the comparator, and the feedback voltage has a linear relationship or a piecewise linear relationship with the second output voltage.

5. The pulse width modulation circuit with constant power output according to any one of claims 1 to 4, characterized in that, The power switch device is an N-channel metal oxide semiconductor field effect transistor or a P-channel metal oxide semiconductor field effect transistor.

6. The pulse width modulation circuit with constant power output according to any one of claims 1 to 4, characterized in that, When the output of the buffer changes from high level to low level, the logic control circuit is used to control the power switch device to conduct; when the output of the buffer changes from low level to high level, the logic control circuit is used to control the power switch device to turn off.

7. The pulse width modulation circuit with constant power output according to claim 1, characterized in that, The output signal of the first output end in the triangular wave generator is a square wave signal; the output signal of the second output end is a triangular wave signal, and the output frequency of the second output end is the same as that of the first output end.

8. A pulse width modulation method, characterized in that, In the pulse width modulation circuit for constant power output according to any one of claims 1 to 7, the method includes: The power switch and sampling circuit generates a feedback voltage according to the output power, and outputs the feedback voltage to the comparator; The comparator generates a comparison result according to the feedback voltage and one output signal of the triangular wave generator, and sends the comparison result to the logic control circuit; The logic control circuit generates a pulse width modulation signal according to the comparison result and the other output signal of the triangular wave generator, and sends the pulse width modulation signal to the power switch and sampling circuit through the buffer. The pulse width modulation signal is used to control the output duty cycle of the power switch and sampling circuit, and the output duty cycle is used to adjust the output power of the pulse width modulation circuit for constant power output so that the output power is constant.

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