Method for manufacturing a semiconductor device having reduced contact resistance

Abstract

Embodiments of the present disclosure generally relate to methods for forming transistors. More specifically, the embodiments described herein generally relate to methods for forming source / drain contacts. In one embodiment, the method includes forming a trench in a dielectric material to expose the source / drain regions of a transistor; performing a pre-clean process on the exposed source / drain regions; forming a doped semiconductor layer on the source / drain regions by an epitaxial deposition process; and filling the trench with a conductor. Due to the higher dopant concentration in the doped semiconductor layer, the doped semiconductor layer has a lower resistance than the source / drain regions. As a result, the contact resistance of the source / drain regions is reduced.

Description

[0001] Background

[0002] Field

[0003] Embodiments of the present disclosure generally relate to methods for forming transistors. More specifically, the embodiments described herein generally relate to methods for forming source / drain contacts.

[0004] Description of Related Art

[0005] One key challenge in semiconductor design, fabrication, and operation is contact resistance. For example, the source and drain regions of a fin field-effect transistor (FinFET) device can be etched to form source / drain contact trenches, resulting in increased contact resistance. The result of increased contact resistance is a reduction in the performance of circuit devices including transistors and other device structures formed on a semiconductor substrate.

[0006] There is a need for semiconductor processing methods for forming transistors with reduced contact resistance.

[0007] Overview

[0008] Embodiments of the present disclosure generally relate to methods for forming transistors. More specifically, the embodiments described herein generally relate to methods for forming source / drain contacts. In one embodiment, a method for forming a contact includes forming a trench in a dielectric material to expose a source / drain region; performing a pre-clean process on the source / drain region; forming a doped semiconductor layer on the source / drain region; and filling the trench with a conductor.

[0009] In another embodiment, a semiconductor device includes source / drain regions extending from a semiconductor structure; a doped semiconductor layer disposed on a first portion of the source / drain regions; a metal silicide layer disposed on the doped semiconductor layer; a cap layer disposed on the metal silicide layer; and a conductor disposed on the cap layer.

[0010] In another embodiment, a processing system includes a first transfer chamber; a plurality of process chambers coupled to the first transfer chamber; and a controller configured to cause processes to be performed in the processing system, the processes including the steps of: performing a pre-clean process on the source / drain regions; forming a doped semiconductor layer on the source / drain regions; and filling a trench with a conductor.

[0011] Brief Description of the Drawings

[0012] To understand the above features of the present disclosure in detail, a more specific description of the present disclosure briefly outlined above can be obtained by referring to the embodiments, and some embodiments are illustrated in the drawings. However, it should be noted that the drawings only illustrate exemplary embodiments and are therefore not considered as limiting the scope of the present disclosure, and other equivalent embodiments can be recognized.

[0013] Figure 1 is a flowchart of a method for forming contacts.

[0014] Figures 2A - 2G Illustrated in Figure 1 various views of a transistor during different stages of the method.

[0015] Figure 3 is a schematic top view of an exemplary multi-chamber processing system suitable for performing Figure 1 the method.

[0016] For the sake of facilitating understanding, the same reference numerals have been used as much as possible to represent the same elements common to the various figures. It is contemplated that the elements and features of one embodiment can be beneficially incorporated into other embodiments without further elaboration.

[0017] Detailed Description

[0018] The present disclosure generally relates to a method for forming a transistor. More specifically, the methods described herein generally relate to a method for forming source / drain contacts. In one embodiment that may include or incorporate one or more of the embodiments described herein, the method includes forming a trench in a dielectric material to expose the source / drain regions of a transistor; performing a pre-clean process on the exposed source / drain regions; forming a doped semiconductor layer on the source / drain regions by an epitaxial deposition process; and filling the trench with a conductor. Due to the higher dopant concentration in the doped semiconductor layer, the doped semiconductor layer has a lower resistance than the source / drain regions. As a result, the contact resistance of the source / drain contacts is reduced.

[0019] The above broadly outlines the technology described in this disclosure. It is contemplated that the concepts of the present disclosure can be implemented for planar transistor devices or for three-dimensional transistor devices, such as fin field-effect transistors (FinFETs), horizontal gate-all-around (HGAA) FETs, vertical gate-all-around (VGAA) FETs, nanowire channel FETs, strained semiconductor devices, and the like.

[0020] Figure 1 is a flowchart of a method 100 for forming contacts. Figures 2A - 2G Illustrated in Figure 1Various views of a transistor during different stages of method 100. Note that method 100 can be utilized to form any other semiconductor structure not presented herein. Those skilled in the art should recognize that not all processes for forming semiconductor devices and associated structures are illustrated in the figures or described herein. Although various operations are illustrated in the figures and described herein, no limitation is implied regarding the order of such steps or the presence or absence of steps. Unless explicitly specified, operations depicted or described in sequence are done so for purposes of explanation only, and do not preclude the possibility that the corresponding steps are actually performed in a parallel or overlapping manner (at least in part), if not entirely in a parallel or overlapping manner.

[0021] Method 100 begins at operation 102 by placing substrate 200 in a process chamber. The process chamber can be an etching chamber. As Figure 2A shown, substrate 200 includes semiconductor layer 202, a plurality of semiconductor structures 204 (only two are shown) extending from semiconductor layer 202, and dielectric material 206 disposed between semiconductor structures 204 on semiconductor layer 202. Semiconductor structures 204 can be semiconductor fins. Semiconductor layer 202 is made of silicon, germanium, silicon germanium, or a III / V compound semiconductor (such as GaAs or InGaAs). Semiconductor layer 202 can be doped with p-type or n-type dopants. In one embodiment that can include or incorporate one or more embodiments described herein, semiconductor layer 202 is doped with a p-type dopant (such as boron). In one embodiment that can include or incorporate one or more embodiments described herein, semiconductor layer 202 is doped with an n-type dopant (such as phosphorus or arsenic). Semiconductor structures 204 are made of the same material as semiconductor layer 202. In one embodiment that can include or incorporate one or more embodiments described herein, semiconductor structures 204 are integral with semiconductor layer 202. Dielectric material 206 can be a shallow trench isolation (STI) region and can be made of SiO, SiN, SiCN, or other suitable dielectric materials.

[0022] Substrate 200 further includes source / drain regions 208 extending from each semiconductor structure 204. In one embodiment that can include or incorporate one or more embodiments described herein, source / drain regions 208 are source regions or drain regions. In one embodiment that can include or incorporate one or more embodiments described herein, as Figure 2AAs shown, the source / drain region 208 includes a merged source and drain region 208. In any embodiment, the source / drain region 208 is made of semiconductor material epitaxially grown on the semiconductor structure 204. The source / drain region 208 is made of silicon, germanium, silicon germanium, or a III / V compound semiconductor (such as GaAs, InGaAs). The source / drain region 208 can be doped with p-type or n-type dopants. In one example, the source / drain region 208 is doped with a p-type dopant (such as boron). Alternatively, the source / drain region 208 is doped with an n-type dopant (such as phosphorus or arsenic). The source / drain region 208 can be epitaxially grown on the semiconductor structure 204, and because of different growth rates on different surface planes, facets can be formed to cause the source / drain region 208 to have a diamond shape.

[0023] A contact etch stop layer (CESL) 210 is formed on the dielectric material 206 and the source / drain region 208. The CESL 210 is made of a dielectric material (such as silicon nitride, silicon oxynitride, silicon carbonitride, or a combination of the above). A dielectric material 212 is disposed on the CESL 210. The dielectric material 212 can be an interlayer dielectric and can be made of a dielectric material (such as silicon oxide, silicon nitride, silicon oxynitride, silicon carbide, or a combination of the above). The substrate 200 can include a plurality of gates (not shown) disposed across the source / drain region 208.

[0024] Next, at operation 104, as Figure 2B shown, trenches 214 are formed in the dielectric material 212 to expose the source / drain region 208. The trenches 214 are formed by removing portions of the dielectric material 212 and the CESL 210 disposed above each source / drain region 208 and exposing the surface 216 of each source / drain region 208. The trenches 214 can be formed by any suitable removal process. In one example, the trenches 214 are formed by a reactive ion etching (RIE) process. A single source or drain region 208 is exposed in each trench 214. Alternatively, as Figure 2B shown, the merged source and drain region 208 is exposed in each trench 214. A portion of the source / drain region 208 is removed during the formation of the trenches 214. The eroded source / drain region 208 has an increased contact resistance. The trenches 214 can be formed in a reactive ion etching (RIE) chamber or other suitable etching chamber.

[0025] Next, at operation 106, a pre-clean process is performed on the exposed surface 216 of the source / drain region 208. The pre-clean process is performed to remove contaminants, such as carbon or oxide contaminants, on the surface 216 of the source / drain region 208. The pre-clean process can be any suitable etching process, such as dry etching, wet etching, or a combination of the foregoing. In one embodiment that can include or incorporate one or more of the embodiments described herein, the pre-clean process includes a wet etching process followed by a dry etching process. The wet etching process can utilize an ammonia or hydrogen fluoride solution. The dry etching process can be a plasma etching process and can utilize a fluorine- or hydrogen-containing etchant. The pre-clean process does not substantially remove any portion of the source / drain region 208.

[0026] The pre-clean process is performed in a first process chamber of the processing system. In one example, the pre-clean process is performed in a process chamber using a remote plasma source. An example process chamber suitable for performing the pre-clean process is an AKTIV Pre-Clean TM chamber or cleaning chamber available from Applied Materials, Inc. of Santa Clara, California, USA. Alternatively, the pre-clean process is performed in an etching chamber, such as an etching chamber using an inductively coupled plasma (ICP) source. An example etching chamber can be a modified decoupled plasma nitridation (DPN) chamber available from Applied Materials, Inc. of Santa Clara, California, USA. However, it is contemplated that other suitably configured chambers from other manufacturers can also be implemented to perform the pre-clean process.

[0027] At operation 108, as Figure 2CAs shown, after a pre-clean process to remove any contaminants from the surface 216, a doped semiconductor layer 220 is formed on the cleaned surface 216 of the source / drain region 208. The doped semiconductor layer 220 can be formed by a selective epitaxial deposition process. As a result of the selective epitaxial deposition process, the doped semiconductor layer 220 is formed on the surface 216 (i.e., on the bottom of the trench 214), and the doped semiconductor layer 220 is not formed on the sidewalls 218 of the trench 214. The selective epitaxial deposition process is performed while the substrate is maintained at a temperature below about 450 degrees Celsius. The doped semiconductor layer 220 can be made of the same material as the source / drain region 208, with the exception that the dopant concentration in the doped semiconductor layer 220 is substantially higher than the dopant concentration in the source / drain region 208. For example, the doped semiconductor layer 220 is made of germanium tin (GeSn) in-situ doped with boron and gallium, silicon germanium (SiGe) in-situ doped with boron, germanium (Ge) in-situ doped with boron and gallium, or silicon in-situ doped with phosphorus and arsenic. In one embodiment that may include or incorporate one or more of the embodiments described herein, the doped semiconductor layer 220 is formed by a dopant soak process. During the dopant soak process, for example, the top portion of the source / drain region 208 from the surface 216 to a predetermined depth is transformed into the doped semiconductor layer 220. For example, during the dopant soak process, the surface 216 of the source / drain region 208 is exposed to one or more gases containing one or more dopants (such as gallium, boron, phosphorus, and arsenic). The doped semiconductor layer 220 can have a thickness in the range from about a few angstroms to about 10 nm. The dopant concentration in the source / drain region 208 is less than the dopant concentration in the doped semiconductor layer 220. The increased dopant concentration in the doped semiconductor layer 220 reduces the contact resistance.

[0028] In one embodiment that may include or incorporate one or more of the embodiments described herein, the doped semiconductor layer 220 is formed in a reduced pressure (RP) epitaxial chamber (Epi chamber) available from Applied Materials, Inc. of Santa Clara, California, USA. However, it is envisioned that other suitably configured chambers from other manufacturers can also be implemented to perform the selective epitaxial deposition or dopant soak process to form the doped semiconductor layer 220.

[0029] Next, at operation 110, as Figure 2DAs shown, a metal silicide layer 222 is formed on the doped semiconductor layer 220 by a selective epitaxial deposition process. As a result of the selective epitaxial deposition process, the metal silicide layer 222 is formed on the doped semiconductor layer 220 (i.e., on the bottom of the trench 214), and the metal silicide layer 222 is not formed on the sidewalls 218 of the trench 214. The metal silicide layer 222 can be titanium silicide, cobalt silicide, ruthenium silicide, or other suitable metal silicides. The metal silicide layer 222 has a thickness in the range from a few angstroms to about 10 nm. The metal silicide layer 222 can be formed in the same process chamber as the doped semiconductor layer 220.

[0030] Next, at operation 112, as Figure 2E shown, a cap layer 224 is formed on the metal silicide layer 222. The cap layer 224 can be made of a nitride or oxide material (such as titanium nitride, silicon nitride, aluminum oxide, hafnium oxide, zirconium oxide, or manganese oxide). The cap layer 224 can be formed by an atomic layer deposition (ALD) process, and as Figure 2E shown, the cap layer 224 can be conformal. If the cap layer 224 is formed by an ALD process, the cap layer 224 is formed on both the sidewalls 218 and the metal silicide layer 222. The deposition of the cap layer 224 can be performed in an ALD chamber. Although other suitable chambers can be utilized, an example of an ALD chamber is available from Applied Materials, Inc. of Santa Clara, California, USA ALD chamber.

[0031] In some embodiments, the cap layer 224 is formed by nitriding the metal silicide layer, and the cap layer 224 is a metal silicon nitride layer. The nitriding process can include exposing the metal silicide layer 222 to a nitrogen-containing plasma or nitrogen-containing ambient such that nitrogen atoms react with atoms at the exposed surface of the metal silicide layer 222 to form a surface nitride layer (e.g., the cap layer 224). The nitriding process can be performed in a plasma chamber using an inductively coupled plasma (ICP) source, such as a modified decoupled plasma nitridation (DPN) chamber available from Applied Materials, Inc. of Santa Clara, California, USA.

[0032] Next, at operation 114, as Figure 2FAs shown, a conductor 226 is formed in the trench 214 to fill the trench 214. The conductor 226 is made of a conductive material (such as metal). In one example, the conductor 226 is made of cobalt. The conductor 226 can be formed by one or more deposition processes. For example, the conductor 226 can be formed by first forming a seed layer and then forming a bulk fill on the seed layer. The seed layer and the bulk fill are made of the same material. The conductor 226 can be formed by a suitable deposition method, such as chemical vapor deposition (CVD) or physical vapor deposition (PVD).

[0033] Figure 2G is a cross-sectional view of the substrate 200 taken along line A-A as shown in Figure 2F As shown in Figure 2G the source / drain regions 208 extend from the semiconductor structure 204. A doped semiconductor layer 220 is disposed on the source / drain regions 208, a metal silicide layer 222 is disposed on the doped semiconductor layer 220, and a cap layer 224 is disposed on the metal silicide layer 222. As shown in Figure 2G CESL 210 and the dielectric material 212 can be disposed above the source / drain regions 208, such as on the cap layer 224. Adjacent source / drain regions 208 are separated by a conductor 234. The conductor 234 can act as a gate of the transistor. One or more layers can be disposed between the source / drain regions 208 and the conductor 234. For example, as shown in Figure 2G spacers 228, a dielectric layer 230, and a work function layer 232 are disposed between the source / drain regions 208 and the conductor 234. The spacers 228 can be made of a dielectric material, such as an oxide or a nitride. The dielectric layer 230 can be a high-k dielectric layer, such as hafnium oxide or titanium oxide. The work function layer 232 can be a nitride layer, such as titanium nitride.

[0034] Returning to reference Figure 1 operations 106, 108, 110, and 112 are performed to reduce the contact resistance of the source / drain contacts in the transistor. In some embodiments, one or more of the operations 106, 108, 110, and 112 can be omitted while still achieving a reduced contact resistance.

[0035] In one embodiment that can include or incorporate one or more of the embodiments described herein, operations 106 and 108 are performed, followed by operation 114 without performing operations 110 and 112. For example, after forming the doped semiconductor layer 220 on the source / drain regions 208, a conductor 226 is formed in the trench 214 and on the doped semiconductor layer 220.

[0036] In one embodiment that may include or incorporate one or more of the embodiments described herein, operation 110 is performed after operation 104, without performing operations 106 and 108. For example, after forming trench 214 to expose source / drain region 208, a metal silicide layer 222 is formed on the exposed source / drain region 208. Operations 112 and 114 are then performed after operation 110.

[0037] In one embodiment that may include or incorporate one or more of the embodiments described herein, operation 110 is performed after operation 104, without performing operations 106 and 108, and operation 114 is performed after operation 110, without performing operation 112. For example, after forming trench 214 to expose source / drain region 208, a metal silicide layer 222 is formed on the exposed source / drain region 208, and a conductor 226 is formed in trench 214 and on metal silicide layer 222.

[0038] Examples of process systems that may be suitably modified in accordance with the teachings provided herein include or an integrated process system, or other suitable process systems commercially available from Applied Materials, Inc. of Santa Clara, California, USA. It is contemplated that other process systems (including those from other manufacturers) may be adapted to benefit from the aspects described herein. Figure 3 According to an embodiment of the present disclosure, a schematic top view of an exemplary multi-chamber process system 300 that may be used to accomplish Figure 1 method 100 illustrated in Figure 3 is shown. As shown, a plurality of process chambers 302 are coupled to a first transfer chamber 304. The first transfer chamber 304 is also coupled to a first pair of pass-through chambers 306. The first transfer chamber 304 has a transfer robot (not shown) disposed at the center for transferring substrates between the pass-through chambers 306 and the process chambers 302. The pass-through chambers 306 are coupled to a second transfer chamber 310, which is coupled to a process chamber 314 configured to perform a pre-clean process (operation 106) and a process chamber 316 configured to perform an epitaxial deposition process (operations 108 / 110). The second transfer chamber 310 has a transfer robot (not shown) disposed at the center for transferring substrates between a set of load lock chambers 312 and the process chamber 314 or the process chamber 316. A factory interface 320 is connected to the second transfer chamber 310 through the load lock chambers 312. The factory interface 320 is coupled to one or more pods 330 on the opposite side of the load lock chambers 312. The pods 330 are typically front-opening unified pods (FOUPs) that are accessible from a clean room.

[0039] During operation, the substrate is first transferred to process chamber 314 where a pre-clean process is performed to remove contaminants, such as carbon or oxide contaminants, from the exposed surfaces of the source / drain regions of the transistors of the substrate. The contaminant removal process is described in Figure 1 under operation 106. Next, the substrate is transferred to process chamber 316 where operation 108 and operation 110 are performed. In some embodiments, any of the process chambers 302 in one or more process chambers 302 can be used to switch process chamber 314 and / or process chamber 316.

[0040] Next, the substrate is transferred to one or more process chambers 302 where operation 112 and operation 114 are performed. Since all operations 106, 108, 110, 112 are performed within the same processing system 300, the vacuum is not broken when the substrate is transferred to various chambers, which reduces the chance of contamination and improves the quality of the deposited epitaxial film.

[0041] In some embodiments, the substrate is provided to an etch chamber (which is not part of the processing system including process chambers 314, 316 and one or more process chambers 302) to perform a trench formation process (operation 104). Once the trench is formed in the dielectric material, the substrate is then transferred to pod 330. Next, the substrate is transferred to process chamber 314 where operation 106 is performed. Next, the substrate is transferred to process chamber 316 and at least one process chamber 302 where operation 108, 110, 112 and 114 are performed.

[0042] System controller 380 is coupled to processing system 300 for controlling processing system 300 or components of processing system 300. For example, system controller 380 can control the operation of processing system 300 using direct control of chambers 302, 304, 306, 310, 312, 314, 316, 320, 330 of processing system 300, or by controlling controllers associated with chambers 302, 304, 306, 310, 312, 314, 316, 320, 330, 360. In operation, system controller 380 implements data collection and feedback from the respective chambers to coordinate the performance of processing system 300.

[0043] System controller 380 generally includes a central processing unit (CPU) 382, a memory 384, and support circuitry 386. CPU 382 can be one of any form of general-purpose processor that can be used in an industrial environment. Memory 384, a non-transitory computer-readable medium, or a machine-readable storage device is accessible by CPU 382 and can be one or more of memories such as random access memory (RAM), read-only memory (ROM), floppy disks, hard disks, or any other form of digital storage device (local or remote). Support circuitry 386 is coupled to CPU 382 and can include a cache, clock circuitry, an input / output subsystem, power supplies, and the like. System controller 380 is configured to execute method 100 stored in memory 384. The various embodiments disclosed herein can generally be implemented under the control of CPU 382 by executing computer instruction codes stored in memory 384 (or in the memory of a particular process chamber) as, for example, a computer program product or a software routine. That is, the computer program product is tangibly embodied in memory 384 (or a non-transitory computer-readable medium or a machine-readable storage device). When the computer instruction codes are executed by CPU 382, CPU 382 controls the chamber to perform operations according to the various embodiments.

[0044] In summary, the embodiments of the present disclosure are capable of forming source / drain contacts with reduced contact resistance by using an integrated process, which allows performing various operations for forming source / drain contacts within the same processing system. In some embodiments, after forming the contact trenches, a pre-clean process and the formation of a doped semiconductor layer are performed on the source / drain regions. The doped semiconductor layer has a higher dopant concentration than the source / drain regions, and the higher dopant concentration results in a reduced contact resistance.

[0045] Although the above is directed to embodiments of the present disclosure, other and further embodiments of the present disclosure can be designed without departing from the basic scope of the present disclosure, and the scope of the present disclosure is determined by the appended claims.

Claims

1. A method for forming a contact, the method comprising the steps of: Providing a contact etch stop layer on a dielectric material and a source / drain region; Forming a trench in the dielectric material by removing portions of the dielectric material and the contact etch stop layer to expose the source / drain region; Performing a pre-clean process on the source / drain region and the dielectric material; Forming a doped semiconductor layer on the source / drain region, wherein the doped semiconductor layer has a higher dopant concentration than the source / drain region; Forming a metal silicide layer on the doped semiconductor layer; Filling the trench with a conductor; Forming a cap layer on the metal silicide layer; And Providing the conductor on the cap layer.

2. The method according to claim 1, further comprising the step of: forming a metal silicide layer on the doped semiconductor layer before filling the trench with the conductor.

3. The method according to claim 2, further comprising the step of: forming a cap layer on the metal silicide layer, wherein the conductor is provided on the cap layer.

4. The method according to claim 3, wherein the doped semiconductor layer comprises doped silicon, doped germanium, doped silicon germanium, or a doped III / V compound semiconductor, and the doped semiconductor layer is formed by a selective epitaxial deposition process.

5. The method according to claim 4, wherein the metal silicide layer comprises titanium silicide, cobalt silicide, or ruthenium silicide, and the metal silicide layer is formed by the selective epitaxial deposition process.

6. The method according to claim 5, wherein the cap layer comprises titanium nitride, silicon nitride, aluminum oxide, hafnium oxide, zirconium oxide, or manganese oxide, and the cap layer is formed by an atomic layer deposition process.

7. The method according to claim 6, wherein the conductor comprises a metal.

8. A semiconductor device manufactured by the method according to claim 1, comprising: A source / drain region extending from a semiconductor structure between dielectric materials; A doped semiconductor layer provided on a first portion of the source / drain region, wherein the doped semiconductor layer has a higher dopant concentration than the source / drain region; A metal silicide layer provided on the doped semiconductor layer; A conductor filling a trench formed in a dielectric material to expose the source / drain region; A cap layer provided on the metal silicide layer and the dielectric material; A conductor provided on the cap layer; And A contact etch stop layer provided on a second portion of the source / drain region.

9. The semiconductor device according to claim 8, wherein the source / drain region comprises silicon, germanium, silicon germanium, or a III / V compound semiconductor.

10. The semiconductor device according to claim 9, wherein the semiconductor structure comprises silicon, germanium, silicon germanium, or a III / V compound semiconductor.

11. The semiconductor device according to claim 10, wherein the doped semiconductor layer comprises doped silicon, doped germanium, doped silicon-germanium, or a doped III / V compound semiconductor, and the doped semiconductor layer is formed by a selective epitaxial deposition process.

12. The semiconductor device according to claim 11, wherein the metal silicide layer comprises titanium silicide, cobalt silicide, or ruthenium silicide.

13. The semiconductor device according to claim 12, wherein the cap layer comprises titanium nitride, silicon nitride, aluminum oxide, hafnium oxide, zirconium oxide, or manganese oxide.

14. The semiconductor device according to claim 8, wherein the contact etch stop layer comprises silicon nitride, silicon oxynitride, silicon carbonitride, or a combination of the foregoing.

15. The semiconductor device according to claim 13, wherein the conductor comprises a metal.

16. A substrate processing system, comprising: a first transfer chamber; A plurality of process chambers, the plurality of process chambers being coupled to the first transfer chamber; and a non-transitory computer-readable medium storing instructions that, when executed by a processor, cause a method to be performed in one or more of the plurality of process chambers, the method comprising: setting a contact etch stop layer on a dielectric material and on source / drain regions; forming trenches in the dielectric material to expose the source / drain regions; performing a pre-clean process on the source / drain regions and the dielectric material; forming a doped semiconductor layer on the source / drain regions, wherein the doped semiconductor layer has a higher dopant concentration than the source / drain regions; and forming a metal silicide layer on the doped semiconductor layer; forming a cap layer on the metal silicide layer; and filling the trenches with a conductor, wherein the conductor is disposed on the cap layer.

17. The processing system according to claim 16, wherein the plurality of process chambers includes a first process chamber configured to perform an epitaxial deposition process.

18. The processing system according to claim 17, wherein the plurality of process chambers further includes a second process chamber configured to perform the pre-clean process.

19. The processing system according to claim 18, further comprising a second transfer chamber coupled to the first transfer chamber through a through-chamber.

Images