Semiconductor device with drift region and back emitter and manufacturing method

Abstract

The invention relates to a semiconductor device having a drift region and a back emitter and a manufacturing method thereof. An epitaxial layer (106) is formed on a bottom substrate (105) on the front side by epitaxy. At least a portion of the bottom substrate (105) is removed from the opposite side of the front side, wherein the bottom substrate (105) is completely removed or the remaining bottom portion (105a) has a thickness of at most 20 μm. Dopants of a first charge type are injected into an injection layer (138) of the epitaxial layer (106) from the opposite side of the front side. A metal drain electrode (320) is formed opposite to the front side. At least the injection layer (138) is heated to a temperature not higher than 500° C., wherein the heating activates only a portion of the injected dopants in the injection layer (138), and after heating, the integrated concentration of the activated dopants along the shortest line between the metal drain electrode (320) and the nearest doped region of the second complementary charge type is at most 1.5E13 cm ‑2 .

Description

Background Art

[0001] The power semiconductor device conducts high load currents and withstands high blocking voltages. The superjunction device includes a superjunction structure having oppositely doped first and second regions formed in a drift region, which is electrically arranged in series with a controllable MOSFET channel. When a blocking voltage is applied to the superjunction device, the lateral electric field rises and clears the mobile charge carriers along the vertical pn junction between the first and second regions. The space charge region begins to expand perpendicularly to the direction of load current flow in the on state. At a relatively low blocking voltage, the mobile charge carriers are completely forced to leave the superjunction structure. When the blocking voltage is further increased, the depleted superjunction structure acts as a quasi-intrinsic layer and the vertical electric field rises.

[0002] The breakdown voltage is independent of the dopant concentration in the superjunction structure, so that the dopant concentration in the superjunction structure can be relatively high. Therefore, superjunction devices generally combine very low on-state resistance with high blocking capability. The better the efficiency of the superjunction structure in terms of blocking capability and semiconductor volume, the better the dopant atoms in the oppositely doped regions of the superjunction structure are balanced and compensate each other.

[0003] Improvements in superjunction semiconductor devices are desired. Summary of the invention

[0004] This object is achieved by the subject matter of the independent claims. The dependent claims relate to further embodiments.

[0005] According to an embodiment, a method for manufacturing a semiconductor device includes: forming an epitaxial layer on a bottom substrate on a front side by epitaxy. At least a portion of the bottom substrate is removed from the opposite side of the front side, wherein the bottom substrate is completely removed or the remaining bottom portion has a thickness of at most 20 μm. Dopants of a first charge type are injected into an injection layer of the epitaxial layer from the opposite side of the front side. A metal drain electrode is formed opposite to the front side, and at least the injection layer is heated to a temperature not higher than 500°C, wherein the heating activates only a portion of the injected dopants in the injection layer, and after heating, the integrated concentration of the activated dopants along the shortest line between the metal drain electrode and the nearest doped region of the second complementary charge type is at most 1.5E13 cm -2 .

[0006] According to another embodiment, a semiconductor device includes a transistor cell formed on a front side of a semiconductor portion along a first surface, and also includes a drain structure located between the transistor cell and a second surface of the semiconductor portion opposite the first surface. The drain structure forms a first pn junction with a body region of the transistor cell, and includes an emitter layer directly adjacent to the second surface. A metal drain electrode directly adjacent to the emitter layer. An integrated concentration of an activated dopant along a shortest line between the metal drain electrode and a nearest doped region of a charge type of the body region is at most 1.5E13 cm -2 .

[0007] According to another embodiment, a semiconductor device includes a transistor cell formed on a front side of a semiconductor portion along a first surface, and also includes a drain structure located between the transistor cell and a second surface of the semiconductor portion opposite to the first surface. The drain structure forms a first pn junction with a body region of the transistor cell and includes a uniformly doped remaining bottom portion directly adjacent to the second surface, wherein a vertical extension of the remaining bottom portion is at most 20 μm. A metal drain electrode directly adjacent to the remaining bottom portion.

[0008] Those skilled in the art will recognize additional features and advantages upon reading the following detailed description, and upon viewing the accompanying drawings. BRIEF DESCRIPTION OF THE DRAWINGS

[0009] The accompanying drawings are included to provide a further understanding of the present invention and are included in and constitute a part of this specification. The accompanying drawings illustrate embodiments of the present invention and together with the description are used to explain the principles of the present invention. Other embodiments and expected advantages of the present invention will be readily understood as they become better understood by reference to the detailed description below.

[0010] Figure 1A is a schematic vertical cross-sectional view of a portion of a base substrate for illustrating a method of manufacturing a semiconductor device including a super junction structure according to an embodiment with the base substrate completely removed.

[0011] Figure 1B is through Figure 1A Schematic vertical cross-sectional view of a portion of a semiconductor substrate obtained by forming an epitaxial layer having a super junction structure on a base substrate.

[0012] Figure 1C After forming transistor cells on the front side Figure 1B Schematic vertical cross-sectional view of a semiconductor substrate portion.

[0013] Figure 1D After removing the bottom substrate Figure 1C Schematic vertical cross-sectional view of a semiconductor substrate portion.

[0014] Figure 1E After dopants are implanted into the epitaxial layer and a metal drain electrode is formed Figure 1D Schematic vertical cross-sectional view of a semiconductor substrate portion.

[0015] Figure 1F It is soldered on the die carrier from Figure 1E The semiconductor substrate is obtained after the semiconductor die Figure 1E Schematic vertical cross-sectional view of a semiconductor substrate portion.

[0016] Figure 1G is shown along the Figure 1F Schematic diagram of the vertical dopant profile of line II.

[0017] Figure 2A is removing Figure 1C A schematic vertical cross-sectional view of a semiconductor substrate portion for illustrating another method of manufacturing a semiconductor device including a super junction structure according to an embodiment and with a bottom substrate partially removed.

[0018] Figure 2B After forming a metal drain electrode on the back Figure 2A Schematic vertical cross-sectional view of a semiconductor substrate portion.

[0019] Figure 2C It is shown along Figure 2B Schematic diagram of the vertical dopant profile of line II-II.

[0020] Figure 3A is a schematic vertical cross-sectional view of a portion of a semiconductor device according to an embodiment involving an implanted emitter layer and a metal drain electrode including a spike.

[0021] Figure 3B is a schematic vertical cross-sectional view of a portion of a semiconductor device having a remaining portion of a base substrate and a metal drain electrode without a spike according to an embodiment.

[0022] Figure 4A is a schematic vertical cross-sectional view of a portion of a semiconductor device having a thick base substrate according to a reference example for discussing the effects of the embodiment.

[0023] Figure 4B is a schematic vertical cross-sectional view of a portion of a semiconductor device having an emitter layer and a field stop layer according to an embodiment.

[0024] Figure 4C is used to compare along Figure 4ALine III-III and along Figure 4B Schematic diagram of the vertical charge carrier distribution along line IV-IV in order to discuss the effects of the embodiment.

[0025] Figure 5A is a schematic diagram for illustrating the effect of the embodiment regarding reverse recovery charge.

[0026] Figure 5B is a schematic diagram illustrating reverse recovery charge as a function of the thickness of a semiconductor die for discussing the effects of the embodiment.

[0027] Figure 5C is a schematic diagram illustrating the influence of the thickness of the base substrate on the on-state resistance for discussing the effects of the embodiment.

[0028] Figure 5D is a schematic diagram illustrating the influence of the thickness of the bottom substrate on the reverse recovery charge for discussing the effects of the embodiment.

[0029] Fig. 6A is a schematic vertical cross-sectional view of a power field effect transistor with a lightly doped drift region according to an embodiment with a completely removed base substrate.

[0030] Figure 6B The diagram is along Fig. 6A Schematic diagram of the vertical dopant profile of line BB.

[0031] Fig. 7A is a schematic vertical cross-sectional view of a power field effect transistor having a super junction structure according to an embodiment with a bottom substrate completely removed.

[0032] Figure 7B The diagram is along Fig. 7A Schematic diagram of the vertical dopant profile of line BB.

[0033] Fig. 8A is a schematic vertical cross-sectional view of a power field effect transistor with a lightly doped drift region according to an embodiment with respect to a remaining bottom portion.

[0034] Figure 8B The diagram is along Fig. 8A Schematic diagram of the vertical dopant profile of line BB.

[0035] Fig.9A is a schematic vertical cross-sectional view of a power field effect transistor having a super junction structure according to an embodiment with respect to a remaining bottom portion.

[0036] Fig. 9B The diagram is along Fig.9A Schematic diagram of the vertical dopant profile of line BB. DETAILED DESCRIPTION

[0037] In the following detailed description, reference is made to the accompanying drawings, which form a part of the detailed description and in which specific embodiments of the present invention are shown as illustrations. It should be understood that other embodiments may be used and structural or logical changes may be implemented without departing from the scope of the present invention. For example, the features illustrated or described for one embodiment can be used in other embodiments or used in conjunction with other embodiments to produce another embodiment. It is intended that the present invention includes such modifications and variations. Examples are described using specific language, which should not be interpreted as limiting the scope of the appended claims. The accompanying drawings are not drawn to scale and are for illustrative purposes only. If not otherwise indicated, corresponding elements are designated by the same reference numerals in different drawings.

[0038] The terms "having", "containing", "including", "comprising" and the like are open-ended terms, and the terms indicate the presence of stated structures, elements or features, but do not exclude the presence of additional elements or features. The articles "a", "an" and "the" are intended to include the plural as well as the singular, unless the context clearly indicates otherwise.

[0039] The term "electrically connected" describes a permanent low-ohmic connection between electrically connected elements, such as direct contact between the elements involved or a low-ohmic connection via metal and / or heavily doped semiconductors. The term "electrically coupled" includes that one or more intermediate elements adapted for signal transmission may be provided between the electrically coupled elements, such as elements controllable to temporarily provide a low-ohmic connection in a first state and a high-ohmic electrical decoupling in a second state.

[0040] The accompanying drawings illustrate relative doping concentrations by indicating "-" or "+" next to the doping type "n" or "p". For example, "n-" represents a doping concentration that is lower than the doping concentration of an "n" doping region, while an "n+" doping region has a higher doping concentration than an "n" doping region. Doping regions of the same relative doping concentration do not necessarily have the same absolute doping concentration. For example, two different "n" doping regions may have the same or different absolute doping concentrations.

[0041] Figure 1A A base substrate 105 is shown which may be obtained from a semiconductor crystal, for example by sawing. The base substrate 105 may be relatively heavily doped, wherein the dopant concentration in the base substrate 105 is approximately uniform.

[0042] The semiconductor material of the bottom substrate 105 may be silicon (Si), germanium (Ge), silicon germanium (SiGe), or A III B VSemiconductor. For example, the bottom substrate 105 is a silicon wafer. The thickness of the bottom substrate 105 between the processing surface 107 on the front side and the support surface 108 on the back side can be in the range of several hundred μm, for example between 500 μm and 850 μm, for example for a silicon wafer with a diameter of 200 mm, the thickness is about 725 μm, and for a silicon wafer with a diameter of 300 mm, the thickness is about 775 μm. The direction parallel to the exposed processing surface 107 of the bottom substrate 105 is the horizontal direction. The normal to the processing surface 107 defines the vertical direction.

[0043] An epitaxial layer 106 having a super junction structure 180 is formed on a processing surface 107 at the front side of a bottom substrate 105. The formation of the super junction structure 180 may be interleaved with the formation of the epitaxial layer 106, wherein the formation of the epitaxial sublayers is alternating with the implantation for forming oppositely doped super junction regions in a multi-epitaxial / multi-implantation process. According to other embodiments, the super junction structure 180 is formed by forming a thick epitaxial sublayer, forming a trench in the thick epitaxial sublayer, and implanting dopants, for example, through the sidewalls of the trench or depositing a doped layer in the trench.

[0044] Figure 1B A super junction structure 180 is shown formed in the epitaxial layer 106 on the front side of the base substrate 105. The super junction structure 180 includes a first region 181 of a first charge type corresponding to a first conductivity type and a second region 182 of a complementary second charge type corresponding to a second conductivity type. The planes of the same doping concentration may be approximately planar and vertical, or may include several protrusions along the vertical direction.

[0045] The transistor cell TC is formed on the front side of the semiconductor substrate 500a, which includes a bottom substrate 105 and an epitaxial layer 106 having a super junction structure 180. The transistor cell TC may be an IGFET (insulated gate field effect transistor) cell electrically connected in parallel to each other. The transistor cell TC may have a planar gate having a gate electrode formed above the main surface 101a of the semiconductor substrate 500a, or the transistor cell TC may be a trench gate extending from the main surface 101a into the semiconductor substrate 500a. The formation of the transistor cell TC may include the formation of another epitaxial sublayer above the super junction structure 180.

[0046] Figure 1CA transistor cell TC formed on the front side of a semiconductor substrate 500a is shown. The illustrated embodiment relates to a transistor cell TC that is an n-IGFET having a p-type body region 120 that directly adjoins a p-type second region 182 of a superjunction structure 180 and separates an n-type source region 110 from an n-type first region 181 of the superjunction structure 180. Other embodiments relate to p-IGFET cells having complementary doping.

[0047] After the formation of the transistor cell TC, for example after the formation of the metal source electrode 310 which is electrically connected to the body region 120 and to the source region 110 of the transistor cell TC via an opening in the interlayer dielectric 210 sandwiched between the main surface 101a and the metal source electrode 310, the substrate carrier 390 can be attached to the semiconductor substrate 500a on the front side.

[0048] The thinning process removes at least a portion of the base substrate 105. The thinning process may be a wafer splitting process or a grinding process along the porous portion of the base substrate 105. The thinning process may remove the entire base substrate 105 and, if applicable, the exposed portion of the epitaxial layer 106, or may leave a remaining bottom portion of the base substrate 105, wherein the remaining bottom portion has a thickness of no more than 20 μm. In the case where the base substrate 105 is completely removed, any conductivity type can be selected for the base substrate 105.

[0049] Figure 1D A semiconductor substrate 500a is shown, wherein Figure 1C The base substrate 105 is completely removed and the implantation surface 102a of the epitaxial layer 106 is exposed at the back side opposite to the substrate carrier 390. The distance a1 between the implantation surface 102a and the second region 182 of the super junction structure 180 is at most 50 μm, for example at most 25 μm.

[0050] Dopants of the first charge type (e.g., donors in the case of an n-channel transistor cell TC) are implanted from the back through the implant surface 102a to form an implant layer 138 along the implant surface 102a. A metal or metallization stack is deposited on the implant surface 102a to form a metal drain electrode 320. The metallization stack of the metal drain electrode 320 may include a nickel silver (NiAg) layer for soldering or a gold tin (AuSn) layer for diffusion soldering. The metal drain electrode 320 may have a flat interface with the epitaxial layer 106, or may include an extension extending into the epitaxial layer 106.

[0051] Figure 1EAn implantation layer 138 is shown formed along the implantation surface 102a. A heat treatment may be applied, wherein the maximum temperature of the heat treatment is at most 500° C., for example at most 350° C., so that only a portion of the implanted dopants in the implantation layer 138 are activated. The heat treatment may be a dedicated heat treatment in a furnace, for example. According to other embodiments, the method for attaching the implanted dopants obtained by sawing from the implantation layer 138 may be described in detail in detail. Figure 1E The process of obtaining the semiconductor die 500b from the semiconductor substrate 500a includes a welding process (eg, soft soldering or diffusion welding) at a temperature of at most 350° C., wherein the welding process anneals the implanted dopants and activates only a portion of the implanted dopants.

[0052] Figure 1F 5 shows a semiconductor device 500 obtained by soldering semiconductor dies 500b which are separated from the semiconductor substrate 500a by removing the substrate carrier 390 from the front side and sawing the semiconductor substrate 500a along the separation tracks. Figure 1E A semiconductor substrate 500a is obtained.

[0053] The solder layer system 365 mechanically and electrically connects the metal drain electrode 320 to the die carrier 360 (such as a copper plate). A dedicated heat treatment and / or soldering process activates a portion of the implanted dopants and Figure 1E The injection layer 138 is transformed into the emitter layer 139, wherein the integrated activated donor concentration along the shortest line connecting the metal drain electrode 320 and the nearest doped region of the conductivity type opposite to that of the emitter layer 139 is no greater than 1.5E13 cm -2 , for example, no more than 8E12cm -2 .

[0054] In the presence of the super junction structure 180, the nearest doped region of the conductivity type opposite to that of the emitter layer 139 is the second region 182 of the super junction structure 180. In the absence of the super junction structure, the nearest doped region of the conductivity type opposite to that of the emitter layer 139 may be the body region 120 of the transistor cell TC.

[0055] The activated donors define a back emitter layer 139 which is strong enough to emit electrons in the on-state of the IGFET under forward bias and to allow holes to tunnel into the metal drain electrode 320 under reverse bias. The holes that reach the metal drain electrode 320 and recombine there reduce the emitter efficiency at the back side so that the average charge carrier plasma density in the case of a forward conducting diode is significantly reduced. The recombination of holes in the metal drain electrode 320 fixes the hole density to zero at the interface between the back emitter layer 139 and the metal drain electrode 320. With the hole density fixed to zero at the semiconductor / metal interface between the emitter layer 139 and the metal drain electrode 320, the hole distribution steadily decreases from the superjunction structure 180 towards the semiconductor / metal interface. As a result, the total reverse recovery charge Qrr is significantly reduced.

[0056] Figure 1G Shown along Figure 1F The vertical donor distribution 401 and the vertical acceptor distribution 402 of line II, where the donor distribution 401 is from the maximum donor density N near the metal / semiconductor interface E The relatively low drift region donor density N drops to a distance corresponding to the vertical extension a0 of the emitter layer 139. drift .

[0057] Figures 2A to 2C Involved Figures 1C to 1F An alternative embodiment wherein Figure 1C Only a portion of the bottom substrate 105 is removed and the thin remaining bottom portion 105a having the concave surface 102b forms a portion of the semiconductor portion of the semiconductor device.

[0058] according to Figure 2A , the remaining thickness a3 of the thinned remaining bottom portion 105a is at most 20 μm, for example at most 10 μm, or at most 8 μm.

[0059] Dopants may be implanted into epitaxial layer 106 through remaining bottom portion 105a, metal drain electrode 320 is formed on recessed surface 102b, and as shown in FIG. Figure 1E and 1F Individual semiconductor dies 500b are obtained from semiconductor substrate 500a as discussed.

[0060] Figure 2B The diagram shows the Figure 2A The semiconductor die 500b is obtained from the semiconductor substrate 500a. The semiconductor portion 100 includes Figure 2A The remaining bottom portion 105a of the drain contact structure 137 is obtained.

[0061] Figure 2C Shown along Figure 2B The vertical donor distribution 411 and the vertical acceptor distribution 412 of line II-II are shown, wherein the donor distribution 411 is approximately uniform for the drain contact structure 137. According to an embodiment, a field stop layer may be formed between the super junction structure 180 and the drain contact structure 137.

[0062] Figure 3A and 3B Details of the electrical contacts at the semiconductor / metal interface on the back side of the semiconductor device 500 are involved.

[0063] exist Figure 3A In the embodiment of the present invention, the bottom substrate is completely removed and a back emitter layer 139 is formed in the semiconductor portion 100 obtained from the epitaxial layer. The metal drain electrode 320 directly adjoins the semiconductor portion 100. The back emitter layer 139 is produced by the implantation of dopants from the back side and a heat treatment, for example during soldering. In the back emitter layer 139, the dopant concentration is higher than the dopant concentration in the portion of the drift region 131 directly adjoining the back emitter layer 139 or, in the case of a field stop layer, higher than the dopant concentration in the portion of the field stop layer directly adjoining the emitter layer 139. The implantation may partially make a part of the semiconductor portion 100 amorphous. The metal and silicon form a eutectic solution, in which the solubility of silicon in aluminum is relatively high. The silicon atoms diffused into the metal drain electrode 320 leave gaps, in which spikes 321 of metal or a metal alloy containing silicon grow into the gaps.

[0064] Figure 3A Peaks 321 of different heights are shown extending from the second surface 102 into the back emitter layer 139. The maximum vertical extension v1 of the peaks 321 may be greater than 1 μm, for example about 4 μm.

[0065] The integrated activated donor concentration along the shortest line 322 connecting the metal drain electrode 320 and any second region 182 of the super junction structure 180 is no greater than 1.5E13 cm -2 , for example, not more than 8E12 cm -2 .

[0066] Under reverse bias, the body diode formed by the drain structure 130 and the body region connected to the second region 182 of the super junction structure is forward biased, and a forward current flows through the semiconductor portion. The hole plasma formed in the semiconductor portion 100 when the body diode is forward biased is fixed to zero at the top of the spike 321. The holes reach the metal drain electrode 320 and recombine there, thereby reducing the electron emitter efficiency. Due to the reduced electron emission, the overall plasma density in the semiconductor portion 100 is significantly reduced. On the other hand, the emitter layer 139 can be a sufficiently robust electron emitter as long as the integrated dopant concentration along the shortest line 322 (i.e., along the narrowest path between the metal drain electrode 320 and the pn junction) is less than 1E13 cm -2 That's it.

[0067] Figure 3B Show direct and by Figure 2A The metal drain electrode 320 is adjacent to the drain contact structure 137 formed by the remaining bottom portion 105a of the bottom substrate shown in the figure, wherein the drain contact structure 137 has a thickness of at most 20 μm (e.g., at most 5 μm). In the drain contact structure 137, the hole concentration drops to zero. If the drain contact structure 137 is thin enough, the hole density at the interface between the drift region 131 and the drain contact structure 137 is lower than the hole density in the comparative example with a thick bottom substrate, so that even if the hole density at the interface between the drift region 131 and the drain contact structure 137 is not equal to 0, the reverse recovery charge is significantly reduced.

[0068] Figures 4A to 4C Hole distribution in a conventional device is compared with hole distribution in a semiconductor device according to an embodiment.

[0069] Figure 4A A portion of a comparative device 509 is shown having a semiconductor portion 100 and a metal drain electrode 320 directly adjoining the semiconductor portion 100 at the second surface 102 on the back side. The semiconductor portion 100 comprises a heavily n-doped drain contact structure 137 formed by a substrate portion thicker than 20 μm, and an epitaxial portion comprising, among other things, a drift region 131 and a field stop layer 135 sandwiched between the drift region 131 and the drain contact structure 137. The lightly doped drift region portion 131a may separate the n-doped first region 181 and the p-type second region 182 of the super junction structure 180 from the field stop layer 135.

[0070] exist Figure 4C , the first vertical net dopant profile 421 shows the net dopant concentration N as a function of the vertical distance d from the superjunction structure 180 of the comparison device 509. nIII (y) The net dopant profile 421 includes a highly doped portion in the drain contact structure 137 .

[0071] exist Figure 4C , hole distribution 425 shows the hole density N as a function of the vertical distance y from the super junction structure 180. hIII (y) When the body diode of the comparative device 509 is forward biased, the hole distribution 425 drops significantly only within the heavily doped drain contact structure 137 and has relatively high levels in the super junction structure 180 and between the super junction structure 180 and the drain contact structure 137 .

[0072] exist Figure 4B In the semiconductor device 500, the bottom substrate is completely removed, and the metal drain electrode 320 is directly adjacent to the emitter layer 139 formed by implantation in a portion of the epitaxial layer. As defined in equation (1), the integrated dopant concentration along the shortest line 322 between the outermost spike and the bottom of the p-type second region 182 of the superjunction structure 180 is at most 1.5E13 cm -2 .

[0073] (1)

[0074] exist Figure 4C , the second vertical net dopant profile 422 is shown as Figure 4B The net dopant concentration N of the superjunction structure 180 of the semiconductor device 500 as a function of the vertical distance y nIV (y).

[0075] The corresponding hole distribution 426 shows the corresponding hole density N as a function of the vertical distance y from the super junction structure 180. hIV (y). Figure 4B When the body diode of the semiconductor device 500 is forward biased, the hole distribution 426 in the metal drain electrode 320 is equal to 0 and drops to zero in the epitaxial layer, equal to 0.

[0076] The shaded area indicates the difference between the hole density in the conventional device 509 and the hole density in the semiconductor device 500 according to the embodiment, and is a measure of the reduction in hole plasma and reverse recovery charge.

[0077] exist Figure 5A , the first distribution 431 shows the gate resistance R g Reverse recovery charge Q of a device with a semiconductor die thickness of 220 μm at different values ​​of rrThe second distribution 432 shows an equivalent distribution for a comparative semiconductor device having a total thickness of 90 μm, wherein the bottom substrate is thinned by 130 μm. The thinning results in a reduction in reverse recovery charge to approximately 30%. The reduction indicates a significantly reduced charge carrier plasma density in a portion of the semiconductor die outside the bottom substrate. The effect applies to a metal drain electrode including a gold tin layer (AuSn) and a diffusion soldered die attach process and a nickel silver (NiAg) metal drain electrode in conjunction with a soft solder die attach process.

[0078] exist Figure 5B In the figure, line 433 plots the reverse recovery charge Q of the semiconductor device. rr The reverse recovery charge decreases sharply shortly before the bottom substrate is completely removed at x=x0.

[0079] exist Figure 5C , line 436 shows the on-state resistance R as a function of the thickness of the semiconductor die. dson Thinning the bottom substrate by 10 μm with a remaining thickness of more than 20 μm only has an effect on R dson With low impact, removal of additional portions of the bottom substrate will R dson Reduced by more than 5%.

[0080] Figure 5D Summarize the effect of the thickness of the bottom substrate on the reverse recovery charge. In the diode operation mode of the semiconductor device, the electron-hole plasma maps the drift region down to the bottom substrate. In the doped bottom substrate, the plasma concentration decreases and is fixed to "zero concentration" at a distance from the interface between the bottom substrate and the epitaxial layer in the range of several μm. Thinning the semiconductor device to this range (over which the plasma concentration is usually reduced in the bottom substrate 105) reduces the plasma concentration at the interface between the bottom substrate and the epitaxial layer, causing holes to begin to reach the metal drain electrode, where recombination occurs, so that the emitter efficiency is reduced and the plasma concentration in the entire device is reduced. If the bottom substrate is completely removed, the charge carrier plasma density is fixed to zero in the epitaxial layer.

[0081] Figures 6A to 9B The above method is applied to an enhancement-type power semiconductor device, such as an n-channel IGFET 505, e.g., a MOSFET (metal oxide semiconductor field effect transistor), having an n-type source region, an n-type drain structure, and a p-type body region. Similar considerations apply to a p-FET having a p-type source region, a p-type drain structure, and an n-type body region. IGFET 505 can have a nominal drain current I greater than 1 A (e.g., greater than 10 A or greater than 100 A).D .

[0082] exist Fig. 6A and 6B In FIG. 5 , the power semiconductor device is an IGFET 505 without a superjunction structure, in which a thinning process (such as wafer separation or wafer grinding) has completely removed the bottom substrate during manufacturing.

[0083] Crystalline semiconductor materials (e.g., silicon (Si), germanium (Ge), silicon germanium (SiGe), or A III B V 1 . A semiconductor portion 100 is formed of a semiconductor material (e.g., a planar first surface 101) having a planar second surface 102 at the back side of the semiconductor portion 100. The minimum distance between the first and second surfaces 101, 102 defines the thickness th and is related to the voltage blocking capability specified for the semiconductor device 500. For example, in the case where the IGFET 505 is specified for a blocking voltage of approximately 500 V, the die thickness th may be in the range from 40 μm to 60 μm. Other IGFETs with higher blocking capabilities may be based on semiconductor portions 100 having a die thickness th of several hundred μm.

[0084] The semiconductor portion 100 may have a rectangular shape with an edge length in the range of several millimeters or a circular shape with a diameter of several centimeters in a plane parallel to the first surface 101. A direction parallel to the first surface 101 is a horizontal direction, and a direction perpendicular to the first surface 101 is a vertical direction.

[0085] The IGFET 505 comprises transistor cells TC formed on the front side of the semiconductor portion 100. Each transistor cell TC comprises an n-type source region and a body region, the body region being formed as part of a body well 120a extending from the first surface 101 into the semiconductor portion 100. The body well 120a forms a first pn junction pn1 with a drain structure 130 between the transistor cell TC and the second surface 102. The body region separates the source region of the transistor cell TC from the drain structure 130. The source region and the body region of the transistor cell TC form a second pn junction and are both connected to a metal source electrode 310. The source electrode 310 may form a source terminal S or may be electrically connected to the source terminal S.

[0086] The gate electrode of transistor cell TC may be electrically connected or coupled to gate terminal G and capacitively coupled to the bulk region in body well 120a through the gate dielectric. Subject to a voltage applied to gate terminal G, an inversion channel is formed in the bulk region and allows electrons to flow through transistor cell TC, so that in the on-state of IGFET 505, the electrons pass through transistor cell TC into drain structure 130.

[0087] The transistor cell TC can be a planar cell having a lateral gate structure arranged outside the outline of the semiconductor portion 100 or a trench cell having a trench gate structure extending from the first surface 101 into the semiconductor portion 100, wherein the source region and the body region of the transistor cell TC can be formed in the mesa portion of the semiconductor portion 100 between the trench gate structures.

[0088] The drain structure 130 includes a heavily doped emitter layer 139 directly adjacent to the second surface 102. The emitter layer 139 forms a low-ohmic interface with a metal drain electrode 320 formed along the second surface 102. For example, the formation of the metal drain electrode 320 may include partially amorphizing a portion of the silicon crystal along the second surface 102 and depositing aluminum, wherein silicon atoms diffuse to some extent into the deposited aluminum layer, and the aluminum atoms fill the resulting voids in the semiconductor crystal caused by the outdiffusion of silicon to form a protrusion or spike extending outwardly by several hundred nanometers or micrometers in the semiconductor portion 100. The drain structure 130 may also include a lightly doped drift region 131 of uniform conductivity. The effective dopant concentration in the drift region 131 may be at least 1E12cm -3 and at most 1E17 cm -3 .

[0089] The doping in the drift region 131 may correspond to an initial background doping of an epitaxial layer used to form the semiconductor portion 100. A field stop layer 135 may be sandwiched between the emitter layer 139 and the drift region 131. The average dopant concentration in the field stop layer 135 is at least 5 times the average dopant concentration in the drift region 131 and is at most half the maximum dopant concentration in the emitter layer 139. The dopant concentration in the field stop layer 135 may steadily decrease with increasing distance from the second surface 102, or may be uniform. According to other embodiments, the average dopant concentration in the field stop layer 135 decreases stepwise with increasing distance from the second surface 102.

[0090] The thickness of the emitter layer 139 may be less than 10 μm. The thickness a2-a0 of the field stop layer 135 may be in the range from 5 μm to 20 μm, for example between 8 μm and 15 μm. The integrated activated donor concentration N between x=0 and x=a1 D Less than 1.5E13cm -2 , for example, up to 8E12 cm -2 .

[0091] Figure 6B The donor distribution 441 and the acceptor distribution 442 along a line perpendicular to the first surface 101 are shown. The hole distribution 443 is fixed to 0 at the interface with the drain electrode 320 so that the reverse recovery charge Qrr At the same time, the effective implantation dose is high enough to form a strong emitter with sufficient radiation intensity.

[0092] Figures 7A to 7B IGFET 505 also includes superjunction structure 180, which includes a first region 181 of the conductivity type of source region and emitter layer 139 and a second region 182 of complementary conductivity type. The average dopant concentration in the superjunction structure is 1E15 cm -3 to 1E18 cm -3 The integrated concentration of activated donors between the drain electrode 320 and the second region 182 is at most 1.5E13 cm -2 , for example, up to 8E12 cm -2 .

[0093] Figure 7B The donor distribution 451 , acceptor distribution 452 , and hole distribution 453 are shown when the body diode is forward biased.

[0094] Figures 8A to 8B The IGFET 505 is Figures 6A to 6B IGFET 505 in FIG. 1 differs in that the remaining portion of the heavily doped bottom substrate forms a drain contact structure 137 sandwiched between drift region 131 and drain electrode 320 or, in the case of a field stop layer 135, between field stop layer 135 and metallic drain electrode 320. Drain contact structure 137 may have a thickness a0 of at most 10 μm, e.g., at most 5 μm. The average dopant concentration in drain contact structure 137 is at least 1E19 cm -3 , and is high enough to form an ohmic contact with the metal of the metal drain electrode 320.

[0095] Figure 8B It is shown that the donor distribution 461 is approximately uniform between x=0 and x=a0 in the drain contact structure 137. The hole distribution 463 in the case of a forward biased body diode is fixed to zero between x=0 and x=a0, where a0 is smaller than the distance at which the hole distribution 463 would be fixed to zero in the case of a thicker drain contact structure 137.

[0096] Figures 9A to 9B It concerns an IGFET 505 comprising a superjunction structure 180 , in which a remaining bottom portion 105a of the bottom substrate forms a drain contact structure 137 .

[0097] according to Fig. 9B, the donor distribution 471 is approximately uniform in the drain contact structure 137 between x=0 and x=a0. The hole distribution 473 in the case of a forward biased body diode is fixed to zero between x=0 and x=a0, where a0 is less than the distance at which the hole distribution 473 would be fixed to zero in the case of a thicker drain contact structure 137.

[0098] Although specific embodiments have been illustrated and described herein, it will be appreciated by those of ordinary skill in the art that various alternative and / or equivalent implementations may replace the specific embodiments shown and described without departing from the scope of the present invention. The present application is intended to include any modifications or variations of the specific embodiments discussed herein. Therefore, it is intended that the present invention be limited only by the claims and their equivalents.

Claims

1. A semiconductor device, comprising: a transistor cell formed on the front side of the semiconductor body along the first surface and comprising a body region of a first conductivity type; a drift region of a second conductivity type opposite to the first conductivity type, disposed between the body region and a second surface of the semiconductor body opposite to the first surface; and an emitter layer of a second conductivity type disposed between the drift region and the second surface of the semiconductor body, the emitter layer having a higher dopant concentration than the drift region; A metal drain electrode directly adjacent to the emitter layer, The metal drain electrode comprises spikes extending into the emitter layer, wherein at least two of the spikes have different heights.

2. The semiconductor device according to claim 1, wherein The integrated concentration of the activated dopant along the shortest line between the metal drain electrode and the nearest doped region of the first conductivity type is at most 1E13 cm -2 .

3. The semiconductor device according to claim 2, wherein: The shortest line extends through the emitter layer and the drift region.

4. The semiconductor device according to claim 2, further comprising: A super junction structure includes a first region with a second conductivity type and a second region with a first conductivity type, wherein the first and second regions of the super junction structure alternate along a horizontal direction parallel to a first surface in a drift region, wherein the most recently doped region of the first conductivity type is the second region of the super junction structure.

5. The semiconductor device according to claim 1, wherein Along the interface between the metal drain electrode and the emitter layer, an activated dopant concentration of the emitter layer allows carrier tunneling of electrons and holes between the metal drain electrode and the emitter layer.

6. The semiconductor device according to claim 1, wherein At least two of the peaks have different heights.

7. The semiconductor device according to claim 1, wherein The maximum vertical extension of the peak is greater than 1 μm. 8 . The semiconductor device according to claim 1 , further comprising a field stop layer of the first conductivity type disposed between the drift region and the emitter layer, wherein the field stop layer has a higher dopant concentration than a drain region and a lower dopant concentration than an emitter layer.

9. The semiconductor device according to claim 1, wherein: The thickness of the emitter layer is at most 10 μm.

10. The semiconductor device according to claim 8, wherein The field stop layer has a thickness between 5 μm and 20 μm.

11. The semiconductor device according to claim 1, wherein The average dopant concentration in the emitter layer is at least 1E19 cm -3 .

12. A semiconductor device comprising A transistor cell is formed on the front side of the semiconductor part (100) along the first surface (101); a drain structure (130) located between the transistor cell and a second surface (102) of the semiconductor portion (100) opposite the first surface (101), wherein the drain structure (130) forms a first pn junction with a body region (120) of the transistor cell and comprises a uniformly doped remaining bottom portion (105a) directly adjoining the second surface (102), wherein the vertical extension of the remaining bottom portion (105a) is at most 20 μm; and a metal drain electrode (320) directly adjacent to the remaining bottom portion (105a); The metal drain electrode (320) comprises peaks (321) extending into the drain structure (130) directly adjacent to the second surface (102), wherein at least two of the peaks have different heights.

Images