Electronic circuit and corresponding method for testing an electronic circuit

Abstract

A combinational circuit block has input pins configured to receive input digital signals and output pins configured to provide output digital signals in accordance with the received input digital signals. A test input pin receives a test input signal. A test output pin provides a test output signal in accordance with the received test input signal. A set of scan registers is selectively coupled to the combinational circuit block or to each other so as to form a scan chain of scan registers serially coupled between the test input pin and the test output pin. The scan registers in the set of scan registers are clocked by a clock signal. At least one input register is coupled between the test input pin and a first scan register of the scan chain. At least one input register is clocked by an inverted copy of the clock signal.

Description

[0001] Priority Claim

[0002] This application claims the benefit of priority of Italian Patent Application No. 102020000001636, filed on January 28, 2020, the content of which is incorporated herein by reference in its entirety to the maximum extent permitted by law. Field of the Invention

[0003] This specification relates to the testing of digital electronic circuits.

[0004] One or more embodiments may be applied to digital electronic circuits adapted to be tested by an Automatic Test Pattern Generation (ATPG) method. Background Art

[0005] Digital circuits may be used to implement logic functions in, for example, mixed-signal devices.

[0006] Such digital circuits may typically be tested by an Automatic Test Pattern Generation (ATPG) method, Transition Fault (TF) testing, and Power Supply Static Current (IDDQ) testing.

[0007] The target fault coverage of these tests may be determined depending on the application (for example, for automotive-grade products, a high fault coverage may be desired).

[0008] In the case of the ATPG test method, achieving the desired fault coverage may include injecting one or more rather long scan sequences at one or more test input pins of the circuit under test. The length of the (one or more) scan sequences may depend on the number of registers (e.g., flip-flops) in the circuit under test. For example, a scan test may rely on a scan sequence including 10 million values (bits) to be sequentially injected at one or more test input pins of the Device Under Test (DUT).

[0009] Traditionally, the ATPG shift clock frequency of the scan registers in the scan path may be set to a value lower than 20 MHz, for example, approximately 10 MHz. Thus, performing a scan test including an input sequence of 10 million values at 10 MHz may take approximately one second to complete.

[0010] In addition, TF testing may also take approximately one second to perform, and IDDQ testing may take approximately 100 milliseconds to perform. As a result, the test time for a single digital circuit in an electronic device (e.g., a mixed-signal device for automotive use) may be longer than two seconds.

[0011] There is a need in the art to reduce the test time of digital circuits. Summary of the Invention

[0012] In an embodiment, reducing test time is facilitated by increasing the ATPG shift clock frequency (“scan frequency”) of a digital circuit. For example, one or more embodiments are directed to performing an ATPG test (e.g., a scan test) at a frequency of 40 MHz or higher.

[0013] According to one or more embodiments, an electronic circuit (e.g., a digital circuit) is provided.

[0014] One or more embodiments may relate to a corresponding method of testing an electronic circuit.

[0015] According to one or more embodiments, an electronic circuit is provided. As is conventional in the art, the electronic circuit may include a combinational circuit block having: a set of input pins configured to receive input digital signals; and a set of output pins configured to provide output digital signals in accordance with the received input digital signals. The circuit may also include: test input pins configured to receive test input signals; and test output pins configured to provide test output signals in accordance with the received test input signals. Additionally, the circuit may include a set of scan registers selectively coupled to the combinational circuit block or to each other to form a scan chain of scan registers serially coupled between the test input pins and the test output pins, the scan registers in the set being sensitive to a clock signal.

[0016] Advantageously, compared to the prior art, the circuit may include at least one input register coupled between the test input pins and a first scan register of the scan chain, the at least one input register being sensitive to an inverted copy of the clock signal received at the scan registers. Thus, the scan registers in the set may be active on one of the rising or falling edges of the clock signal provided to them, while the at least one input register may be active on the other of the rising or falling edges of the clock signal. BRIEF DESCRIPTION OF THE DRAWINGS

[0017] One or more embodiments will now be described, by way of example only, with reference to the accompanying drawings, in which:

[0018] Figure 1 is an exemplary circuit diagram of a digital circuit suitable for ATPG scan testing,

[0019] Figure 2 is an exemplary circuit diagram of a digital circuit suitable for ATPG scan testing according to one or more embodiments,

[0020] Figure 3A and Figure 3B are examples of possible waveforms of a clock signal in one or more embodiments, and

[0021] Figure 4A and Figure 4B are exemplary shmoo plots of possible results of a scan test in one or more embodiments. DETAILED DESCRIPTION

[0022] In the following description, one or more specific details are set forth in order to provide an in - depth understanding of examples of embodiments of this specification. Embodiments may be obtained without one or more specific details, or by using other methods, components, materials, etc. In other instances, well - known structures, materials, or operations are not shown or described in detail so as not to obscure certain aspects of the embodiments.

[0023] References to "an embodiment" or "one embodiment" within the scope of this specification are intended to indicate that a particular configuration, structure, or characteristic described with respect to the embodiment is included in at least one embodiment. Thus, phrases such as "in an embodiment" or "in one embodiment" that may occur in one or more places in this specification do not necessarily refer to the same embodiment. Moreover, in one or more embodiments, specific configurations, structures, or characteristics may be combined in any suitable manner.

[0024] In all the attached drawings herein, the same components or elements are denoted by the same reference numerals / numbers, and for the sake of brevity, the corresponding descriptions will not be repeated.

[0025] The reference numerals used herein are provided for convenience only and thus do not limit the scope or extent of protection of the embodiments.

[0026] By way of introduction to a detailed description of exemplary embodiments, reference may first be made to Figure 1 , which is an exemplary circuit diagram of a digital circuit 10 suitable for ATPG scan testing.

[0027] As is conventional in the art, the digital circuit 10 may include a combinational circuit 100 and clock - controlled memory elements (e.g., registers such as flip - flops) coupled to the combinational circuit 100 in order to implement certain logic functions. The logic functions implemented by the combinational circuit 100 and the associated registers transform input signals received at the input nodes IN1,..., INn of the digital circuit 10 into output signals available at the output nodes OUT1,..., OUTm of the digital circuit 10. The number n of input nodes and the number m of output nodes may depend on the number and type of logic functions implemented by the combinational circuit 100.

[0028] As Figure 1As illustrated, in the case where the digital circuit 10 is designed for automatic test pattern generation (ATPG) scan testing, the clock-controlled memory elements may include scan registers (e.g., scan flip-flops) SR1, SR2, SR3. Each scan register may include a corresponding register element (e.g., flip-flop) R1, R2, R3 driven by a clock signal CLK. Each register may couple its input node D to the output of a corresponding multiplexer circuit M1, M2, M3 such that each scan register may receive input data from two alternative sources depending on the value of a scan enable signal SE that controls the multiplexer circuits M1, M2, M3.

[0029] During normal operation of the digital circuit 10, the scan enable signal SE may be set to a first logic value (e.g., 0) such that the registers R1, R2, R3 are coupled to the combinational circuit 100 to perform a desired logic function.

[0030] During test mode operation of the digital circuit 10, by setting the scan enable signal SE to a second logic value (e.g., 1), the registers R1, R2, R3 may be serially coupled in a so-called scan chain, where each register directly receives input data from the output Q of the previous register in the scan chain. In a test configuration, the first scan register SR1 of the scan chain receives input data from a dedicated test input pin SCAN_IN, and the last scan register SR3 of the scan chain provides output data to a dedicated test output pin SCAN_OUT.

[0031] As is conventional in the art, scan testing may thus be performed by the following steps:

[0032] - Set the scan enable signal SE = 1 and insert (“shift in” or “load”) a test vector in the scan chain through the SCAN_IN pin of the digital circuit 10, the SCAN_IN pin being coupled to the input of the first scan register SR1 of the scan chain;

[0033] - After the entire test vector has been loaded in the scan chain (which may involve a number of clock cycles equal to the number of registers in the chain), set the scan enable signal SE = 0, apply test input values at the input nodes IN1,..., INn and apply one clock pulse to the digital circuit 10, thereby updating the values stored in the registers R1, R2, R3 according to the logic function implemented by the combinational circuit 100; and

[0034] - Set the scan enable signal SE = 1 again and extract ("shift out") the result vector from the scan chain via the SCAN_OUT pin of the digital circuit 10 and read the values of the signals provided at the output nodes OUT1, ..., OUTm. The SCAN_OUT pin is coupled to the output of the last scan register SR3 of the scan chain.

[0035] When the result vector is shifted out of the scan chain, successive input test vectors can be shifted in.

[0036] It should be understood that, for clarity only, the clock-controlled memory elements are shown as separate elements from the combinational circuit 100. In an actual implementation of the digital circuit 10, the memory elements may be within the same silicon region of the combinational circuit 100.

[0037] It will be understood that, for clarity and ease of illustration only, Figure 1 The digital circuit 10 including three scan registers SR1, SR2, SR3 is illustrated. In one or more embodiments, the digital circuit 10 may include dozens, hundreds, or even more scan registers.

[0038] In one or more embodiments, the scan registers may be configured to be divided into multiple independent scan chains that run the scan test in parallel, each scan chain having its own SCAN_IN pin and SCAN_OUT pin. According to one or more embodiments, appropriate design techniques may be used to reduce the number of input pins SCAN_IN (i.e., the number of input pins SCAN_IN may be lower than the number of scan chains in the circuit), while the number of SCAN_OUT pins may be equal to the number of scan chains.

[0039] Preferably, the scan chains may include a similar number of scan registers (e.g., in the case where there are two scan chains, approximately half of the scan registers may be connected in the first scan chain and the remaining scan registers may be connected in the second scan chain). Providing scan chains of similar length (e.g., including a similar number of scan registers) may improve the parallelization of the scan test, thereby reducing the test time and increasing the efficiency of the test process.

[0040] To perform a complete scan test, multiple test vectors may be provided sequentially at the (one or more) SCAN_IN pins.

[0041] As is conventional in the art, all the scan registers SR1, SR2, SR3 in the scan chain are configured to receive the same clock signal CLK. The scan registers SR1, SR2, SR3 may capture the input values at a determined portion of the clock cycle, typically at the rising edge of the clock signal CLK.

[0042] Figure 1The circuits illustrated in may provide unsatisfactory test performance in a range where the scan frequency that can be used to run a scan test may be limited. Such frequency limitations may be due to the (one or more) propagation delays of signals in the scan chains of registers R1, R2, R3 (i.e., in the internal pipeline registers) and / or the delays of the clock signals received at registers R1, R2, R3. For example, the clock network delays of registers R1, R2, R3 can typically be about 10 ns.

[0043] As Figure 2 One or more embodiments illustrated in may facilitate an increase in the scan frequency during testing.

[0044] As Figure 2 Illustrated in, digital circuit 10' may include at least one additional "head" register (e.g., flip-flop) that is coupled at the start (e.g., input) of the scan chains of registers SR1, SR2, SR3.

[0045] In a preferred embodiment, as Figure 2 Illustrated in, digital circuit 10' may include a pair of head registers H1, H2 coupled at the input of the scan chain. The input of the first head register H1 may be coupled to the SCAN_IN pin of digital circuit 10' to receive the (one or more) scan sequences during the scan test phase. The input of the second head register H2 may be coupled to the output of the first head register H1. The output of the second head register H2 may be coupled to the test input of the first scan register SR1 of the scan chain (i.e., the input selected when SE = 1, i.e., when the test mode is enabled).

[0046] It should be noted that implementing two head registers H1, H2 may be more preferred than implementing a single head register, provided that this can result in an improved digital layout implementation. In particular, providing a pair of head registers H1, H2 may facilitate controlling the timing margin in the clock tree network.

[0047] In one or more embodiments, the (one or more) head registers H1, H2 may be configured to receive an inverted copy of the clock signal CLK The inverted copy is applied to the scan registers SR1, SR2, SR3. This can be obtained by providing an inverter gate 20 between the input pin CLK of digital circuit 10' and the (one or more) clock inputs of the (one or more) head registers H1, H2. Thus, compared to the scan registers SR1, SR2, SR3, the (one or more) head registers H1, H2 may capture the input values at different parts of the cycle of the clock signal CLK (e.g., the (one or more) head registers H1, H2 may capture the value at the falling edge of the clock signal CLK).

[0048] In one or more embodiments, providing at least one head register H1 / H2 driven by an inverted clock signal can facilitate increasing the timing setup margin such that the test shift clock can run faster than in known solutions.

[0049] Additionally, the digital circuit 10' may include at least one additional "tail" register (e.g., a flip-flop) coupled at the end (e.g., at the output) of the scan chains of registers SR1, SR2, SR3.

[0050] In a preferred embodiment, as Figure 2 illustrated, the digital circuit 10' may include a pair of tail registers T1, T2 coupled at the output of the scan chain. The input of the first tail register T1 may be coupled to the output of the last scan register SR3 of the scan chain. The input of the second tail register T2 may be coupled to the output of the first tail register T1. The output of the second tail register T2 may be coupled to the SCAN_OUT pin of the digital circuit 10' to provide an output scan sequence during the scan test phase.

[0051] In one or more embodiments, the tail register(s) T1, T2 may be configured to receive the same clock signal CLK applied to the scan registers SR1, SR2, SR3. Thus, the tail register(s) T1, T2 may capture the value of the input at the same part of the cycle of the clock signal CLK as the scan registers SR1, SR2, SR3 (e.g., the tail register(s) T1, T2 may capture the value at the rising edge of the clock signal CLK).

[0052] In one or more embodiments, providing at least one tail register T1 / T2 driven by the clock signal CLK can facilitate increasing the timing setup margin such that the test shift clock can run faster than in known solutions.

[0053] Thus, in one or more embodiments, the binary values of the input test sequence may be shifted into the scan chain (at register H1) at the falling edge of the clock signal CLK, while the scan registers SR1, SR2, SR3 and the tail register(s) T1, T2 may operate at the rising edge of the clock signal CLK (e.g., may capture the value of the corresponding input signal). As a result, one or more embodiments may provide additional time margin to account for possible delays within the scan chain ("pipeline") and / or possible delays due to parasitic effects on the test board (e.g., parasitic capacitance at the SCAN_OUT pin).

[0054] Accordingly, one or more embodiments may include coupling pipeline registers H1, H2 (e.g., two registers in series) between the SCAN_IN pin and the input of the first scan register SR1 of the scan chain, and coupling pipeline registers T1, T2 (e.g., two registers in series) between the output of the last scan register SR3 of the scan chain and the SCAN_OUT pin, where the pipeline registers H1, H2 are driven by an inverted copy of the clock signal CLK This can provide more margin for input delay or other (propagation) delays, and thus can facilitate an increase in the shift clock frequency.

[0055] As a result, the execution speed of scan testing and / or transition fault testing can be increased (e.g., the scan frequency can be doubled), thereby reducing (e.g., dividing by 2) the test time required to provide a specific target fault coverage for a logic IP (“intellectual property block” or “intellectual property core”).

[0056] In one or more embodiments, the shift clock signal CLK may include a “pulse” at the end portion of its cycle. The duration of such a pulse can (also) depend on the characteristics of the automatic test equipment (ATE) used for scan testing. In particular, the pulse duration can be set to the minimum width of the ATE test / design. For example, a “zeroed” clock signal of 40 MHz can have a full cycle of 20 ns and a high pulse lasting 9 ns. Thus, the previous low-to-high plus high-to-low can become less than 9 ns, which may result in a signal with (very) high bandwidth.

[0057] For example, Figure 3A and Figure 3B are examples of possible waveforms of the clock signal CLK in one or more embodiments.

[0058] Figure 3A is an example of a clock signal CLK having a cycle of approximately 30 ns (1 ns = 10 -9 s), corresponding to a shift frequency of approximately 33 MHz. The clock signal is low (e.g., 0) between 0 ns and 20 ns, high (e.g., 1) between 20 ns and 29 ns, and then returns to zero between 29 ns and 30 ns.

[0059] As Figure 3A illustrated, the scan input (scanIn) data setup time requirement can be calculated as:

[0060] Clock falling edge + internal clock network delay = 29 ns + 10 ns = 39 ns

[0061] As Figure 3A illustrated, the scan output (scanOut) IO timing setup margin can be calculated as:

[0062] T 移位 –Internal clock delay = 30 ns – 10 ns = 20 ns

[0063] By controlling the tail registers T1, T2 to have a smaller clock network delay, e.g., 5 ns, the setup margin of the scan output (scanOut) IO timing can be increased to:

[0064] T 移位 –Internal clock delay = 30 ns – 5 ns = 25 ns

[0065] Figure 3B is an example of a clock signal CLK having a period of approximately 20 ns (1 ns = 10 -9 s), corresponding to a shift frequency of approximately 50 MHz. The clock signal is low (e.g., 0) between 0 ns and 10 ns, high (e.g., 1) between 10 ns and 19 ns, and then returns to zero between 19 ns and 20 ns.

[0066] In one or more embodiments, the clock signal CLK can thus be a "return-to-zero" clock signal.

[0067] Figure 4A and Figure 4B is an example of a Shmoo plot of possible results of a scan test in one or more embodiments, where a value equal to 0 indicates a successful test and a value other than 0 indicates an unsuccessful test.

[0068] The circuit under test is supplied with a voltage of 3.3 V. A Shmoo plot is obtained by scanning the test frequency (i.e., the scan frequency) from 1 MHz to 50 MHz in steps of 2 MHz and by changing the minimum output high voltage Voh (i.e., the minimum value, above which the output signal SCAN_OUT is considered to represent a logic one) in steps of 0.2 V between 1.2 V and 3.0 V. Figure 4A is an example of a test performed on an ATE board having a 26 pF parasitic capacitance at the SCAN_OUT pin. Figure 4B is an example of a test performed on an ATE board having a 43 pF parasitic capacitance at the SCAN_OUT pin.

[0069] As Figure 4A illustrated, one or more embodiments can facilitate correctly performing a test of the digital circuit 10' at scan frequencies up to 50 MHz or possibly higher.

[0070] As illustrated herein, an electronic circuit (e.g., 10') may include: a combinational circuit block (e.g., 100) having a set of input pins (e.g., IN1, ..., INn) configured to receive input digital signals and a set of output pins (e.g., OUT1, ..., OUTm) configured to provide output digital signals based on the received input digital signals; a test input pin (e.g., SCAN_IN) configured to receive a test input signal, and a test output pin (e.g., SCAN_OUT) configured to provide a test output signal based on the received test input signal; a set of scan registers (e.g., SR1, SR2, SR3), wherein the scan registers in the set of scan registers are selectively (e.g., SE) coupled (e.g., M1, M2, M3) to the combinational circuit block or to each other to form a scan chain of scan registers serially coupled between the test input pin and the test output pin, the scan registers in the set of scan registers being sensitive to a clock signal (e.g., CLK); and at least one input register (e.g., H1, H2) coupled between the test input pin and a first scan register (e.g., SR1) of the scan chain, wherein the at least one input register is sensitive to an inverted copy (e.g., 20) of the clock signal.

[0071] As illustrated herein, the scan registers in the set of scan registers may be active on one of the rising or falling edges of the clock signal provided thereto, and the at least one input register may be active on the other of the rising or falling edges of the clock signal.

[0072] As illustrated herein, the at least one input register may include a first input register (e.g., H1) and a second input register (e.g., H2) serially coupled between the test input pin and the first scan register of the scan chain. The first input register may be configured to receive test input data from the test input pin and propagate the test input data to the second input register, and the second input register may be configured to receive the test input data from the first input register and propagate the test input data to the first scan register of the scan chain.

[0073] As illustrated herein, the electronic circuit may include at least one output register (e.g., T1, T2) coupled between a last scan register (e.g., SR3) of the scan chain and the test output pin, wherein the at least one output register is sensitive to the clock signal.

[0074] As illustrated herein, at least one output register may include a first output register (e.g., T1) and a second output register (e.g., T2) serially coupled between a last scan register of a scan chain and a test output pin. The first output register may be configured to receive test output data from the last scan register of the scan chain and propagate the test output data to the second output register, and the second output register may be configured to receive the test output data from the first output register and propagate the test output data to the test output pin.

[0075] As illustrated herein, an electronic circuit may include a plurality of test input pins and a plurality of test output pins, the test input pins being configured to receive respective test input signals, and the test output pins being configured to provide respective test output signals in accordance with the received test input signals. Scan registers in the set of scan registers may be selectively coupled to each other to form a plurality of scan chains of scan registers serially coupled between the test input pins and the test output pins.

[0076] As illustrated herein, scan registers in the set of scan registers may be active on a rising edge of a clock signal, and at least one input register may be active on a falling edge of the clock signal.

[0077] As illustrated herein, a method of testing an electronic circuit may include: selectively coupling scan registers in the set of scan registers to each other to form a scan chain of scan registers serially coupled between a test input pin and a test output pin of the electronic circuit; providing a test input signal at the test input pin of the electronic circuit, wherein the test input signal includes a sequence of binary values to be shifted into the scan registers serially coupled between the test input pin and the test output pin, wherein the scan registers in the set of scan registers are active on one of a rising edge or a falling edge of a clock signal; sensing a test output signal at the test output pin of the electronic circuit, wherein the test output signal includes a sequence of binary values shifted out from the scan registers serially coupled between the test input pin and the test output pin; and operating at least one input register that is active on the other of the rising edge or the falling edge of the clock signal.

[0078] Without prejudice to the basic principles, details and embodiments may vary even significantly with respect to what is described only by way of example, without departing from the scope of protection.

[0079] The scope of protection is defined by the appended claims.

[0080] The claims are an integral part of the technical teachings provided herein with respect to the embodiments.

Claims

1. An electronic circuit, comprising: A combinational circuit block having: a set of input pins configured to receive input digital signals; And a set of output pins configured to provide output digital signals based on the received input digital signals; A test input pin configured to receive a test input signal; A test output pin configured to provide a test output signal based on the test input signal; A set of scan registers, wherein the scan registers in the set of scan registers are selectively coupled to the combinational circuit block or to each other to form a scan chain of scan registers serially coupled between the test input pin and the test output pin, wherein the scan registers in the set of scan registers are clocked by a clock signal; And At least one input register coupled between the test input pin and a first scan register of the scan chain, wherein the at least one input register is clocked by an inverted copy of the clock signal.

2. The electronic circuit according to claim 1: Wherein the scan registers in the set of scan registers are valid on one of the rising edge or the falling edge of the clock signal; and Wherein the at least one input register is valid on the other of the rising edge or the falling edge of the clock signal.

3. The electronic circuit according to claim 1, wherein the at least one input register includes a first input register and a second input register serially coupled between the test input pin and the first scan register of the scan chain, wherein: The first input register is configured to receive test input data from the test input pin and propagate the test input data to the second input register; and The second input register is configured to receive the test input data from the first input register and propagate the test input data to the first scan register of the scan chain.

4. The electronic circuit according to claim 1, further comprising at least one output register coupled between a last scan register of the scan chain and the test output pin, wherein the at least one output register is clocked by the clock signal.

5. The electronic circuit according to claim 4, wherein the at least one output register includes a first output register and a second output register serially coupled between the last scan register of the scan chain and the test output pin, wherein: The first output register is configured to receive test output data from the last scan register of the scan chain and propagate the test output data to the second output register; and The second output register is configured to receive the test output data from the first output register and propagate the test output data to the test output pin.

6. The electronic circuit according to claim 1 further comprises: A plurality of test input pins configured to receive respective test input signals; and a plurality of test output pins, configured to provide corresponding test output signals in accordance with the received test input signals, wherein the scan registers in the set of scan registers are selectively coupled to each other to form a plurality of scan chains of scan registers serially coupled between corresponding test input pins and test output pins.

7. The electronic circuit according to claim 1, wherein the scan registers in the set of scan registers are active on the rising edge of the clock signal, and the at least one input register is active on the falling edge of the clock signal.

8. A method of testing an electronic circuit, comprising: receiving a test input signal at a test input pin of the electronic circuit, wherein the test input signal comprises a sequence of binary values; shifting the received test input signal into at least one input register that is active on one of the rising edge or the falling edge of a clock signal; shifting the received test input signal from the at least one input register into a set of scan registers that are serially coupled to each other to form a scan chain, wherein the set of scan registers is active on the other of the rising edge or the falling edge of the clock signal; and sensing a test output signal at a test output pin of the electronic circuit, wherein the test output signal comprises a sequence of binary values shifted out from the set of scan registers forming the scan chain.

9. The method according to claim 8: wherein shifting the received test input signal from the at least one input register into the set of scan registers includes: clocking the set of scan registers with the clock signal; and wherein shifting the received test input signal into the at least one input register comprises: clocking the at least one input register with an inverted copy of the clock signal.

10. An electronic circuit, comprising: a combinational circuit block having: a set of input pins configured to receive input digital signals; and a set of output pins configured to provide output digital signals in accordance with the received input digital signals; a test input pin configured to receive a test input signal; a test output pin configured to provide a test output signal in accordance with the test input signal; a set of scan registers, wherein the scan registers in the set of scan registers are selectively coupled to the combinational circuit block or to each other to form a scan chain of scan registers serially coupled between the test input pin and the test output pin; at least one input register coupled between the test input pin and a first scan register of the scan chain; wherein the scan registers in the set of scan registers are active on one of the rising edge or the falling edge of a clock signal; and wherein the at least one input register is active on the other of the rising edge or the falling edge of the clock signal.

11. The electronic circuit according to claim 10, wherein the at least one input register comprises a first input register and a second input register serially coupled between the test input pin and the first scan register of the scan chain, wherein: The first input register is configured to receive test input data from the test input pin and propagate the test input data to the second input register; and The second input register is configured to receive the test input data from the first input register and propagate the test input data to the first scan register of the scan chain.

12. The electronic circuit according to claim 10, further comprising at least one output register, the output register being coupled between the last scan register of the scan chain and the test output pin, wherein the at least one output register is valid on one of the rising edge or the falling edge of the clock signal.

13. The electronic circuit according to claim 12, wherein the at least one output register includes a first output register and a second output register serially coupled between the last scan register of the scan chain and the test output pin, wherein: The first output register is configured to receive test output data from the last scan register of the scan chain and propagate the test output data to the second output register; and The second output register is configured to receive the test output data from the first output register and propagate the test output data to the test output pin.

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