Array substrate, display panel and electronic device with double-gate structure

Abstract

The present disclosure provides an array substrate, a display panel, and an electronic device with a double-gate structure. The array substrate includes: a plurality of gate lines and a plurality of data lines. Two columns of sub-pixel regions are provided between two adjacent data lines, and two gate lines are provided between two adjacent rows of sub-pixel regions; the sum of the first capacitor and the second capacitor of each sub-pixel region in each pixel group in the array substrate is the same. The present disclosure adjusts the relevant structures of each sub-pixel region in each pixel group in the array substrate to make the sum of the first capacitor and the second capacitor corresponding to all sub-pixel regions in the pixel group the same, thereby ensuring that the degree of pixel voltage fluctuation caused by the jump voltage of the gate line in the sub-pixel region is the same, making the brightness changes of all sub-pixel regions the same, avoiding the generation of moiré patterns, achieving a better display effect, and improving the user experience.

Description

Technical Field

[0001] The present disclosure relates to the field of display technologies, and particularly to an array substrate, a display panel, and an electronic device having a dual-gate structure. Background Art

[0002] With the continuous upgrade of the ultra-high-definition video industry, 4K TVs have been basically popularized in the market, and the 8K TV market has also taken initial shape. However, due to the large number of data lines in 8K products, the number of Chip On Film (COF) is relatively large, resulting in an increase in panel costs. Moreover, the excessive number of COFs makes the design of packaging materials and the whole machine difficult. In the prior art, in order to reduce production costs, a thin-film transistor liquid crystal display (TFT-LCD) with a dual-gate structure is proposed. By increasing the number of gate lines and reducing the number of data lines, the number of COFs is reduced, and then the number of corresponding driving chips is reduced, so as to achieve the purpose of reducing production costs.

[0003] However, when the gate voltage jumps, it will affect the floating of the pixel voltage, resulting in differences in the brightness of each column of pixels at different polarities. When the user shakes their head to observe the display screen, it is easy to lose frames and appear head-shaking patterns, affecting the display effect of the screen and the user experience. Summary of the Invention

[0004] The purpose of the embodiments of the present disclosure is to provide an array substrate, a display panel, and an electronic device having a dual-gate structure, so as to solve the problem of easy generation of head-shaking patterns caused by gate voltage jumps in the prior art.

[0005] The embodiments of the present disclosure adopt the following technical solutions: An array substrate with a dual-gate structure at least includes: a plurality of gate lines, a plurality of data lines, two columns of sub-pixel regions are arranged between adjacent two data lines, and two gate lines are arranged between adjacent two rows of sub-pixel regions; the sum of the first capacitance and the second capacitance of each sub-pixel region in each pixel group in the array substrate is the same; wherein, the pixel group is a plurality of sub-pixel regions arranged in a 2×2 matrix array between adjacent two data lines; the first capacitance is the capacitance between the gate line part corresponding to each sub-pixel region and the source and drain electrodes of the sub-pixel region; the second capacitance is the capacitance between the gate line part corresponding to each sub-pixel region and the pixel electrode of the sub-pixel region.

[0006] In some embodiments, the overlapping area between the gate corresponding to at least one sub-pixel region in each pixel group and the source and drain electrodes of the sub-pixel region is different from the overlapping areas of the other sub-pixel regions in the pixel group.

[0007] In some embodiments, the width of the source-drain of at least one of the sub-pixel regions in each pixel group is different from the width of the source-drain of other sub-pixel regions in the pixel group; wherein, the width of the source-drain of the sub-pixel region is the width of the overlapping portion between the source-drain of the sub-pixel region and the gate of the sub-pixel region.

[0008] In some embodiments, in the pixel group, the sub-pixel region located in the first row and the first column of the matrix array is the first sub-pixel region, the sub-pixel region located in the first row and the second column is the second sub-pixel region, the sub-pixel region located in the second row and the first column is the third sub-pixel region, and the sub-pixel region located in the second row and the second column is the fourth sub-pixel region; the source-drain width of the fourth sub-pixel region is greater than the source-drain width of any other sub-pixel region in the pixel group, the source-drain width of the first sub-pixel region is greater than the source-drain widths of the second and third sub-pixel regions, and the source-drain width of the second sub-pixel region is greater than the source-drain width of the third sub-pixel region.

[0009] In some embodiments, the length of the source-drain of at least one of the sub-pixel regions in each pixel group is different from the length of the source-drain of other sub-pixel regions in the pixel group; wherein, the length of the source-drain of the sub-pixel region is the length of the overlapping portion between the source-drain of the sub-pixel region and the gate of the sub-pixel region.

[0010] In some embodiments, in the pixel group, the sub-pixel region located in the first row and the first column of the matrix array is the first sub-pixel region, the sub-pixel region located in the first row and the second column is the second sub-pixel region, the sub-pixel region located in the second row and the first column is the third sub-pixel region, and the sub-pixel region located in the second row and the second column is the fourth sub-pixel region; the source-drain length of the fourth sub-pixel region is greater than the source-drain length of any other sub-pixel region in the pixel group, the source-drain length of the first sub-pixel region is greater than the source-drain lengths of the second and third sub-pixel regions, and the source-drain length of the second sub-pixel region is greater than the source-drain length of the third sub-pixel region.

[0011] In some embodiments, the distance between the gate line portion of at least one of the sub-pixel regions in each pixel group and the edge of the pixel electrode on the side of the sub-pixel region close to the gate line is different from the distance of other sub-pixel regions in the pixel group.

[0012] In some embodiments, in the pixel group, the sub-pixel region located in the first row and the first column of the matrix array is the first sub-pixel region, the sub-pixel region located in the first row and the second column is the second sub-pixel region, the sub-pixel region located in the second row and the first column is the third sub-pixel region, and the sub-pixel region located in the second row and the second column is the fourth sub-pixel region; the distance of the third sub-pixel region is greater than the distance of any other sub-pixel region within the pixel group, the distance of the second sub-pixel region is greater than the distances of the first sub-pixel region and the fourth sub-pixel region, and the distance of the first sub-pixel region is greater than the distance of the fourth sub-pixel region.

[0013] In some embodiments, in each pixel group, at least one gate line of the sub-pixel region is provided with a groove structure on a side close to the pixel electrode of the sub-pixel region.

[0014] In some embodiments, the cross-section of the groove structure includes at least one of the following shapes: rectangle, semi-circle, and zigzag.

[0015] Embodiments of the present disclosure also provide a display panel, which at least includes an array substrate with the double-gate structure as described above.

[0016] Embodiments of the present disclosure also provide an electronic device, characterized in that the electronic device at least includes the display panel as described above.

[0017] The beneficial effects of the embodiments of the present disclosure are as follows: By adjusting the relevant structures of each sub-pixel region in each pixel group within the array substrate, the sum of the first capacitance and the second capacitance corresponding to all sub-pixel regions in the pixel group is made the same, thereby ensuring that the degree of pixel voltage fluctuation caused by the gate line jump voltage in the sub-pixel region is the same, making the brightness changes of all sub-pixel regions the same, avoiding the generation of moiré patterns, achieving a better display effect, and improving the user experience. Description of the Drawings

[0018] In order to more clearly illustrate the technical solutions in the embodiments of the present disclosure or the prior art, the following will briefly introduce the drawings required for use in the description of the embodiments or the prior art. Obviously, the drawings in the following description are only some embodiments recorded in the present disclosure. For those of ordinary skill in the art, other drawings can be obtained based on these drawings without creative efforts.

[0019] Figure 1 It is a partial setting schematic diagram of a double-gate structure array substrate in the prior art;

[0020] Figure 2 It is a schematic diagram of pixel voltage fluctuation in the first sub-pixel region in the prior art;

[0021] Figure 3 It is a schematic diagram of the connection of some pixels of an array substrate with a double-gate structure in the prior art;

[0022] Figure 4 It is a schematic diagram of the two brightness levels of pixels of an array substrate with a double-gate structure in the prior art;

[0023] Figure 5 It is a schematic diagram of a pixel group in the first embodiment of the present disclosure;

[0024] Figure 6 It is a schematic diagram of the adjustment of the source-drain width in the first embodiment of the present disclosure;

[0025] Figure 7 It is a schematic diagram of the adjustment of the source-drain length in the first embodiment of the present disclosure;

[0026] Figure 8 It is a schematic diagram of the adjustment of the gate line in the first embodiment of the present disclosure. Detailed implementation manners

[0027] Reference is made herein to the various schemes and features of the present disclosure with reference to the accompanying drawings.

[0028] It should be understood that various modifications can be made to the embodiments claimed herein. Therefore, the above description should not be construed as limiting, but merely as an example of the embodiments. Those skilled in the art will envision other modifications within the scope and spirit of the present disclosure.

[0029] The accompanying drawings, which are included in and constitute a part of this specification, illustrate embodiments of the present disclosure and, together with the general description of the present disclosure given above and the detailed description of the embodiments given below, serve to explain the principles of the present disclosure.

[0030] These and other features of the present disclosure will become apparent from the following description of the preferred forms of the embodiments, given by way of non-limiting example with reference to the accompanying drawings.

[0031] It should also be understood that, although the present disclosure has been described with reference to some specific examples, those skilled in the art can surely implement many other equivalent forms of the present disclosure, which have the features as claimed and thus are all within the protection scope defined hereby.

[0032] When combined with the accompanying drawings, in view of the following detailed description, the above and other aspects, features and advantages of the present disclosure will become more apparent.

[0033] Specific embodiments of the present disclosure are described hereinafter with reference to the accompanying drawings; however, it should be understood that the embodiments claimed are merely examples of the present disclosure, which may be implemented in a variety of ways. Well-known and / or repeated functions and structures are not described in detail to avoid obscuring the present disclosure with unnecessary or redundant details. Therefore, the specific structural and functional details claimed herein are not intended to be limiting, but merely serve as a basis and representative basis for the claims to teach those skilled in the art to use the present disclosure in a variety of ways with substantially any suitable detailed structure.

[0034] This specification may use the phrases "in one embodiment," "in another embodiment," "in a further embodiment," or "in other embodiments," all of which may refer to one or more of the same or different embodiments according to the present disclosure.

[0035] Figure 1 FIG. 1 shows a schematic diagram of a partial arrangement of a dual-gate structure array substrate in the prior art. Figure 1 Analyze the pixel structure in the first sub-pixel area ( Figure 1 For pixel 1 in the first row and first column, the gate of its TFT is connected to gate line 1 (G1), its source and drain are connected to data line 1 (D1), and its drain is connected to its own pixel electrode. When displaying, G1 controls Pixel 1 to turn on first. When G1 is turned off, the gate line voltage jumps. Due to the parasitic capacitance Cgs between the gate and source and drain of the TFT, the pixel voltage of the first sub-pixel area will be pulled down by △Vp1; when G2 is turned off, due to the jump of the gate line voltage of the next row, the pixel voltage of the first sub-pixel area will be pulled down again by △Vp1'. Therefore, the pixel voltage of the first sub-pixel area will be pulled twice, such as Figure 2 As shown. For the second sub-pixel area ( Figure 1 When G2 is turned off, the gate voltage jumps and causes the pixel voltage to be pulled down by △Vp2. Similarly, the third sub-pixel area ( Figure 1 The pixel 3 in the second row and first column of the pixel 2 will also be pulled down twice by the closing of G3 and G4, which are △Vp3 and △Vp3' respectively. Figure 1 The pixel 4 in the second row and second column will have its pixel voltage pulled down by △Vp4 due to the closing of G4.

[0036] Figure 3 The schematic diagram of some pixel connections of the dual-gate structure array substrate in the prior art is shown. Due to the different TFT positions and the different connection methods with the pixels, Figure 3The bold black solid line in the figure represents the area corresponding to the gate line portion corresponding to the first sub-pixel area to 4 and its own pixel electrode. This area corresponds to the formation of a lateral capacitor Cgp. Based on the capacitor formula C=εS / d, when the distance d between the two side plates of the capacitor remains unchanged, the larger the area S facing each other between the two side plates, the larger the capacitance value C of the capacitor. Therefore, for the first sub-pixel area and the third sub-pixel area, the capacitance value Cgp1 of the lateral capacitor 1 of the first sub-pixel area is less than the capacitance value Cgp2 of the lateral capacitor 3 of the third sub-pixel area, and the capacitance value Cgp1' of the lateral capacitor 2 of the first sub-pixel area is less than the capacitance value Cgp2' of the lateral capacitor 4 of the third sub-pixel area. Therefore, △Vp3 is greater than △Vp1, and △Vp3' is greater than △Vp1'. According to the change in pixel voltage caused by the voltage jump of the gate line of the row where the pixel is located and the gate line of the next row of the row, as well as the TFT position of each pixel, when actually displaying, the brightness of a column of pixels is as follows: Figure 4 As shown, when two consecutive columns of pixels are bright or dark, there is a difference in brightness of the pixels during the display process. When a person shakes his head to observe the display, frame loss occurs and shaking head wrinkles appear.

[0037] In order to solve the above problems, the first embodiment of the present disclosure provides an array substrate of a dual-gate structure, which array substrate includes at least a plurality of gate lines and a plurality of data lines, two columns of sub-pixel regions are arranged between two adjacent data lines, and two gate lines are arranged between two adjacent rows of sub-pixel regions. Usually, the gate lines are arranged in the horizontal direction, and the data lines are arranged in the vertical direction. In this case, two columns of sub-pixel regions are arranged between the two data lines, and two rows of gate lines are arranged between the two adjacent rows of sub-pixel regions; in other embodiments, the gate lines may also be arranged in the vertical direction, and the data lines may be arranged in the horizontal direction. In this case, two rows of sub-pixel regions are arranged between the two adjacent columns of data lines, and two columns of gate lines are correspondingly arranged between the two adjacent columns of sub-pixel regions.

[0038] In order to solve the problem of poor display effects such as shaking head lines, the present disclosure can adjust the relevant structures of each sub-pixel area in the array substrate, such as the setting of the corresponding gate line position and size, the setting of the source and drain size and position, etc., so that the sum of the first capacitor and the second capacitor of all sub-pixel areas in the same pixel group is the same, so that the brightness of each pixel area in the group is the same after the gate line voltage jumps; in actual implementation, the error between the sum of the first capacitor and the second capacitor of any sub-pixel area in the group and the sum of the first capacitor and the second capacitor of other sub-pixel areas in the group can be within a preset error range to minimize the problem of uneven brightness caused by gate line voltage jumps. Among them, a pixel group is a plurality of sub-pixel areas arranged in a 2*2 matrix array between two adjacent data lines, such as Figure 5As shown by the part enclosed by the dashed line in the middle, the first capacitor in this embodiment is the capacitor between the gate corresponding to each sub-pixel region and the source-drain electrodes of the sub-pixel region, that is, there is a parasitic capacitance Cgs between the gate and the source-drain electrodes. The second capacitor is the capacitor between the gate line part corresponding to each sub-pixel region and the pixel electrode of the sub-pixel region, that is, the lateral capacitance Cgp. When the value of Cgs + Cgp in each sub-pixel region within the pixel group is the same, the problem of inconsistent floating of the pixel electrodes in the sub-pixel regions caused by the TFT station difference can be compensated.

[0039] It should be noted that the preset error range can be adjusted according to the size of the array substrate, the size of the sub-pixel region, or the first capacitor and the second capacitor of each sub-pixel region, and no specific limitation is made in this embodiment; in an ideal case, it can be ensured that the sum values of the first capacitor and the second capacitor in each sub-pixel region within the pixel group are all the same to achieve a better display optimization effect.

[0040] Figure 5 In a pixel group shown, there may be differences between the second capacitors of each sub-pixel region. In actual implementation, any one sub-pixel region in the pixel group can be selected as a reference, and by adjusting the values of the first capacitors of the other three sub-pixel regions in the group, the same sum value can be achieved. Specifically, the first capacitor is the parasitic capacitance between the gate and the source-drain electrodes of the sub-pixel region, and the magnitude of its capacitance value is related to the distance and the facing area between the gate and the source-drain electrodes. If the distance between the gate and the source-drain electrodes is adjusted, the problem of uneven thickness in each region of the array substrate will occur. Therefore, in this embodiment, it is preferably to adjust the facing area between the gate and the source-drain electrodes to adjust the magnitude of the first capacitor of the sub-pixel region. In some embodiments, due to the differences between the second capacitors of each sub-pixel region, after determining the reference pixel, there should be at least one sub-pixel region in the current pixel group where the overlapping area between the gate and the source-drain electrodes is different from the overlapping areas between the gate and the source-drain electrodes of the other sub-pixel regions in the group, so as to achieve the adjustment of the first capacitor of the sub-pixel region. In actual implementation, usually the overlapping areas between the gate and the source-drain electrodes of two sub-pixel regions in a pixel group need to be adjusted, or according to actual requirements, combined with factors such as pixel size and TFT station in the array substrate, the first capacitors of all sub-pixel regions in the pixel group can also be adjusted simultaneously, and no specific limitation is made in this embodiment.

[0041] In some embodiments, the overlapping area between the source-drain electrodes and their gate can be adjusted by adjusting the width of the source-drain part of the sub-pixel region in the pixel group. Figure 6The schematic diagram of the gate part and the source-drain part of the sub-pixel region is shown. For each sub-pixel region, it is independently controlled through the corresponding TFT. The TFT includes a gate, a source, and a drain. The gate is connected to the gate line and has an overlapping region with the source-drain. There is a channel between the source and the drain. When a voltage is applied to the gate, the channel between the source and the drain is turned on, and then the source and the drain are turned on, realizing the opening of the sub-pixel region. When the gate voltage is turned off, the corresponding sub-pixel region is turned off. Figure 6 The U-shaped structure and the L-shaped structure in it are the source and the drain of the TFT in the sub-pixel region respectively. Which end is the source and which end is the drain can be set according to the actual situation. The part overlapping with the source-drain region is the gate, and the gate is directly connected to the gate line or manufactured integrally. Specifically, when adjusting the overlapping area between the source-drain and the gate, the part overlapping with the gate in the L-shaped structure can be directly adjusted, thereby simplifying the adjustment method and facilitating calculation.

[0042] Furthermore, in a pixel group, there is at least one sub-pixel region whose source-drain width is different from that of other sub-pixel regions in the pixel group. Here, the source-drain width of the sub-pixel region mainly refers to the width of the overlapping part between the source-drain of the sub-pixel region and the gate of the sub-pixel region. Specifically, combining the positions of each sub-pixel region set in this embodiment and the configuration of the TFT, when the source-drain width of the fourth sub-pixel region is greater than that of any other sub-pixel region in the pixel group, the source-drain width of the first sub-pixel region is greater than that of the second and third sub-pixel regions, and the source-drain width of the second sub-pixel region is greater than that of the third sub-pixel region, the sum of the first capacitance and the second capacitance of each sub-pixel region can be basically kept consistent. As Figure 6 shown, taking the third sub-pixel region as a reference, the source-drain width of the third sub-pixel region is 5 microns, while the source-drain width of the fourth sub-pixel region is 9 microns. Figure 6 The source-drain width of the first sub-pixel region not shown in it is 6.5 microns, and the source-drain width of the second sub-pixel region is 6 microns. At this time, the sum of the first capacitance and the second capacitance of each determined sub-pixel region can be basically kept consistent, avoiding the generation of moiré patterns when the gate line voltage jumps.

[0043] In some embodiments, the overlapping area between the source-drain and its gate can also be adjusted by adjusting the length of the source-drain part of the sub-pixel region in the pixel group. Specifically, in a pixel group, there is at least one sub-pixel region whose source-drain length is different from that of the source-drain of other sub-pixel regions in the pixel group. Here, the source-drain length of the sub-pixel region mainly refers to the length of the overlapping part between the source-drain of the sub-pixel region and the gate of the sub-pixel region. Specifically, considering the positions of each sub-pixel region set in this embodiment and the configuration of the TFT, when the source-drain length of the fourth sub-pixel region is greater than the source-drain length of any other sub-pixel region in the pixel group, the source-drain length of the first sub-pixel region is greater than the source-drain lengths of the second and third sub-pixel regions, and the source-drain length of the second sub-pixel region is greater than the source-drain length of the third sub-pixel region, the sum values of the first and second capacitors of each sub-pixel region can be basically kept consistent, as Figure 7 shown. Taking the third sub-pixel region as a reference, the source-drain length of the third sub-pixel region is 19.35 microns, while the source-drain length of the fourth sub-pixel region is 22.35 microns, Figure 7 the source-drain length of the first sub-pixel region (not shown in the figure) is 20.85 microns, and the source-drain length of the second sub-pixel region is 20.35 microns. At this time, the sum values of the first and second capacitors of each corresponding determined sub-pixel region are basically kept consistent, avoiding the generation of moiré patterns when the gate line voltage jumps.

[0044] It should be understood that taking the first capacitor or the second capacitor between the first sub-pixel region and the third sub-pixel region as an example, combined with Figure 3 , the second capacitor Cgp1 of the first sub-pixel region is less than the capacitance value Cgp2 of the second capacitor of the third sub-pixel region, and at the same time Cgp1’ is less than Cgp2’. Therefore, if the sum values of the first capacitor or the second capacitor between the first sub-pixel region and the third sub-pixel region are to be the same, it is necessary to make the first capacitor of the first sub-pixel region greater than the first capacitor of the third sub-pixel region. Combining with the capacitor formula, when the distance d remains unchanged, the larger the overlapping area S between the two side plates, the larger the capacitance value C of the capacitor. Therefore, by increasing the overlapping area between the gate and the source-drain of the first sub-pixel region, the first capacitance value of the first sub-pixel region can be increased. Specifically, in this embodiment, the adjustment of the first capacitance value is achieved by adjusting the width or length of the source-drain, and the adjustment amplitude can be determined in combination with the difference in the second capacitance values between the sub-pixel regions.

[0045] In addition, the parameter values adjusted for the corresponding source-drain electrodes of each sub-pixel region described in the above embodiments of adjusting the source-drain width and source-drain length are only one possible set of adjustment parameters during implementation. In actual use, those skilled in the art can independently adjust according to the parameter conditions of the actual array substrate, as long as the Cgs + Cgp values of all sub-pixel regions within the same pixel group are basically the same.

[0046] In some embodiments, it is also possible to adjust the sum value by adjusting the value of the second capacitor while keeping the first capacitor unchanged. The second capacitor is the lateral capacitance between the gate line portion of the sub-pixel region and its own pixel electrode. Referring to the calculation formula of the capacitor, it can actually adjust the capacitance value by adjusting the overlapping area between the two plates and the distance between the plates. In this embodiment, it is preferably to adjust the second capacitor by adjusting the distance between the gate and the adjacent pixel electrode, that is, the distance between the gate line portion of at least one sub-pixel region in each pixel group and the edge of the pixel electrode on the side close to the gate line of this sub-pixel region is different from the distances of other sub-pixel regions in this pixel group. Specifically, considering the positions of each sub-pixel region set in this embodiment and the configuration of the TFT, when the distance in the third sub-pixel region is greater than the distance in any other sub-pixel region within the pixel group, the distance in the second sub-pixel region is greater than the distances in the first sub-pixel region and the fourth sub-pixel region, and the distance in the first sub-pixel region is greater than the distance in the fourth sub-pixel region, the sum values of the first capacitor and the second capacitor of each sub-pixel region can be basically kept the same.

[0047] It should be understood that taking the first capacitor or the second capacitor between the first sub-pixel region and the third sub-pixel region as an example, the second capacitor Cgp1 of the first sub-pixel region is less than the capacitance value Cgp2 of the second capacitor of the third sub-pixel region, and at the same time Cgp1’ is less than Cgp2’. Therefore, if we want to ensure that the sum values of the first capacitor or the second capacitor between the first sub-pixel region and the third sub-pixel region are the same, while keeping the first capacitor of the sub-pixel region unchanged, we can also directly reduce the value of the second capacitor of the third sub-pixel region to make its sum value basically the same as that of the first sub-pixel region. Combining with the capacitor formula, when the facing area S between the two plates remains unchanged, the larger the distance d between the plates, the smaller the capacitance value C of the capacitor. Therefore, by increasing the distance between the gate line portion of the third sub-pixel region and its own pixel electrode, the capacitance value of its second capacitor can be reduced. Specifically, in this embodiment, the adjustment of the second capacitor value is realized by adjusting the distance between the gate line portion of the pixel region and its own pixel electrode, and the adjustment amplitude can be determined in combination with the difference in the first capacitor values between the sub-pixel regions.

[0048] Further, a groove structure can be provided on the surface of the gate line portion on the side close to the pixel electrode. The position corresponding to the groove is equivalent to increasing the distance between the gate line portion and the pixel electrode, adjusting the second capacitance value. By providing a groove structure in at least one sub-pixel region in the pixel group, the adjustment of the Cgs+Cgp value of the sub-pixel region can be achieved. According to the differences between the sub-pixel regions, groove structures of different sizes can be correspondingly provided to make the Cgs+Cgp values of all sub-pixel regions in the pixel group consistent, achieving the optimization of the display effect between pixels and avoiding the generation of moiré patterns. In actual use, the cross-sectional shape of the groove structure can be any one of a rectangle, a semicircle, a zigzag, etc., and the actual opening size and shape can be adjusted according to requirements, which are not limited in this embodiment.

[0049] In some embodiments, for a certain pixel group or several pixel groups, while adjusting the distance between the gate of the sub-pixel region in the group and the adjacent pixel electrode, a groove structure can be further provided to achieve a better adjustment effect. For example, Figure 8 as shown, the distance between the position where no groove is provided on the gate line portion of the third sub-pixel region and the edge of the pixel electrode is 5.4 micrometers, and the groove structure is a rectangular groove of 5*10 micrometers. Therefore, the distance between the bottom of the groove and the edge of the pixel electrode is 10.4 micrometers. Corresponding to the same pixel group, no groove structure is provided in the first sub-pixel region, the second sub-pixel region, and the fourth sub-pixel region ( Figure 8 not shown in the figure), and the distances between their gate line portions and the edges of their respective pixel electrodes are 7 micrometers, 7.4 micrometers, and 5.4 micrometers respectively.

[0050] In this embodiment, by adjusting the relevant structures of each sub-pixel region in each pixel group in the array substrate, the sum values of the first capacitance and the second capacitance corresponding to all sub-pixel regions in the pixel group are made the same, thereby ensuring that the degree of pixel voltage fluctuation caused by the gate line jump voltage in the sub-pixel region is the same, making the brightness changes of all sub-pixel regions the same, avoiding the generation of moiré patterns, achieving a better display effect, and enhancing the user experience.

[0051] The second embodiment of the present disclosure provides a display panel, such as a thin-film transistor liquid crystal display panel. The display panel at least has the array substrate with the double-gate structure provided in the first embodiment of the present disclosure. By adjusting the relevant structures of each sub-pixel region in each pixel group in the array substrate, the sum values of the first capacitance and the second capacitance corresponding to all sub-pixel regions in the pixel group are made the same, thereby ensuring that the degree of pixel voltage fluctuation caused by the gate line jump voltage in the sub-pixel region is the same, making the brightness changes of all sub-pixel regions the same, avoiding the generation of moiré patterns, achieving a better display effect, and enhancing the user experience.

[0052] The third embodiment of the present disclosure provides an electronic device, such as the display screen of a computer or a television, an all-in-one device, a tablet computer, etc. The electronic device at least includes the display panel provided in the second embodiment of the present disclosure, and based on the relevant structure adjustment of the sub-pixel regions of the array substrate in the display panel, the sum value of the first capacitance and the second capacitance corresponding to all sub-pixel regions in the pixel group is made the same, thereby ensuring that the degree of pixel voltage fluctuation caused by the gate line jump voltage in the sub-pixel regions is the same, making the brightness change of all sub-pixel regions the same, avoiding the generation of moiré patterns, achieving a better display effect, and improving the user experience.

[0053] The above has described multiple embodiments of the present disclosure in detail, but the present disclosure is not limited to these specific embodiments. Based on the concept of the present disclosure, those skilled in the art can make various variations and modifications to the embodiments, and these variations and modifications should all fall within the scope of protection required by the present disclosure.

Claims

1. An array substrate with a double-gate structure, characterized in that At least including: a plurality of gate lines, a plurality of data lines, two columns of sub-pixel regions are arranged between two adjacent data lines, and two gate lines are arranged between two adjacent rows of sub-pixel regions; The error between the sum value of the first capacitance and the second capacitance of any one sub-pixel region in each pixel group in the array substrate and the sum value of the first capacitance and the second capacitance of other sub-pixel regions in the pixel group is within a preset error range; wherein, The pixel group is a plurality of sub-pixel regions arranged in a 2×2 matrix array between two adjacent data lines; The first capacitance is the capacitance between the gate line portion corresponding to each sub-pixel region and the source-drain of the sub-pixel region; The second capacitance is the capacitance between the gate line portion corresponding to each sub-pixel region and the pixel electrode of the sub-pixel region; In each pixel group, the distance between the gate line portion of at least one sub-pixel region and the edge of the pixel electrode on the side close to the gate line of the sub-pixel region is different from the distance of other sub-pixel regions in the pixel group; In the pixel group, the sub-pixel region located in the first row and the first column of the matrix array is the first sub-pixel region, the sub-pixel region located in the first row and the second column is the second sub-pixel region, the sub-pixel region located in the second row and the first column is the third sub-pixel region, and the sub-pixel region located in the second row and the second column is the fourth sub-pixel region; The distance of the third sub-pixel region is greater than the distance of any other sub-pixel region in the pixel group, the distance of the second sub-pixel region is greater than the distance of the first sub-pixel region and the fourth sub-pixel region, and the distance of the first sub-pixel region is greater than the distance of the fourth sub-pixel region.

2. The array substrate according to claim 1, wherein In each pixel group, at least one sub-pixel region has a groove structure provided on the side of the gate line close to the pixel electrode of the sub-pixel region.

3. The array substrate according to claim 2, wherein The cross-section of the groove structure at least includes one of the following shapes: rectangle, semi-circle, zigzag.

4. An array substrate with a double-gate structure, characterized in that, At least including: a plurality of gate lines, a plurality of data lines, two columns of sub-pixel regions are arranged between two adjacent data lines, and two gate lines are arranged between two adjacent rows of sub-pixel regions; The error between the sum value of the first capacitance and the second capacitance of any one sub-pixel region in each pixel group in the array substrate and the sum value of the first capacitance and the second capacitance of other sub-pixel regions in the pixel group is within a preset error range; wherein, The pixel group is a plurality of sub-pixel regions arranged in a 2×2 matrix array between two adjacent data lines; The first capacitance is the capacitance between the gate line portion corresponding to each sub-pixel region and the source-drain of the sub-pixel region; The second capacitance is the capacitance between the gate line portion corresponding to each sub-pixel region and the pixel electrode of the sub-pixel region; In each pixel group, the overlapping area between the gate corresponding to at least one sub-pixel region and the source-drain of the sub-pixel region is different from the overlapping area of other sub-pixel regions in the pixel group; In the pixel group, the sub-pixel region located in the first row and the first column of the matrix array is the first sub-pixel region, the sub-pixel region located in the first row and the second column is the second sub-pixel region, the sub-pixel region located in the second row and the first column is the third sub-pixel region, and the sub-pixel region located in the second row and the second column is the fourth sub-pixel region; The source-drain width of the fourth sub-pixel region is greater than that of any other sub-pixel region in the pixel group, the source-drain width of the first sub-pixel region is greater than that of the second and third sub-pixel regions, and the source-drain width of the second sub-pixel region is greater than that of the third sub-pixel region; wherein, the source-drain width of the sub-pixel region is the width of the overlapping portion between the source-drain of the sub-pixel region and the gate of the sub-pixel region.

5. An array substrate with a double-gate structure, characterized in that, It at least includes: a plurality of gate lines and a plurality of data lines. Two columns of sub-pixel regions are arranged between two adjacent data lines, and two gate lines are arranged between two adjacent rows of sub-pixel regions; The error between the sum value of the first capacitance and the second capacitance of any sub-pixel region in each pixel group of the array substrate and the sum value of the first capacitance and the second capacitance of other sub-pixel regions in the pixel group is within a preset error range; wherein, The pixel group is a plurality of sub-pixel regions arranged in a 2×2 matrix array between two adjacent data lines; The first capacitance is the capacitance between the gate line part corresponding to each sub-pixel region and the source-drain of the sub-pixel region; The second capacitance is the capacitance between the gate line part corresponding to each sub-pixel region and the pixel electrode of the sub-pixel region; In each pixel group, there is at least one sub-pixel region where the overlapping area between the gate corresponding to the sub-pixel region and the source-drain of the sub-pixel region is different from the overlapping areas of other sub-pixel regions in the pixel group; In the pixel group, the sub-pixel region located in the first row and the first column of the matrix array is the first sub-pixel region, the sub-pixel region located in the first row and the second column is the second sub-pixel region, the sub-pixel region located in the second row and the first column is the third sub-pixel region, and the sub-pixel region located in the second row and the second column is the fourth sub-pixel region; The source-drain length of the fourth sub-pixel region is greater than that of any other sub-pixel region in the pixel group, the source-drain length of the first sub-pixel region is greater than that of the second and third sub-pixel regions, and the source-drain length of the second sub-pixel region is greater than that of the third sub-pixel region; wherein, the source-drain length of the sub-pixel region is the length of the overlapping portion between the source-drain of the sub-pixel region and the gate of the sub-pixel region.

6. A display panel, characterized in that, The display panel at least includes the array substrate with a double-gate structure according to any one of claims 1 to 5.

7. An electronic device, characterized in that, The electronic device at least includes the display panel according to claim 6.

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