Storage array

Abstract

The present disclosure provides a storage array. The storage array includes a silicon substrate, a control circuit, and at least one layer of memory cells arranged in an array; the control circuit is disposed on the silicon substrate, and at least one layer of memory cell layers is stacked on the silicon substrate or on the side of the control circuit away from the silicon substrate; the memory cell includes a selector; wherein, the selector includes a substrate prepared from a two-dimensional material. By using a two-dimensional material to prepare the substrate of the selector in the storage array of the present disclosure, when the prepared selector forms a memory cell, different memory cells can be stacked. When the memory cells form a storage array, the storage array can form a multi-layer array arrangement of stacked memory cells, thereby reducing the occupied area of the storage array including the multi-layer array arrangement of memory cells and achieving high integration of the storage array.

Description

Technical Field

[0001] Embodiments of the present disclosure relate to the technical field of storage circuits, and particularly to a storage array. Background Art

[0002] Memory cells in a storage array generally include a selector and a memory. During operation, a specified memory can be selected for storing or reading information by controlling the selection of the selector. In related technologies, most memory cells are formed by a three-dimensional selector and a memory. In this way, when the storage array includes multiple memory cells, the memory cells can only be arranged in the same layer, resulting in a large occupied area and volume of the storage array, which is not conducive to the integration of the storage array. Summary of the Invention

[0003] The present disclosure provides a storage array to reduce the occupied area of a storage array including multiple memory cells and achieve high integration of the storage array.

[0004] In a first aspect, embodiments of the present disclosure provide a storage array, including a silicon substrate, a control circuit, and at least one layer of memory cells arranged in an array;

[0005] The control circuit is disposed on the silicon substrate, and at least one layer of memory cell layers is stacked on the silicon substrate or on the side of the control circuit away from the silicon substrate;

[0006] The memory cell includes a selector;

[0007] Wherein, the selector includes a substrate prepared from a two-dimensional material.

[0008] Further, the storage array further includes at least one layer of conductive layer; at least one layer of memory cell layers is stacked on the side of the control circuit away from the silicon substrate; along the thickness direction of the silicon substrate, the conductive layer is disposed between the control circuit and the memory cell, and the control circuit is connected to the memory cell through the conductive layer.

[0009] Further, the storage array further includes at least one layer of conductive layer, and the conductive layer is disposed on the silicon substrate; at least one layer of memory cell layers is stacked on the silicon substrate, and the control circuit is connected to the memory cell through the conductive layer.

[0010] Further, the control circuit includes a detection circuit, a word selection circuit, and a bit selection circuit;

[0011] The detection circuit, the word selection circuit, and the bit selection circuit are respectively connected to the memory cell through the conductive layer.

[0012] Further, the storage array includes at least two layers of memory cells, and further includes an insulating layer, and the insulating layer is disposed between adjacent two layers of memory cells.

[0013] Further, the storage array includes at least two layers of memory cells and also includes layer selectors; the number of layer selectors is the same as the number of layers of memory cells, and each layer selector is connected in series with one layer of memory cells;

[0014] The layer selector is used to select one layer from at least two layers of memory cells.

[0015] Further, the structure of the layer selector is the same as that of the selector.

[0016] Further, the two-dimensional material includes at least one of graphene, boron nitride, molybdenum disulfide, tungsten disulfide, and Mxene.

[0017] Further, the selector further includes a selection tube disposed on the substrate, and the selection tube is a transistor-type selection tube;

[0018] The first pole of the selection tube is connected to the selection line, the gate of the selection tube is connected to the word line, and the second pole of the selection tube is connected to the bit line.

[0019] Further, the control circuit includes a detection circuit. The word lines of the memory cells arranged in the same column are connected to the same word line, the bit lines of the memory cells arranged in the same row are connected to the same bit line, and the selection lines of the memory cells arranged in the same layer are connected to the detection circuit.

[0020] Further, the memory cell further includes a memory, and the memory includes a non-volatile memory.

[0021] In the storage array of the present disclosure, when forming the memory cells by using a two-dimensional material to prepare the substrate of the selector, different memory cells can be stacked. When the memory cells form a storage array, the storage array can form a stacked multi-layer array arrangement of memory cells, thereby reducing the occupied area of the memory cells including the multi-layer array arrangement and realizing the high integration of the storage array. BRIEF DESCRIPTION OF THE DRAWINGS

[0022] Figure 1 A schematic structural diagram of a storage array provided for the related art;

[0023] Figure 2 A schematic structural diagram of a memory cell provided for the related art;

[0024] Figure 3 A schematic structural diagram of a storage array provided by an embodiment of the present disclosure;

[0025] Figure 4 Another schematic structural diagram of a storage array provided by an embodiment of the present disclosure;

[0026] Figure 5Schematic structural diagram of a memory cell provided by an embodiment of the present disclosure;

[0027] Figure 6 Schematic structural diagram of another storage array provided by an embodiment of the present disclosure;

[0028] Figure 7 Schematic structural diagram of another storage array provided by an embodiment of the present disclosure;

[0029] Figure 8 Schematic structural diagram of another storage array provided by an embodiment of the present disclosure;

[0030] Figure 9 Top - view structural diagram of a storage array provided by an embodiment of the present disclosure;

[0031] Figure 10 Schematic structural diagram of another storage array provided by an embodiment of the present disclosure;

[0032] Figure 11 Schematic structural diagram of another storage array provided by an embodiment of the present disclosure;

[0033] Figure 12 Schematic structural diagram of another storage array provided by an embodiment of the present disclosure;

[0034] Figure 13 Schematic structural diagram of a selector provided by an embodiment of the present disclosure. Detailed implementation manners

[0035] To make the objectives, technical solutions, and advantages of the embodiments of the present disclosure clearer, the technical solutions in the embodiments of the present disclosure will be clearly and completely described below with reference to the accompanying drawings in the embodiments of the present disclosure. Obviously, the described embodiments are some, but not all, of the embodiments of the present disclosure. All other embodiments obtained by those of ordinary skill in the art based on the embodiments of the present disclosure without creative efforts shall fall within the protection scope of the present disclosure.

[0036] With the development of memories, the strobe circuit or selector plays a crucial role in memories. By controlling the strobe circuit or selector, a specified memory can be selected for storing or reading information.

[0037] Figure 1 Schematic structural diagram of a storage array provided by the related art. As Figure 1 shown, the storage array includes multiple memory cells. Each memory cell consists of a selector tube and a memory. Among them, the selector tube of the memory cell controls the specified memory for storing or reading by selecting a specified diode according to the one - way conduction characteristic of the diode. However, the controllability of the diode is poor, which easily leads to the failure of the selector tube.

[0038] Figure 2 A schematic structural diagram of a memory cell provided for related technologies. As Figure 2 shown, the memory cell includes a selector 101 and a memory 102. Among them, the selector 101 is composed of a two-terminal device with resistive switching characteristics. The selector 101 is connected to the memory 102. Only when the selection voltage of the selector 101 reaches the threshold and becomes in a low-resistance state, can the memory 102 be sensed, and then content can be read and written in the memory 102.

[0039] Therefore, the selector 101 has the following problems: The conduction principle of the selector 101 is based on atomic movement or phase change. When the number of switching times increases, there will be a retention effect of atoms or phases, resulting in unstable selection voltage, and even causing the selector 101 to fail, and thus the repeatability is poor, the stability is poor, and the service life is uncontrollable. It can be seen from this that the selection control and adjustment of the selector 101 of the above-mentioned memory cell are difficult, and thus, for a memory array composed of multiple such memory cells, there is also a problem that the selection control and adjustment of the selector 101 are difficult.

[0040] To simplify the control process of the selector 101 of the above-mentioned memory cell, the memory cell in related technologies can also be fabricated using a three-dimensional selector and a memory. Among them, the three-dimensional selector includes a silicon substrate, and a gate, a first pole, and a second pole provided on the silicon substrate. Among them, the gate is connected to a word line, the first pole is connected to a control line, and the second pole is connected to the memory through a metal layer. The three-dimensional selector can transmit the content of the word line to the memory by directly controlling the control line without controlling the selection voltage. Thus, compared with Figure 2 the memory cell, the memory cell using the three-dimensional selector simplifies the control process of the selector.

[0041] However, for the memory cell fabricated using the three-dimensional selector, due to the silicon substrate used in the three-dimensional selector, when multiple memory cells form a memory array, the memory cells can only be arranged in the same layer, resulting in a relatively large occupied area of the memory array, a relatively large volume of the memory array, and being not conducive to the integration of the memory array.

[0042] Figure 3 A schematic structural diagram of a memory array provided by an embodiment of the present disclosure, Figure 4 Another schematic structural diagram of a memory array provided by an embodiment of the present disclosure, Figure 5 A schematic structural diagram of a memory cell provided by an embodiment of the present disclosure. Refer to Figure 3 、 Figure 4 and Figure 5, the memory array includes a silicon substrate 110, a control circuit 120, and at least one layer of memory cells 130 arranged in an array; the control circuit 120 is disposed on the silicon substrate 110, and at least one layer of memory cells 130 is stacked on the silicon substrate 110 or on the side of the control circuit 120 away from the silicon substrate 110; the memory cell 130 includes a selector 131; wherein, the selector 131 includes a substrate 132 made of a two-dimensional material.

[0043] Among them, the main function of the memory cell 130 is to store data information. The control circuit 120 is connected to the memory cells 130 arranged in an array, and can control whether the memory cells 130 store or read data information. The silicon substrate 110 is a substrate that supports the control circuit 120 and at least one layer of memory cells 130 arranged in an array. At least one layer of memory cells 130 can be stacked on the silicon substrate 110, or can be disposed on the side of the control circuit 120 away from the silicon substrate 110.

[0044] Exemplarily, referring to Figure 3 , at least one layer of memory cells 130 can be stacked on the silicon substrate 110. At this time, both the control circuit 120 and at least one layer of memory cells 130 are disposed on the silicon substrate 110. The control circuit 120 and at least one layer of memory cells 130 arranged in an array can be electrically connected through wires or a conductive metal layer, so that the control circuit 120 stores or reads data information from at least one layer of memory cells 130 arranged in an array.

[0045] In other embodiments, referring to Figure 4 , the control circuit 120 can also be disposed on the silicon substrate 110, and at least one layer of memory cells 130 is stacked on the side of the control circuit 120 away from the silicon substrate 110. A conductive layer can be provided on the control circuit 120 to be electrically connected to the memory cells 130, so that the control circuit 120 stores or reads data information from at least one layer of memory cells 130 arranged in an array.

[0046] In addition, referring to Figure 5 , the memory cell 130 includes a selector 131, and the selector 131 includes a substrate 132 made of a two-dimensional material. Among them, a material with a thickness ranging from a single atomic layer to several atomic layers is called a two-dimensional material. The two-dimensional material used for the substrate 132 of the selector 131 is a new material with an ordered structure, growing in a two-dimensional plane, being ultrathin in the third dimension, and achieving electrical conduction without interlayer stacking. The ultrathin characteristic of the two-dimensional material in the third dimension is expected to solve the short-channel effect faced by conventional semiconductors, which can further reduce the size of the selector 131. When forming the memory cell 130 with the selector 131, the volume of the memory cell 130 can be reduced.

[0047] In addition, in the present disclosure, when forming the memory cell 130 by using a two-dimensional material to prepare the substrate 132 of the selector 131, different memory cells 130 can be stacked. When the memory cells 130 form a memory array, the memory array can form a memory cell 130 arranged in a stacked multi-layer array, so as to reduce the occupied area of the memory cell 130 including the multi-layer array arrangement and achieve a high integration of the memory array.

[0048] Figure 6 FIG. is a schematic structural diagram of another memory array provided by an embodiment of the present disclosure. As Figure 6 shown, the memory array further includes at least one conductive layer 140; at least one layer of memory cells 130 is stacked on a side of the control circuit 120 away from the silicon substrate 110; along the thickness direction of the silicon substrate 110, the conductive layer 140 is disposed between the control circuit 120 and the memory cells 130, and the control circuit 120 is connected to the memory cells 130 through the conductive layer 140.

[0049] Among them, the conductive layer 140 is disposed between a side of the control circuit 120 away from the silicon substrate 110 and a side of the memory cells 130 close to the silicon substrate 110, and is connected to a side of the control circuit 120 away from the silicon substrate 110 and a side of the memory cells 130 close to the silicon substrate 110, so that the control circuit 120 can be connected to the memory cells 130 through the conductive layer 140.

[0050] Specifically, an insulating layer is disposed between the control circuit 120 and the memory cells 130, and through holes for aligning the control circuit 120 and the memory cells 130 are disposed on the insulating layer. When forming the conductive layer 140, a conductive substance can be filled in the through holes of the insulating layer that align the control circuit 120 and the memory cells 130, so as to realize the connection between the control circuit 120 and the memory cells 130 through the conductive layer 140, and enable the control circuit 120 to store or read data information from the memory cells 130.

[0051] Figure 7 FIG. is a schematic structural diagram of another memory array provided by an embodiment of the present disclosure. As Figure 7 shown, the memory array further includes at least one conductive layer 140, and the conductive layer 140 is disposed on the silicon substrate 110; at least one layer of memory cells 130 is stacked on the silicon substrate 110, and the control circuit 120 is connected to the memory cells 130 through the conductive layer 140.

[0052] Among them, the control circuit 120, the memory cell 130, and the conductive layer 140 are all disposed on the silicon substrate 110. Both ends of the conductive layer 140 are respectively connected to the control circuit 120 and the memory cell 130, so that the control circuit 120 can be connected to the memory cell 130 through the conductive layer 140. Specifically, the conductive layer 140 is disposed between the control circuit 120 and the memory cell 130, so that the control circuit 120 is connected to the memory cell 130 through the conductive layer 140, thereby enabling the control circuit 120 to store or read data information from the memory cell 130.

[0053] Figure 8 This is a schematic top view structure diagram of another storage array provided by an embodiment of the present disclosure. As Figure 8 shown, the control circuit 120 includes a detection circuit 121, a word selection circuit 122, and a bit selection circuit 123; the detection circuit 121, the word selection circuit 122, and the bit selection circuit 123 are respectively connected to the memory cell 130 through the conductive layer 140.

[0054] Among them, the control circuit 120 includes a detection circuit 121, a word selection circuit 122, and a bit selection circuit 123. The detection circuit 121, the word selection circuit 122, and the bit selection circuit 123 are disposed on the silicon substrate 110, and at least one layer of memory cells 130 is stacked on the side of the detection circuit 121, the word selection circuit 122, and the bit selection circuit 123 away from the silicon substrate 110. The conductive layer 140 is disposed between the side of the detection circuit 121, the word selection circuit 122, and the bit selection circuit 123 away from the silicon substrate 110 and the side of the memory cell 130 close to the silicon substrate 110, and is connected to the side of the control circuit 120 away from the silicon substrate 110 and the side of the memory cell 130 close to the silicon substrate 110, so that the control circuit 120 can be connected to the memory cell 130 through the conductive layer 140. Specifically, an insulating layer is disposed between the control circuit 120 and the memory cell 130, and three through holes are formed in the insulating layer. When forming the conductive layer 140, a conductive substance is filled in the through holes of the insulating layer, so that the detection circuit 121, the word selection circuit 122, and the bit selection circuit 123 are connected to the memory cell 130 through the conductive layer 140, enabling the control circuit 120 to store or read data information from the memory cell 130.

[0055] Figure 9 This is a schematic top view structure diagram of a storage array provided by an embodiment of the present disclosure. As Figure 9As shown, the control circuit 120 includes a detection circuit 121, a word selection circuit 122, and a bit selection circuit 123 disposed on a substrate. A conductive layer 140 and memory cells 130 are also disposed on the silicon substrate 110. Among them, a conductive layer 140 connecting the detection circuit 121, the word selection circuit 122, and the bit selection circuit 123 to the memory cells 130 is respectively disposed on the silicon substrate 110, so that the detection circuit 121, the word selection circuit 122, and the bit selection circuit 123 are connected to the memory cells 130 through the conductive layer 140, thereby enabling the control circuit 120 to store or read data information from the memory cells 130.

[0056] In some alternative embodiments, the memory cells 130 include a selection line, a word line, and a bit line. Figure 10 This is a schematic structural diagram of another storage array provided by an embodiment of the present disclosure. As Figure 10 shown, the word lines of the memory cells arranged in the same column are connected to the same word line, the bit lines of the memory cells arranged in the same row are connected to the same bit line, and the selection lines of the memory cells arranged in the same layer are connected to the detection circuit 121. The detection circuit 121 can provide a fixed potential for the memory cells in the same layer. The word selection circuit is connected to the word lines of each column of the memory cells in each layer, and is used to control the potential change of the word lines of each column of the memory cells, so as to control writing or reading to the word lines according to the conduction state of the selection transistor. The bit selection circuit is connected to the bit lines of each row of the memory cells in each layer, and is used to control the potential change of the bit lines of each row of the memory cells, so as to control the conduction state of the selection transistor of the memory cells, and realize selecting a specified memory cell to store or read information.

[0057] Taking Figure 10 as an example for exemplary illustration, among them, the storage array includes a layer of memory cells ①, memory cells ②, memory cells ③, memory cells ④, memory cells ⑤, and memory cells ⑥ arranged in a 2-row and 3-column array. Among them, the detection circuit 121 is connected to the memory cells; the word selection circuit is respectively connected to the word lines 411, word lines 412, and word lines 413; the bit selection circuit is respectively connected to the bit lines 431 and bit lines 432. For example, the detection circuit 121 can provide a fixed potential for the memory cells, the word selection circuit can provide a word signal for the memory cells through the word line 411, and the bit selection circuit can provide a bit signal for the memory cells through the bit line 431; at this time, the memory cell ① can store or read data. Thus, the detection circuit 121, the word selection circuit, and the bit selection circuit can control each memory cell in the storage array to store or read data.

[0058] Figure 11 This is a schematic structural diagram of another storage array provided by an embodiment of the present disclosure. As Figure 11As shown, the storage array includes at least two layers of memory cells 130, and further includes an insulating layer 141 disposed between adjacent two layers of memory cells 130.

[0059] Among them, the insulating layer 141 is disposed between adjacent two layers of memory cells 130. The insulating layer 141 is an insulating material layer, which can isolate the occurrence of electrical connection between adjacent two layers of memory cells 130 and reduce the mutual influence between adjacent two layers of memory cells 130. Thus, disposing the insulating layer 141 between adjacent two layers of memory cells 130 can ensure that there is no electrical connection between adjacent layers of memory cells 130 due to reasons such as leakage, and can effectively block the mutual influence between adjacent layers of memory cells 130.

[0060] Figure 12 It is a schematic structural diagram of another storage array provided by an embodiment of the present disclosure. As Figure 12 shown, the storage array includes at least two layers of memory cells 130, and further includes a layer selector 150; among them, the number of layer selectors 150 can be the same as the number of layers of memory cells 130, and each layer selector 150 is connected in series with one layer of memory cells 130; the layer selector 150 is used to select one layer from at least two layers of memory cells 130.

[0061] Among them, each layer of memory cells 130 is correspondingly disposed with one layer selector 150. As Figure 12 shown, the word selection circuit 122 is connected to each layer selector 150, and the layer selector 150 can control whether the word line of one layer of memory cells 130 can be written or read. When the layer selector 150 is turned on and controls that the word line of one layer of memory cells 130 can be written or read, the word selection circuit 122 can provide a word signal for the memory cells 130 through the word line.

[0062] It should be noted that the above embodiment only exemplarily shows a connection manner of the layer selector 150. Among them, the bit selection circuit 123 can also be connected to the layer selector 150; or the word selection circuit 122 and the bit selection circuit 123 are simultaneously connected to the layer selector 150, and designers can set according to actual needs.

[0063] Exemplarily, referring to Figure 10 , the storage array can include two layers of memory cells ①, memory cells ②, memory cells ③, memory cells ④, memory cells ⑤, and memory cells ⑥ arranged in an array of 2 rows and 3 columns as Figure 10 shown. For example, the word selection circuit can be respectively connected to the first layer selector and the second layer selector. The first layer selector can control whether the word line of the first layer of memory cells can be written or read, and the second layer selector can control whether the word line of the second layer of memory cells can be written or read.

[0064] In some alternative embodiments, the word lines of the same column of the first - layer storage array and the second - layer storage array can be connected in series and then connected to the word - selection circuit; the bit lines of the same row of the first - layer storage array and the second - layer storage array can be connected in series and then connected to the bit - selection circuit; the first - layer storage array and the second - layer storage array are respectively connected to the detection circuit 121.

[0065] When the first - layer selector is turned on, the word lines of the first - layer storage array can be used for writing or reading. The bit - selection circuit can provide a bit signal for the memory cells through the bit lines, and the detection circuit 121 can provide a fixed potential for the first - layer storage array. For example, the word - selection circuit can provide a word signal for the memory cells through the word line 411, the bit - selection circuit can provide a bit signal for the memory cells through the bit line 431, and the detection circuit 121 can provide a fixed potential for the first - layer storage array; at this time, the first - layer memory cell ① can store or read data. Thus, through the layer selector, the detection circuit 121, the word - selection circuit, and the bit - selection circuit, each memory cell in the storage array can be controlled to store or read data.

[0066] Optionally, the structure of the layer selector is the same as that of the selector.

[0067] Among them, the structure of the layer selector is the same as that of the selector, that is, the layer selector includes a substrate made of two - dimensional material. According to the characteristic that the two - dimensional material is ultrathin in the third dimension and can achieve electrical conduction without inter - layer stacking, the size of the layer selector can be reduced.

[0068] Optionally, the two - dimensional material includes at least one of graphene, boron nitride, molybdenum disulfide, tungsten disulfide, and Mxene.

[0069] Among them, graphene is the most typical representative of two - dimensional materials, with only one atomic thickness. Carbon atoms are bonded in - plane in the form of covalent bonds to form a hexagonal honeycomb - like planar structure. In addition to graphene, the two - dimensional materials also include boron nitride, molybdenum disulfide, tungsten disulfide, and Mxene. The two - dimensional material of the substrate of the selector in the present disclosure can be one or more of graphene, boron nitride, molybdenum disulfide, tungsten disulfide, and Mxene, which can eliminate the dependence on the silicon substrate, reduce the waste of silicon materials, and increase the integration degree of the storage array.

[0070] Figure 13 It is a schematic structural diagram of a selector provided for this embodiment. As Figure 13 shown, the selector 131 further includes a selection tube 133 disposed on the substrate 132. The selection tube 133 is a transistor - type selection tube; the first pole 221 of the selection tube 133 is connected to the selection line, the gate 222 of the selection tube 133 is connected to the word line, and the second pole 223 of the selection tube 133 is connected to the bit line.

[0071] Among them, the strobe tube 133 is a transistor type strobe tube. Transistors have the characteristics of low cost, small size, long life, resistance to mechanical shock, and high efficiency, and thus have been widely used. Specifically, the strobe line is connected to the first pole 221 of the strobe tube 133 to control the strobe state of the strobe tube 133; the gate 222 of the strobe tube 133 is connected to the word line, and the signal written to or read from the word line can be controlled according to the conduction state of the strobe tube 133; the second pole 223 of the strobe tube 133 is connected to the bit line. Since the bit line can be a ground wire, that is, the second pole 223 of the strobe tube 133 is grounded. Exemplarily, if the strobe tube 133 is an N-type transistor, the word line controlling the strobe tube 133 provides a high voltage to the gate 222 of the strobe tube 133, and the bit line provides a low voltage to the second pole 223 of the strobe tube 133. When the control strobe line provides a positive voltage to the first pole 221 of the strobe tube 133 and the voltage difference between the word line and the strobe line is greater than the threshold voltage of the strobe tube 133, the strobe tube 133 will conduct. The word line controlling the strobe tube 133 provides a high voltage to the gate 222 of the strobe tube 133, and the bit line provides a low voltage to the second pole 223 of the strobe tube 133. When the control strobe line does not provide a positive voltage or does not provide a voltage to the first pole 221 of the strobe tube 133, the strobe tube 133 will turn off. Thus, in the case where the word line controlling the strobe tube 133 provides a high voltage for writing and the bit line provides a low voltage to the second pole 223 of the strobe tube 133, only by controlling the potential of the strobe line can the strobe tube 133 be controlled to be in a conducting state or a closed state.

[0072] It should be noted that the first pole 221 and the second pole 223 of the strobe tube 133 can be interchanged. In other embodiments, it can be set according to the actual situation, and the embodiments of the present disclosure do not limit this.

[0073] Continue to refer to Figure 10 , the control circuit includes a detection circuit 121. The word lines of the memory cells arranged in the same column are connected to the same word line, the bit lines of the memory cells arranged in the same row are connected to the same bit line, and the strobe lines of the memory cells arranged in the same layer are connected to the detection circuit 121.

[0074] Exemplarily, memory cells ①, ②, ③, ④, ⑤, and ⑥ are shown arranged in an array of 2 rows and 3 columns. Among them, the word lines of memory cells ① and ④ arranged in the first column are both connected to word line 411; the word lines of memory cells ② and ⑤ arranged in the second column are both connected to word line 412; the word lines of memory cells ③ and ⑥ arranged in the third column are both connected to word line 413. The bit lines of memory cells ①, ②, and ③ arranged in the first row are all connected to bit line 431; the bit lines of memory cells ④, ⑤, and ⑥ arranged in the second row are all connected to bit line 432. The select lines of memory cells ①, ②, ③, ④, ⑤, and ⑥ are all connected to detection circuit 121.

[0075] Specifically, if the select transistors in memory cells ①, ②, ③, ④, ⑤, and ⑥ are all N-type transistors, detection circuit 121 provides a fixed potential, such as ground, for the select lines of all memory cells. When word line 412 transmits write data and bit line 432 provides a positive voltage, memory cell ⑤ can store the write data transmitted by word line 412 at this time.

[0076] Optionally, the memory cell further includes a memory, and the memory includes a non-volatile memory.

[0077] Among them, a non-volatile memory refers to a memory in which the stored data does not disappear when the current is turned off. For example, a magnetic random access memory (MRAM) is a non-volatile magnetic random access memory that has the high-speed read and write capabilities of a static random access memory, as well as the high integration of a dynamic random access memory, and can basically be written repeatedly an infinite number of times. A resistive random access memory (RRAM) is a rewritable memory technology that can significantly improve durability and data transfer speed. A phase change memory has the advantages of small memory cell size, non-volatility, long cycle life, good stability, low power consumption, and strong embeddable functions, especially with outstanding advantages in the miniaturization of device feature sizes. A ferroelectric memory is a non-volatile memory that does not lose its content when powered off and has the advantages of high speed, high density, low power consumption, and radiation resistance.

[0078] Finally, it should be noted that the above embodiments are only used to illustrate the technical solutions of the present disclosure, rather than to limit them; although the present disclosure has been described in detail with reference to the foregoing embodiments, those of ordinary skill in the art should understand that they can still modify the technical solutions recorded in the foregoing embodiments, or perform equivalent replacements on some of the technical features; and these modifications or replacements do not make the essence of the corresponding technical solutions deviate from the spirit and scope of the technical solutions of the various embodiments of the present disclosure.

Claims

1. A storage array, characterized in that, It includes a silicon substrate, a control circuit, and at least two layers of memory cells arranged in an array; The control circuit is disposed on the silicon substrate, and at least two layers of the memory cell layers are stacked on the silicon substrate or on the side of the control circuit away from the silicon substrate; The memory cell includes a selector; Wherein, the selector includes a substrate made of a two-dimensional material, and the two-dimensional material is a material with an ordered structure, grown in a two-dimensional plane, and capable of achieving electrical conduction without interlayer stacking; The memory array further includes an insulating layer, and the insulating layer is disposed between two adjacent layers of the memory cells; The memory array further includes a layer selector, the number of the layer selectors is the same as the number of layers of the memory cells, and each layer selector is connected in series with one layer of the memory cells; the layer selector is used to select one layer of at least two layers of the memory cells; the structure of the layer selector is the same as the structure of the selector; 2. The storage array according to claim 1, wherein It further includes at least one conductive layer; at least two layers of the memory cell layers are stacked on the side of the control circuit away from the silicon substrate; along the thickness direction of the silicon substrate, the conductive layer is disposed between the control circuit and the memory cells, and the control circuit is connected to the memory cells through the conductive layer.

3. The storage array according to claim 1, wherein It further includes at least one conductive layer, and the conductive layer is disposed on the silicon substrate; at least two layers of the memory cell layers are stacked on the silicon substrate, and the control circuit is connected to the memory cells through the conductive layer.

4. The storage array according to claim 2 or 3, wherein The control circuit includes a detection circuit, a word selection circuit, and a bit selection circuit; The detection circuit, the word selection circuit, and the bit selection circuit are respectively connected to the memory cells through the conductive layer.

5. The storage array according to claim 1, wherein The two-dimensional material includes at least one of graphene, boron nitride, molybdenum disulfide, tungsten disulfide, and Mxene.

6. The storage array according to claim 1, wherein The selector further includes a selection tube disposed on the substrate, and the selection tube is a transistor-type selection tube; The first pole of the selection tube is connected to the selection line, the gate of the selection tube is connected to the word line, and the second pole of the selection tube is connected to the bit line.

7. The storage array according to claim 6, wherein The control circuit includes a detection circuit, the word lines of the memory cells arranged in the same column are connected to the same word line, the bit lines of the memory cells arranged in the same row are connected to the same bit line, and the selection lines of the memory cells arranged in the same layer are connected to the detection circuit.

8. The storage array according to claim 1, wherein, The memory cell further includes a memory, and the memory includes a non-volatile memory.

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