Memory device, memory cell, and method of creating a standard cell layout

Abstract

A memory device includes a first memory cell having a first polysilicon line associated with a first read word line and intersecting a first active region and a second active region, and a second polysilicon line and a first continuous active edge over polysilicon line associated with a first program word line, the second polysilicon line intersecting the second active region and the first continuous active edge over polysilicon line intersecting the first active region. The memory device also includes a second memory cell adjacent to the first memory cell, the second memory cell having a third polysilicon line associated with a second read word line and intersecting the first active region and the second active region, and a fourth polysilicon line and a second continuous active edge over polysilicon line associated with a second program word line, the fourth polysilicon line intersecting the first active region and the second continuous active edge over polysilicon line intersecting the second active region to form a cross-arrangement of continuous active edge over polysilicon lines.

Description

Technical Field

[0001] This disclosure generally relates to standard cell layouts, and more particularly to reducing the total cell area of ​​an antifuse cell array and current leakage between antifuse cells in an antifuse cell array. Background Technology

[0002] Integrated circuits are widely used in a variety of applications. Designing an integrated circuit is a multi-step process. Specifically, integrated circuit design begins with describing the required functionality of the integrated circuit. Based on the functional description, transistor-level circuitry is designed, and a netlist defining the interconnectivity of the various transistors in the circuit is developed. The netlist can be simulated and tested to verify the required functionality of the circuit implementation and predict operating parameters. The netlist is then used to create a standard cell layout for the circuit. The standard cell layout contains standard components or standard cells from a standard cell library and shows how those cells are interconnected. Antifuse memory cells are one type of standard component. However, current antifuse memory cells have limitations in their configuration. Attached Figure Description

[0003] The various aspects of this disclosure will be best understood by reading the following detailed description in conjunction with the accompanying drawings. It should be noted that, in accordance with industry standard practice, the various features are not drawn to scale. In fact, for clarity of explanation, the dimensions of the various features may be arbitrarily increased or decreased.

[0004] Figure 1 This is an example block diagram of a computing system according to some embodiments.

[0005] Figure 2 It is an example antifuse cell array according to some embodiments.

[0006] Figure 3 According to some embodiments Figure 2 An example layout of an antifuse cell array.

[0007] Figure 4 According to some embodiments Figure 2 Another example layout of the antifuse cell array.

[0008] Figure 5 According to some embodiments Figure 2 Another example layout of the antifuse cell array.

[0009] Figure 6 It is another example of an antifuse cell array according to some embodiments.

[0010] Figure 7 According to some embodiments Figure 6 An example layout of an antifuse cell array.

[0011] Figure 8This is an illustration based on some embodiments. Figure 2 The instance layout of the unit cell definition in the antifuse cell array.

[0012] Figure 9 This is an illustration based on some embodiments. Figure 2 Another instance layout of the definition of another unit cell in the antifuse cell array.

[0013] Explanation of icon numbers

[0014] 100: Computing system;

[0015] 105: Main unit;

[0016] 110: Memory devices;

[0017] 115: Input device;

[0018] 120: Output device;

[0019] 125A, 125B, 125C: Interface;

[0020] 130A, 130N: Core of the Central Processing Unit;

[0021] 135: Application of standard cell layout;

[0022] 140: Memory controller;

[0023] 145: Storage array;

[0024] 150: Manufacturing tools;

[0025] 200, 600: Antifuse unit array;

[0026] 205, 605: First antifuse unit;

[0027] 210, 610: Second antifuse unit;

[0028] 215: Third antifuse unit;

[0029] 220: Fourth antifuse unit;

[0030] 225A, 225B, 225C, 225D: Programmable transistors;

[0031] 230A, 230B, 230C, 230D: Read transistors;

[0032] 235, 615, BL: bit lines;

[0033] 240A, 240B, 240C, 240D, 535B, 535C, 535D, 650, 655, 765, WLP: Programming word lines;

[0034] 245A, 245B, 245C, 245D, WLR: Read word lines;

[0035] 300, 400, 410A, 410B, 410C, 410D, 500, 510A, 510B, 510C, 510D, 700, 800, 900: Layout;

[0036] 305: Active region;

[0037] 310A, 310B, 310C, 310D, 315A, 315B, 315C, 315D, 330, 335, 415A, 415B, 415C, 415D, 425A, 425B, 425C, 425D, 535A, 720, 725, 730, 745, 755, 855: Polycrystalline silicon wire;

[0038] 320, 325, 430A, 430B, 430C, 430D, 455, 525, 530A, 530B, 735, 740, 770, 815, 835, CPODE: Polysilicon lines on the edge of continuous active regions;

[0039] 405, 505, 705: Partial list;

[0040] 420A, 515, 710: First active region;

[0041] 420B, 520, 715: Second active region;

[0042] 435, 440A, 440B, 440C, 440D, 440E, 440F, 445A, 445B, 445C, 445D, 445E, 445F, 750A, 750B, 750C, 760A, 760B, 775A, 775B: Metal on the diffusion layer;

[0043] 450: Adjacent antifuse unit;

[0044] 540: Discontinuous metal on the diffusion layer;

[0045] 620, 635: First read transistor;

[0046] 625, 640: Second readout transistor;

[0047] 630, 645: Programmable transistors;

[0048] 660, 670: First read word lines;

[0049] 665, 675: Second read word lines;

[0050] 805, 905: Unit 1;

[0051] 810, 910: Unit 2;

[0052] 820, 925: First polysilicon production line;

[0053] 825, 930: Second polysilicon production line;

[0054] 830, 935: Third polysilicon production line;

[0055] 840, 950: The fourth polysilicon production line;

[0056] 845, 955: The fifth polysilicon production line;

[0057] 850, 960: The sixth polysilicon production line;

[0058] 915: Polysilicon line on the edge of the first continuous active region;

[0059] 920: Polysilicon line on the edge of the second continuous active region;

[0060] 940: Polysilicon line on the edge of the third continuous active region;

[0061] 945: Polysilicon line on the edge of the fourth continuous active region;

[0062] A, B, C, D: Units;

[0063] x, y: Direction. Detailed Implementation

[0064] The following disclosure provides numerous different embodiments or instances for implementing various features of the provided subject matter. Specific examples of components and arrangements are described below to simplify this disclosure. Of course, these are merely examples and are not intended to be limiting. For example, in the following description, the formation of a first feature on or on a second feature may include embodiments where the first and second features are formed in direct contact, and may also include embodiments where an additional feature may be formed between the first and second features so that the first and second features do not need to be in direct contact. Furthermore, reference numerals and / or letters may be repeated in various instances of this disclosure. This repetition is for simplicity and clarity and does not, in itself, define a relationship between the various embodiments and / or configurations discussed.

[0065] Additionally, for ease of description, spatial relative terms such as “beneath,” “below,” “lower,” “above,” “upper,” and similar terms may be used herein to describe the relationship between one element or feature and another, as shown in the figures. Besides the orientations depicted in the figures, the spatial relative terms are intended to cover different orientations of the device during use or operation. The device may be oriented in other ways (rotated 90 degrees or in other orientations), and the spatial relative descriptors used herein will be interpreted accordingly.

[0066] For reference Figure 1 Example block diagrams of a computing system 100 are illustrated according to some embodiments of this disclosure. The computing system 100 can be used by a circuit or layout designer for standard cell layout of circuitry. As used herein, "circuit" or "integrated circuit" refers to the interconnection of electrical components such as resistors, transistors, switches, battery packs, inductors, or other types of semiconductor devices configured to implement desired functionality. The computing system 100 includes a host device 105 associated with a memory device 110. The host device 105 is configured to receive input from one or more input devices 115 and provide output to one or more output devices 120. The host device 105 is configured to communicate with the memory device 110, the input device 115, and the output device 120 via appropriate interfaces 125A, 125B, and 125C, respectively. The computing system 100 can be implemented in a variety of computing devices, such as computers (e.g., desktop computers, laptop computers, servers, data centers, etc.), tablet computers, personal digital assistants, mobile devices, other handheld or portable devices, or any other computing unit suitable for a standard cell layout using the host device 105.

[0067] Input device 115 may include any of a variety of input technologies, such as a keyboard, stylus, touchscreen, mouse, trackball, keypad, microphone, voice recognition, motion recognition, remote controller, input port, one or more buttons, dial pad, joystick, and any other input peripheral associated with host device 105 that allows an external source (e.g., a user, such as a circuit or layout designer) to input information (e.g., data) into the host device and send instructions to the host device. Similarly, output device 120 may include a variety of output technologies, such as external memory, printer, speaker, display, microphone, LED, headset, video device, and any other output peripheral configured to receive information (e.g., data) from host device 105. "Data" input to and / or output from host device 105 may include any of the following: various types of text data, circuit data, signal data, semiconductor device data, graphic data, combinations thereof, or other types of analog and / or digital data suitable for processing using computing system 100.

[0068] Host device 105 includes or is associated with one or more processing units / processors, such as Central Processing Unit (CPU) cores 130A to 130N. CPU cores 130A to 130N may be implemented as Application Specific Integrated Circuits (ASICs), Field Programmable Gate Arrays (FPGAs), or any other type of processing unit. Each of CPU cores 130A to 130N is configured to execute instructions for running one or more applications on host device 105. In some embodiments, the instructions and data required to run one or more applications may be stored in memory device 110. Host device 105 may also be configured to store the results of running one or more applications in memory device 110. Therefore, host device 105 may be configured to request various operations from memory device 110. For example, host device 105 may request memory device 110 to read data, write data, update or delete data, and / or perform management or other operations.

[0069] The host device 105 can be configured to run one such application, which may be a standard cell layout application 135. The standard cell layout application 135 may be part of a computer-aided design or electronic design automation software suite that can be used by a user of the host device 105 to create a standard cell layout of a circuit (also referred to herein as a “layout,” “layout diagram,” “layout design,” and the like). The standard cell layout of a circuit can show various components / connections of the circuit to be manufactured. For example, a standard cell layout can show one or more active regions, gates, sources, and drains, metal lines, via contacts, openings in pads, one or more metal layers, power supplies, etc., representing various components of the circuit, and how those components are interconnected when placed in / on a semiconductor substrate (e.g., a silicon wafer). A standard cell layout can be implemented by following a design process that may include one or more of logic design, physical design, or placement and wiring. The standard cell layout can be expressed in one or more data files, such as a GDSII file format or a DFII file format. In other embodiments, other file formats may be used. Therefore, using the standard cell layout application 135, a circuit designer can create a standard cell layout of a circuit. In some embodiments, instructions required to execute or run the standard cell layout application 135 may be stored in the memory device 110. The standard cell layout application 135 may be executed by one or more of CPU cores 130A to CPU cores 130N using instructions associated with the standard cell layout application from the memory device 110.

[0070] Still referencing Figure 1The memory device 110 includes a memory controller 140 configured to read data from or write data to the memory array 145. In some embodiments, the memory array 145 may be a one-time programmable (OTP) memory array. An OTP memory array is a type of non-volatile memory that retains data stored therein after the memory device 110 is powered off. In some embodiments, the OTP memory array may include a plurality of anti-fuse cells, each of which may be configured to store at least one bit of data. In some embodiments, the memory array 145 may additionally include other types of volatile and / or non-volatile memory. For example, in some embodiments, the storage array 145 may also include NAND flash memory cores, NOR flash memory cores, static random access memory (SRAM) cores, dynamic random access memory (DRAM) cores, magnetoresistive random access memory (MRAM) cores, phase change memory (PCM) cores, resistive random access memory (ReRAM) cores, 3D XPoint memory cores, ferroelectric random-access memory (FeRAM) cores, and other types of memory cores suitable for use within the storage array. Generally, the storage array 145 may include any of the following: various random access memory (RAM), read-only memory (ROM), programmable ROM (PROM), erasable PROM (EPROM), electrically EPROM (EEPROM), hard disk drive, flash drive, memory tape, optical drive, cloud storage, or any combination of primary and / or secondary memory suitable for performing the operations described herein.

[0071] The memories within memory array 145 can be controlled individually and independently by memory controller 140. In other words, memory controller 140 can be configured to communicate individually and independently with each memory within memory array 145. Through communication with memory array 145, memory controller 140 can be configured to read data from or write data to memory array in response to instructions received from host device 105. Although illustrated as part of memory device 110, in some embodiments, memory controller 140 may be part of host device 105 or another component of computing system 100 and associated with memory device. Memory controller 140 can be implemented as logic circuitry in software, hardware, firmware, or a combination thereof to perform the functions described herein. For example, in some embodiments, memory controller 140 can be configured to retrieve instructions associated with standard cell layout application 135 stored in memory array 145 of memory device 110 upon receiving a request from host device 105.

[0072] In some embodiments, the computing system 100 may also be associated with various manufacturing tools 150. In particular, the manufacturing tools 150 may be used to prepare and fabricate a set of masks based on a standard cell layout created by a standard cell layout application 135. This set of masks may define the geometry of photolithography steps used during the semiconductor fabrication of the circuit. Although the manufacturing tools 150 are illustrated as being separated from the host device 105, in some embodiments, at least some of the functionality of the manufacturing tools may be implemented via the host device, for example, via the standard cell layout application 135 or another application associated with the standard cell layout application.

[0073] To prepare a set of masks, manufacturing tool 150 can be used to translate the standard cell layout of the circuit into a representative data file (RDF). The RDF can then be used to create a set of physical masks to fabricate the circuit.

[0074] In some embodiments, fabricating the set of masks may include using photolithographic enhancement techniques to perform optical proximity correction (OPC) to compensate for image errors in the standard cell layout, such as those caused by diffraction, interference, other processing effects, and the like. In some embodiments, a mask rule checker (MRC) of the fabrication tool 150 may use a set of mask generation rules to check the standard cell layout that has been processed in the OPC. The mask generation rules may contain certain geometric and / or connectivity constraints to ensure sufficient margins, take into account variability in semiconductor manufacturing processes, etc. In some embodiments, the MRC may modify the standard cell layout during the fabrication of the set of masks to compensate for limitations. In some embodiments, the fabrication of the set of masks may also include resolution enhancement techniques (RET), such as off-axis illumination, sub-resolution assist features, phase-shifting masks, other suitable techniques and the like, or combinations thereof.

[0075] In some embodiments, the fabrication of the set of masks may further include lithography process checking (LPC) to simulate processes implemented to manufacture circuits. LPC can simulate these processes based on a standard cell layout to create a simulated fabricated device of the circuit. LPC may consider various factors to simulate circuit fabrication, such as aerial image contrast, depth of focus (DOF), mask error enhancement factor (MEEF), other suitable factors, and combinations thereof. In some embodiments, after a simulated fabricated device has been created by LPC, if the simulated device does not meet certain design rules, OPC and / or MRC may be repeated to further optimize the standard cell layout.

[0076] To fabricate the set of masks, a mask writer can convert RDF into an image on a substrate (e.g., a mask or semiconductor wafer). In some embodiments, an electron beam or a combination of electron beams can be used to form a mask pattern on the semiconductor wafer to form the mask. In some embodiments, the mask pattern may include one or more opaque areas and one or more transparent areas. A radiation beam (e.g., an ultraviolet (UV) beam) used to expose an image-sensitive material layer (e.g., photoresist) coated on the semiconductor wafer may be blocked by the opaque areas and transmitted through the transparent areas. In one example, the mask pattern may include a transparent substrate (e.g., fused silica) and an opaque material (e.g., chromium) coated in the opaque areas to form the mask. In other embodiments, other or additional techniques may be used to fabricate the mask.

[0077] Once the mask is fabricated, a manufacturing entity (such as a manufacturing plant or semiconductor foundry) can use the fabricated mask to fabricate circuits. In some embodiments, fabricating a circuit may involve depositing one or more materials in / on a semiconductor wafer using a mask (or multiple masks). The semiconductor wafer may comprise a silicon substrate or other substrate having a layer of material formed thereon. The semiconductor wafer may further comprise one or more of various doped regions, dielectric features, multilayer interconnects, and the like formed using one or more of the masks.

[0078] It should be understood that although the manufacturing tool 150 is described as performing certain operations for preparing and then manufacturing the set of masks, in some embodiments, the various processes may differ from those described. In some embodiments, additional or other processes or operations may be used to prepare and manufacture the set of masks. It should also be understood that... Figure 1 Only some components of the computing system 100 are illustrated and described herein. However, the computing system 100 may include other components, such as various battery packs and power supplies, networking interfaces, routers, switches, external memory systems, controllers, etc. Generally, the computing system 100 may include any of the various hardware, software, and / or firmware components required or deemed necessary to perform the functions described herein. Similarly, the host device 105, input device 115, output device 120, and memory device 110, which include the memory controller 140 and memory array 145, may include other hardware, software, and / or firmware components deemed necessary or necessary to perform the functions described herein.

[0079] Instead refer to Figure 2An example antifuse cell array 200 is illustrated according to some embodiments of the present disclosure. The antifuse cell array 200 includes a first antifuse cell 205, a second antifuse cell 210, a third antifuse cell 215, and a fourth antifuse cell 220. In some embodiments, as illustrated, each of the first antifuse cell 205, the second antifuse cell 210, the third antifuse cell 215, and the fourth antifuse cell 220 includes two transistors. Therefore, each of the first antifuse cell 205, the second antifuse cell 210, the third antifuse cell 215, and the fourth antifuse cell 220 is a 2T cell configuration. Additionally, in some embodiments, each of the first antifuse cell 205, the second antifuse cell 210, the third antifuse cell 215, and the fourth antifuse cell 220 may be configured to store one data bit.

[0080] Although four antifuse cells (e.g., first antifuse cell 205, second antifuse cell 210, third antifuse cell 215, and fourth antifuse cell 220) extending in a single cell row have been depicted in the antifuse cell array 200, in some embodiments, a single cell row of the antifuse cell array (which extends in the X direction) may contain more or fewer than four cells. Additionally, although... Figure 2 Not shown, but the antifuse cell array 200 may also include antifuse cells extending in the Y direction. In other words, the antifuse cell array 200 may include multiple cell rows, wherein each cell row has multiple antifuse cells similar to the first antifuse cell 205, the second antifuse cell 210, the third antifuse cell 215, and the fourth antifuse cell 220.

[0081] Furthermore, although each of the first antifuse unit 205, the second antifuse unit 210, the third antifuse unit 215, and the fourth antifuse unit 220 is illustrated as an n-type transistor, in some embodiments, one or more of the first antifuse unit, the second antifuse unit, the third antifuse unit, and the fourth antifuse unit may be a p-type transistor. Each of the first antifuse unit 205, the second antifuse unit 210, the third antifuse unit 215, and the fourth antifuse unit 220 includes a programming transistor 225A, a programming transistor 225B, a programming transistor 225C, and a programming transistor 225D configured to store a data bit (e.g., one data bit), and each includes a read transistor 230A, a read transistor 230B, a read transistor 230C, and a read transistor 230D configured to facilitate reading data stored in the associated programming transistor.

[0082] The source or drain terminals of the read transistors 230A to 230D of each of the first antifuse unit 205, the second antifuse unit 210, the third antifuse unit 215, and the fourth antifuse unit 220 are connected to the bit line 235. Therefore, each of the first antifuse unit 205, the second antifuse unit 210, the third antifuse unit 215, and the fourth antifuse unit 220 includes a programming transistor (e.g., programming transistors 225A to 225D) and a read transistor (e.g., read transistors 230A to 230D) and shares the bit line 235. When multiple cell rows are provided in the antifuse unit array 200, the antifuse unit in each cell row may be associated with a bit line. Therefore, in some embodiments, the antifuse unit array 200 may include multiple bit lines.

[0083] Additionally, the gate terminals of programming transistors 225A to 225D of each of the first antifuse unit 205, the second antifuse unit 210, the third antifuse unit 215, and the fourth antifuse unit 220 are connected to the program word line (WLP). Therefore, programming transistor 225A of the first antifuse unit 205 is connected to program word line 240A, programming transistor 225B of the second antifuse unit 210 is connected to program word line 240B, programming transistor 225C of the third antifuse unit 215 is connected to program word line 240C, and programming transistor 225D of the fourth antifuse unit 220 is connected to program word line 240D. Each of the programming word lines 240A to 240D can be used to apply a programming voltage at a programming voltage level to program one of the associated programming transistors 225A to 225D. Alternatively, each of the programming word lines 240A to 240D can be used to apply a read voltage level to read data stored in an associated one of the programming transistors 225A to 225D.

[0084] To program a bit in programming transistor 225A, a programming voltage at the programming voltage level can be applied to programming word line 240A, and a reference voltage can be applied to bit line 235. The difference between the programming voltage and the reference voltage generates an electric field on the dielectric semiconductor layer of programming transistor 225A. The electric field can be large enough to continuously alter (e.g., break down) the dielectric semiconductor layer of programming transistor 225A, thereby reducing the resistance of the dielectric semiconductor layer and programming the data bit in the programming transistor. Programming transistors 225B to 225D can similarly be programmed via their respective programming word lines 240B to 240D. Reading transistors 230A to 230D can be turned off during programming operation.

[0085] Similarly, the gate terminals of read transistors 230A to 230D of each of the first antifuse unit 205, the second antifuse unit 210, the third antifuse unit 215, and the fourth antifuse unit 220 are connected to the read word line (WLR). For example, read transistor 230A of the first antifuse unit 205 is connected to read word line 245A, read transistor 230B of the second antifuse unit 210 is connected to read word line 245B, read transistor 230C of the third antifuse unit 215 is connected to read word line 245C, and read transistor 230D of the fourth antifuse unit 220 is connected to read word line 245D. Each of the read word lines 245A to 245D can be used to apply sufficient voltage to turn on an associated read transistor 230A to 230D for reading data stored in an associated programmable transistor 225A to 225D.

[0086] To read data stored in programming transistors 225A to 225D, one of the associated read transistors 230A to 230D can be turned on, and a corresponding read voltage can be applied via a corresponding one of the programming word lines 240A to 240D. For example, to read data stored in programming transistor 225A, a sufficient voltage can be applied to read word line 245A to turn on read transistor 230A, a read voltage at the read voltage level can be applied to programming word line 240A, and a reference voltage can be applied to bit line 235. The difference between the read voltage and the reference voltage generates an electric field on the dielectric semiconductor layer of programming transistor 225A. The electric field is small enough to avoid continuously changing the dielectric semiconductor layer, but large enough to generate a read current flowing through the turned-on read transistor 230A. The read current flows through bit line 235 and is sensed by a sense amplifier (not shown) connected to the bit line to read the bit stored in programming transistor 225A. The magnitude and polarity of the read current may depend on the magnitude and polarity of the read voltage applied to the programming word line 240A relative to the reference voltage applied to the bit line 235, and one or more resistors discussed below. Similarly, data stored in programming transistors 225B to 225D may be read via one of the associated reading transistors 230B to 230D and bit line 235, respectively.

[0087] refer to Figure 3An example layout 300 of an antifuse cell array 200 is illustrated according to some embodiments of the present disclosure. Therefore, layout 300 includes a layout design of a first antifuse cell 205, a second antifuse cell 210, a third antifuse cell 215, and a fourth antifuse cell 220. The source and drain terminals of the programming transistors 225A to 225D and the read transistors 230A to 230D of each of the first antifuse cell 205, the second antifuse cell 210, the third antifuse cell 215, and the fourth antifuse cell 220 are formed in an active region 305. The active region 305 may (e.g., via an interconnect layer, not shown) be connected to a bit line 235 (…). Figure 2 (Not shown in the diagram). The active region 305 can be a fin region of one or more three-dimensional field-effect transistors (e.g., FinFET, gate-all-around (GAA) transistors), or an oxide-defined (OD) region of one or more planar metal-oxide-semiconductor field-effect transistors (MOSFETs), such that the active region can serve as the source or drain feature of the respective transistor. The active region 305 can extend along the cell row direction. Therefore, the active region 305 can extend in the X direction.

[0088] The gate terminal of each of the first antifuse unit 205, the second antifuse unit 210, the third antifuse unit 215, and the fourth antifuse unit 220 can be represented by a polysilicon line extending perpendicular to the cell row direction. Therefore, the polysilicon line extends in the Y direction and intersects the active region 305. Thus, programmable word lines 240A to 240D and read word lines 245A to 245D can be connected to or otherwise associated with the polysilicon line. The programmable word lines 240A to 240D and read word lines 245A to 245D of each of the first antifuse unit 205, the second antifuse unit 210, the third antifuse unit 215, and the fourth antifuse unit 220 can be connected to the polysilicon line. For example, the programming word lines 240A to 240D of the first antifuse unit 205, the second antifuse unit 210, the third antifuse unit 215, and the fourth antifuse unit 220 can be associated with the corresponding polysilicon lines 310A to 310D, respectively. Similarly, the read word lines 245A to 245D of the first antifuse unit 205, the second antifuse unit 210, the third antifuse unit 215, and the fourth antifuse unit 220 can be associated with the corresponding polysilicon lines 315A to 315D, respectively.

[0089] In some embodiments, two antifuse units may share an active region. For example, in some embodiments, the first antifuse unit 205 and the second antifuse unit 210 may be formed on one shared active region, while the third antifuse unit 215 and the fourth antifuse unit 220 may be formed on another shared active region. In this case, a predetermined gap extending in the X direction may be provided between the two shared active regions to reduce current leakage between the first antifuse unit 205 / second antifuse unit 210 and the third antifuse unit 215 / fourth antifuse unit 220. For example, in this embodiment, a predetermined gap may be provided between polysilicon lines 310B and 310C. Although the gap reduces current leakage between adjacent / nearby antifuse units, the gap increases the total cell area of ​​the antifuse unit array 200.

[0090] To reduce the total cell area of ​​the antifuse cell array 200, in various embodiments, this disclosure provides a mechanism that allows the first antifuse cell 205, the second antifuse cell 210, the third antifuse cell 215, and the fourth antifuse cell 220 to be formed on a common active region (e.g., active region 305), such as... Figure 3 As illustrated in the diagram. However, the active region 305, shared by the first antifuse unit 205, the second antifuse unit 210, the third antifuse unit 215, and the fourth antifuse unit 220, increases the current leakage between the antifuse units of the antifuse unit array 200. To minimize current leakage, in some embodiments, this disclosure also provides a mechanism that uses a dummy polysilicon line over active region edge (also referred to herein as PODE) in regions where gaps are already provided in a conventional standard cell layout. Since the active region 305 is continuous and shared by the first antifuse unit 205 / second antifuse unit 210 and the third antifuse unit 215 / fourth antifuse unit 220, the PODE can be considered as a common PODE or a continuous PODE (also referred to herein as CPODE).

[0091] In some embodiments, shallow trench isolation (STI) technology can be used to form PODEs or CPODEs. During the fabrication of the antifuse cell array 200, PODEs or CPODEs can be generated by forming trenches in a semiconductor wafer (on which the antifuse cell array is fabricated) and these trenches can be deposited using a dielectric material. By using a dielectric material, PODEs or CPODEs do not provide electrical or conductive paths and can prevent or at least reduce / minimize current leakage on components (where PODEs or CPODEs are positioned between the components).

[0092] Therefore, in various embodiments, in order to use a common active region (e.g., active region 305) and avoid current leakage between the active region portions of the first antifuse unit 205 / second antifuse unit 210 and the active region portions of the third antifuse unit 215 / fourth antifuse unit 220, CPODE 320 and CPODE 325 can be disposed between polysilicon lines 310B and 310C. CPODE 320 and CPODE 325 are not connected to active region 305. Therefore, CPODE 320 and CPODE 325 do not provide an electrical path between polysilicon lines 310B and 310C. In various embodiments, by using CPODE 320 and CPODE 325, the active region 305 can be a common active region between the first antifuse unit 205 / the second antifuse unit 210 and the third antifuse unit 215 / the fourth antifuse unit 220 to eliminate the gaps discussed above, thereby reducing the total cell area of ​​the antifuse unit array 200 while preventing or at least reducing / minimizing current leakage between adjacent / neighboring cells.

[0093] Although two CPODEs (e.g., CPODE 320 and CPODE 325) are depicted between polysilicon lines 310B and 310C, in some embodiments, more or fewer CPODEs may be provided between those polysilicon lines. Furthermore, although this disclosure has discussed forming CPODE 320 and CPODE 325 between the second antifuse unit 210 and the third antifuse unit 315 (e.g., since those units are typically formed on separate active regions), in some embodiments, one or more CPODEs may instead be provided between each adjacent antifuse unit. For example, in some embodiments, one or more CPODEs may be provided between the first antifuse unit 205 and the second antifuse unit 210, one or more CPODEs may be provided between the second antifuse unit and the third antifuse unit 215, and / or one or more CPODEs may be provided between the third antifuse unit and the fourth antifuse unit 220 (depending on the structure of the active regions of those antifuse units).

[0094] Additionally, in some embodiments, programming word lines 240A to 240D can be considered as larger current leakage sources than read word lines 245A to 245D. Therefore, in some embodiments, it may be advantageous to position the CPODE adjacent to the programming word lines of adjacent antifuse units. For example, in some embodiments, instead of or in addition to providing CPODE 320 and CPODE 325, one or more CPODEs can be positioned adjacent to and between polysilicon lines 310A and 330, and one or more CPODEs can be positioned adjacent to and between polysilicon lines 310D and 335. In other embodiments, one or more CPODEs may be positioned adjacent to read word lines 245A to 245B of adjacent antifuse units, except (or alternatively) one or more CPODEs adjacent to programming word lines 240A to 240D and / or CPODEs 320 and 325. For example, in some embodiments, one or more CPODEs may be positioned between polysilicon lines 315A and 315B, and one or more CPODEs may be positioned between polysilicon lines 315C and 315D.

[0095] Therefore, in various embodiments, CPODE enables the use of a common active region (e.g., active region 305) to reduce both the cell area of ​​the antifuse cell array 200 and current leakage between adjacent antifuse cells. It has been found that, in various embodiments, using CPODE (e.g., CPODE 320 and CPODE 325) can reduce the total cell area of ​​the antifuse cell array 200 by approximately thirty-four percent. As used herein, the terms “adjacent” or “nearby” antifuse cells mean two antifuse cells that are adjacent to each other without any other intervening antifuse cells. Thus, in the antifuse cell array 200, the first antifuse cell 205 is adjacent to the second antifuse cell 210, the second antifuse cell is adjacent to the first and third antifuse cells 215, the third antifuse cell is adjacent to the second and fourth antifuse cells 220, and the fourth antifuse cell is adjacent to the third antifuse cell.

[0096] The following text can be used to... Figure 4 The layout described herein is used to further reduce the total cell area of ​​the antifuse cell array 200. Specifically, by using... Figure 4 This layout can reduce the total area of ​​the antifuse unit array 200 by approximately 45%. Therefore, referring to... Figure 4Alternative layouts 400 are illustrated according to some embodiments of this disclosure. A portion 405 of layout 400 corresponds to the layout of the antifuse cell array 200. By using layout 400 in portion 405, the total cell area of ​​the antifuse cell array 200 can be reduced by approximately 45 percent (compared to approximately 34 percent of layout 300), while preventing or at least reducing / minimizing current leakage, thereby providing greater benefits than layout 300. Layout 400 achieves this greater reduction in total cell area by using a combination of polysilicon lines with gate terminals associated with programming word lines and CPODEs, and by using a cross arrangement of CPODEs, as discussed below.

[0097] Section 405 illustrates a layout 410A of the first antifuse unit 205. Layout 410A includes polysilicon lines 415A to represent the read word lines 245A of the first antifuse unit 205. Layout 410A also includes a combination of polysilicon lines 425A and CPODE 430A to represent the programming word lines 240A of the first antifuse unit 205. Section 405 similarly includes layouts 410B of the second antifuse unit 210, layout 410C of the third antifuse unit 315, and layout 410D of the fourth antifuse unit 220. For readability, only boxes are drawn around layout 410A of the first antifuse unit 205. Similar to layout 410A, each of layouts 410B to 410D includes polysilicon lines to represent the read word lines of the corresponding antifuse unit, and combinations of polysilicon lines and CPODEs for the programming word lines of the corresponding antifuse units.

[0098] For example, layout 410B includes a polysilicon line 415B to represent the read word line 245B of the second antifuse unit 210, layout 410C includes a polysilicon line 415C to represent the read word line 245C of the third antifuse unit 215, and layout 410D includes a polysilicon line 415D to represent the read word line 245D of the fourth antifuse unit 220. Each of the polysilicon lines 415A to 415D intersects with both the first active region 420A and the second active region 420B. Additionally, each of layouts 410B to 410D also includes a combination of a polysilicon line and a CPODE to represent the programming word line of the corresponding antifuse unit. For example, layout 410B includes polysilicon line 425B and CPODE 430B to represent programming word line 240B of the second antifuse unit 210, layout 410C includes polysilicon line 425C and CPODE 430C to represent programming word line 240C of the third antifuse unit 215, and layout 410D includes polysilicon line 425D and CPODE 430D to represent programming word line 240D of the fourth antifuse unit 220. Therefore, in layout 400, each of programming word lines 240A to 240D is represented by a combination of a corresponding one of polysilicon lines 425A to 425D and a corresponding one of CPODE 430A to CPODE 430D.

[0099] Additionally, in some embodiments, each of polysilicon lines 425A to 425D and each of CPODEs 430A to 430D intersects with either a first active region 420A or a second active region 420B. Specifically, in some embodiments, if a polysilicon line (e.g., polysilicon lines 425A to 425D) associated with a particular programming word line intersects with the first active region 420A, then the CPODE of that programming word line intersects with the second active region 420B. Thus, for example, in some embodiments, polysilicon line 425A of programming word line 240A intersects with the second active region 420B, while the CPODE 430A of that programming word line intersects with the first active region 420A. Similarly, in some embodiments, for each of programming word lines 240B to 240D, polysilicon lines 425B to 425D and CPODEs 430B to 430D associated with those programming word lines intersect with either the first active region 420A or the second active region 420B. Although not shown in layout 400, bit line 235 is connected to the first active region 420A and the second active region 420B.

[0100] Additionally, in some embodiments, specific polysilicon lines of the programming word lines are separated from each other by a small gap in the Y direction. For example, in some embodiments, polysilicon line 425A is separated from CPODE 430A by a small gap in the Y direction. Similarly, in some embodiments, polysilicon lines 425B, 425C, and 425D are each separated from CPODE 430B, CPODE 430C, and CPODE 430D by a small gap in the Y direction. The size of the gap may differ between one embodiment and another. Furthermore, in some embodiments, the gaps between polysilicon lines 425A to 425D and between CPODE 430A to CPODE 430D for each of the programming word lines 240A to 240D may be the same, while in other embodiments, the gaps between one programming word line and another may be different. Therefore, compared to the polysilicon lines 415A to 415B associated with read word lines 245A to 245D (which extend without gaps from the first active region 420A to the second active region 420B as continuous polysilicon lines), the polysilicon lines 425A to 425D and CPODE 430A to 430B of each of the programming word lines 240A to 240D are separated by gaps. In some embodiments, the polysilicon lines 425A to 425D and CPODE 430A to 430B of one or more of the programming word lines 240A to 240D need not be separated by any gaps. In some embodiments, and as illustrated, polysilicon lines 425A to 425D and CPODE 430A to 430B associated with a particular programming word line may be aligned in the Y direction (e.g., on a straight vertical line). In other embodiments, polysilicon lines 425A to 425D and CPODE 430A to 430B associated with a particular programming word line may be slightly offset in the X direction.

[0101] Additionally, in some embodiments, polysilicon lines 425A to 425D and CPODEs 430A to 430B are arranged in a cross configuration. Specifically, as shown below... Figure 4As illustrated, in some embodiments, if a CPODE associated with a programming word line of an antifuse unit intersects with a first active region 420A, then a CPODE associated with a programming word line of an adjacent antifuse unit intersects with a second active region 420B. For example, since CPODE 430A associated with programming word line 240A of the first antifuse unit 205 intersects with the first active region 420A, CPODE 430B associated with programming word line 240B of the second antifuse unit 210 intersects with the second active region 420B. Similarly, the CPODE 430C associated with the programming word line 430C of the third antifuse unit 215 intersects with the first active region 420A (because the CPODE 430B associated with the programming word line 430B of the second antifuse unit 215 and the CPODE 430D associated with the programming word line 430D of the fourth antifuse unit 220 both intersect with the second active region 420B). Therefore, the CPODE associated with the programming word line of one antifuse unit is formed on the first active region 420A, while the CPODE associated with the programming word line of an adjacent antifuse unit is formed on the second active region 420B, thus alternating between the first and second active regions. This alternating arrangement of CPODE 430A to CPODE 430D on the first active region 420A and the second active region 420B in adjacent antifuse units is referred to herein as a cross arrangement of CPODEs.

[0102] In addition, such as Figure 4 As illustrated, in some embodiments, the first active region 420A and the second active region 420B are spaced apart from each other. The size of the space between the first active region 420A and the second active region 420B may differ between one embodiment and another. The first active region 420A and the second active region 420B are also connected to each other via one or more metal over diffusion layers disposed between polysilicon lines 415A to 415D and between polysilicon lines 425A to 425D and between CPODEs 430A to 430D. For example, in some embodiments, the first active region 420A may be connected to the second active region 420B via a metal over diffusion layer 435. The metal over oxide layer 435 provides an electrical or conductive path between the first active region 420A and the second active region 420B. In addition to the metal 435 on the diffusion layer extending continuously from the first active region 420A to the second active region 420B between adjacent programming word lines, thus intersecting with both the first and second active regions.

[0103] "Adjacent programmable word lines" means that a polysilicon line (or CPODE) associated with a programmable word line of an antifuse cell is immediately adjacent to a CPODE (or polysilicon line) associated with a programmable word line of an adjacent antifuse cell, without having any other intervening polysilicon lines or CPODEs associated with the programmable word line or read word line. Therefore, for example, polysilicon lines 425C / CPODE 430C and 425B / CPODE 430B are adjacent programmable word lines. However, polysilicon lines 425C / CPODE 430C and 425D / CPODE 430D are not adjacent programmable word lines. Similarly, "adjacent read word lines" means that a polysilicon line associated with a read word line is immediately adjacent to another polysilicon line associated with another read word line, without having any other intervening polysilicon lines associated with the programmable word line or read word line. Therefore, for example, polysilicon lines 415C and 415D are adjacent read word lines. However, polysilicon line 415C and polysilicon line 415B are not adjacent read word lines.

[0104] Therefore, in portion 405, the metals 440A to 440F on the diffusion layer continuously extend between and intersect with the first active region 420A and the second active region 420B, while the metals 445A to 445F on the oxide layer in portion 405 intersect with either the first or second active region. The metals 440A to 440F on the diffusion layer are referred to herein as continuous metal over diffusion layer, while the metals 445A to 445F on diffusion layer are referred to herein as discontinuous metal over diffusion layer. The metals 445A to 445F on diffusion layer are positioned between adjacent programming word lines. For example, on the diffusion layer, metal 445C is located between polysilicon line 425B and CPODE 430C, which are adjacent programming word lines. Similarly, on the diffusion layer, metal 445D is located between CPODE 430B and polysilicon line 425C, which are adjacent programming word lines.

[0105] By separating the first active region 420A and the second active region 420B, by using a combination of polysilicon lines (e.g., polysilicon lines 425A to 425D) and CPODEs (e.g., CPODEs 430A to 430D) on the programming word lines, and by using a combination of continuous metals (e.g., metals 440A to 440F) and discontinuous metals (e.g., metals 445A to 445F) on the diffusion layer, this disclosure prevents or at least reduces or minimizes current leakage to / from adjacent antifuse cells, while reducing the total cell area of ​​the antifuse cell array 200.

[0106] For example, and specifically referring to layout 410A, current can flow through the first active region 420A, the second active region 420B, and the metal 440A on the oxide layer through the polysilicon line 425A to the polysilicon line 415A. However, current flowing through the polysilicon line 425A can be prevented from flowing to the adjacent antifuse cell 450 by CPODE 430A and CPODE 455, which provide electrical isolation between the first antifuse cell 205 and the adjacent antifuse cell 450. Furthermore, by using CPODE 430A to CPODE 430D, each of the first active region 420A and the second active region 420B can be formed as a continuous active region shared by all antifuse cells in the same cell row, as described above. Figure 3 As discussed in [the document]. Therefore, the cross arrangement of CPODEs reduces the total cell area of ​​the antifuse cell array 200, while preventing or reducing / minimizing current leakage to adjacent antifuse cells.

[0107] It should be understood that although a single case of continuous metal on the diffusion layer (e.g., metal 440A to metal 440F on the oxide layer) or discontinuous metal on the diffusion layer (e.g., metal 445A to metal 445F on the oxide layer) is illustrated in each location where those layers are present, in some embodiments, more than one metal diffusion layer may be provided in one or more of those locations. Additionally, in some embodiments, more than one CPODE may be associated with each polysilicon line. Therefore, in some embodiments, each programmable word line may be associated with a combination of a polysilicon line and more than one CPODE, rather than with a combination of a polysilicon line and one CPODE. In some embodiments, more than one polysilicon line may be associated with each programmable word line.

[0108] In addition, although Figure 4 The diagram illustrates two active regions (e.g., a first active region 420A and a second active region 420B), but in some embodiments, layout 400 may include more than two active regions. Additionally, it should be understood that... Figure 4 Only some of the components of layout 400 are shown. However, other components that are typically included in or considered necessary in a standard cell layout can be included, such as metal interconnect layers, through-hole contacts, power rails, etc. In some embodiments, the size can be further reduced by using additional CPODEs. Figure 4 Current leakage in layout 400, as described below Figure 5 As described in the layout.

[0109] Now for reference Figure 5 Another example layout 500 is illustrated according to some embodiments of this disclosure. Layout 500 is similar to layout 400 and therefore is not described in full again. Layout 500 includes a portion 505 corresponding to the layout of the antifuse cell array 200. Similar to portion 405, portion 505 includes layout 510A of the first antifuse cell 205, layout 510B of the second antifuse cell 210, layout 510C of the third antifuse cell 215, and layout 510D of the fourth antifuse cell 220. Each of layouts 510A to 510D includes a polysilicon line intersecting with both the first active region 515 and the second active region 520 as a read word line. Each of layouts 510A to 510D also includes a combination of a polysilicon line associated with a programmable word line and a CPODE. The polysilicon line is spaced apart from the CPODE and intersects with either the first active region 515 or the second active region 520. Additionally, layout 500 provides a cross arrangement of CPODEs, such that the placement of CPODEs alternates between being located on the first active region 515 and being located on the second active region 520, as discussed above. Part 505 also includes one or more metals on a diffusion layer to connect the first active region 515 to the second active region 520, while preventing or reducing / minimizing leakage to / from adjacent antifuse cells.

[0110] Compared to layout 400, layout 500 also includes an additional CPODE 525. In some embodiments, CPODE 525 extends continuously from the first active region 515 to the second active region 520, thereby intersecting both the first and second active regions. In some embodiments, CPODE 525 may be disposed between adjacent programming word lines. For example, CPODE 530A may be disposed between polysilicon line 535A (represented by a combination of polysilicon line and CPODE) and programming word line 535B (also represented by a combination of polysilicon line and CPODE). Similarly, CPODE 530B may be disposed between programming word line 535C and programming word line 535D. Although a single CPODE 525 may be disposed between adjacent programming word lines, in some embodiments, more than one CPODE may be disposed between adjacent programming word lines. CPODE 525 further prevents or reduces / minimizes current leakage to / from adjacent antifuse cells. In some embodiments, each case of CPODE 525 can be side-mounted on either side by a discontinuous metal 540 on the diffusion layer. Therefore, layout 500 includes two sets of discontinuous metals 540 on the diffusion layer between adjacent programmable word lines, rather than... Figure 4 Discontinuous metals on a single diffused layer between adjacent programming word lines (e.g., metal 445A to metal 445F on an oxide layer).

[0111] Despite the above Figures 2 to 5 The layout of a 2T configuration unit (e.g., antifuse unit array 200) is described, but the following... Figure 6 and Figure 7 Describe the layout of the 3T configuration unit. Therefore, refer to... Figure 6 An example antifuse cell array 600 is illustrated according to some embodiments of the present disclosure. The antifuse cell array 600 is a 3T configuration. In other words, the antifuse cell array 600 includes three transistors in each antifuse cell. The antifuse cell array 600 is illustrated as including a first antifuse cell 605 and a second antifuse cell 610 in a cell row extending in the X direction. Although only two antifuse cells are illustrated in the antifuse cell array 600 in a cell row, in other embodiments, more than two antifuse cells may be included in the antifuse cell array in a cell row. Furthermore, although only a single cell row of antifuse cells is illustrated in the antifuse cell array 600, in other embodiments, multiple cell rows may be provided, each cell row having multiple antifuse cells.

[0112] Each of the first antifuse cell 605 and the second antifuse cell 610 is connected to bit line 615. When multiple cell rows are provided, each cell row can be connected to a bit line, thereby having multiple bit lines in the antifuse cell array 600. Additionally, each of the first antifuse cell 605 and the second antifuse cell 610 includes a programming transistor and two read transistors. For example, the first antifuse cell 605 includes a first read transistor 620 and a second read transistor 625, as well as a programming transistor 630. Similarly, the second antifuse cell 610 includes a first read transistor 635, a second read transistor 640, and a programming transistor 645. A first terminal (e.g., source or drain) of the first read transistor 620 of the first antifuse cell 605 is connected to bit line 615, while a second terminal (e.g., drain or source) of the first read transistor is connected to a first terminal (e.g., drain or source) of the second read transistor 625. A second terminal (e.g., source or drain) of the second read transistor 625 is connected to a first terminal (source or drain) of the programming transistor 630. The second terminal (e.g., drain or source) of the programmable transistor 630 is floating. The second antifuse unit 610 is similarly connected. Although the various transistors in the first antifuse unit 605 and the second antifuse unit 610 are drawn as n-type transistors, in other embodiments, p-type transistors may be used.

[0113] The gate terminal of each of programming transistors 630 and 645 is connected to a programming word line. For example, the gate terminal of programming transistor 630 is connected to programming word line 650, and the gate terminal of programming transistor 645 is connected to programming word line 655. The gate terminal of each of the read transistors is connected to a read word line. For example, the gate terminal of the first read transistor 620 is connected to the first read word line 660, and the gate terminal of the second read transistor 625 is connected to the second read word line 665. Similarly, the gate terminal of the first read transistor 635 is connected to the first read word line 670, and the gate terminal of the second read transistor 640 is connected to the second read word line 675.

[0114] By using the cross arrangement of CPODEs, the total cell area of ​​the antifuse cell array 600 can be reduced, and current leakage in adjacent antifuse cells can be prevented or at least reduced / minimized, as described below. Figure 7 As discussed in [the text]. Therefore, refer to [the text]. Figure 7An example layout 700 is illustrated according to some embodiments of this disclosure. A portion 705 of layout 700 corresponds to the layout of the first antifuse cell 605. Antifuse cell 610 may be laid out similarly to antifuse cell 605. Layout 700 is similar to layouts 400 and 500, and wherein a cross arrangement of CPODEs is used to reduce the total cell area and to prevent or at least reduce / minimize current leakage to / from adjacent antifuse cells.

[0115] Therefore, in some embodiments, the layout 700 of the first antifuse unit 605 in portion 705 includes a first active region 710 and a second active region 715, and polysilicon lines form the gate terminals of a first read transistor 620 and a second read transistor 625 on the first active region 710 and the second active region 715. For example, the polysilicon line 720 may form the gate terminal of the first read transistor 620, with a first read word line 660 connected to the gate terminal, and the polysilicon line 725 may form the gate terminal of the second read transistor 625, with a second read word line 665 connected to the gate terminal. In some embodiments, the polysilicon lines 720 and 725 extend continuously from the first active region 710 to the second active region 715, thereby intersecting both the first and second active regions.

[0116] In some embodiments, the gate terminal of the programmable transistor 630 (to which the programming word line 650 is connected) may be formed as a combination of a polysilicon line and a CPODE. Therefore, as discussed above, the gate terminal of the programmable transistor 630 may include a polysilicon line 730 and a CPODE 735, each of which intersects with a first active region 710 or a second active region 715. For example, and as... Figure 7 As illustrated, the polysilicon line 730 intersects with the second active region 715, while the CPODE 735 intersects with the first active region 710. Due to the intersecting arrangement of the CPODEs, the second antifuse unit 610 allows its programmable transistor 645's CPODE 740 to intersect with the second active region 715, while the polysilicon line 745 of the programmable transistor can intersect with the first active region 710. Therefore, in some embodiments, the CPODEs alternate between the first active region 710 and the second active region 715 in adjacent antifuse units. Consequently, the polysilicon lines associated with the CPODEs also alternate between the second active region 715 and the first active region 710.

[0117] Additionally, in some embodiments, the first active region 710 and the second active region 715 may be interconnected by one or more diffusion layer on-metals. In some embodiments, diffusion layer on-metals extending continuously from the first active region 710 to the second active region 715 may be disposed between two adjacent read word lines, and between adjacent read word lines and program word lines. Thus, for example, diffusion layer on-metal 750A may be formed between polysilicon lines 720 and 725. Similarly, diffusion layer on-metal 750B may be disposed between polysilicon lines 720 and 755 (which are associated with the first read word line 670 of the second antifuse unit 610). Diffusion layer on-metal 750C may also be disposed between polysilicon line 725 representing the second read word line 665 and polysilicon line 730 / CPODE 735 representing the program word line 650. Thus, diffusion layer on-metals may be disposed between two adjacent read word lines. Metal on the diffusion layer can also be disposed between adjacent read word lines and programmable word lines. "Adjacent read word lines and programmable word lines" means that a polysilicon line (or CPODE) associated with a programmable word line is immediately adjacent to the polysilicon line associated with the read word line without any other intervening polysilicon lines or CPODEs associated with the programmable or read word line. Therefore, for example, polysilicon line 725 and polysilicon line 730 / CPODE 735 are adjacent read word lines and programmable word lines. However, polysilicon line 720 and polysilicon line 730 / CPODE 735 are not adjacent read word lines and programmable word lines.

[0118] On-diffusion layer metals 750A to 750C provide a conductive path between the first active region 710 and the second active region 715. Therefore, in some embodiments, each of the on-diffusion layer metals 750A to 750C intersects with both the first active region 710 and the second active region 715. Thus, the on-diffusion layer metals 750A to 750C are referred to herein as continuous on-diffusion layer metals. In some embodiments, layout 700 may also include discontinuous on-diffusion layer metals between two adjacent programming word lines. Discontinuous on-diffusion layer metals intersect with either the first active region 710 or the second active region 715, but not with both. Discontinuous on-diffusion layer metals provide electrical isolation between the first active region 710 and the second active region 715, thereby preventing leakage to / from adjacent antifuse cells, as discussed above. For example, in some embodiments, layout 700 may include on-layer metal 760A and on-layer metal 760B between programming word lines represented by polysilicon lines 730 and CPODE 735 and adjacent programming word lines 765. On-layer metal 760A intersects only with the second active region 715, while on-layer metal 760B intersects only with the first active region 710. Therefore, current flowing through the polysilicon lines 730 and the second active region 715 is prevented from flowing into the first active region 710.

[0119] In some embodiments, similar to layout 500, an additional CPODE 770 may be provided. In other embodiments, similar to layout 400, CPODE 770 may be omitted. CPODE 770 may intersect with both the first active region 710 and the second active region 715, and may be disposed between two adjacent programming word lines. Additionally, when CPODE 770 is provided, in some embodiments, CPODE may be sandwiched between metals on the diffusion layer, for example, between metals 760A / 760B and metals 775A / 775B on the diffusion layer. When CPODE 770 is not provided, metals 775A / 775B on the diffusion layer may be omitted. Metals 775A / 775B on the diffusion layer are discontinuous layers similar to metals 760A / 760B on the diffusion layer. Therefore, the metal 775A / 775B on the diffusion layer intersects with the first active region 710 or the second active region 715. The CPODE 770 provides additional protection against leakage between adjacent antifuse units. When configured, similar to the CPODE in layout 500, the CPODE 770 is laid out between adjacent programmable word lines.

[0120] Although layout 700 is discussed with respect to the layout of portion 705 and the first antifuse unit 605, a similar layout may be provided for the second antifuse unit 610 and any additional antifuse units in the antifuse unit array 600. Furthermore, although continuous metal on a single diffusion layer is depicted between two adjacent read word lines or between adjacent read word lines and programmable word lines, in some embodiments, multiple metals on the diffusion layer may be disposed in at least some of adjacent read word lines and at least some of adjacent read word lines and programmable word lines. Additionally, although discontinuous metal on a single diffusion layer intersecting a particular active region is depicted between two adjacent programmable word lines or between an additional CPODE (e.g., CPODE 770) and an adjacent programmable word line, in some embodiments, multiple such metals on the diffusion layer may be disposed in either or both locations.

[0121] In some embodiments, one or more unit cells may be defined, and the unit cells may be arranged to form layout 400, layout 500, and layout 700. Figure 8 This illustrates an instance of the defined unit cell, while Figure 9 This illustrates another instance of defining a unit cell.

[0122] Instead refer to Figure 8Another example layout 800 is illustrated according to some embodiments of this disclosure. Layout 800 is similar to layout 400. Layout 800 illustrates the definition of unit cells that can be used to create layout 400. For example, in some embodiments, layout 800 may be created by a combination of a first unit (“A” unit) 805 and a second unit (“B” unit) 810. Each of the first unit 805 and the second unit 810 includes an active region in which source and drain terminals of an antifuse unit are formed, and one or more polysilicon lines and CPODEs for the gate terminals of the antifuse unit. Additionally, each of the first unit 805 and the second unit 810 may represent two bits in a 2T configuration or one bit in a 3T configuration. The first unit 805 may include a CPODE 815 representing the gate terminal of a program word line, a first polysilicon line 820 (“WLR”) representing the gate terminal of a read word line, a second polysilicon line 825 (“WLR”) representing the gate terminal of a read word line, and a third polysilicon line 830 (“WLP”) representing the gate terminal of a program word line. Therefore, the first unit 805 may include CPODE > WLR * 2 > WLP, meaning that CPODE 815 is adjacent to two WLRs (e.g., the first polysilicon line 820 and the second polysilicon line 825), and the two WLRs are in turn adjacent to WLPs (e.g., the third polysilicon line 830).

[0123] The second unit 810 is a combination of a programming word line CPODE 835, a fourth polysilicon line 840 (“WLP”) of another programming word line, a fifth polysilicon line 845 (“WLR”) of a read word line, and a sixth polysilicon line 850 (“WLR”) of another read word line. Therefore, the second unit 810 may contain CPODE > WLP > WLR * 2, meaning that CPODE 835 is adjacent to WLP (e.g., the fourth polysilicon line 840), and WLP is adjacent to two WLRs (e.g., the fifth polysilicon line 845 and the sixth polysilicon line 850). By using a combination of the first unit 805 and the second unit 810 in the X and / or Y directions, a layout 800 with a cross arrangement of CPODEs (e.g., CPODE 815, CPODE 835) can be obtained. Each of the first unit 805 and the second unit 810 may be used once or more in the X or Y directions or both.

[0124] Additionally, the first cell 805 in the first cell row can be shifted to the right in the X direction relative to the second cell 810 in the second cell row by one polysilicon line spacing. The polysilicon line spacing can be defined as the center-to-center distance between a polysilicon line and its adjacent interconnect. For example, in... Figure 8In this configuration, the polysilicon line spacing can be the center-to-center distance between CPODE 815 and polysilicon line 855. Therefore, when creating layout 800 using a combination of first cell 805 and second cell 810, the first cell can be shifted to the right relative to the second cell by one polysilicon spacing. Layout 400 can be obtained by shifting and placing multiple of the first cell 805 and second cell 810. In some embodiments, the first cell 805 and second cell 810 can be defined as standard cells and stored in a standard cell library for use in creating layout 400.

[0125] In some embodiments, the first unit 805 may be shifted to the left in the X direction relative to the second unit by one polysilicon pitch. In other embodiments, depending on the layout, the first unit 805 may be shifted by more than one polysilicon pitch. In some embodiments, the second unit 810 may be shifted relative to the first unit 805 by one or more polysilicon pitches. The first unit 805 and the second unit 810 may also be used to create a 3T configuration layout.

[0126] refer to Figure 9 Example layout 900 is illustrated according to some embodiments of this disclosure. Layout 900 is similar to layout 500. In some embodiments, a first cell 905 (“C” cell) in a first cell row and a second cell 910 (“D” cell) in a second cell row may be defined. Each of the first cell 905 and the second cell 910 may include an active region in which source and drain terminals of an antifuse cell are formed, and one or more polysilicon lines and CPODEs for the gate terminals of the antifuse cell. Layout 500 with a cross arrangement of CPODEs can be obtained by combining the first cell 905 and the second cell 910 placed in the X and Y directions. Each of the first cell 905 and the second cell 910 may represent two bits in a 2T configuration or one bit in a 3T configuration. The first unit 905 may include a first CPODE 915 of additional CPODE 525, a second CPODE 920 of programming word lines, a first polysilicon line 925 (“WLR”) of read word lines, a second polysilicon line 930 (“WLR”) of read word lines, and a third polysilicon line 935 (“WLP”) of programming word lines. Therefore, the first unit 905 may be defined by CPODE*2>WLR*2>WLP, meaning that the first CPODE 915 is adjacent to the second CPODE 920, the second CPODE 920 is adjacent to two WLRs (e.g., the first polysilicon line 925 and the second polysilicon line 930), and the two WLRs are adjacent to the WLP (e.g., the third polysilicon line 935).

[0127] The second unit 910 is a combination of the third CPODE 940, the fourth CPODE 945 of the programming word line, the fourth polysilicon line 950 (“WLP”) of another programming word line, the fifth polysilicon line 955 (“WLR”) of the read word line, and the sixth polysilicon line 960 (“WLR”) of another read word line. Therefore, the second unit 910 can be defined by CPODE*2>WLP>WLR*2, meaning that the third CPODE 940 and the fourth CPODE 945 are adjacent to the WLP (e.g., the fourth polysilicon line 950), and the WLP is in turn adjacent to two WLRs (e.g., the fifth polysilicon line 955 and the sixth polysilicon line 960).

[0128] Additionally, the first cell 905 in the first cell row may be shifted to the right in the X direction relative to the second cell 910 in the second cell row by one polysilicon line pitch. In some embodiments, the first cell 905 may be shifted to the left in the X direction relative to the second cell 910 by one polysilicon pitch. In other embodiments, depending on the layout, the first cell 905 may be shifted relative to the second cell 910 by more than one polysilicon pitch. In some embodiments, the second cell 910 may be shifted relative to the first cell 905 by one or more polysilicon pitches. By using a combination of the first cell 905 and the second cell 910 in the X and / or Y directions, a layout 500 with a CPODE cross arrangement can be obtained. Each of the first cell 905 and the second cell 910 may be used once or more in the X or Y direction or both to obtain the layout 500. In some embodiments, the first cell 905 and the second cell 910 may be defined as standard cells and stored in a standard cell library for use in creating the layout 500. Additionally, the first cell 905 and the second cell 910 may also be used to create a layout 700 with a 3T configuration.

[0129] Therefore, by using a cross arrangement of CPODEs, the total cell area of ​​the antifuse cell array can be reduced (e.g., because active regions can be shared rather than separated). Additionally, current leakage to / from adjacent antifuse cells can be reduced. In some embodiments, CPODEs can be formed with a CPODE degree relative to adjacent polysilicon lines in the substrate. In some embodiments, the CPODE degree can be greater than or equal to 45° and less than or equal to 135°. In other embodiments, other CPODE degrees deemed appropriate may be used.

[0130] According to some aspects of this disclosure, a memory device is disclosed. The memory device includes a first memory cell having: a first polysilicon line associated with a first read word line and intersecting with a first active region and a second active region; a second polysilicon line and a continuous polysilicon line over active region edge (CPODE) associated with a first programming word line, the second polysilicon line intersecting with the second active region and the first CPODE intersecting with the first active region. The memory device further includes a second memory cell adjacent to the first memory cell, the second memory cell having: a third polysilicon line associated with a second read word line and intersecting with both the first and second active regions; and a fourth polysilicon line and a second CPODE associated with the second programming word line, the fourth polysilicon line intersecting with the first active region and the second CPODE intersecting with the second active region to form a cross arrangement of CPODEs.

[0131] In some embodiments, the memory device further includes a third consecutive active region edge polysilicon line and a fourth consecutive active region edge polysilicon line enclosing the first memory cell and the second memory cell, wherein each of the third consecutive active region edge polysilicon line and the fourth consecutive active region edge polysilicon line intersects the first active region and the second active region. In some embodiments, the memory device further includes diffusion layer metal intersecting the first active region and the second active region, wherein the diffusion layer metal is located between two adjacent read word lines. In some embodiments, the memory device further includes diffusion layer metal intersecting the first active region and the second active region, wherein the diffusion layer metal is located between adjacent read word lines and program word lines. In some embodiments, the second polysilicon line is spaced apart from the first consecutive active region edge polysilicon line in a second direction perpendicular to the first direction, and the first active region and the second active region extend in the first direction. In some embodiments, adjacent program word lines are separated by diffusion layer metal intersecting the first active region or the second active region. In some embodiments, adjacent programming word lines are further separated by polysilicon lines on the edges of a third consecutive active region that intersects the first and second active regions. In some embodiments, the first memory cell further includes a fifth polysilicon line associated with a third read word line and intersecting the first and second active regions, and wherein the second memory cell includes a sixth polysilicon line associated with a fourth read word line and intersecting the first and second active regions.

[0132] According to some other aspects of this disclosure, a memory cell is disclosed. The memory cell includes: a first transistor having a read word line connected to a first gate terminal of the first transistor; and a second transistor having a programmable word line connected to a second gate terminal of the second transistor. The first gate terminal includes a first polysilicon line intersecting a first active region and a second active region, and the second gate terminal includes a combination of a second polysilicon line intersecting the second active region and a continuous active region edge polysilicon line (CPODE) intersecting the first active region. The first active region and the second active region extend in a first direction, and the first polysilicon line, the second polysilicon line, and the CPODE extend in a second direction perpendicular to the first direction.

[0133] In some embodiments, the second polysilicon line is aligned with and spaced apart from the polysilicon lines on the edges of the continuous active regions in the second direction. In some embodiments, the memory cell further includes a metal on a diffusion layer extending in the second direction between the first and second polysilicon lines and intersecting the first and second active regions. In some embodiments, the memory cell further includes a third transistor having a second read word line connected to a third gate terminal of the third transistor, wherein the third gate terminal includes a third polysilicon line extending in the second direction and intersecting the first and second active regions. In some embodiments, the memory cell further includes additional polysilicon lines on the edges of the continuous active regions extending in the second direction and intersecting the first and second active regions.

[0134] According to another aspect of this disclosure, a method is disclosed. The method includes: placing a first cell in a first cell row having a first active region extending in a first direction, the first cell having a polysilicon line (CPODE) on a first continuous active region edge, a first polysilicon line associated with a first read word line, a second polysilicon line associated with a second read word line, and a third polysilicon line associated with a first programmable word line. The method further includes: placing a second cell in a second cell row having a second active region extending in the first direction, the second cell having a second CPODE, a fourth polysilicon line associated with a second programmable word line, a fifth polysilicon line associated with a third read word line, and a sixth polysilicon line associated with the fourth read word line. The first cell is shifted relative to the second cell in the first direction by a polysilicon line spacing.

[0135] In some embodiments, the first unit further includes a third continuous active region edge polysilicon line adjacent to the first continuous active region edge polysilicon line. In some embodiments, the second unit further includes a third continuous active region edge polysilicon line adjacent to the second continuous active region edge polysilicon line. In some embodiments, the first continuous active region edge polysilicon line is formed relative to the first polysilicon line with a continuous active region edge polysilicon line degree, wherein the continuous active region edge polysilicon line degree is greater than or equal to 45° and less than or equal to 135°. In some embodiments, the second continuous active region edge polysilicon line is formed relative to the fourth polysilicon line with a continuous active region edge polysilicon line degree, wherein the continuous active region edge polysilicon line degree is greater than or equal to 45° and less than or equal to 135°. In some embodiments, after the first unit and the second unit are placed in the layout, the first polysilicon line is connected to the fifth polysilicon line in a second direction perpendicular to the first direction, and the second polysilicon line is connected to the sixth polysilicon line in the second direction. In some embodiments, the method for creating a standard cell layout for an integrated circuit further includes placing a first diffusion layer on metal between a polysilicon line at the edge of the first continuous active region and the first polysilicon line, placing a second diffusion layer on metal between the first polysilicon line and the second polysilicon line, and placing a third diffusion layer on metal between the second polysilicon line and the third polysilicon line.

[0136] The foregoing summary outlines features of several embodiments to enable those skilled in the art to better understand aspects of this disclosure. Those skilled in the art will understand that this disclosure can be readily used as a basis for designing or modifying other processes and structures for achieving the same purposes and / or benefits as the embodiments described herein. Those skilled in the art will also recognize that such equivalent constructions do not depart from the spirit and scope of this disclosure, and that various changes, substitutions, and modifications can be made herein without departing from the spirit and scope of this disclosure.

Claims

1. A memory device, comprising: The first storage unit includes: A first polysilicon line, associated with a first read word line and intersecting with a first active region and a second active region; and The second polysilicon line and the polysilicon line on the edge of the first continuous active region are associated with the first programming word line, the second polysilicon line intersects the second active region and the polysilicon line on the edge of the first continuous active region intersects the first active region; and A second storage unit, adjacent to the first storage unit, includes: A third polysilicon line is associated with the second read word line and intersects with the first active region and the second active region; and The fourth polysilicon line and the second polysilicon line on the edge of the continuous active region are associated with the second programming word line. The fourth polysilicon line intersects with the first active region and the second polysilicon line on the edge of the continuous active region intersects with the second active region to form a cross arrangement of polysilicon lines on the edge of the continuous active region.

2. The memory device according to claim 1, further comprising: Polysilicon lines on the edges of a third consecutive active region and a fourth consecutive active region, which enclose the first memory cell and the second memory cell, intersect with the first active region and the second active region, respectively.

3. The memory device according to claim 1, further comprising: Metal on the diffusion layer that intersects with the first active region and the second active region, wherein the metal on the diffusion layer is located between two adjacent read word lines.

4. The memory device according to claim 1, further comprising: Metal on the diffusion layer intersecting the first active region and the second active region, wherein the metal on the diffusion layer is located between adjacent read word lines and programmable word lines.

5. The memory device of claim 1, wherein the second polysilicon line is spaced apart from the polysilicon line on the edge of the first continuous active region in a second direction perpendicular to the first direction, and the first active region and the second active region extend in the first direction.

6. The memory device of claim 1, wherein adjacent programming word lines are separated by metal on a diffusion layer intersecting the first active region or the second active region.

7. The memory device of claim 6, wherein adjacent programming word lines are further separated by polysilicon lines on the edges of a third consecutive active region intersecting the first active region and the second active region.

8. The memory device of claim 1, wherein the first memory cell further comprises a fifth polysilicon line associated with a third read word line and intersecting with the first active region and the second active region, and wherein the second memory cell comprises a sixth polysilicon line associated with a fourth read word line and intersecting with the first active region and the second active region.

9. A storage unit, comprising: A first transistor has a read word line connected to a first gate terminal of the first transistor; as well as The second transistor has a programming word line connected to the second gate terminal of the second transistor. The first gate terminal includes a first polysilicon line that intersects with the first active region and the second active region; The second gate terminal includes a combination of a second polysilicon line intersecting the second active region and a polysilicon line on the edge of a continuous active region intersecting the first active region; and The first active region and the second active region extend in a first direction, and the first polysilicon line, the second polysilicon line, and the polysilicon line on the edge of the continuous active region extend in a second direction perpendicular to the first direction.

10. The memory cell of claim 9, wherein the second polysilicon line is aligned and spaced apart from the polysilicon lines on the edge of the continuous active region in the second direction.

11. The storage unit according to claim 9, further comprising: The metal on the diffusion layer extends in the second direction between the first polysilicon line and the second polysilicon line and intersects with the first active region and the second active region.

12. The storage unit according to claim 9, further comprising: A third transistor having a second read word line connected to a third gate terminal of the third transistor, wherein the third gate terminal includes a third polysilicon line extending in the second direction and intersecting the first active region and the second active region.

13. The storage unit according to claim 9, further comprising: Polysilicon lines extending in the second direction and intersecting the first and second active regions on the edges of additional continuous active regions.

14. A memory device, comprising: The first antifuse memory unit includes: A first polysilicon line is associated with a first programming word line of the first antifuse memory cell, wherein the first polysilicon line intersects with a first active region; and A polysilicon line on the edge of a first continuous active region, wherein the polysilicon line on the edge of the first continuous active region intersects with a second active region; and A second antifuse memory cell is adjacent to the first antifuse memory cell, and the second antifuse memory cell includes: A second polysilicon line is associated with a second programming word line of the second antifuse memory cell, wherein the second polysilicon line intersects with the second active region; and Polysilicon lines on the edge of a second continuous active region, wherein the polysilicon lines on the edge of the second continuous active region intersect with the first active region to form a cross arrangement of polysilicon lines on the edge of the continuous active region.

15. The memory device of claim 14, wherein the first antifuse memory cell further comprises a third polysilicon line associated with the first read word line, and wherein the third polysilicon line intersects with the first active region and the second active region.

16. The memory device of claim 14, wherein the second antifuse memory cell further comprises a third polysilicon line associated with the second read word line, and wherein the third polysilicon line intersects the first active region and the second active region.

17. The memory device of claim 14, further comprising: Polysilicon lines on the edges of the third and fourth consecutive active regions that enclose the first and second antifuse memory cells are provided, wherein each of the third and fourth consecutive active region polysilicon lines intersects with the first and second active regions.

18. The memory device of claim 14, wherein the first polysilicon line is spaced apart from the polysilicon line on the edge of the first continuous active region in a second direction perpendicular to the first direction, and the first active region and the second active region extend in the first direction.

19. The memory device of claim 14, wherein adjacent programming word lines are separated by metal on a diffusion layer intersecting the first active region or the second active region.

20. The memory device of claim 14, wherein the first active region and the second active region are spaced apart in a second direction perpendicular to the first direction, and the first active region and the second active region extend in the first direction.

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