Semiconductor devices and amplifiers

Abstract

The present invention provides a semiconductor device and amplifier that reduce the inductance of a bonding wire. The semiconductor device comprises: a ground plane; a capacitor disposed on the ground plane and having a first upper surface; a semiconductor chip disposed on the ground plane and having a second upper surface; a bonding wire connecting the first upper surface and the second upper surface; and at least one conductive member disposed on the ground plane and electrically connected to the ground plane, wherein, when viewed from above relative to the ground plane, the bonding wire extends in a first direction and a direction orthogonal to the first direction is a second direction, the conductive member is positioned away from the bonding wire in the second direction when viewed from above.

Description

Technical Field

[0001] The present disclosure relates to a semiconductor device. Background Art

[0002] An electronic circuit is known, comprising: a dielectric substrate provided on a ground conductor surface; a semiconductor substrate provided on the ground conductor surface; bonding wires connecting a wiring pattern on the dielectric substrate and an electrode on the semiconductor substrate; and a metal block electrically connected to the ground conductor surface. In this electronic circuit, the metal block is arranged below the bonding wire (for example, see Patent Document 1). Figure 7 ).

[0003] Prior art literature

[0004] Patent Literature

[0005] Patent Document 1: Japanese Patent Application Laid-Open No. 2012-151694 Summary of the Invention

[0006] Problems to be solved by the invention

[0007] If the inductance of the bonding wire increases, the phase of the signal passing through the bonding wire shifts, and desired characteristics related to signal transmission may not be obtained.

[0008] The present disclosure provides a semiconductor device and an amplifier capable of reducing the inductance of a bonding wire.

[0009] Technical solutions to problems

[0010] The present disclosure provides a semiconductor device comprising:

[0011] ground plane;

[0012] a capacitor disposed on the ground plane and having a first upper surface;

[0013] a semiconductor chip disposed on the ground plane and having a second upper surface;

[0014] a bonding wire connecting the first upper surface and the second upper surface; and

[0015] at least one conductive member disposed on the ground plane and electrically connected to the ground plane,

[0016] When the bonding wire extends in a first direction and a direction perpendicular to the first direction is defined as a second direction in a plan view relative to the ground plane, the conductive member is positioned away from the bonding wire in the second direction in the plan view.

[0017] In addition, the present disclosure provides an amplifier comprising:

[0018] ground plane;

[0019] a first capacitor disposed on the ground plane and having a first upper surface;

[0020] a first transistor disposed above the ground plane and having a second upper surface;

[0021] at least one first bonding wire connecting the first upper surface and the second upper surface;

[0022] at least one conductive member disposed on the ground plane and electrically connected to the ground plane;

[0023] a second capacitor disposed on the ground plane and having a third upper surface;

[0024] a second transistor disposed above the ground plane and having a fourth upper surface;

[0025] a plurality of second bonding wires connecting the third upper surface and the fourth upper surface; and

[0026] A substrate is provided on the ground plane and has a space extending through the ground plane.

[0027] the first transistor and the second transistor are connected in parallel to each other via the first capacitor and the second capacitor,

[0028] The first transistor is of a lower output type than the second transistor,

[0029] The number of the first bonding wires is smaller than the number of the second bonding wires.

[0030] When the first bonding wire extends in a first direction and a direction perpendicular to the first direction is defined as a second direction in a plan view relative to the ground plane, the conductive member is positioned away from the first bonding wire in the second direction in the plan view.

[0031] Effects of the Invention

[0032] According to the present disclosure, it is possible to provide a semiconductor device and an amplifier capable of reducing the inductance of a bonding wire. BRIEF DESCRIPTION OF THE DRAWINGS

[0033] Figure 1 It is a perspective view showing a structural example of the semiconductor device in the first embodiment.

[0034] Figure 2 It is a plan view showing a structural example of the semiconductor device in the first embodiment.

[0035] Figure 3 It is a plan view showing a structural example (modification example) of the semiconductor device in the first embodiment.

[0036] Figure 4 This is a diagram showing a first example of the positional relationship between the conductive member and the bonding wire.

[0037] Figure 5 This is a diagram showing a second example of the positional relationship between the conductive member and the bonding wire.

[0038] Figure 6 This is a diagram showing a third example of the positional relationship between the conductive member and the bonding wire.

[0039] Figure 7 It is a plan view showing a structural example of a semiconductor device in the second embodiment.

[0040] Figure 8 It is a cross-sectional view showing a structural example of a semiconductor device in the second embodiment.

[0041] Figure 9 This is a circuit block diagram showing a configuration example of an amplifier in one embodiment.

[0042] Figure 10 This is a circuit diagram showing a configuration example of a portion of an amplifier in one embodiment.

[0043] Figure 11 This is a table showing an example of simulation results.

[0044] Figure 12 This is a graph showing an example of simulation results. DETAILED DESCRIPTION

[0045] [Description of Embodiments of the Present Disclosure]

[0046] First, embodiments of the present disclosure are listed for description.

[0047] (1) A semiconductor device according to one embodiment of the present invention includes:

[0048] ground plane;

[0049] a capacitor disposed on the ground plane and having a first upper surface;

[0050] a semiconductor chip disposed on the ground plane and having a second upper surface;

[0051] a bonding wire connecting the first upper surface and the second upper surface; and

[0052] at least one conductive member disposed on the ground plane and electrically connected to the ground plane,

[0053] In a plan view relative to the ground plane, the direction in which the bonding line extends is defined as a first direction, and a direction perpendicular to the first direction is defined as a second direction.

[0054] The conductive member is located at a position separated from the bonding wire in the second direction in the plan view.

[0055] According to (1), the conductive member is located at a position separated from the bonding wire in the second direction when viewed from above. Therefore, at least a portion of the magnetic lines of force (magnetic field) generated concentrically around the bonding wire is blocked by the conductive member. By blocking at least a portion of the magnetic field generated by the bonding wire by the conductive member, the inductance of the bonding wire can be reduced.

[0056] In addition, the bonding wire is bent in a manner protruding upward. Therefore, in a manner in which the metal block is located only below the bonding wire (for example, the method of Patent Document 1), Figure 7 ), in order to improve the effect of reducing the inductance of the bonding wire, it is required to deform the upper end of the metal block into a shape that is bent in a manner that protrudes upward. However, such a bending deformation is difficult in terms of manufacturing and cost. In contrast, in the method (1), since the conductive member is located at a position separated from the bonding wire in the second direction, even if the conductive member is not deformed as described above, it is possible to easily bring the conductive member close to the bonding wire (especially the top portion that protrudes upward). Therefore, the method (1) can easily reduce the inductance of the bonding wire compared to the method in which the metal block is only located below the bonding wire.

[0057] In addition, in the case where the metal block is located only below the bonding wire (for example, the method of Patent Document 1), Figure 7 ) is difficult to assemble the bonding wire unless the metal block is installed. In contrast, in the embodiment (1), since the conductive member is located at a position separated from the bonding wire in the second direction when viewed from above, the bonding wire can be assembled either before or after the conductive member is installed. This improves the degree of freedom in manufacturing the semiconductor device.

[0058] (2) The shortest distance from the conductive member to the top of the bonding wire may be less than the shortest distance from the ground plane to the top.

[0059] According to (2), since the conductive member is close to the bonding wire, the area where the magnetic field generated from the bonding wire is blocked by the conductive member becomes larger. Therefore, the inductance of the bonding wire can be further reduced.

[0060] (3) A mode may be adopted in which the maximum height of the conductive member from the ground plane is equal to or greater than the height of the top of the bonding wire from the ground plane.

[0061] According to (3), since the magnetic field from the top of the bonding wire to the upper side is partially blocked by the conductive member, the area where the magnetic field generated from the bonding wire is blocked by the conductive member becomes larger. Therefore, the inductance of the bonding wire can be further reduced.

[0062] (4) The conductive member may be located between the capacitor and the semiconductor chip in the plan view.

[0063] According to (4), since the conductive member is close to the bonding wire, the area where the magnetic field generated from the bonding wire is blocked by the conductive member becomes larger. Therefore, the inductance of the bonding wire can be further reduced.

[0064] (5) The conductive member may overlap at least a portion of the bonding wire when viewed from the side in the second direction.

[0065] According to (5), since the area where the magnetic field generated concentrically around at least a portion of the bonding wire is blocked by the conductive member becomes larger, the inductance of the bonding wire can be further reduced.

[0066] (6) The conductive member may overlap at least a top portion of the bonding wire when viewed from the side in the second direction.

[0067] According to (6), since the area where the magnetic field generated concentrically with the top of the bonding wire as the center is blocked by the conductive member becomes larger, the inductance of the bonding wire can be further reduced.

[0068] (7) In the plan view, when the direction opposite to the second direction is set as the third direction,

[0069] For example,

[0070] The first conductive member included in the conductive member is located at a position separated from the bonding line in the second direction in the plan view.

[0071] The second conductive member included in the conductive member is located at a position separated from the bonding wire in the third direction in the plan view.

[0072] According to (7), the magnetic field generated by the bonding wire in the second direction is partially blocked by the first conductive member, and the magnetic field generated by the bonding wire in the third direction is partially blocked by the second conductive member. This increases the area over which the conductive member blocks the magnetic field generated by the bonding wire, thereby further reducing the inductance of the bonding wire.

[0073] (8) A method may be adopted in which a substrate is provided on the ground plane and has a space extending through the ground plane.

[0074] The conductive member, the bonding wire, the capacitor, and the semiconductor chip are arranged in the space.

[0075] According to (8), since the conductive member, the bonding wire, the capacitor, and the semiconductor chip are arranged in the space, even if a substrate is additionally provided on the ground plane, an increase in the thickness of the semiconductor device in the planar view can be suppressed.

[0076] (9) Alternatively, the semiconductor chip may be a transistor.

[0077] According to (9), since the capacitor and the bonding wire can be used to match the impedance seen from the transistor, impedance matching can be performed for the fundamental wave and higher harmonics of the signal passing through the transistor. By reducing the inductance of the bonding wire, the increase in the dispersion of the impedance with respect to the second harmonic can be suppressed. As a result, impedance matching with respect to the second harmonic can be performed with high precision over a wide frequency band, thereby expanding the frequency range in which the desired amplification efficiency of the transistor is achieved.

[0078] (10) An amplifier according to one embodiment of the present disclosure includes:

[0079] ground plane;

[0080] a first capacitor disposed on the ground plane and having a first upper surface;

[0081] a first transistor disposed above the ground plane and having a second upper surface;

[0082] at least one first bonding wire connecting the first upper surface and the second upper surface;

[0083] at least one conductive member disposed on the ground plane and electrically connected to the ground plane;

[0084] a second capacitor disposed on the ground plane and having a third upper surface;

[0085] a second transistor disposed above the ground plane and having a fourth upper surface;

[0086] a plurality of second bonding wires connecting the third upper surface and the fourth upper surface; and

[0087] A substrate is provided on the ground plane and has a space extending through the ground plane.

[0088] The conductive member, the first capacitor, the first transistor, the first bonding wire, the second capacitor, the second transistor, and the second bonding wire are arranged in the space.

[0089] the first transistor and the second transistor are connected in parallel to each other via the first capacitor and the second capacitor,

[0090] The first transistor is of a lower output type than the second transistor,

[0091] The number of the first bonding wires is smaller than the number of the second bonding wires.

[0092] In a plan view relative to the ground plane, the direction in which the first bonding line extends is defined as a first direction, and a direction perpendicular to the first direction is defined as a second direction.

[0093] The conductive member is located at a position separated from the first bonding wire in the second direction in the plan view.

[0094] According to (10), the conductive member is located at a position separated from the first bonding wire in the second direction when viewed from above. Therefore, at least a portion of the magnetic lines of force (magnetic field) generated concentrically around the first bonding wire is blocked by the conductive member. By blocking at least a portion of the magnetic field generated by the first bonding wire by the conductive member, the inductance of the first bonding wire can be reduced.

[0095] Furthermore, according to (10), since the impedance viewed from the first transistor is matched using the first capacitor and the first bonding wire, impedance matching can be performed for the fundamental wave and higher harmonics of the signal passing through the first transistor. Since the impedance viewed from the second transistor can be matched using the second capacitor and the second bonding wire, impedance matching can be performed for the fundamental wave and higher harmonics of the signal passing through the second transistor.

[0096] In addition, in (10), the first transistor is of a low-output type compared to the second transistor, and the number of the first bonding wires is smaller than the number of the second bonding wires. Therefore, the change in the inductance of the first bonding wire has a greater impact on the impedance matching of the higher harmonics than the change in the inductance of the second bonding wire. However, according to (10), by reducing the inductance of the first bonding wire, it is possible to suppress the increase in the dispersion of the impedance of the second harmonic relative to the signal passing through the first transistor. As a result, it is possible to perform impedance matching for the second harmonic with high precision over a wide bandwidth, thereby expanding the frequency range in which the desired amplification efficiency of the first transistor is achieved. As a result, it is possible to realize a wide-band amplifier for achieving the desired amplification efficiency.

[0097] In addition, in the case where the metal block is located only below the bonding wire (for example, the method of Patent Document 1), Figure 7 ) is difficult to assemble the bonding wire unless the metal block is installed. In contrast, in the embodiment (10), since the conductive member is located at a position separated from the first bonding wire in the second direction in the plan view, the first bonding wire can be assembled either before or after the conductive member is installed. Therefore, the degree of freedom in manufacturing the amplifier is increased.

[0098] Next, specific examples of semiconductor devices and amplifiers in the embodiments of the present disclosure will be described with reference to the accompanying drawings. The present invention is not limited to these examples but is defined by the claims and is intended to include all modifications within the meaning and scope of the claims.

[0099] [Details of the embodiments of the present disclosure]

[0100] Figure 1 It is a perspective view showing a structural example of the semiconductor device in the first embodiment. Figure 2 1 is a plan view showing a configuration example of a semiconductor device in the first embodiment. Figure 1 and Figure 2 , a structural example of the semiconductor device in the first embodiment is described.

[0101] In addition, for ease of understanding, the scales of the components in the accompanying drawings are sometimes different from the actual ones. In the embodiments of the present disclosure, a three-dimensional rectangular coordinate system of three-axis directions (X-axis direction, Y-axis direction, and Z-axis direction) is used. For parallel, right-angled, orthogonal, horizontal, vertical, up and down, left and right directions, a degree of offset that does not damage the effect of the embodiments of the present disclosure is allowed. The X-axis direction, the Y-axis direction, and the Z-axis direction respectively represent the direction parallel to the X-axis, the direction parallel to the Y-axis, and the direction parallel to the Z-axis. The X-axis direction, the Y-axis direction, and the Z-axis direction are orthogonal to each other. The XY plane, the YZ plane, and the ZX plane respectively represent an imaginary plane parallel to the X-axis direction and the Y-axis direction, an imaginary plane parallel to the Y-axis direction and the Z-axis direction, and an imaginary plane parallel to the Z-axis direction and the X-axis direction.

[0102] Figure 1 、 Figure 2 The semiconductor device 101 shown includes a ground plane 10 , a capacitor 20 , a semiconductor chip 30 , a bonding wire 40 , a first conductive member 50 , and a second conductive member 60 .

[0103] The ground plane 10 is a conductor surface for grounding. The ground plane 10 is, for example, the surface of a conductor plate or a conductor film made of copper or the like.

[0104] Capacitor 20 is an element disposed on ground plane 10 and has a first upper surface 21. Capacitor 20 is, for example, a diode capacitor (Japanese: ダイキャパシタ) having a back electrode in contact with ground plane 10. Because the back electrode of capacitor 20 is in contact with ground plane 10, the back electrode of capacitor 20 is grounded to ground plane 10, and heat from capacitor 20 is dissipated to ground plane 10. Capacitor 20 has a first electrode 22 formed on first upper surface 21. Capacitor 20 has a capacitance portion between first electrode 22 and the back electrode.

[0105] Semiconductor chip 30 is an element disposed on ground plane 10 and has a second upper surface 31. Semiconductor chip 30 has a back surface electrode in contact with ground plane 10. Because the back surface electrode of semiconductor chip 30 is in contact with ground plane 10, the back surface electrode of semiconductor chip 30 is grounded to ground plane 10, and heat from semiconductor chip 30 is dissipated to ground plane 10. Semiconductor chip 30 has a second electrode 32 formed on second upper surface 31.

[0106] Semiconductor chip 30 is, for example, a transistor such as a GaN (gallium nitride) device. Compared to other semiconductor devices (such as Si-LDMOS (silicon laterally diffused metal oxide semiconductor) or GaAs-FET (gallium arsenide field-effect transistor)), GaN devices have a wide bandgap and high mobility, resulting in excellent high-frequency output characteristics. Semiconductor chip 30 may also be a semiconductor element other than a transistor (such as a diode).

[0107] The bonding wire 40 is a conductor that connects the first upper surface 21 and the second upper surface 31. The bonding wire 40 has a first end 41 electrically connected to the first electrode 22 on the first upper surface 21 and a second end 42 electrically connected to the second electrode 32 on the second upper surface 31. The bonding wire 40 has a top 43 that is farthest from the ground plane 10 and is bent at the top 43 as the vertex.

[0108] The first conductive member 50 and the second conductive member 60 are disposed on the ground plane 10 and are electrically connected to the ground plane 10. Figure 1 The outer shape shown is a rectangular parallelepiped, but other shapes are also possible. The first conductive member 50 and the second conductive member 60 each have a surface facing the bonding wire 40. Figure 1 In the embodiment shown, there are surfaces parallel to the ZX plane.

[0109] The first and second conductive members 50 and 60 may not have conductive interiors as long as at least a portion of their surfaces are covered with a conductive material such as gold plating. The first and second conductive members 50 and 60 are fixed to the ground plane 10 using a conductive adhesive such as silver paste.

[0110] Figure 2 The semiconductor device 101 is shown in a top view relative to the ground plane 10. In the top view relative to the ground plane 10, the direction in which the bonding wire 40 extends is set as a first direction, the direction perpendicular to the first direction is set as a second direction, and the direction opposite to the second direction is set as a third direction. Figure 2 In the example of the first direction, the positive X-axis direction is an example of the first direction, the negative Y-axis direction is an example of the second direction, and the positive Y-axis direction is an example of the third direction. Figure 2 In FIG. 1 , the top view relative to the ground plane 10 refers to a viewpoint viewed from the normal direction (Z-axis direction) of the ground plane 10 .

[0111] The first conductive member 50 is positioned away from the bonding wire 40 in the negative Y-axis direction when viewed from above the ground plane 10, and the second conductive member 60 is positioned away from the bonding wire 40 in the positive Y-axis direction when viewed from above the ground plane 10. Therefore, the first conductive member 50 blocks the magnetic field generated from the bonding wire 40 on the negative Y-axis side, while the second conductive member 60 blocks the magnetic field generated from the bonding wire 40 on the positive Y-axis side. Thus, the magnetic field generated from the bonding wire 40 is blocked by the first conductive member 50 and the second conductive member 60, located on both sides of the bonding wire 40. Consequently, the inductance of the bonding wire 40 is reduced to a greater extent than in a configuration in which a conductive member is disposed only on one side of the bonding wire 40 (e.g., a configuration in which the second conductive member 60 is absent).

[0112] It is also possible to omit one of the first conductive member 50 and the second conductive member 60. In this embodiment, the inductance of the bonding wire 40 can be reduced by the remaining conductive member.

[0113] The number of first conductive members 50 located at a position spaced apart from the side surface on the negative Y-axis direction of the bonding wire 40 in the negative Y-axis direction is not limited to one and may be multiple. The number of second conductive members 60 located at a position spaced apart from the side surface on the positive Y-axis direction of the bonding wire 40 in the positive Y-axis direction is not limited to one and may be multiple.

[0114] At least one of the first conductive member 50 and the second conductive member 60 is located, for example, between the capacitor 20 and the semiconductor chip 30 when viewed from above the ground plane 10. As a result, since the at least one conductive member is close to the bonding wire 40, the area where the magnetic field generated by the bonding wire 40 is blocked by the at least one conductive member becomes larger. Therefore, the inductance of the bonding wire 40 can be further reduced. Figure 2 In the illustrated embodiment, both the first conductive member 50 and the second conductive member 60 are located between the capacitor 20 and the semiconductor chip 30 in a plan view relative to the ground plane 10 .

[0115] Figure 3 FIG is a top view showing a structural example (modification) of the semiconductor device in the first embodiment. Figure 3 As shown, both the first conductive member 50 and the second conductive member 60 may not be located between the capacitor 20 and the semiconductor chip 30 when viewed from above the ground plane 10. Figure 3 In the embodiment shown, the magnetic field portion on the negative Y-axis direction side of the magnetic field generated by the bonding wire 40 is blocked by the first conductive member 50, and the magnetic field portion on the positive Y-axis direction side of the magnetic field generated by the bonding wire 40 is blocked by the second conductive member 60. Figure 3 In the illustrated embodiment, the inductance of the bonding wire 40 can also be reduced.

[0116] exist Figure 1 and Figure 2For example, the shortest distance d1 from the first conductive member 50 to the top 43 of the bonding wire 40 is less than the shortest distance from the ground plane 10 to the top 43 (for example, the height h0 from the ground plane 10 to the lower surface of the top 43). As a result, since the first conductive member 50 is close to the bonding wire 40, the area where the magnetic field generated by the bonding wire 40 is blocked by the first conductive member 50 becomes larger. Therefore, the inductance of the bonding wire 40 can be further reduced. Similarly, the shortest distance d2 from the second conductive member 60 to the top 43 of the bonding wire 40 can also be less than the shortest distance from the ground plane 10 to the top 43 (for example, the height h0 from the ground plane 10 to the lower surface of the top 43). As a result, the inductance of the bonding wire 40 can be further reduced.

[0117] Figure 4 1 is a diagram showing a first example of the positional relationship between the conductive member and the bonding wire. Figure 4 As shown, the maximum height h5 of the first conductive member 50 from the ground plane 10 may also be less than the height of the top 43 of the bonding wire 40 from the ground plane 10 (for example, the height h0 from the ground plane 10 to the lower surface of the top 43). Figure 4 In the illustrated embodiment as well, the magnetic field generated concentrically around the top portion 43 can be blocked by the first conductive member 50 , thereby reducing the inductance of the bonding wire 40 .

[0118] like Figure 4 As shown, the maximum height h6 of the second conductive member 60 from the ground plane 10 may be smaller than the height of the top 43 of the bonding wire 40 from the ground plane 10 (for example, the height h0 from the ground plane 10 to the lower surface of the top 43). Similar to the first conductive member 50, the inductance of the bonding wire 40 can be reduced.

[0119] Figure 5 : is a diagram showing a second example of the positional relationship between the conductive member and the bonding wire. Figure 5 As shown, the maximum height h5 of the first conductive member 50 from the ground plane 10 may be greater than the height h0 and less than the height h3. The height h0 represents the height from the ground plane 10 to the lower surface of the top 43, and the height h3 represents the height from the ground plane 10 to the upper surface of the top 43. Figure 5 In the embodiment shown, the first conductive member 50 can also block the magnetic field generated concentrically around the top portion 43, thereby reducing the inductance of the bonding wire 40. Similarly, even if the maximum height h6 of the second conductive member 60 from the ground plane 10 is set to be greater than the height h0 and less than the height h3, the inductance of the bonding wire 40 can be reduced.

[0120] Figure 6 : is a diagram showing a third example of the positional relationship between the conductive member and the bonding wire. Figure 6As shown in FIG. 1 , the maximum height h5 of the first conductive member 50 from the ground plane 10 may also be greater than the height h3. Figure 6 In the embodiment shown, the first conductive member 50 can also block the magnetic field generated concentrically around the top portion 43, thereby reducing the inductance of the bonding wire 40. Similarly, even if the maximum height h6 of the second conductive member 60 from the ground plane 10 is set to be greater than the height h3, the inductance of the bonding wire 40 can be reduced.

[0121] Figure 7 It is a plan view showing a structural example of a semiconductor device in the second embodiment. Figure 8 2 is a cross-sectional view showing a configuration example of a semiconductor device in a second embodiment. Figure 7 and Figure 8 , a configuration example of a semiconductor device in the second embodiment will be described. The description of the same configuration as in the above embodiment will be omitted or simplified by citing the above description.

[0122] Figure 7 、 8 The semiconductor device 102 shown includes a conductor plate 11, a capacitor 120, a first transistor 130, a bonding wire 40, a first conductive member 50, a second conductive member 60, and a substrate 12. The first transistor 130 is an example of a semiconductor chip.

[0123] The upper surface of the conductor plate 11 is the ground plane 10. The conductor plate 11 is, for example, a copper plate.

[0124] Substrate 12 is, for example, a dielectric substrate disposed on ground plane 10. Substrate 12 has a substrate upper surface 13 and a substrate lower surface 14. Substrate lower surface 14 contacts ground plane 10. A space 15 is formed in substrate 12, extending through ground plane 10. Space 15 is, for example, a hole extending from substrate upper surface 13 to substrate lower surface 14, also known as a cavity. Space 15 is not limited to a complete hole and may also be open on its side. Ground plane 10 is exposed through space 15.

[0125] The first conductive member 50, the second conductive member 60, the bonding wire 40, the capacitor 120, and the first transistor 130 are arranged in the space 15. Since the first conductive member 50 and the like are arranged in the space 15, even if the substrate 12 is provided on the ground plane 10, an increase in the thickness of the semiconductor device 102 when viewed from the side can be suppressed.

[0126] In capacitor 120, first electrode 22 and third electrode 23 are formed on first upper surface 21. Capacitor 120 has a first capacitance formed between first electrode 22 and the back electrode and a second capacitance formed between third electrode 23 and the back electrode.

[0127] The bonding wire 140 is a conductor that connects the first electrode 22 and the third electrode 23 , and has a wire end 141 electrically connected to the third electrode 23 and a wire end 142 electrically connected to the first electrode 22 .

[0128] Bonding wire 70 is a conductor that connects substrate upper surface 13 to first upper surface 21, and has wire end 71 electrically connected to electrode 91 on substrate upper surface 13 and wire end 72 electrically connected to third electrode 23 on first upper surface 21. Electrode 91 is electrically connected to input terminal 111 directly or via a member (not shown).

[0129] In the first transistor 130, a second electrode 32 and a fourth electrode 33 are formed on the second upper surface 31. For example, the second electrode 32 is a gate electrode, and the fourth electrode 33 is a drain electrode.

[0130] Bonding wire 80 is a conductor connecting second upper surface 31 to substrate upper surface 13 and has a wire end 81 electrically connected to fourth electrode 33 on second upper surface 31 and a wire end 82 electrically connected to electrode 92 on substrate upper surface 13. Electrode 92 is electrically connected to main output terminal 112.

[0131] exist Figure 8 In the embodiment, the first conductive member 50 and the second conductive member 60 overlap at least a portion of the bonding wire 40 when viewed from the side in the Y-axis direction. This increases the area where the magnetic field generated concentrically around at least a portion of the bonding wire 40 is blocked by the first conductive member 50 and the second conductive member 60, thereby further reducing the inductance of the bonding wire 40.

[0132] exist Figure 8 In the embodiment, the first conductive member 50 and the second conductive member 60 overlap with at least the top portion 43 of the bonding wire 40 when viewed from the side in the Y-axis direction. This increases the area where the magnetic field generated concentrically around the top portion 43 is blocked by the first conductive member 50 and the second conductive member 60, thereby further reducing the inductance of the bonding wire 40.

[0133] Figure 9 This is a circuit block diagram showing a configuration example of an amplifier in one embodiment. The above description is cited, and the same configurations as those in the above embodiment are omitted or simplified. Figure 9 The amplifier 103 shown is a Doherty-type amplifier in which a first transistor 130 and a second transistor 230 are connected in parallel to each other via a first capacitor 120 and a second capacitor 220 .

[0134] The amplifier 103 includes an input circuit having an input terminal 111, a matching circuit 93, a driver amplifier 90, a matching circuit 94, and a divider 99. The amplifier 103 includes a carrier amplifier circuit having a matching circuit 97, a first bonding wire 40, a first transistor 130, a bonding wire 80, a matching circuit 95, and a main output terminal 112. The amplifier 103 includes a peak amplifier circuit having a matching circuit 297, a second bonding wire 240, a second transistor 230, a bonding wire 280, a matching circuit 96, and a peak output terminal 113. The amplifier 103 also includes a first conductive member 50 and a second conductive member 60.

[0135] Matching circuit 97 includes filter section 170, bonding wire 70, and first capacitor 120. Matching circuit 297 includes filter section 270, bonding wire 273, and second capacitor 220. Matching circuit 97 and matching circuit 297 have the same circuit structure.

[0136] like Figure 10 As shown, the filter unit 170 includes an inductor 171 and a capacitor 172, and the filter unit 270 includes an inductor 271 and a capacitor 272. The first capacitor 120 includes a first capacitor unit 121 and a second capacitor unit 122. One end of each of the first capacitor unit 121 and the second capacitor unit 122 is connected to each other via a bonding wire 140. The second capacitor 220 includes a third capacitor unit 221 and a fourth capacitor unit 222. One end of each of the third capacitor unit 221 and the fourth capacitor unit 222 is connected to each other via a bonding wire 241.

[0137] The first conductive member 50, the second conductive member 60, the first capacitor 120, the first transistor 130, the first bonding wire 40, the second capacitor 220, the second transistor 230 and the second bonding wire 240 are arranged in the space 15 (see Figure 7 The above components other than those arranged in the space 15 are mounted on the substrate 12 .

[0138] exist Figure 9In the embodiment, the first transistor 130 is of a low-output type compared to the second transistor 230, and the number of the first bonding wires 40 is less than the number of the second bonding wires 240. The number of the first bonding wires 40 is at least one (for example, one), and the number of the second bonding wires 240 is multiple (for example, two). Therefore, the change in the inductance of the first bonding wire 40 has a greater impact on the impedance matching of the higher harmonics than the change in the inductance of the second bonding wire 240. However, according to the amplifier 103, by reducing the inductance of the first bonding wire 40, the increase in the dispersion of the impedance of the second harmonic of the signal passing through the first transistor 130 can be suppressed. As a result, the impedance matching for the second harmonic can be performed with high precision in a wide bandwidth, thereby expanding the frequency range in which the desired amplification efficiency of the first transistor 130 is achieved. As a result, a wide-band amplifier 103 for achieving the desired amplification efficiency can be achieved.

[0139] The larger the area that blocks the magnetic field generated from the bonding wire, the higher the effect of reducing the inductance of the bonding wire. Therefore, the most effective method is used when the number of bonding wires is small, especially when there is only one bonding wire.

[0140] Figure 11 This is a table showing an example of simulation results. Figure 12 Yes Figure 11 The graph shows an example of simulation results. Figure 11 、 12 Indicates Figure 1 In the structure shown, the inductance (L value) of the bonding wire 40 and its reduction amount are shown when both the shortest distances d1 and d2 are changed while the height h0 is fixed at 0.27 mm. Figure 11 The column with h0=0.27mm and d1, d2=∞ indicates the Figure 1 The structure shown here excludes the data for the comparative embodiment (the first and second conductive members 50 and 60). The L value reduction represents the reduction in L value from the comparative embodiment. By making the shortest distances d1 and d2 shorter than the height h0, the L value reduction increases.

[0141] While the embodiments have been described above, it should be understood that various modifications and improvements may be made to the embodiments and details without departing from the spirit and scope of the claims, and that various modifications and improvements may be made, such as combination with or replacement of part or all of other embodiments.

[0142] Description of labels

[0143] 10 Ground plane

[0144] 11 Conductor plate

[0145] 12 substrate

[0146] 13 Upper surface of substrate

[0147] 14 Lower surface of substrate

[0148] 15 Space

[0149] 20 capacitors

[0150] 21 First upper surface

[0151] 22 first electrode

[0152] 23 Third electrode

[0153] 30 semiconductor chips

[0154] 31 Second upper surface

[0155] 32 second electrode

[0156] 33 Fourth electrode

[0157] 40 First bonding line

[0158] 40 bonding wire

[0159] 41 First Line End

[0160] 42 Second line end

[0161] 43 Top

[0162] 50 first conductive member

[0163] 60 second conductive member

[0164] 70 bonding wire

[0165] 71 line end

[0166] 72 line end

[0167] 80 bonding wire

[0168] 81 line end

[0169] 82 line end

[0170] 90 Driver Amplifier

[0171] 91 electrodes

[0172] 92 electrodes

[0173] 93 Matching Circuit

[0174] 94 Matching Circuit

[0175] 95 Matching Circuit

[0176] 96 Matching Circuit

[0177] 97 Matching Circuit

[0178] 99 Distributor

[0179] 101 Semiconductor Devices

[0180] 102 Semiconductor devices

[0181] 103 Amplifier

[0182] 111 Input terminal

[0183] 112 Main output terminals

[0184] 113 Peak output terminal

[0185] 120 First capacitor

[0186] 120 capacitors

[0187] 121 first capacitor unit

[0188] 122 second capacitor unit

[0189] 130 First Transistor

[0190] 140 bonding wire

[0191] 141 line end

[0192] 142 line end

[0193] 170 Filter Unit

[0194] 171 Inductor

[0195] 172 capacitors

[0196] 220 Second capacitor

[0197] 221 Third capacitor unit

[0198] 222 fourth capacitor unit

[0199] 230 Second transistor

[0200] 240 Second bonding line

[0201] 241 bonding wire

[0202] 270 Filter Unit

[0203] 271 Inductor

[0204] 272 capacitors

[0205] 273 bonding wire

[0206] 280 bonding wire

[0207] 297 Matching Circuit

Claims

1. A semiconductor device comprising: ground plane; a capacitor disposed on the ground plane and having a first upper surface; a semiconductor chip disposed on the ground plane and having a second upper surface; a bonding wire connecting the first upper surface and the second upper surface; and at least one conductive member disposed on the ground plane and electrically connected to the ground plane, When the bonding wire extends in a first direction and a direction perpendicular to the first direction is defined as a second direction in a plan view relative to the ground plane, the conductive member is positioned away from the bonding wire in the second direction in the plan view.

2. The semiconductor device according to claim 1, wherein The shortest distance from the conductive member to the top of the bonding wire is less than the shortest distance from the ground plane to the top.

3. The semiconductor device according to claim 1 or 2, wherein The maximum height of the conductive member from the ground plane is greater than or equal to the height of the top of the bonding wire from the ground plane.

4. The semiconductor device according to claim 1 or 2, wherein The conductive member is located between the capacitor and the semiconductor chip in the plan view.

5. The semiconductor device according to claim 1 or 2, wherein The conductive member overlaps with at least a portion of the bonding wire when viewed from the side in the second direction. The semiconductor device according to claim 5 , wherein: The conductive member overlaps with at least a top portion of the bonding wire when viewed from the side in the second direction.

7. The semiconductor device according to claim 1 or 2, wherein In the plan view, when the direction opposite to the second direction is set as the third direction, The first conductive member included in the conductive member is located at a position separated from the bonding line in the second direction in the plan view. The second conductive member included in the conductive member is located at a position separated from the bonding wire in the third direction in the plan view.

8. The semiconductor device according to claim 1 or 2, wherein The semiconductor device includes a substrate provided on the ground plane and having a space extending through the ground plane. The conductive member, the bonding wire, the capacitor, and the semiconductor chip are arranged in the space.

9. The semiconductor device according to claim 1 or 2, wherein The semiconductor chip is a transistor.

10. An amplifier comprising: ground plane; a first capacitor disposed on the ground plane and having a first upper surface; a first transistor disposed above the ground plane and having a second upper surface; at least one first bonding wire connecting the first upper surface and the second upper surface; at least one conductive member disposed on the ground plane and electrically connected to the ground plane; a second capacitor disposed on the ground plane and having a third upper surface; a second transistor disposed above the ground plane and having a fourth upper surface; a plurality of second bonding wires connecting the third upper surface and the fourth upper surface; and A substrate is provided on the ground plane and has a space extending through the ground plane. The conductive member, the first capacitor, the first transistor, the first bonding wire, the second capacitor, the second transistor, and the second bonding wire are arranged in the space. the first transistor and the second transistor are connected in parallel to each other via the first capacitor and the second capacitor, The first transistor is of a lower output type than the second transistor, The number of the first bonding wires is smaller than the number of the second bonding wires. When the first bonding wire extends in a first direction and a direction perpendicular to the first direction is defined as a second direction in a plan view relative to the ground plane, the conductive member is positioned away from the first bonding wire in the second direction in the plan view.

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