PIN mesa diode with overcurrent protection

Abstract

The application is entitled: PIN mesa diode with overcurrent protection. A system includes a pixel, the pixel including a diffusion layer in contact with an absorption layer. The diffusion layer and the absorption layer are in contact with each other along an interface inside a mesa. A groove surrounding the mesa is defined in the absorption layer. An overflow contact is located in the groove.

Description

Background of the Invention 1. Technical Field

[0002] The present disclosure relates to diodes, and more particularly to photodiodes such as used in pixels for imaging. 2. Background Art

[0004] The lower the dark current of the photodiode in an imaging device, the better the image quality. Similarly, the higher the sensitivity of the photodiode in an imaging device, the better the image quality. At high light levels, excess photons generate high currents, which can damage the detector and / or cause more stress on the readout integrated circuit (ROIC). A photodetector array (PDA) with a mesa structure improves the modulation transfer function (MTF) of the imaging device.

[0005] These conventional techniques have been deemed satisfactory for their intended purposes. However, there continues to be a need for improved systems and methods for photodiodes used in imaging devices. The present disclosure provides a solution to this need. Summary of the invention

[0006] A system includes a pixel, the pixel including a diffusion layer in contact with an absorption layer. The diffusion layer and the absorption layer are in contact with each other along an interface inside a mesa. A groove surrounding the mesa is defined in the cap layer and the absorption layer. An overflow contact is located in the groove.

[0007] The overflow contact may surround the mesa. The pixel may be one of a plurality of similar pixels arranged in a grid pattern, wherein the grooves separate each pixel from adjacent ones of the pixels. The overflow contact may be disposed in a base of the grooves, thereby forming an overflow contact grid, wherein the pixel is located in a space of the overflow contact grid between intersection lines of the overflow contact grid.

[0008] The trench may have a base between the sidewalls of the trench, wherein the overflow contact is disposed on the base, and wherein there is a lateral gap on the base between the overflow contact and each of the sidewalls. The overflow contact may be disposed on a transparent conductive oxide (TCO), which in turn contacts the absorber layer. The TCO may include multiple layers of ZnO, TiO2 and / or indium tin oxide (ITO). The TCO may be formed in a gap within the SiNx layer. A contact metal may be electrically connected to the diffusion layer, configured to electrically connect the diffusion layer to a readout integrated circuit (ROIC).

[0009] The overflow contact may be metallic. The cap layer may be deposited on the absorber layer opposite the substrate. The cap layer may include InP. A SiNx layer may be included above the cap layer. The SiNx layer may directly contact the absorber layer within the trench. An anti-reflective layer may be deposited on the substrate opposite the absorber layer. The absorber layer may include InGaAs, wherein the pixel is sensitive to illumination in the infrared wavelength. It is also contemplated that the absorber layer may include Si, wherein the pixel is sensitive to illumination in the visible wavelength.

[0010] A method includes forming trenches in an absorber layer of a pixel array, wherein the trenches are formed in a grid pattern surrounding respective pixels of the pixel array, wherein each pixel is surrounded by the intersection lines of the grid. The method includes forming overflow contacts in the trenches following the grid pattern.

[0011] The method may include depositing a SiNx layer on the absorber layer after forming the trench, wherein forming the overflow contact in the trench is performed after depositing the SiNx layer. Forming the overflow contact in the trench may include forming the overflow contact on a transparent oxide layer (TCO) formed in a gap in the SiNx layer.

[0012] These and other features of the disclosed systems and methods will become more readily apparent to those skilled in the art from the following detailed description of the preferred embodiments taken in conjunction with the accompanying drawings. BRIEF DESCRIPTION OF THE DRAWINGS

[0013] Therefore, those skilled in the art to which the present disclosure relates will readily understand how to make and use the apparatus and methods of the present disclosure without undue experimentation, and preferred embodiments thereof will be described in detail below with reference to certain drawings, in which:

[0014] Figure 1 is a schematic cross-sectional elevation view of an embodiment of a system constructed in accordance with the present disclosure, showing a flooding contact; and

[0015] Figure 2 yes Figure 1 A schematic plan view of a system showing a grid pattern of multiple pixels. DETAILED DESCRIPTION

[0016] Reference will now be made to the accompanying drawings, in which like reference numerals identify similar structural features or aspects of the present disclosure. For purposes of explanation and illustration, and not limitation, Figure 1 A partial view of an embodiment of a system according to the present disclosure is shown in FIG. 1 and generally designated by the reference numeral 100 . Figure 2Other embodiments of the system according to the present disclosure or aspects thereof are provided in, as will be described. The systems and methods described herein can be used to reduce overcurrent, increase sensitivity, and reduce stress on a readout integrated circuit (ROIC) in an imaging device.

[0017] System 100 includes pixel 102 including diffusion layer 104 in contact with absorber layer 106. Diffusion layer 104 and absorber layer 106 contact each other along interface 108 inside mesa 109. A trench 110 is defined in absorber layer 106 surrounding mesa 109. An overflow contact 112 is disposed in trench 110.

[0018] Reference now Figure 2 , pixel 102 is one of a plurality of similar pixels 102 arranged in a square tiled grid pattern 114, Figure 2 1, a portion of the square tiled grid pattern is indicated by reference numeral 114 and an associated dashed line. The trench 110 separates each pixel 102 from adjacent pixels in the pixels 102. An overflow contact 112 surrounds each mesa 109. The overflow contact 112 is disposed in a base 116 of the trench 110 (eg, Figure 1 ), thereby forming an overflow contact grid 118. A portion of the overflow contact grid 118 is Figure 2 The pixels 102 are in the spaces of the overflow contact grid 118 between the intersection lines 120 of the overflow contact grid 118 .

[0019] Reference again Figure 1 , the base 116 of the trench 110 is located between the sidewalls 122 of the trench 110. The overflow contact 112 is disposed on the base 116, and there is a lateral gap 124 between the overflow contact 112 and each of the sidewalls 122 on the base 116. The overflow contact is disposed on a transparent conductive oxide (TCO) 126, which in turn contacts the absorber layer 106. The TCO 126 may include multiple layers of ZnO, TiO2, and / or indium tin oxide (ITO). The film resistivity of the TCO 126 may be designed based on the detector operating conditions, which may be implemented by adjusting the doping level of the TCO 126. The TCO 126 may be formed in the gap 128 within the SiNx layer 130. For each pixel 102 (e.g., such as Figure 2 ), the contact metal 132 is electrically connected between the diffusion layer 104 and the read-out integrated circuit (ROIC) 134. The TCO 126 normally acts as an insulator, but when the current reaches a predetermined maximum level, the resistance barrier of the TCO 126 is broken, and the excess current can flow through the TCO to the common current sink 144 on the ROIC 134.

[0020] Overflow contact 112 can be metallic. A cap layer 136, such as InP, can be deposited on the absorber layer opposite to substrate 138, which can be InP or any other suitable material. A SiNx layer 130 is included above the cap layer. SiNx layer 130 directly contacts absorber layer 106 within trench 110. An anti-reflective layer 140 can optionally be deposited on substrate 138 opposite to absorber layer 106. Absorber layer 106 can include InGaAs, for example, to make pixel 102 sensitive to illumination at infrared wavelengths. It is also contemplated that absorber layer 106 can include Si, for example, to make pixel 102 sensitive to illumination in visible wavelengths. Those skilled in the art will readily appreciate that any other suitable material can be used to provide sensitivity in any other suitable wavelength.

[0021] One method includes including in a pixel array (e.g., Figure 2 A trench (e.g., trench 110) is formed in an absorber layer (e.g., absorber layer 106) of a pixel array 102 having a square tile grid pattern 114 in the pixel array. The trench is arranged in a grid pattern (e.g., trench 110) surrounding corresponding pixels of the pixel array. Figure 2 A grid pattern 114 is formed in which each pixel is separated by an intersection line of the grid (e.g., Figure 2 The method includes forming an overflow contact, for example, overflow contact 112, in the trench following a grid pattern. The method may include depositing a SiNx layer, for example, SiNx layer 130, on the absorption layer after forming the trench, wherein forming the overflow contact in the trench is performed after depositing the SiNx layer. Forming the overflow contact in the trench may include forming the overflow contact on a transparent oxide layer (TCO) (for example, TCO 126) formed in a gap (for example, gap 128) in the SiNx layer. The diffusion layer 104 is the P portion of the PIN diode, the absorption layer 106 is the I portion of the PIN diode, and the substrate 138 is the N portion of the PIN diode.

[0022] The methods and systems of the present disclosure as described above and as shown in the accompanying drawings allow for reduced overcurrent, increased sensitivity, and reduced stress on a readout integrated circuit (ROIC) in an imaging device. This can improve image quality and reduce ROIC design requirements and signal processing complexity compared to conventional configurations. Although the apparatus and methods of the present disclosure have been shown and described with reference to preferred embodiments, those skilled in the art will readily appreciate that changes and / or modifications may be made thereto without departing from the scope of the present disclosure.

Claims

1. A system (100), comprising: A pixel (102), the pixel (102) comprising a diffusion layer (104) in contact with an absorption layer (106), wherein the diffusion layer and the absorption layer are in contact with each other along an interface (108) inside a mesa (109); a groove (110) defined in the absorber layer (106) surrounding the mesa (109); and An overflow contact (112), the overflow contact (112) being located in the groove (110); wherein the groove (110) has a base (116) between side walls (122) of the groove, wherein the overflow contact (112) is disposed on the base (116), and wherein a lateral gap (124) is present on the base (116) between the overflow contact (112) and each of the side walls (122); wherein the overflow contact (112) is disposed on a transparent conductive oxide (TCO) (126), which in turn contacts the absorber layer (106); and The TCO (126) is formed in a gap (128) within the SiNx layer (130) within the trench (110).

2. The system of claim 1, wherein the overflow contact (112) surrounds the mesa (109).

3. A system according to claim 1 or 2, wherein the pixel (102) is one of a plurality of pixels arranged in a grid pattern, wherein the groove separates each pixel from adjacent ones of the pixels, and wherein the overflow contact (112) of each pixel is disposed on the base of the groove to form an overflow contact grid, wherein the pixel is located in the space of the overflow contact grid between intersection lines of the overflow contact grid.

4. The system of any preceding claim, wherein the overflow contact (112) is metallic.

5. The system of any preceding claim, further comprising a cap layer (136) deposited on the absorber layer (106) opposite the substrate (138). The system of claim 5 , wherein the cap layer comprises InP.

7. The system of claim 5 or 6, further comprising the SiNx layer (130) above the cap layer.

8. The system of claim 7, wherein the SiNx layer (130) directly contacts the absorber layer (106).

9. The system of claim 5, 6, 7 or 8, further comprising an anti-reflection layer (140) deposited on the substrate (138) opposite the absorber layer.

10. The system of any preceding claim, further comprising contact metal (132) electrically connected to the diffusion layer (104), configured to electrically connect the diffusion layer to a read-out integrated circuit (ROIC) (134).

11. The system of claim 10, further comprising the ROIC, the ROIC being in electrical communication with the contact metal.

12. The system of any preceding claim, wherein the TCO (126) comprises multiple layers of ZnO, TiO2 and / or Indium Tin Oxide (ITO).

13. The system of any preceding claim, wherein the absorber layer (106) comprises InGaAs, and wherein the pixel is sensitive to illumination in infrared wavelengths.

14. The system of any preceding claim, wherein the absorbing layer (106) comprises Si, and wherein the pixel is sensitive to illumination in visible wavelengths.

15. A method comprising: forming grooves (110) in an absorber layer (106) of a pixel array, wherein the grooves are formed in a grid pattern (114) surrounding corresponding pixels of the pixel array, wherein each pixel is surrounded by intersection lines of the grid pattern; depositing a SiNx layer (130) on the absorption layer (106) after forming the trench; and forming an overflow contact (112) in the trench (110) following the grid pattern, wherein forming the overflow contact in the trench is performed after depositing the SiNx layer; The forming of the overflow contact (112) in the trench (110) includes forming the overflow contact on a transparent oxide layer (TCO) formed in a gap (128) in the SiNx layer in the trench.

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