Integrated circuit and method of operating integrated circuitry

Abstract

Embodiments are disclosed herein relating to integrated circuits including a multi-bit storage system with energy saving. In one configuration, the multi-bit storage system includes a first storage circuit, a second storage circuit, a prediction circuit, and a clock gating circuit. In one aspect, the first storage circuit updates a first output bit from a first input bit in response to a trigger signal, and the second storage circuit updates a second output bit from a second input bit in response to the trigger signal. In one aspect, the prediction circuit generates a trigger enable signal indicating whether at least one of the first output bit or the second output bit is predicted to change state. In one aspect, the clock gating circuit generates the trigger signal based on the trigger enable signal. A method of operating an integrated circuit system is also disclosed herein.

Description

TECHNICAL FIELD

[0001] The present disclosure relates to integrated circuits and methods of operating integrated circuit systems, and more particularly, to an integrated circuit including or to implement a multi-element storage system for energy saving and methods of operating integrated circuit systems. BACKGROUND

[0002] Development of integrated circuit design allows integrated circuits to perform complex functions. In one aspect, an integrated circuit includes digital logic circuits that can perform logic computations based on electrical signals (e.g., voltage or current) representing corresponding bits of data. For example, a signal having 1 V can represent a state or logic value of “1,” where a signal having 0 V can represent a state or logic value of “0.” In various applications, synchronous logic circuits can perform various logic computations synchronously based on a clock signal. To achieve synchronous logic computations, flip-flops or latches can store or hold data for a period of time according to the clock signal. The data held or stored by the flip-flops or latches enables one or more logic computations to be performed in a reliable manner. SUMMARY

[0003] Some embodiments of the present disclosure provide an integrated circuit. An integrated circuit, comprising a first storage circuit, a second storage circuit, a prediction circuit, and a clock gating circuit. The first storage circuit is to update a first output bit according to a first input bit in response to a trigger signal. The second storage circuit is to update a second output bit according to a second input bit in response to the trigger signal. The prediction circuit is coupled to the first storage circuit and the second storage circuit, the prediction circuit is to generate a trigger enable signal indicating whether at least one of the first output bit or the second output bit is predicted to change state. The clock gating circuit is coupled to the prediction circuit, the clock gating circuit includes an AND gate and a set of transistors coupled to the AND gate, the set of transistors to detect an edge of a clock signal, wherein the clock gating circuit is to generate the trigger signal having a first state based on the trigger enable signal and according to a first edge of the clock signal, and to hold the trigger signal having the first state until a second edge of the clock signal subsequent to the first edge occurs.

[0004] According to some embodiments of the disclosure, an integrated circuit is disclosed. The integrated circuit includes a first storage circuit, a second storage circuit, a prediction circuit, and a clock gating circuit. The first storage circuit updates a first output bit based on a first input bit in response to a trigger signal. The second storage circuit updates a second output bit based on a second input bit in response to the trigger signal. The prediction circuit is coupled to the first storage circuit and the second storage circuit. The prediction circuit predicts whether a state of the first output bit is predicted to change and predicts whether a state of the second output bit is predicted to change, and generates a trigger enable signal based on the prediction of whether the state of the first output bit is predicted to change and the prediction of whether the state of the second output bit is predicted to change. The trigger signal is generated based at least in part on the trigger enable signal. The clock gating circuit is coupled to the first storage circuit and the second storage circuit. The clock gating circuit includes an AND gate and a set of transistors coupled to the AND gate, the set of transistors detecting edges of a clock signal. The clock gating circuit adjusts the trigger signal based on a first edge of the clock signal and the trigger enable signal, and holds the adjusted trigger signal until a second edge of the clock signal subsequent to the first edge occurs.

[0005] According to some embodiments of the disclosure, a method of operating an integrated circuit system is disclosed. The method includes determining whether at least one of a plurality of output bits of a plurality of flip-flop circuits is predicted to change state, enabling a clock gating circuit in response to determining that at least one of the plurality of output bits of the plurality of flip-flop circuits is predicted to change state, the clock gating circuit including an AND gate and a set of transistors coupled to the AND gate, the set of transistors detecting edges of a clock signal, adjusting a trigger signal from a first state to a second state by the clock gating circuit based on a first edge of the clock signal when the clock gating circuit is enabled, holding the second state of the trigger signal by the clock gating circuit until a second edge of the clock signal subsequent to the first edge occurs, and updating one or more of the plurality of output bits of the plurality of flip-flop circuits based on one or more corresponding input bits in response to the trigger signal changing from the first state to the second state.

[0006] According to some embodiments of the disclosure, an integrated circuit is disclosed. The integrated circuit includes a plurality of storage circuits, a prediction circuit, and a clock gating circuit. The plurality of storage circuits updates a plurality of output bits in response to a trigger signal. The prediction circuit generates a trigger signal. The trigger signal indicates whether at least one of the plurality of output bits is predicted to change state. The clock gating circuit generates the trigger signal having a first state based on a first edge of a clock signal in response to the trigger enable signal, and holds the trigger signal having the first state until a second edge of the clock signal subsequent to the first edge of the clock signal occurs.

[0007] According to some embodiments of the disclosure, an integrated circuit is disclosed. The integrated circuit includes a first storage circuit, a second storage circuit, a prediction circuit, and a clock gating circuit. The first storage circuit updates a first output bit based on a first input bit in response to a trigger signal. The second storage circuit updates a second output bit based on a second input bit in response to the trigger signal. The prediction circuit predicts whether a state of the first output bit is predicted to change. The prediction circuit predicts whether a state of the second output bit is predicted to change. The prediction circuit generates a trigger enable signal based on the prediction of whether the state of the first output bit is predicted to change and the prediction of whether the state of the second output bit is predicted to change, and the trigger signal is based at least in part on the trigger enable signal. The clock gating circuit adjusts the trigger signal based on a first edge of a clock signal and the trigger enable signal, and holds the adjusted trigger signal until a second edge of the clock signal occurs subsequent to the first edge of the clock signal.

[0008] According to some embodiments of the disclosure, a method of operating an integrated circuit system is disclosed. The method includes determining whether at least one of a plurality of output bits of a plurality of storage circuits is predicted to change state, enabling a clock gating circuit in response to determining whether at least one of the plurality of output bits of the plurality of storage circuits is predicted to change state, adjusting a trigger signal from a first state to a second state by the clock gating circuit in response to a first edge of a clock signal when the clock gating circuit is enabled, holding the second state of the trigger signal by the clock gating circuit until a second edge of the clock signal occurs subsequent to the first edge of the clock signal, and updating one or more of the plurality of output bits of the plurality of storage circuits based on one or more corresponding input bits in response to the trigger signal changing from the first state to the second state. BRIEF DESCRIPTION OF DRAWINGS

[0009] An exemplary aspect of some embodiments of the present disclosure is best understood from the following detailed description when read with the accompanying drawings. It is emphasized that various features are not to scale. In fact, the dimensions of various features can be arbitrarily increased or decreased for the sake of discussion. Embodiments of the present disclosure will be described and explained with additional specificity and detail through the use of the accompanying drawings in which:

[0010] Figure 1 A schematic diagram of a multi-bit storage system according to one embodiment;

[0011] Figure 2 A schematic diagram of an example prediction circuit for a multi-bit storage system shown in Figure 1 FIG. 1 according to some embodiments;

[0012] Figure 3 A schematic diagram of an XOR gate for a prediction circuit shown in Figure 2 FIG. 2 according to some embodiments;

[0013] Figure 4 A schematic diagram of an example prediction circuit for a multi-bit storage system shown inFigure 2 schematic diagram of an OR gate of a prediction circuit as shown in

[0014] Figure 5 for operation of a multi-bit storage system according to some embodiments Figure 1 schematic diagram of a clock gating circuit of a multi-bit storage system as shown in

[0015] Figure 6 for operation of a multi-bit storage system according to some embodiments

[0016] Figure 7 for operation of a multi-bit storage system according to some embodiments

[0017] Figure 8 for operation of a multi-bit storage system according to some embodiments

[0018] Figure 9 for operation of a multi-bit storage system according to some embodiments

[0019]

Symbol Legend

[0020] 105: trigger signal

[0021] 110: multi-bit storage system

[0022] 120A: storage circuit

[0023] 120N: storage circuit

[0024] 130: prediction circuit

[0025] 135: trigger enable signal

[0026] 150: clock gating circuit

[0027] 155: clock signal

[0028] 210A: XOR gate

[0029] 210N: XOR gate

[0030] 210X: XOR gate

[0031] 215A: prediction signal

[0032] 215B: prediction signal

[0033] 215C: prediction signal

[0034] 215D: prediction signal

[0035] 215E: prediction signal

[0036] 215F: prediction signal

[0037] 215G: predicted signal

[0038] 215H: predicted signal

[0039] 215N: predicted signal

[0040] 220: OR gate

[0041] 410A: NOR gate

[0042] 410B: NOR gate

[0043] 410C: NOR gate

[0044] 410D: NOR gate

[0045] 420: NAND gate

[0046] 510: NAND gate

[0047] 600: timing diagram

[0048] 700: method

[0049] 705: operation

[0050] 710: operation

[0051] 720: operation

[0052] 725: operation

[0053] 730: operation

[0054] 740: operation

[0055] 745: operation

[0056] 750: operation

[0057] 755: operation

[0058] 800: layout diagram

[0059] 810A: first region

[0060] 810B: second region

[0061] 820: third region

[0062] 900: computing system

[0063] 905: host device

[0064] 910: memory element

[0065] 915: input device

[0066] 920: output device

[0067] 925A: interface

[0068] 925B: interface

[0069] 925C: interface

[0070] 930A: CPU core

[0071] 930N: CPU core

[0072] 935: standard cell application

[0073] 940: memory controller

[0074] 945: memory array

[0075] In_A: input bit

[0076] In_N: input bit

[0077] IN: input port

[0078] IN_A1: input port

[0079] IN_A2: input port

[0080] IN_N1: input port

[0081] IN_N2: input port

[0082] IN_X1: input port

[0083] IN_X2: input port

[0084] IN_ORA: first input port

[0085] IN_ORB: second input port

[0086] IN_ORC: first input port

[0087] IN_ORD: second input port

[0088] IN_ORE: first input port

[0089] IN_ORF: second input port

[0090] IN_ORG: first input port

[0091] IN_ORH: second input port

[0092] INV1: inverter

[0093] INV2: inverter

[0094] INV3: inverter

[0095] OUT: output port

[0096] OUT_X: output port

[0097] Out_A: output bit

[0098] Out_N: output bit

[0099] Out_NORA: output port

[0100] Out_NORB: output port

[0101] Out_NORC: output port

[0102] Out_NORD: output port

[0103] EN_OUT: output port

[0104] EN: enable port

[0105] CLK: clock port

[0106] VDD: power rail

[0107] GND: ground rail

[0108] N1: node

[0109] N2: node

[0110] N3: node

[0111] T1: transistor

[0112] T2: transistor

[0113] T3: transistor

[0114] T4: transistor

[0115] T5: transistor

[0116] T6: transistor

[0117] T7: transistor

[0118] T8: transistor

[0119] T9: transistor

[0120] T10: transistor

[0121] T11: transistor

[0122] T51: transistor

[0123] T52: transistor

[0124] T53: transistor

[0125] T54: transistor

[0126] T55: transistor

[0127] T56: transistor

[0128] T57: transistor

[0129] t1: time

[0130] t2: time

[0131] t3: time

[0132] t4: time

[0133] t5: time

[0134] t6: time DETAILED DESCRIPTION

[0135] The following disclosure provides many different embodiments, or examples, for implementing different features of the provided subject matter. Specific examples of components and arrangements are described below to simplify the present disclosure. These are, of course, merely examples and are not intended to be limiting. For example, the formation of a first feature over or on a second feature in the description that follows can include embodiments in which the first and second features are formed in direct contact, and can also include embodiments in which additional features can be formed between the first and second features, such that the first and second features can not be in direct contact. In addition, the present disclosure can repeat use of certain elements or

[0136] In addition, spatially relative terms, such as "beneath", "below", "lower", "above", "upper" and the like, can be used herein for ease of description to describe one element or feature's relationship to another element(s) or feature(s) as illustrated in the figures. Such spatially relative terms can be intended to encompass different orientations of the device in use or operation in addition to the orientation depicted in the figures. The device can be otherwise oriented (rotated 90 degrees or at other orientations) and the spatially relative descriptors used herein interpreted accordingly.

[0137] Embodiments of integrated circuits including a multi-bit storage system that conserves power are disclosed herein. In one configuration, the multi-bit storage system includes a first storage circuit, a second storage circuit, a prediction circuit, and a clock gating circuit. In one aspect, the first storage circuit updates a first output bit from a first input bit in response to a trigger signal, and the second storage circuit updates a second output bit from a second input bit in response to the trigger signal. In one aspect, the prediction circuit generates a trigger enable signal that indicates whether at least one of the first output bit or the second output bit is predicted to change state. In one aspect, the clock gating circuit generates the trigger signal from the trigger enable signal.

[0138] Advantageously, the multi-bit storage system disclosed in some embodiments can operate in a power-conserving manner. In one implementation, a plurality of storage circuits (e.g., flip-flops) can be operated synchronously from a clock signal from a common clock driver circuit (e.g., one or more inverters). However, when the common clock driver circuit provides a periodic pulse or clock signal to a large number of storage circuits (e.g., 7 or more) at a high frequency or high data rate (e.g., over 1 GHz or 1 Gbps), such a common clock driver circuit can consume a large amount of power due to capacitive loading at the output of the common clock driver circuit. For example, the periodic switching of voltage at the output of the common clock driver circuit connected to the large number of storage circuits can result in a large amount of power consumption. In various embodiments disclosed herein, it can be predicted whether at least one of a plurality of output bits of a storage circuit (e.g., a flip-flop) will change state. Further, in response to the prediction that at least one of the plurality of output bits of the storage circuit will change state, a clock signal or a trigger signal that facilitates the storage circuit updating the output bit of the storage circuit can be dynamically or adaptively provided to the storage circuit. Thus, frequent switching by the common clock driver circuit can be avoided to achieve power conservation. In one example, by dynamically or adaptively facilitating or causing the plurality of storage circuits to update the output bits based on the prediction as disclosed herein, the power consumption can be reduced by up to 64% as compared to providing a periodic pulse or clock signal to the plurality of storage circuits at a high frequency or high data rate (e.g., over 1 GHz or 1 Gbps).

[0139] Figure 1A schematic diagram of a multi-bit storage system 110 according to one implementation. In some embodiments, the multi-bit storage system 110 is implemented as an integrated circuit. In some embodiments, the multi-bit storage system 110 is implemented as two or more separate systems or circuits. In some embodiments, the multi-bit storage system 110 includes a number N of storage circuits 120A...120N. N can be an even number (e.g., 4, 8, 16, 32, etc.) or any positive integer. In some embodiments, the multi-bit storage system 110 also includes a prediction circuit 130 and a clock gating circuit 150. These components can operate together to predict whether at least one of the output bits stored by the storage circuits 120A...120N will change state and dynamically or adaptively provide a trigger signal 105 to the storage circuits 120A...120N to update the output bits Out_A...Out_N stored by the storage circuits 120A...120N. In one aspect, the multi-bit storage system 110 operates as a multi-bit flip-flop. In some embodiments, the multi-bit storage system 110 includes more, fewer, or different components than those shown in FIG. 1. Figure 1

[0140] In some embodiments, the storage circuits 120A...120N are circuits that can store data for a period of time. Each of the storage circuits 120...120N can be embodied as a flip-flop, a latch, or any synchronous circuit that can hold data according to the trigger signal 105. In some embodiments, the storage circuits 120A...120N can be replaced by any components that can perform the functions of the storage circuits 120A...120N described in some embodiments herein. In one example, the storage circuit 120X includes an input port IN to receive an input bit In_X, a clock port CLK to receive the trigger signal 105, and an output port OUT to provide an output bit Out_X. In one example, in response to detecting a predetermined edge (e.g., a rising edge or a falling edge) of the trigger signal 105, the storage circuit 120X implemented as a flip-flop updates the output bit Out_X at the output port OUT by replacing the output bit Out_X with the input bit In_X received at the input port. In one example, in response to not detecting a predetermined edge (e.g., a rising edge or a falling edge) of the trigger signal 105, the storage circuit 120X implemented as a flip-flop can maintain or hold the output bit Out_X at the output port OUT.

[0141] ​In some embodiments, the prediction circuit 130 is a circuit that predicts whether at least one of the output bits Out_A...Out_N of the storage circuits 120A...120N will change state, and generates the trigger enable signal 135 in accordance with this prediction. In some embodiments, the prediction circuit 130 can be replaced by any component that can perform the functions of the prediction circuit 130 described in some embodiments herein. In one configuration, the prediction circuit 130 includes input ports IN_A1...IN_N1 coupled to the output ports OUT of the corresponding storage circuits 120A...120N, input ports IN_A2...IN_N2 coupled to the input ports IN of the corresponding storage circuits 120A...120N, and an output port EN_OUT coupled to the enable port EN of the clock gating circuit 150. In this configuration, for each output bit Out_X, the prediction circuit 130 can determine whether the state of the output bit Out_X will change state by comparing the output bit Out_X with the corresponding input bit In_X. In accordance with this determination, the prediction circuit 130 can determine whether at least one of the output bits Out_A...Out_N of the storage circuits 120A...120N will change state, and generate the trigger enable signal 135 in accordance with this determination. For example, the prediction circuit 130 generates the trigger enable signal 135 having a first state (e.g., a logic value of "1") indicating that at least one of the output bits Out_A...Out_N of the storage circuits 120A...120N will change state. For example, the prediction circuit 130 generates the trigger enable signal 135 having a second state (e.g., a logic value of "0") indicating that the states of the output bits Out_A...Out_N of the storage circuits 120A...120N will remain unchanged. The prediction circuit 130 can provide the trigger enable signal 135 to the clock gating circuit 150 to enable or disable the clock gating circuit 150. The operation and configuration of the prediction circuit 130 are described in more detail below with reference to FIGS. 2A and 2B. Figures 2 to 7 A detailed description of the operation and configuration of the prediction circuit 130 is provided.

[0142] In some embodiments, clock gating circuit 150 is a circuit that dynamically or adaptively generates trigger signal 105 based on clock signal 155. Clock signal 155 may have periodic pulses of a high frequency (e.g., 1 GHz or higher). Clock gating circuit 150 may be implemented as a latch or flip-flop. In some embodiments, clock gating circuit 150 may be replaced by any component capable of performing the functions of clock gating circuit 150 as described in some embodiments herein. In one configuration, clock gating circuit 150 includes an input port for receiving clock signal 155, an enable port EN coupled to output port EN_OUT of prediction circuit 130, and an output port OUT coupled to clock port CLK of storage circuits 120A…120N. In this configuration, clock gating circuit 150 is dynamically or adaptively enabled or disabled based on trigger enable signal 135 to generate trigger signal 105. In one example, clock gating circuit 150 is enabled in response to a trigger enable signal 135 having a first state (e.g., logic value "1"). For example, when clock gating circuit 150 is enabled, it may wait for the rising edge of clock signal 155. In response to the rising edge of clock signal 155, when clock gating circuit 150 is enabled, it may change the state of trigger signal 105, for example, from a second state (e.g., logic value "0") to a first state (e.g., logic value "1"). In one example, clock gating circuit 150 is disabled in response to a trigger enable signal 135 having a second state (e.g., logic value "0"). When clock gating circuit 150 is disabled, it may wait for the falling edge of clock signal 155. In response to the falling edge of the clock signal 155 when the clock gating circuit 150 is deactivated, the clock gating circuit 150 may output a predetermined state (e.g., logic value "0") at the output port OUT as a trigger signal 105. In one state, the rising edge of the trigger signal 105 may cause the storage circuits 120A…120N to update the output bits Out_A…Out_N according to the input bits In_A…In_N.

[0143] Advantageously, the multi-bit storage system 110 can operate in an energy-efficient manner. In one configuration, the clock gating circuit 150 can connect to a large number (e.g., 8, 16, or 32) of storage circuits 120 to provide trigger signals 105. Frequent or periodic switching at the output port OUT of the clock gating circuit 150 can result in significant power consumption. By dynamically or adaptively enabling and disabling the clock gating circuit 150 based on predictions from the prediction circuit 130, the number of trigger signal switching (or state changes) can be reduced, thereby achieving energy savings.

[0144] Figure 2 According to some embodiments, in Figure 1A schematic diagram of an example prediction circuit 130 of the multi-bit storage system 110 shown in FIG. 1. In some embodiments, the prediction circuit 130 includes N number of XOR gates and an OR gate 220. Together, these components can operate to predict whether at least one of the output bits Out_A...Out_N of the storage circuits 120A...120N will change state, and generate the trigger enable signal 135 in accordance with this prediction. In some embodiments, the prediction circuit 130 includes more, fewer, or different components than those shown in FIG. 1. Figure 2 In some embodiments, the prediction circuit 130 includes more, fewer, or different components than those shown in FIG. 1.

[0145] In some embodiments, each of the XOR gates 210A...210N is a circuit that predicts whether a corresponding one of the prediction output bits Out_A...Out_N will change state. In some embodiments, the XOR gates 210A...210N can be replaced by any components that can perform the functions of the XOR gates 210A...210N described in some embodiments herein. In one configuration, each XOR gate 210X includes a first input port IN_X1 coupled to an output port OUT of a corresponding storage circuit 120X, a second input port IN_X2 coupled to an input port IN of the corresponding storage circuit 120X, and an output port coupled to a corresponding input port of the OR gate 220. In this configuration, the XOR gate 210X receives the output bit Out_X of the storage circuit 120X at the first input port IN_X1 and the input bit In_X of the storage circuit 120X at the second input port IN_X2. Further, the XOR gate 210X compares the output bit Out_X of the storage circuit 120X with the input bit In_X of the storage circuit 120X, and generates a prediction signal 215X in accordance with this comparison. For example, in response to the input bit In_X and the output bit Out_X of the storage circuit 120X being different, the XOR gate 210X can generate the prediction signal 215X having a first state (e.g., a logic value of “1”), which indicates that the state of the output bit Out_X of the storage circuit 120X is predicted to change. For example, in response to the input bit In_X and the output bit Out_X of the storage circuit 120X being equal to each other, the XOR gate 210X can generate the prediction signal 215X having a second state (e.g., a logic value of “0”), which indicates that the state of the output bit Out_X of the storage circuit 120X is predicted to remain unchanged. Each XOR gate 210X can provide the corresponding prediction signal 215X to the OR gate 220.

[0146] In some embodiments, OR gate 220 is a circuit that receives prediction signals 215A...215N from XOR gates 210A...210N and generates a trigger enable signal 135 based on prediction signals 215A...215N. In some embodiments, OR gate 220 can be replaced by any component that can perform the function of OR gate 220 described in some embodiments herein. In one configuration, OR gate 220 includes N number of input ports coupled to output ports of corresponding XOR gates 210A...210N, and an output port EN OUT coupled to an enable port EN of clock gating circuit 150. In this configuration, OR gate 220 can determine whether at least one of output bits Out A...Out N of storage circuits 120A...120N is to change state based on prediction signals 215A...215N, and generate a trigger enable signal 135 based on this determination. For example, in response to at least one of prediction signals 215A...215N having a first state (e.g., a logic value of “1”), OR gate 220 can generate a trigger enable signal having a first state (e.g., a logic value of “1”) to enable clock gating circuit 150. For example, in response to each of prediction signals 215A...215N having a second state (e.g., a logic value of “0”), OR gate 220 can generate a trigger enable signal having a second state (e.g., a logic value of “0”) to disable clock gating circuit 150.

[0147] Figure 3 A schematic diagram of an XOR gate 210X of prediction circuit 130 shown in Figure 2 In some embodiments, XOR gate 210X includes transistors T1...T11. Transistors T1, T2, T6, T7, T9 can be P-type transistors (e.g., P-type MOSFETs or P-type FinFETs), and transistors T3, T4, T8, T10, T11 can be N-type transistors (e.g., N-type MOSFETs or N-type FinFETs). These components can operate together to compare an input bit In X of storage circuit 120X received at input port IN X2 with an output bit Out X of storage circuit 120X received at input port IN X1, and generate a prediction signal 215X at output port OUT X. In some embodiments, XOR gate 210 includes more, fewer, or different components than those shown in Figure 3 In some embodiments, XOR gate 210 includes more, fewer, or different components than those shown in

[0148] In one configuration, transistor Tl includes a gate electrode coupled to input port IN X2, a source electrode coupled to a power rail VDD that provides a supply voltage, and a drain electrode. In one configuration, transistor T2 includes a gate electrode coupled to input port IN Xl, a source electrode coupled to the drain electrode of transistor Tl, and a drain electrode coupled to node Nl. In one configuration, transistor T3 includes a gate electrode coupled to input port IN Xl, a source electrode coupled to a ground rail GND that provides a ground voltage, and a drain electrode coupled to node Nl. In one configuration, transistor T4 includes a gate electrode coupled to input port IN X2, a source electrode coupled to ground rail GND, and a drain electrode coupled to node Nl.

[0149] In one configuration, transistor T6 includes a gate electrode coupled to input port IN Xl, and a source electrode coupled to power rail VDD. In one configuration, transistor T9 includes a gate electrode coupled to input port IN X2, a source electrode coupled to power rail VDD, and a drain electrode coupled to the drain electrode of transistor T6. In one configuration, transistor T7 includes a gate electrode coupled to node Nl, a source electrode coupled to the drain electrodes of transistors T6, T9, and a drain electrode coupled to output port OUT. In one configuration, transistor T8 includes a gate electrode coupled to node Nl, a source electrode coupled to ground rail GND, and a drain electrode coupled to output port OUT. In one configuration, transistor Tl l includes a gate electrode coupled to input port IN X2, and a source electrode coupled to ground rail GND. In one configuration, transistor TlO includes a gate electrode coupled to input port IN Xl, a source electrode coupled to the drain electrode of transistor Tl l, and a drain electrode coupled to output port OUT.

[0150] In this configuration, XOR gate 210X can compare the input bit In X of storage circuit 120X received at input port IN X2 with the output bit Out X of storage circuit 120X received at input port IN Xl, and generate prediction signal 215X at output port OUT. For example, in response to the input bit In X and the output bit Out X of storage circuit 120X being different, XOR gate 210X can generate prediction signal 215X having a first state (e.g., a logic value of "1"), which indicates that the state of the output bit Out X of storage circuit 120X is predicted to change. For example, in response to the input bit In X and the output bit Out X of storage circuit 120X being equal to each other, XOR gate 210X can generate prediction signal 215X having a second state (e.g., a logic value of "0"), which indicates that the state of the output bit Out X of storage circuit 120X is predicted to remain unchanged.

[0151] Figure 4 A schematic diagram of an OR gate 220 of the prediction circuit 130 shown in Figure 2 In some embodiments, the OR gate 220 shown in Figure 4 The OR gate 220 shown in FIG. 2 is an 8-input OR gate. In other embodiments, the OR gate 220 can have more or a different number of inputs than those shown in FIG. 2. In one aspect, the OR gate 220 includes a first stage of two-input NOR gates 410A, 410B, 410C, 410D and a second stage of four-input NAND gates 420. These components can operate together to perform OR operations on the prediction signals 215A...215H. In other embodiments, the OR gate 220 includes more, fewer, or different components than those shown in FIG. 2. Figure 4 Figure 4 In one aspect, the two-input NOR gate 410A includes a first input port IN ORA coupled to an output port of the XOR gate 210A to receive the prediction signal 215A, a second input port IN ORB coupled to an output port of the XOR gate 210B to receive the prediction signal 215B, and an output port OUT NOR A. In this configuration, the NOR gate 410A can perform a NOR logic operation on the prediction signals 215A, 215B and output the result of the NOR logic operation at the output port OUT NOR A. The NOR gate 410B can be configured in a similar manner to the NOR gate 410A and perform a NOR operation on the prediction signals 215C, 215D. Additionally, the NOR gate 410C can be configured in a similar manner to the NOR gate 410A and perform a NOR operation on the prediction signals 215E, 215F. Additionally, the NOR gate 410D can be configured in a similar manner to the NOR gate 410A and perform a NOR operation on the prediction signals 215G, 215H.

[0152] In one configuration, the NAND gate 420 includes input ports coupled to the output ports OUT NOR A, OUT NOR B, OUT NOR C, OUT NOR D of the NOR gates 410A, 410B, 410C, 410D, respectively, and an enable output port EN OUT coupled to the enable port EN of the clock gating circuit 150. In this configuration, the NAND gate 420 can perform a four-input NAND logic operation on the outputs of the NOR gates 410A, 410B, 410C, 410D to produce the trigger enable signal 135 at the enable output port EN OUT. In one aspect, the NAND operation performed on the results of the NOR operations performed on the prediction signals 215A to 215H exhibits the same results as the OR logic operations performed on the prediction signals 215A to 215H.

[0153] In one configuration, the NAND gate 420 includes input ports coupled to the output ports OUT NOR A, OUT NOR B, OUT NOR C, OUT NOR D of the NOR gates 410A, 410B, 410C, 410D, respectively, and an enable output port EN OUT coupled to the enable port EN of the clock gating circuit 150. In this configuration, the NAND gate 420 can perform a four-input NAND logic operation on the outputs of the NOR gates 410A, 410B, 410C, 410D to produce the trigger enable signal 135 at the enable output port EN OUT. In one aspect, the NAND operation performed on the results of the NOR operations performed on the prediction signals 215A to 215H exhibits the same results as the OR logic operations performed on the prediction signals 215A to 215H.

[0154] Advantageously, as Figure 4 ​The method shown, which performs eight or more bits of OR logic operations via two or more stages, can improve the speed of logic computation. In one example, an eight-bit OR logic operation can be performed by an eight-bit NOR gate and an inverter at the output of the eight-bit NOR gate. However, implementing an eight-bit NOR gate can increase capacitive load and reduce operation speed. Combining a large number (e.g., eight or more) bits of OR logic operations via two or more stages with... Figure 4 The NOR and AND operations shown can reduce capacitive load, thereby improving the processing speed.

[0155] Figure 5 According to some embodiments, in Figure 1 The diagram shows a clock gating circuit 150 of the multi-bit storage system 110. In some embodiments, the clock gating circuit 150 includes inverters INV1, INV2, INV3, a NAND gate 510, and transistors T51, T52, T53, T54, T55, T56, and T57. In some embodiments, transistors T51, T52, and T55 are implemented as P-type transistors (e.g., P-type MOSFETs or P-type FinFETs), and transistors T53, T54, T56, and T57 are implemented as N-type transistors (e.g., N-type MOSFETs or N-type FinFETs). These components can operate together in response to a trigger enable signal 135 to generate a trigger signal 105 according to a clock signal 155. In some embodiments, the clock gating circuit 150 includes a... Figure 5 The components shown may be more, fewer, or different from those shown.

[0156] In one configuration, the first input port of NAND gate 510 is coupled to the input port IN of clock gating circuit 150, the second input port of NAND gate 510 is coupled to node N2, and the output port of NAND gate 510 is coupled to node N3. In another configuration, the input port of inverter INV3 is coupled to node N3, and the output port of inverter INV3 is coupled to the output port OUT of clock gating circuit 150. In yet another configuration, the input port of inverter INV1 is coupled to the enable port EN of clock gating circuit 150, and the output port of inverter INV1 is coupled to the gate electrodes of transistors T52 and T54. In yet another configuration, the input port of inverter INV2 is coupled to node N2, and the output port of inverter INV2 is coupled to the gate electrode of transistor T56.

[0157] In one configuration, the source electrode of transistor T51 is coupled to a power rail VDD that supplies a supply voltage, and the gate electrode of transistor T51 is coupled to an input port IN of the clocked gate circuit. In one configuration, the source electrode of transistor T52 is coupled to the drain electrode of transistor T51, and the drain electrode of transistor T52 is coupled to node N2. In one configuration, the drain electrode of transistor T53 is coupled to node N2, and the gate electrode of transistor T53 is coupled to node N3. In one configuration, the drain electrode of transistor T54 is coupled to the source electrode of transistor T53, and the source electrode of transistor T54 is coupled to a ground rail GND that supplies a ground voltage. In one configuration, the source electrode of transistor T55 is coupled to the power rail VDD, the gate electrode of transistor T55 is coupled to node N3, and the drain electrode of transistor T55 is coupled to node N2. In one configuration, the drain electrode of transistor T56 is coupled to node N2, and the source electrode of transistor T56 is coupled to the drain electrode of transistor T57. In one configuration, the gate electrode of transistor T57 is coupled to the input port IN of the clocked gate circuit 150, and the source electrode of transistor T57 is coupled to the ground rail GND.

[0158] In this configuration, based on the trigger enable signal 135 at the enable port EN, the clock gating circuit 150 generates the trigger signal 105 at the output port OUT according to the clock signal 155 at the input port IN. In one aspect, in response to the trigger enable signal 135 having a first state (e.g., a logic value of "1"), the clock gating circuit 150 can be enabled. When the clock gating circuit 150 is enabled, the clock gating circuit 150 can output the trigger signal 105 having a second state (e.g., a logic value of "0") and wait for a rising edge of the clock signal 155 at the input port IN. When the clock gating circuit 150 is enabled, in response to the rising edge of the clock signal 155, the clock gating circuit 150 can change the state of the trigger signal 105. For example, the trigger signal 105 can transition from the second state (e.g., a logic value of "0") to the first state (e.g., a logic value of "1") according to the clock signal 155. In one aspect, the rising edge of the trigger signal 105 causes or results in the storage circuit 120A...120N to update the output bits Out_A...Out_N according to the corresponding input bits In_A...In_N. After the output bits Out_A...Out_N are updated, the trigger enable signal 135 can be set to the second state (e.g., a logic value of "0") to disable the clock gating circuit 150. When the clock gating circuit 150 is disabled, the clock gating circuit 150 can wait for a falling edge of the clock signal 155. In response to the falling edge of the clock signal 155 when the clock gating circuit 150 is disabled, the clock gating circuit 150 can output the second state (e.g., a logic value of "0") as the trigger signal 105. When the clock gating circuit 150 is disabled, the clock gating circuit 150 can not wait for or respond to a rising edge of the clock signal 155.

[0159] Advantageously, the clock gating circuit 150 dynamically or adaptively generates or adjusts the trigger signal 105 in response to the trigger enable signal 135 indicating whether at least one of the output bits Out_A...Out_N is predicted to change state. By dynamically or adaptively generating the trigger signal 105 in response to the prediction of whether at least one of the output bits Out_A...Out_N is predicted to change state, the number of toggles of the trigger signal 105 can be reduced compared to the number of toggles of the clock signal 155. As a result, the clock gating circuit 150 can drive the storage circuit 120A...120N in an energy-efficient manner.

[0160] Figure 6 An example timing diagram 600 for the operation of the multi-bit storage system 110 according to some embodiments. For simplicity, the timing diagram 600 shows the operation of a single storage circuit 120A. However, the operations shown in the timing diagram 600 can apply to the plurality of storage circuits 120A...120N.

[0161] In one aspect, the clock signal 155 includes a plurality of periodic pulses. For example, at time Tl, the clock signal 155 toggles from a second state (e.g., 0V or a logical "0") to a first state (e.g., IV or a logical "1"). At time Tl, because the state of the input bit In_A is the same as the state of the output bit Out_A, the prediction circuit 130 can predict that the output bit Out_A will remain the same. In addition, the prediction circuit 130 can generate the toggle enable signal 135 having the second state (e.g., a logical value of "0") to disable the clock gating circuit 150. Because the toggle enable signal 135 has the second state, the clock gating circuit 150 can be disabled and can not respond to a rising edge of the clock signal at time Tl. In addition, the clock gating circuit 150 can output the toggle signal 105 having the second state, causing the storage circuit 120A to maintain the output bit Out_A.

[0162] At time T2, the clock signal 155 toggles from the first state to the second state. When the clock gating circuit 150 is disabled, the clock gating circuit 150 can set the toggle signal 105 to the second state (e.g., a logical value of "0") in response to a falling edge of the clock signal 155. Because the state of the toggle signal 105 was the second state before time T2, the clock gating circuit 150 maintains the toggle signal 105 having the second state in response to the falling edge of the clock signal 155 at time T2.

[0163] At time T3, the input bit In_A toggles from the second state (e.g., a logical value of "0") to the first state (e.g., a logical value of "1"). Because the state of the input bit In_A is different from the state of the output bit Out_A at time T3, the prediction circuit 130 can decide to predict that the output bit Out_A will change. In addition, the prediction circuit 130 can generate the toggle enable signal 135 having the first state (e.g., a logical value of "1") to enable the clock gating circuit 150. Because the clock gating circuit 150 is enabled, the clock gating circuit 150 can wait for a rising edge of the clock signal 155. The storage circuit 120A can maintain the output bit Out_A until the rising edge of the clock signal 155 is detected.

[0164] At time T4, the clock signal 155 toggles from the second state to the first state while the clock gating circuit 150 is enabled. Because the clock gating circuit 150 is enabled at time T4 when the clock gating circuit 150 is enabled, the clock gating circuit 150 can change the state of the toggle signal 105 from the second state to the first state. Thus, the toggle signal 105 can have a rising edge at time T4. In one aspect, the storage circuit 120A can detect the rising edge of the toggle signal 105 at time T4 and update the output bit Out_A according to the input bit In_A. For example, in response to the rising edge of the toggle signal 105, the state of the output bit Out_A toggles from the second state to the first state at time T4. After the output bit Out_A is updated, because the input bit In_A and the output bit Out_A of the storage circuit 120A have the same state, the toggle enable signal 135 can be set to the second state to disable the clock gating circuit 150. When the clock gating circuit 150 is disabled, the clock gating circuit 150 can wait for a falling edge of the clock signal 155. While waiting for the falling edge of the clock signal 155, the storage circuit 120A can maintain the output bit Out_A.

[0165] At time T5, the clock gating circuit 150 detects a falling edge of the clock signal 155 when the clock gating circuit 150 is disabled. In response to detecting the falling edge of the clock signal 155 at time T5 when the clock gating circuit 150 is disabled, the clock gating circuit 150 can set or change the state of the toggle signal 105 from the first state to the second state.

[0166] At time T6, the clock signal 155 toggles from the second state to the first state. Because the clock gating circuit 150 is disabled at time T6, the clock gating circuit 150 can not respond to the rising edge of the clock signal 155 and maintain the toggle signal 105 with the second state. Thus, the storage circuit 120A can not update the output bit Out_A at time T6.

[0167] Figure 7 A flowchart of a method 700 of operation of a multi-bit storage system 110 according to some embodiments. The method 700 can be performed by the multi-bit storage system 110 of Figure 1 In some embodiments, the method 700 is performed by another entity. In some embodiments, the method 700 includes more, fewer, or different steps than those shown in FIG. 7. Figure 7

[0168] ​In operation 705, the multi-bit storage system 110 determines whether the output bit (e.g., output bit Out_A...Out_N) of the storage circuit (e.g., storage circuit 120A...120N) is predicted to change state. In one aspect, operation 705 includes operations 710, 720, 725.

[0169] In operation 710, the multi-bit storage system 110 receives the input bit (e.g., input bit In_A...In_N) of the storage circuit (e.g., storage circuit 120A...120N). Each storage circuit 120X can be a flip-flop circuit or a latch circuit. Each storage circuit 120X can receive a corresponding input bit In_X.

[0170] In operation 720, the multi-bit storage system 110 generates a prediction signal (e.g., prediction signal 215A...215N) including a prediction circuit (e.g., prediction circuit 130). Each prediction signal (e.g., prediction signal 215X) can indicate whether the output bit (e.g., output bit Out_X) of the corresponding storage circuit (e.g., storage circuit 120X) is predicted to change state. In one approach, the prediction circuit 130 compares the input bit (e.g., input bit In_X) and the output bit (e.g., output bit Out_X) of the corresponding storage circuit (e.g., storage circuit 120X) to determine whether the state of the output bit is predicted to change. For example, in response to the state of the input bit (e.g., input bit In_X) and the state of the output bit (e.g., output bit Out_X) being equal to each other, the prediction circuit 130 can determine that the state of the output bit (e.g., output bit Out_X) is predicted to remain unchanged. For example, in response to the state of the input bit (e.g., input bit In_X) and the state of the output bit (e.g., output bit Out_X) being different, the prediction circuit 130 can determine that the state of the output bit (e.g., output bit Out_X) is predicted to change.

[0171] In operation 725, the multi-bit storage system 110 including the prediction circuit (e.g., the prediction circuit 130) generates a trigger enable signal (e.g., the trigger enable signal 135) in accordance with the prediction signals (e.g., the prediction signals 215A...215N) from operation 720. In one aspect, the trigger enable signal (e.g., the trigger enable signal 135) indicates whether to enable or disable the clocked gate circuit 150. In one approach, in response to at least one of the prediction signals (e.g., the prediction signal 215X) indicating that a state of an output bit (e.g., the output bit Out_X) of a corresponding storage circuit (e.g., the storage circuit 120X) is predicted to change, the prediction circuit 130 generates the trigger enable signal (e.g., the trigger enable signal 135) having a first state (e.g., a logic value of "1"). In one approach, in response to the prediction signals (e.g., the prediction signals 215A...215N) indicating that the states of the output bits (e.g., the output bits Out_A...Out_N) of the storage circuits (e.g., the storage circuits 120A...120N) are predicted to remain unchanged, the prediction circuit 130 generates the trigger enable signal (e.g., the trigger enable signal 135) having a second state (e.g., a logic value of "0").

[0172] In operation 730, the multi-bit storage system 110 (e.g., the prediction circuit 130) enables or disables the clocked gate circuit 150 in accordance with the trigger enable signal (e.g., the trigger enable signal 135) from operation 725. In one example, the prediction circuit 130 provides the trigger enable signal 135 having the first state (e.g., a logic value of "1") to the clocked gate circuit 150 for enabling the clocked gate circuit 150. In one example, the prediction circuit 130 provides the trigger enable signal having the second state (e.g., a logic value of "0") to the clocked gate circuit 150 for disabling the clocked gate circuit 150.

[0173] In operation 740, in response to enabling the clocked gate circuit 150, the multi-bit storage system 110 including the clocked gate circuit (e.g., the clocked gate circuit 150) sets or adjusts the trigger signal (e.g., the trigger signal 105) in accordance with a first edge of the clock signal (e.g., the clock signal 155). In one approach, in response to enabling the clocked gate circuit 150, the clocked gate circuit 150 can wait for a rising edge of the clock signal 155. While waiting for the rising edge of the clock signal 155, the clocked gate circuit 150 can set or maintain the trigger signal 105 having the second state (e.g., a logic value of "0"). In response to detecting the rising edge of the clock signal 155, while the clocked gate circuit 150 is enabled, the clocked gate circuit 150 can change or adjust the state of the trigger signal 105 from the second state (e.g., a logic value of "0") to the first state (e.g., a logic value of "1").

[0174] In operation 750, in response to the trigger signal (e.g., trigger signal 105), the multi-bit storage system 110 including the storage circuits (e.g., storage circuits 120A...120N) can update the output bits (e.g., output bits Out_A...Out_N) of the storage circuits according to the input bits (e.g., input bits In_A...In_N). In one approach, each storage circuit 120X can receive the trigger signal 105 from operation 750 and update the output bit Out_X according to the input bit In_X. For example, in response to a rising edge of the trigger signal 105, the storage circuit 120X can replace the output bit Out_X with the input bit In_X. After the output bits are updated, the multi-bit storage system 110 can return to operation 705.

[0175] In operation 745, in response to the disable clock gating circuit 150, the multi-bit storage system 110 including the clock gating circuit 150 (e.g., clock gating circuit 150) can set or adjust the trigger signal (e.g., trigger signal 105) according to the second edge of the clock signal (e.g., clock signal 155). In one approach, in response to the disable clock gating circuit 150, the clock gating circuit 150 can wait for a falling edge of the clock signal 155. In response to detecting the falling edge of the clock signal 155, the clock gating circuit 150 can set or maintain the trigger signal 105 to have the second state (e.g., logic value "0").

[0176] In operation 755, in response to the trigger signal (e.g., trigger signal 105) having the second state (e.g., logic value "0") without a rising edge, the multi-bit storage system 110 including the storage circuits (e.g., storage circuits 120A...120N) can maintain the output bits (e.g., output bits Out_A...Out_N). While maintaining the output bits (e.g., output bits Out_A...Out_N), the multi-bit storage system 110 can perform operation 705 and / or operation 730 until the trigger signal (e.g., trigger signal 105) is updated to have a rising edge in response to any change in the input bits in operation 740.

[0177] Advantageously, the clock gating circuit 150 dynamically or adaptively generates or adjusts the trigger signal 105 in response to the trigger enable signal 135 indicating whether a change in state of at least one of the output bits Out_A...Out_N is predicted. By dynamically or adaptively generating the trigger signal 105 in response to the prediction of whether a change in state of at least one of the output bits Out_A...Out_N is predicted, the number of toggles of the trigger signal 105 can be reduced compared to the number of toggles of the clock signal 155. As a result, the clock gating circuit 150 can drive the storage circuits 120A...120N in an energy-efficient manner.

[0178] Figure 8 An example layout 800 of a multi-bit storage system 110 according to some embodiments. Figure 1 In some embodiments, the multi-bit storage system 110 includes an even number of storage circuits 120A...120N. In one aspect, a first set of the storage circuits 120A...120N is disposed in a first region 810A, and a second set of the storage circuits 120A...120N is disposed in a second region 810B, with the prediction circuit 130 and the clock gating circuit 150 disposed in a third region 820 between the first region 810A and the second region 810B. By disposing the prediction circuit 130 and the clock gating circuit 150 between the first set of storage circuits 120A...120N and the second set of storage circuits 120, the distance between the storage circuit farthest from the prediction circuit 130 and the clock gating circuit 150 can be reduced. As a result, the delay caused by the logic computations performed by the prediction circuit 130 and the clock gating circuit 150 can be reduced.

[0179] Referring now to Figure 9 An example block diagram of a computing system 900 is shown, in accordance with some embodiments of the present disclosure. The computing system 900 is used by a circuit or layout designer for integrated circuit design. As used in some embodiments herein, a "circuit" is an interconnection of electrical components, such as resistors, transistors, switches, batteries, inductors, or other types of semiconductor elements for implementing a desired function. The computing system 900 includes a host device 905 associated with a memory element 910. The host device 905 can be used to receive input from one or more input devices 915 and provide output to one or more output devices 920. The host device 905 can be used to communicate with the memory element 910, the input devices 915, and the output devices 920 via appropriate interfaces 925A, 925B, and 925C, respectively. The computing system 900 can be implemented in a variety of computing devices, such as a computer (e.g., desktop, laptop, server, data center, etc.), a tablet computer, a personal digital assistant, a mobile device, other handheld or portable device, or any other computing unit suitable for performing schematic and / or layout design using the host device 905.

[0180] Input device 915 can include any of a variety of input technologies, such as a keyboard, a stylus, a touch screen, a mouse, a trackball, a keypad, a microphone, voice recognition, motion recognition, a remote control, an input port, one or more buttons, a dial, a joystick, and any other input peripheral associated with host device 905 and allowing an external source, such as a user (e.g., a circuit or layout designer), to enter information (e.g., data) into and send instructions to host device 905. Similarly, output device 920 can include a variety of output technologies, such as an external memory, a printer, a speaker, a display, a microphone, a light emitting diode, a headset, a video device, and any other output peripheral to receive information (e.g., data) from host device 905. The "data" input to and / or output from host device 905 can include any of a variety of textual data, circuit data, signal data, semiconductor element data, graphical data, combinations thereof, or other types of analog and / or digital data suitable for processing using computing system 900.

[0181] The host device 905 includes one or more processing units / processors, such as central processing unit ("CPU") cores 930A-930N, or is associated with the same. The CPU cores 930A-930N can be implemented as special application integrated circuits ("ASICs"), field programmable gate arrays ("FPGAs"), or any other type of processing unit. Each of the CPU cores 930A-930N can be used to execute instructions for running one or more application programs of the host device 905. In some embodiments, the instructions and data to run one or more application programs can be stored within the memory element 910. The host device 905 can also be used to store results of running one or more application programs within the memory element 910. Thus, the host device 905 can be used to request the memory element 910 to perform a variety of operations. For example, the host device 905 can request the memory element 910 to read data, write data, update or delete data, and / or perform administrative or other operations. One such application program that the host device 905 can be used to run can be a standard cell application program 935. The standard cell application program 935 can be part of a computer-aided design or electronic design automation software suite that can be used by a user of the host device 905 to use, create, or modify standard cells of a circuit. In some embodiments, the instructions to execute or run the standard cell application program 935 can be stored within the memory element 910. The standard cell application program 935 can be executed by one or more of the CPU cores 930A-930N using instructions associated with the standard cell application program from the memory element 910. In one example, the standard cell application program 935 allows a user to utilize pre-generated schematics and / or layout maps of the multi-bit storage system 110 or a portion of the multi-bit storage system 110. After the layout design of the integrated circuit is complete, multiple portions of the integrated circuit (e.g., including the multi-bit storage system 110 or a portion of the multi-bit storage system 110) can be manufactured by a manufacturing facility according to the layout design.

[0182] Still referring to Figure 9Memory element 910 includes a memory controller 940 to read data from or write data to memory array 945. Memory array 945 can include a variety of volatile and / or non-volatile memories. For example, in some embodiments, memory array 945 can include a core of NAND flash memory. In other embodiments, memory array 945 can include a core of NOR flash memory, a core of static random access memory (SRAM), a core of dynamic random access memory (DRAM), a core of magnetoresistive random access memory (MRAM), a core of phase change memory (PCM), a core of resistive random access memory (ReRAM), a core of 3D XPoint memory, a core of ferroelectric random access memory (FeRAM), and other types of memory cores suitable for use within a memory array. The memories within memory array 945 can be controlled individually and independently by memory controller 940. In other words, memory controller 940 can be used to individually and independently communicate with each memory within memory array 945. By communicating with memory array 945, memory controller 940 can be used to read data from or write data to memory array 945 in response to instructions received from host device 905. Although shown as part of memory element 910, in some embodiments, memory controller 940 can be part of host device 905 or part of another component of computing system 900 and associated with memory element. Memory controller 940 can be implemented as a logic circuit in software, hardware, firmware, or a combination thereof to perform the functions described herein. For example, in some embodiments, upon receiving a request from host device 905, memory controller 940 can be used to retrieve instructions associated with standard cell application 935 stored in memory array 945 of memory element 910.

[0183] It should be appreciated that Figure 9 Only some components of computing system 900 are shown and described in FIG. 9. However, computing system 900 can include other components, such as various batteries and power sources, network interfaces, routers, switches, external memory systems, controllers, and the like. In general, computing system 900 can include any of a variety of hardware, software, and / or firmware necessary or deemed necessary in performing the functions described herein. Similarly, host device 905, input device 915, output device 920, and memory element 910 (including controller 940 and memory array 945) can include other hardware, software, and / or firmware components deemed necessary or required in performing the functions described herein in some embodiments.

[0184] One aspect of the description is directed to an integrated circuit including a multi-bit storage system. In some embodiments, the integrated circuit includes a first storage circuit to update a first output bit based on a first input bit in response to a trigger signal. In some embodiments, the integrated circuit includes a second storage circuit to update a second output bit based on a second input bit in response to the trigger signal. In some embodiments, the integrated circuit includes a prediction circuit coupled to the first storage circuit and the second storage circuit. The prediction circuit is to generate a trigger enable signal indicating whether at least one of the first output bit or the second output bit is predicted to change state. In some embodiments, the integrated circuit includes a clock gating circuit coupled to the prediction circuit. The clock gating circuit is to generate the trigger signal based on a rising edge of a clock signal in response to the trigger enable signal indicating that at least one of the first output bit or the second output bit is predicted to change state, and to generate the trigger signal based on a falling edge of the clock signal in response to the trigger enable signal indicating that (i) the first output bit is predicted to remain unchanged, and (ii) the second output bit is predicted to remain unchanged.

[0185] In some embodiments, the clock gating circuit is to adjust the trigger signal based on a rising edge of a clock signal in response to the trigger enable signal indicating that at least one of the first output bit or the second output bit is predicted to change state, and to adjust the trigger signal based on a falling edge of the clock signal in response to the trigger enable signal indicating that (i) the first output bit is predicted to remain unchanged, and (ii) the second output bit is predicted to remain unchanged.

[0186] In some embodiments, the prediction circuit is to generate a first prediction signal indicating whether the first output bit is predicted to change state, and to generate a second prediction signal indicating whether the second output bit is predicted to change state.

[0187] In some embodiments, the prediction circuit includes an OR gate. The OR gate includes a plurality of input ports and an output port. The input ports are coupled to the first storage circuit and the second storage circuit. The output port is coupled to the clock gating circuit. The OR gate receives the first prediction signal and the second prediction signal at the input ports, and generates the trigger enable signal at the output port based on at least one of the first prediction signal or the second prediction signal.

[0188] In some embodiments, the OR gate is to generate the trigger enable signal having a first state indicating that at least one of the first output bit or the second output bit is predicted to change state in response to at least one of (i) the first prediction signal indicating that the first output bit is predicted to change state, or (ii) the second prediction signal indicating that the second output bit is predicted to change state, and to generate the trigger enable signal having a second state indicating that the first output bit and the second output bit are predicted to remain unchanged in response to (i) the first prediction signal indicating that the first output bit is predicted to remain unchanged, and (ii) the second prediction signal indicating that the second output bit is predicted to remain unchanged.

[0189] In some embodiments, the prediction circuit further comprises an XOR gate. The XOR gate comprises a first input port, a second input port, and an output port. The first input port is coupled to the input port of the storage circuit, the first input port to receive the first input bit. The second input port is coupled to the output port of the storage circuit, the second input port to receive the first output bit from the output port of the storage circuit. The output port is coupled to one of the input ports of the OR gate, the output port of the XOR gate to output the first prediction signal according to the first input bit and the first output bit.

[0190] In some embodiments, the XOR gate is to compare the first input bit received at the first input port of the XOR gate with the first output bit received at the second input port of the XOR gate; and generate the first prediction signal at the output port of the XOR gate according to a result of the comparison.

[0191] In some embodiments, the XOR gate is to generate the first prediction signal having a first state in response to the first input bit and the first output bit being different, the first state indicating that the state of the first output bit is predicted to change; and generate the first prediction signal having a second state in response to the first input bit and the first output bit being equal to each other, the second state indicating that the state of the first output bit is predicted to remain unchanged.

[0192] In some embodiments, the prediction circuit and the clock gating circuit are disposed between the first storage circuit and the second storage circuit.

[0193] In some embodiments, the first storage circuit is a first flip-flop circuit, and the second storage circuit is a second flip-flop circuit. The prediction circuit comprises a first XOR gate, a second XOR gate, and an OR gate. The first XOR gate has an input port coupled to an output port of the first flip-flop circuit. The second XOR gate has an input port coupled to an output port of the second flip-flop circuit. The OR gate has a first input port coupled to an output port of the first XOR gate, a second input port coupled to an output port of the second XOR gate, and an output port coupled to the output port of the clock gating circuit.

[0194] One aspect of the description is directed to an integrated circuit including a multi-bit storage system. In some embodiments, the integrated circuit includes a first storage circuit to update a first output bit based on a first input bit in response to a trigger signal. In some embodiments, the integrated circuit includes a second storage circuit to update a second output bit based on a second input bit in response to the trigger signal. In some embodiments, the integrated circuit includes a prediction circuit coupled to the first storage circuit and the second storage circuit. In some embodiments, the prediction circuit is to predict whether a state of the first output bit is predicted to change and to predict whether a state of the second output bit is predicted to change. In some embodiments, the prediction circuit is to generate a trigger enable signal based on the prediction of whether the state of the first output bit is predicted to change and the prediction of whether the state of the second output bit is predicted to change. The trigger signal can be generated based at least in part on the trigger enable signal.

[0195] In some embodiments, the integrated circuit further includes a clock gating circuit. The clock gating circuit is coupled to the first storage circuit and the second storage circuit. The clock gating circuit is to adjust the trigger signal based on a rising edge of a clock signal in response to the trigger enable signal indicating at least one of (i) the state of the first output bit is predicted to change or (ii) the state of the second output bit is predicted to change and to adjust the trigger signal based on a falling edge of the clock signal in response to the trigger enable signal indicating (i) the state of the first output bit is predicted to remain unchanged and (ii) the state of the second output bit is predicted to remain unchanged.

[0196] In some embodiments, the first storage circuit includes a flip-flop circuit. The flip-flop circuit includes an input port, a clock port, and an output port. The input port is to receive the first input bit. The clock port is coupled to the clock gating circuit. The clock port is to receive the trigger signal from the clock gating circuit. The output port is to provide the first output bit.

[0197] In some embodiments, the prediction circuit includes an exclusive OR gate. The exclusive OR gate includes a first input port, a second input port, and an output port. The first input port is coupled to the input port of the flip-flop circuit to receive the first input bit. The second input port is coupled to the output port of the flip-flop circuit to receive the first output bit from the output port of the flip-flop circuit. The output port is to output a first prediction signal indicating whether the state of the first output bit is predicted to change based on the first input bit and the first output bit. The trigger enable signal is generated based at least in part on the first prediction signal.

[0198] In some embodiments, the XOR gate is to compare a first input bit received at a first input port of the XOR gate with a first output bit received at a second input port of the XOR gate; and generate the first prediction signal in accordance with a result of the comparison.

[0199] In some embodiments, the prediction circuit and the clock gating circuit are disposed between the first storage circuit and the second storage circuit.

[0200] In some embodiments, the first storage circuit is a first flip-flop circuit, and the second storage circuit is a second flip-flop circuit. The prediction circuit includes a first XOR gate, a second XOR gate, and an OR gate. The first XOR gate has an input port coupled to an output of the first flip-flop circuit. The second XOR gate has an input port coupled to an output of the second flip-flop circuit. The OR gate has a first input port coupled to an output port of the first XOR gate, a second input port coupled to an output port of the second XOR gate, and an output port coupled to the clock gating circuit.

[0201] One aspect of the description is directed to a method of operating a multi-bit storage system. In some embodiments, the method includes determining whether at least one of a plurality of output bits of a plurality of flip-flop circuits is predicted to change state. In some embodiments, the method includes enabling a clock gating circuit in response to determining that the at least one of the output bits of the flip-flop circuits is predicted to change the state. In some embodiments, the method includes adjusting a trigger signal from a first state to a second state in accordance with a first edge of a clock signal when the clock gating circuit is enabled. In some embodiments, the method includes updating one or more of the output bits of the flip-flop circuits in accordance with one or more corresponding input bits in response to the trigger signal changing from the first state to the second state. In some embodiments, the method includes disabling the clock gating circuit in response to determining that the output bits of the flip-flop circuits are predicted to remain unchanged. In some embodiments, the method includes resetting a state of the trigger signal to the second state in accordance with a second edge of the clock signal when the clock gating circuit is disabled. In some embodiments, the first edge of the clock signal is one of a rising edge and a falling edge of the clock signal, and wherein the second edge of the clock signal is the other of the rising edge and the falling edge of the clock signal.

[0202] The foregoing overview of features of several embodiments enables one of ordinary skill in the art to better understand the nature of some embodiments of the present disclosure. One of ordinary skill in the art will readily understand that they can use some embodiments of the present disclosure as a basis for designing or modifying other processes and structures to implement the same purposes and / or achieve the same advantages of the embodiments introduced herein without departing from the spirit and scope of some embodiments of the present disclosure. One of ordinary skill in the art will also recognize the interchangeable use of the terms "logic" and "circuit" in some embodiments of the present disclosure, and will appreciate that they can employ both structures and techniques in some embodiments of the present disclosure without departing from the spirit and scope of some embodiments of the present disclosure.

Claims

1. An integrated circuit, characterized in that, include: A first storage circuit is used to update a first output bit in response to a trigger signal based on a first input bit; A second storage circuit is provided to update a second output bit in response to the trigger signal based on a second input bit. A prediction circuit, coupled to the first storage circuit and the second storage circuit, is used to generate a trigger enable signal indicating whether it is predicted that at least one of the first output bit or the second output bit will change a state. as well as A clock-gated circuit, coupled to the prediction circuit, includes an AND gate and a set of transistors coupled to the AND gate, the set of transistors being used to detect an edge of a clock signal, wherein the clock-gated circuit is used to: Based on the trigger enable signal and according to a first edge of the clock signal, a trigger signal having a first state is generated; and The trigger signal remains in the first state until a second edge of the clock signal following the first edge appears.

2. The integrated circuit according to claim 1, characterized in that, This clock gate circuit is used for: In response to the trigger enable signal, wherein the trigger enable signal indicates that at least one of the first output bit or the second output bit is predicted to change its state, the trigger signal is adjusted according to a rising edge of the clock signal; and In response to the trigger enable signal indicating (i) that the state of the first output bit is predicted to remain unchanged; and (ii) that the state of the second output bit is predicted to remain unchanged, the trigger signal is adjusted according to a falling edge of the clock signal.

3. The integrated circuit according to claim 1, characterized in that, This predictive circuit is used for: Generate a first prediction signal indicating whether it is predicted that the state of the first output bit will change; as well as A second prediction signal is generated to indicate whether the state of the second output bit is predicted to change.

4. The integrated circuit according to claim 3, characterized in that, The prediction circuit includes: One OR gate, including: Multiple input ports are coupled to the first storage circuit and the second storage circuit; and An output port is coupled to a clock gating circuit. The OR gate receives the first prediction signal and the second prediction signal at the plurality of input ports and generates the trigger enable signal at the output port based on at least one of the first prediction signal or the second prediction signal.

5. The integrated circuit according to claim 4, characterized in that, The OR gate is used to: In response to (i) the first prediction signal indicating that the state of the first output bit is predicted to change; or (ii) the second prediction signal indicating that the state of the second output bit is predicted to change, a trigger enable signal having a second state indicating that at least one of the state of the first output bit or the state of the second output bit is predicted to change. as well as In response to (i) the first prediction signal indicating that the state predicted for the first output bit will remain unchanged; (ii) The second prediction signal indicates that the state of the second output bit is predicted to remain unchanged, and generates the trigger enable signal having a third state, the third state indicating that the state of the first output bit and the state of the second output bit are predicted to remain unchanged.

6. The integrated circuit according to claim 4, characterized in that, The prediction circuit further includes: An XOR gate includes: A first input port is coupled to an input port of the first storage circuit, the first input port being used to receive the first input bit; A second input port is coupled to an output port of the first storage circuit, the second input port being used to receive the first output bit from the output port of the first storage circuit; as well as An output port is coupled to one of the plurality of input ports of the OR gate, the output port of the XOR gate being used to output the first prediction signal based on the first input bit and the first output bit.

7. The integrated circuit according to claim 6, characterized in that, The XOR gate is used to: Compare the first input bit received at the first input port of the XOR gate with the first output bit received at the second input port of the XOR gate; as well as Based on the result of the comparison, the first prediction signal is generated at the output port of the XOR gate.

8. The integrated circuit according to claim 7, characterized in that, The XOR gate is used to: In response to the difference between the first input bit and the first output bit, a first prediction signal with a second state is generated, the second state indicating that the state of the first output bit is predicted to change. as well as In response to the first input bit and the first output bit being equal to each other, a first prediction signal with a third state is generated, the third state indicating that the predicted state of the first output bit will remain unchanged.

9. The integrated circuit according to claim 1, characterized in that, The prediction circuit and the clock gating circuit are located between the first storage circuit and the second storage circuit.

10. The integrated circuit according to claim 1, characterized in that, The AND gate includes a NAND gate and an inverter circuit coupled to an output of the NAND gate, wherein the set of transistors is coupled to an input of the NAND gate and an output of the NAND gate.

11. An integrated circuit, characterized in that, include: A first storage circuit is configured to update a first output bit in response to a trigger signal based on a first input bit; A second storage circuit for updating a second output bit according to a second input bit in response to the trigger signal; A prediction circuit, coupled to the first storage circuit and the second storage circuit, is used to: Predict whether a state of the first output bit will change; Predict whether a state of the second output bit will change; as well as A trigger enable signal is generated based on a prediction of whether the state of the first output bit will change and a prediction of whether the state of the second output bit will change. The trigger enable signal is generated at least in part based on the trigger enable signal. as well as A clock-gated circuit, coupled to the first storage circuit and the second storage circuit, wherein the clock-gated circuit includes an AND gate and a set of transistors coupled to the AND gate, the set of transistors being used to detect an edge of a clock signal, wherein the clock-gated circuit is used to: The trigger signal is adjusted according to a first edge of the clock signal and the trigger enable signal; and The adjusted trigger signal is maintained until a second edge of the clock signal following the first edge appears.

12. The integrated circuit according to claim 11, characterized in that, This clock gate circuit is used for: In response to at least one of the trigger enable signal indicating (i) a predicted change in the state of the first output bit; or (ii) a predicted change in the state of the second output bit, the trigger signal is adjusted based on a rising edge of the clock signal; and In response to the trigger enable signal indicating (i) that the state of the first output bit is predicted to remain unchanged; and (ii) that the state of the second output bit is predicted to remain unchanged, the trigger signal is adjusted according to a falling edge of the clock signal.

13. The integrated circuit according to claim 12, characterized in that, The first storage circuit includes: A flip-flop circuit includes: An input port is used to receive the first input bit; A clock port is coupled to the clock gating circuit, and the clock port is used to receive the trigger signal from the clock gating circuit; as well as An output port is used to provide a first output bit.

14. The integrated circuit according to claim 13, characterized in that, The prediction circuit includes: An XOR gate includes: A first input port is coupled to the input port of the flip-flop circuit, the first input port being used to receive the first input bit; A second input port is coupled to the output port of the flip-flop circuit, the second input port being used to receive the first output bit from the output port of the flip-flop circuit; as well as An output port is configured to output a first prediction signal, based on the first input bit and the first output bit, indicating whether a change in the state of the first output bit is predicted, the trigger enable signal being generated at least in part based on the first prediction signal.

15. The integrated circuit according to claim 14, characterized in that, The XOR gate is used to: Compare the first input bit received at the first input port of the XOR gate with the first output bit received at the second input port of the XOR gate; and The first prediction signal is generated based on the result of this comparison.

16. The integrated circuit according to claim 12, characterized in that, The prediction circuit and the clock gating circuit are located between the first storage circuit and the second storage circuit.

17. The integrated circuit according to claim 11, characterized in that, The AND gate includes a NAND gate and an inverter circuit coupled to an output of the NAND gate, wherein the set of transistors is coupled to an input of the NAND gate and an output of the NAND gate.

18. A method for operating an integrated circuit system, characterized in that, include: Determine whether it is predicted that at least one of the multiple output bits of multiple flip-flop circuits will change a state; In response to the determination that at least one of the plurality of output bits of the plurality of flip-flop circuits will change the state, a clock gating circuit is enabled, the clock gating circuit including an AND gate and a set of transistors coupled to the AND gate for detecting an edge of a clock signal. When the clock gating circuit is enabled, a trigger signal is adjusted from a first state to a second state through the clock gating circuit according to a first edge of the clock signal. The clock gating circuit maintains the second state of the trigger signal until a second edge of the clock signal following the first edge appears; and In response to the trigger signal changing from the first state to the second state, one or more of the plurality of output bits of the plurality of flip-flop circuits are updated according to one or more corresponding input bits.

19. The method according to claim 18, characterized in that, Further includes: In response to the decision that the plurality of output bits of the plurality of flip-flop circuits will remain unchanged, the clock gating circuit is disabled; as well as When the clock gating circuit is deactivated, the state of the trigger signal is reset to the first state according to a second edge of the clock signal.

20. The method according to claim 19, characterized in that, The first edge of the clock signal is one of a rising edge and a falling edge of the clock signal, and the second edge of the clock signal is the other of the rising edge and the falling edge of the clock signal.

21. An integrated circuit, characterized in that, include: Multiple storage circuits are used to update multiple output bits in response to a trigger signal; A prediction circuit is used to generate a trigger enable signal that indicates whether it is predicted that at least one of the plurality of output bits will change a state. as well as A clock-gated circuit is used to: Based on the trigger enable signal, the trigger signal having a first state is generated according to a first edge of a clock signal; as well as The trigger signal remains in the first state until a second edge appears following the first edge of the clock signal.

22. The integrated circuit according to claim 21, characterized in that, This clock gate circuit is used for: In response to the trigger enable signal indicating that at least one of the output bits is predicted to change its state, the trigger signal is adjusted according to a rising edge of the clock signal; and In response to the trigger enable signal indicating that the multiple states of the multiple output bits are predicted to remain unchanged, the trigger signal is adjusted according to a falling edge of the clock signal.

23. The integrated circuit according to claim 21, characterized in that, The prediction circuit generates multiple prediction signals, each of which indicates whether a state of a corresponding output bit among the multiple output bits is predicted to change.

24. The integrated circuit according to claim 23, characterized in that, The prediction circuit includes: One OR gate, including: Multiple input ports are used to receive the multiple prediction signals; as well as An output port is provided for generating the trigger enable signal based on at least one of the plurality of predicted signals.

25. The integrated circuit according to claim 24, characterized in that, The OR gate is used to: In response to at least one of the plurality of prediction signals indicating that the state of the corresponding output bit is predicted to change, a trigger enable signal having a second state is generated, the second state indicating that at least one of the plurality of output bits is predicted to change. as well as In response to each of the plurality of prediction signals indicating that the state of the corresponding output bit is predicted to remain unchanged, a trigger enable signal with a third state is generated, the third state indicating that the plurality of states of the plurality of output bits are predicted to remain unchanged.

26. The integrated circuit according to claim 24, characterized in that, The prediction circuit further includes: An XOR gate includes: A first input port is provided to receive an input bit, which is provided as an input to a first storage circuit among the plurality of storage circuits. A second input port is used to receive an output bit from the plurality of output bits from the first storage circuit; as well as An output port is provided for outputting one of the plurality of prediction signals based on the input bits and the output bits.

27. The integrated circuit according to claim 26, characterized in that, The XOR gate is used to: Compare the input bit and the output bit; and Based on the comparison, the predicted signal is generated at the output port of the XOR gate.

28. The integrated circuit according to claim 27, characterized in that, The XOR gate is used to: In response to the difference between the input bit and the output bit, a prediction signal with a second state is generated, the second state indicating that a state of the output bit is predicted to change. as well as In response to the same input bit and the same output bit, a prediction signal with a third state is generated, the third state indicating that the state of the output bit is predicted to remain unchanged.

29. The integrated circuit according to claim 21, characterized in that, The prediction circuit and the clock gating circuit are positioned between two of the plurality of storage circuits.

30. An integrated circuit, characterized in that, include: A first storage circuit for updating a first output bit according to a first input bit in response to a trigger signal; A second storage circuit is used to update a second output bit according to a second input bit in response to the trigger signal; A predictive circuit, used to: Predict whether a state of the first output bit will change; Predict whether a state of the second output bit will change; as well as A trigger enable signal is generated based on a prediction of whether a state of the first output bit will change and a prediction of whether a state of the second output bit will change. The trigger enable signal is generated at least in part based on the trigger enable signal. as well as A clock-gated circuit is used to: Adjust the trigger signal according to a first edge of a clock signal and the trigger enable signal; and The adjusted trigger signal is maintained until a second edge appears following the first edge of the clock signal.

31. The integrated circuit according to claim 30, characterized in that, This clock gate circuit is used for: In response to at least one of the trigger enable signal indicating (i) that the state of the first output bit is predicted to change or (ii) that the state of the second output bit is predicted to change, the trigger signal is adjusted according to a rising edge of the clock signal; and In response to the trigger enable signal indicating (i) that the state of the first output bit is predicted to remain unchanged and (ii) that the state of the second output bit is predicted to remain unchanged, the trigger signal is adjusted according to a falling edge of the clock signal.

32. The integrated circuit according to claim 31, characterized in that, The first storage circuit includes: A flip-flop circuit includes: An input port is used to receive the first input bit; A clock port is used to receive the trigger signal from the clock gating circuit; as well as An output port is used to provide the first output bit.

33. The integrated circuit according to claim 32, characterized in that, The prediction circuit includes: An XOR gate includes: A first input port is used to receive the first input bit; A second input port is provided for receiving the first output bit from the output port of the flip-flop circuit. as well as An output port is provided for outputting a first prediction signal based on the first input bit and the first output bit, the first prediction signal indicating whether the state of the first output bit is predicted to change, and the trigger enable signal is generated at least in part based on the first prediction signal.

34. The integrated circuit according to claim 33, characterized in that, The XOR gate is used to: Compare the first input bit received at the first input port of the XOR gate with the first output bit received at the second input port of the XOR gate; as well as The first prediction signal is generated based on the comparison.

35. The integrated circuit according to claim 34, characterized in that, The XOR gate is used to: In response to the difference between the first input bit and the first output bit, a first prediction signal with a first state is generated, the first state indicating that the state of the first output bit is predicted to change. as well as In response to the first input bit and the first output bit being the same, a first prediction signal with a second state is generated, the second state indicating that the state of the first output bit is predicted to remain unchanged.

36. The integrated circuit according to claim 32, characterized in that, The prediction circuit and the clock gating circuit are positioned between the first storage circuit and the second storage circuit.

37. A method for operating an integrated circuit system, characterized in that, include: Determine whether at least one of the multiple output bits of multiple storage circuits is predicted to change a state; In response to determining whether at least one of the plurality of output bits of the plurality of storage circuits is predicted to change the state, a clock gating circuit is enabled. When the clock gating circuit is enabled, in response to a first edge of a clock signal, a trigger signal is adjusted from a first state to a second state through the clock gating circuit. The clock gating circuit maintains the second state of the trigger signal until a second edge following the first edge of the clock signal appears; and In response to the trigger signal changing from the first state to the second state, one or more of the output bits of the plurality of storage circuits are updated according to one or more corresponding input bits.

38. The method according to claim 37, characterized in that, Further includes: In response to the determination that the plurality of output bits of the plurality of storage circuits are predicted to remain unchanged, the clock gating circuit is deactivated.

39. The method according to claim 38, characterized in that, Further includes: In response to the second edge of the clock signal, the trigger signal is reset to have the first state.

40. The method according to claim 38, characterized in that, The first edge of the clock signal is one of a rising edge and a falling edge of the clock signal, and the second edge of the clock signal is the other of the rising edge and the falling edge of the clock signal.

Images