Semiconductor device and method for forming the same

Abstract

The present disclosure relates to semiconductor devices and methods for forming the same. One method includes forming a gate electrode on a semiconductor region, recessing the gate electrode to form a groove, performing a first deposition process to form a first metal layer on the gate electrode and in the groove, wherein the first deposition process is performed using a first precursor, and performing a second deposition process using a second precursor different from the first precursor to form a second metal layer on the first metal layer. The first metal layer and the second metal layer contain the same metal. The method also includes forming a dielectric hard mask over the second metal layer and forming a gate contact plug through the dielectric hard mask. The gate contact plug contacts a top surface of the second metal layer.

Description

Technical Field

[0001] The present disclosure relates to semiconductor devices and methods of forming the same. Background Art

[0002] Metal oxide semiconductor (MOS) devices are fundamental building blocks in integrated circuits. Existing MOS devices typically have a gate electrode formed from polysilicon doped with p-type or n-type impurities (using doping operations such as ion implantation or thermal diffusion). The work function of the gate electrode can be tuned to the band-edge of silicon. For n-type metal oxide semiconductor (NMOS) devices, the work function can be tuned to approach the conduction band of silicon. For p-type metal oxide semiconductor (PMOS) devices, the work function can be tuned to approach the valence band of silicon. By selecting appropriate impurities, tuning the work function of the polysilicon gate electrode can be achieved.

[0003] MOS devices with polysilicon gate electrodes exhibit carrier depletion, also known as the polysilicon depletion effect. The polysilicon depletion effect occurs when an applied electric field sweeps carriers from the gate region near the gate dielectric, forming a depletion layer. In n-doped polysilicon layers, the depletion layer consists of ionized, non-mobile donor sites, whereas in p-doped polysilicon layers, the depletion layer consists of ionized, non-mobile acceptor sites. The depletion effect results in an increase in the effective gate dielectric thickness, making it more difficult to create an inversion layer at the surface of the semiconductor.

[0004] The poly depletion problem can be solved by forming a metal gate electrode, wherein the metal gate used in NMOS devices and PMOS devices can also have a band-edge work function. Therefore, the resulting metal gate includes multiple layers to accommodate the requirements of NMOS devices and PMOS devices. Summary of the Invention

[0005] According to one embodiment of the present disclosure, a method for forming a semiconductor device is provided, comprising: forming a gate electrode over a semiconductor region; recessing the gate electrode to generate a groove; performing a first deposition process to form a first metal layer over the gate electrode and in the groove, wherein the first deposition process is performed using a first precursor; performing a second deposition process using a second precursor different from the first precursor to form a second metal layer on the first metal layer, wherein the first metal layer and the second metal layer contain the same metal; forming a dielectric hard mask over the second metal layer; and forming a gate contact plug through the dielectric hard mask, wherein the gate contact plug contacts a top surface of the second metal layer.

[0006] According to another embodiment of the present disclosure, a semiconductor device is provided, comprising: a semiconductor region; a gate dielectric located above the semiconductor region; a gate electrode comprising: a first portion including a work function layer located in the first portion; and a second portion covering the first portion and in contact with the first portion, wherein the second portion includes fluorine and chlorine, and wherein the second portion comprises: a bottom sublayer, wherein a first peak atomic percentage of chlorine is in the bottom sublayer; and a top sublayer located above the bottom sublayer and in contact with the bottom sublayer, wherein a second peak atomic percentage of fluorine is in the top sublayer, and wherein the bottom sublayer and the top sublayer contain the same metal; and a gate contact plug located above the top sublayer and in contact with the top sublayer.

[0007] According to another embodiment of the present disclosure, a semiconductor device is provided, comprising: a semiconductor substrate; an isolation region extending into the semiconductor substrate; a semiconductor fin protruding higher than a portion of the isolation region located on an opposite side of the semiconductor fin; and a gate stack comprising: a high-k gate dielectric located on the semiconductor fin; a work function layer located on the high-k gate dielectric; a barrier layer; a first tungsten layer located above and in contact with the work function layer and the barrier layer; and a second tungsten layer located above and in contact with the first tungsten layer, wherein the first tungsten layer and the second tungsten layer are distinguishable from each other. BRIEF DESCRIPTION OF THE DRAWINGS

[0008] Various aspects of the present disclosure will be best understood from the following detailed description when read in conjunction with the accompanying drawings. It should be noted that, in accordance with standard practice in the industry, various features are not drawn to scale. In fact, the dimensions of the various features may be arbitrarily increased or decreased for clarity of discussion.

[0009] Figures 1-6 、 Figure 7A 、 Figure 7B 、 Figure 8A 、 Figure 8B 、 Figures 9-19 、 Figure 20A and Figure 20B Cross-sectional and perspective views illustrate intermediate stages in the formation of a fin field effect transistor (FinFET), according to some embodiments.

[0010] Figure 21 A plan view of a FinFET is shown in accordance with some embodiments.

[0011] Figure 22 The distribution of some elements according to some embodiments is shown.

[0012] Figure 23A flowchart illustrating a process flow for forming a FinFET according to some embodiments is shown. DETAILED DESCRIPTION

[0013] The following disclosure provides many different embodiments or examples for implementing the different features of the present invention. Specific examples of components and arrangements are described below to simplify the present disclosure. Of course, these are merely examples and are not intended to be limiting. For example, in the following description, forming a first feature above or on a second feature may include an embodiment in which the first feature and the second feature are formed in direct contact, and may also include an embodiment in which an additional feature may be formed between the first feature and the second feature so that the first feature and the second feature may not be in direct contact. In addition, the present disclosure may repeat reference numerals and / or characters in various examples. This repetition is for the purpose of simplicity and clarity and does not, in itself, represent a relationship between the various embodiments and / or configurations discussed.

[0014] Furthermore, spatially relative terms (e.g., "below," "beneath," "below," "above," "upper," etc.) may be used herein to facilitate describing the relationship of one element or feature relative to another element or feature(s) illustrated in the figures. These spatially relative terms are intended to encompass different orientations of the device in use or operation in addition to the orientation depicted in the figures. The device may be otherwise oriented (rotated 90 degrees or at other orientations), and the spatially relative descriptors used herein should be interpreted accordingly.

[0015] According to some embodiments, a transistor having a hybrid capping layer and a method for forming the same are provided. A first low-resistivity conductive layer is formed over and in contact with a recessed metal gate. The first low-resistivity conductive layer is used as a seed layer so that a second low-resistivity conductive layer is selectively formed to a desired thickness. The resistivity of the low-resistivity conductive layer is lower than the resistivity of at least some layers in the metal gate, thereby reducing the overall gate resistance of the metal gate. According to some embodiments, intermediate stages of forming a transistor are shown. Some variations of some embodiments are discussed. In the various views and illustrative embodiments, the same reference numerals are used to represent the same elements. Although method embodiments may be discussed as being performed in a particular order, other method embodiments may be performed in any logical order. According to an embodiment, the formation of a fin field-effect transistor (FinFET) is used as an example to explain the concepts of the present disclosure. Other types of transistors, such as planar transistors, may also employ the concepts of the present disclosure. According to some embodiments of the present disclosure, a metal (replacement) gate of a FinFET is formed. The metal gate is then etched and recessed to generate a groove.

[0016] Figures 1-6 、 Figure 7A、 Figure 7B 、 Figure 8A 、 Figure 8B 、 Figures 9-19 、 Figure 20A and Figure 20B The cross-sectional and perspective views of intermediate stages in the formation of a FinFET according to some embodiments of the present disclosure are shown. The processes shown in these figures are also schematically reflected in Figure 23 In the process flow 200 shown in FIG.

[0017] refer to Figure 1 , a substrate 20 is provided. The substrate 20 may be a semiconductor substrate, such as a bulk semiconductor substrate, a semiconductor on insulator (SOI) substrate, etc., which may be doped (e.g., doped with p-type or n-type dopants) or undoped. The semiconductor substrate 20 may be a portion of a wafer 10 (e.g., a silicon wafer). Typically, an SOI substrate is a layer of semiconductor material formed on an insulating layer. The insulator layer may be, for example, a buried oxide (BOX) layer, a silicon oxide layer, etc. The insulator layer is disposed on a substrate (typically a silicon or glass substrate). Other substrates, such as multilayer or gradient substrates, may also be used. In some embodiments, the semiconductor material of the semiconductor substrate 20 may include silicon; germanium; compound semiconductors including carbon-doped silicon, gallium arsenide, gallium phosphide, indium phosphide, indium arsenide, and / or indium antimonide; alloy semiconductors including SiGe, GaAsP, AlInAs, AlGaAs, GaInAs, GaInP, and / or GaInAsP; or combinations of the foregoing.

[0018] Further references Figure 1 , a well region 22 is formed in the substrate 20. The corresponding process is Figure 23 The process flow 200 is shown as process 202. According to some embodiments of the present disclosure, the well region 22 is a P-type well region formed by implanting P-type impurities into the substrate 20. The P-type impurities may be boron, indium, etc. According to other embodiments of the present disclosure, the well region 22 is an N-type well region formed by implanting N-type impurities into the substrate 20. The N-type impurities may be phosphorus, arsenic, antimony, etc. The resulting well region 22 may extend to the top surface of the substrate 20. The concentration of N-type or P-type impurities may be equal to or less than 10 18 cm -3 , for example, at about 10 17 cm -3 to about 10 18 cm -3 within the range between.

[0019] refer to Figure 2 , the isolation region 24 is formed to extend from the top surface of the substrate 20 into the substrate 20. The isolation region 24 may be alternatively referred to as a shallow trench isolation (STI) region hereinafter. Figure 23The process flow 200 shown is shown as process 204. The portion of the substrate 20 located between adjacent STI regions 24 is called a semiconductor strip 26. In order to form the STI region 24, a pad oxide layer 28 and a hard mask layer 30 are formed on the semiconductor substrate 20 and then patterned. The pad oxide layer 28 can be a thin film formed of silicon oxide. According to some disclosed embodiments, the pad oxide layer 28 is formed in a thermal oxidation process, in which the top surface layer of the semiconductor substrate 20 is oxidized. The pad oxide layer 28 serves as an adhesion layer between the semiconductor substrate 20 and the hard mask layer 30. The pad oxide layer 28 can also serve as an etch stop layer for etching the hard mask layer 30. According to some embodiments of the present disclosure, the hard mask layer 30 is formed of silicon nitride, for example using low pressure chemical vapor deposition (LPCVD). According to other embodiments of the present disclosure, the hard mask layer 30 is formed by thermal nitridation of silicon or plasma enhanced chemical vapor deposition (PECVD). A photoresist (not shown) is formed on the hard mask layer 30 and then patterned. The hard mask layer 30 is then patterned using the patterned photoresist as an etching mask to form the hard mask 30, as shown in FIG. Figure 2 shown.

[0020] Next, using patterned hard mask layer 30 as an etch mask, pad oxide layer 28 and substrate 20 are etched, followed by filling the resulting trenches in substrate 20 with dielectric material(s). A planarization process, such as a chemical mechanical polishing (CMP) process or a mechanical grinding process, is performed to remove excess dielectric material, and the remaining dielectric material(s) are STI regions 24. STI regions 24 may include a liner dielectric (not shown), which may be a thermal oxide formed by thermal oxidation of a surface layer of substrate 20. The liner dielectric may also be a deposited silicon oxide layer, silicon nitride layer, or the like, formed using, for example, atomic layer deposition (ALD), high-density plasma chemical vapor deposition (HDPCVD), or chemical vapor deposition (CVD). STI regions 24 may also include a dielectric material located above the liner oxide, wherein the dielectric material may be formed using flowable chemical vapor deposition (FCVD), spin coating, or the like. According to some embodiments, the dielectric material located above the liner dielectric may include silicon oxide.

[0021] The top surface of hard mask 30 and the top surface of STI regions 24 can be substantially flush with each other. Semiconductor strips 26 are located between adjacent STI regions 24. According to some embodiments of the present disclosure, semiconductor strips 26 are part of the original substrate 20, and therefore the material of semiconductor strips 26 is the same as the material of substrate 20. According to alternative embodiments of the present disclosure, semiconductor strips 26 are replacement strips formed by etching the portion of substrate 20 located between STI regions 24 to form grooves, and performing epitaxy to re-grow another semiconductor material in the grooves. Thus, semiconductor strips 26 are formed of a semiconductor material different from that of substrate 20. According to some embodiments, semiconductor strips 26 are formed of silicon germanium, silicon carbon, or a III-V compound semiconductor material. Hard mask 30 is then removed.

[0022] refer to Figure 3 , so that the STI region 24 is recessed so that the top portion of the semiconductor strip 26 protrudes above the top surface 24A of the remaining portion of the STI region 24 to form a protruding fin 36. Figure 23 This is shown as process 206 in the illustrated process flow 200. Pad oxide 28 is also removed. Etching can be performed using a dry etch process, where, for example, HF3 and NH3 are used as etching gases. During the etching process, a plasma can be generated. Argon can also be included. According to an alternative embodiment of the present disclosure, recessing of STI regions 24 is performed using a wet etch process. The etching chemistry can include, for example, HF.

[0023] In the above embodiments, the fins can be patterned by any suitable method. For example, the fins can be patterned using one or more photolithography processes including double patterning or multi-patterning processes. Typically, double patterning or multi-patterning processes combine photolithography and self-alignment processes, thereby allowing the spacing of the patterns produced to be smaller than that obtainable using a single direct photolithography process, for example. For example, in one embodiment, a sacrificial layer is formed over a substrate and patterned using a photolithography process. Spacers are formed next to the patterned sacrificial layer using a self-alignment process. The sacrificial layer is then removed, and the remaining spacers or mandrels can then be used to pattern the fins.

[0024] refer to Figure 4 , forming a dummy gate stack 38 to extend over the top surface and sidewalls of the (protruding) fin 36. Figure 23The process flow 200 is shown as process 208. The dummy gate stack 38 may include a dummy gate dielectric 40 and a dummy gate electrode 42 located above the dummy gate dielectric 40. The dummy gate dielectric 40 may be formed of silicon oxide or a similar material. For example, polysilicon may be used to form the dummy gate electrode 42, and other materials may also be used. Each of the dummy gate stacks 38 may also include one (or more) hard mask layers 44 located above the dummy gate electrode 42. The hard mask layer 44 may be formed of silicon nitride, silicon oxide, silicon carbon nitride, or a multilayer thereof. The dummy gate stack 38 may span a single or multiple protruding fins 36 and / or STI regions 24. The length direction of the dummy gate stack 38 is also perpendicular to the length direction of the protruding fin 36.

[0025] Next, gate spacers 46 are formed on the sidewalls of the dummy gate stack 38. Figure 23 The process flow 200 is also shown as process 208. According to some embodiments of the present disclosure, the gate spacer 46 is formed of (one or more) low-k dielectric materials (e.g., porous silicon oxynitride, porous silicon carbonitride, porous silicon nitride, etc.), and can have a single-layer structure or a multi-layer structure including multiple dielectric layers. The dielectric constant (k value) of the gate spacer 46 is lower than 3.8 and can be lower than about 3.0, for example, in the range between about 2.5 and about 3.0.

[0026] An etching process is then performed to etch the portion of the protruding fin 36 that is not covered by the dummy gate stack 38 and the gate spacer 46, resulting in Figure 5 The corresponding process is Figure 23 This is shown as process 210 in the illustrated process flow 200. The recess can be anisotropic so that the portion of fin 36 directly below dummy gate stack 38 and gate spacer 46 is protected from etching. According to some embodiments, the top surface of recessed semiconductor strip 26 can be lower than top surface 24A of STI region 24. Thus, recess 50 is formed. Recess 50 includes portions on opposite sides of dummy gate stack 38 and a portion between the remaining portions of protruding fin 36.

[0027] Next, epitaxial regions (source / drain regions) 54 are formed by selectively growing (by epitaxy) semiconductor material in the recesses 50, resulting in Figure 6 The corresponding process is Figure 23The process flow 200 shown is shown as process 212. Depending on whether the resulting FinFET is a p-type FinFET or an n-type FinFET, p-type or n-type impurities can be in-situ doped by epitaxy. For example, when the resulting FinFET is a p-type FinFET, silicon germanium boron (SiGeB), silicon boron (SiB), etc. can be grown. On the contrary, when the resulting FinFET is an n-type FinFET, silicon phosphorus (SiP), silicon carbon phosphorus (SiCP), etc. can be grown. According to an alternative embodiment of the present disclosure, the epitaxial region 54 includes a III-V compound semiconductor, such as GaAs, InP, GaN, InGaAs, InAlAs, GaSb, AlSb, AlAs, AlP, GaP, a combination of the foregoing, or a multilayer of the foregoing. After the groove 50 is filled with the epitaxial region 54, further epitaxial growth of the epitaxial region 54 causes the epitaxial region 54 to expand horizontally, and a facet can be formed. Further growth of the epitaxial region 54 can also cause adjacent epitaxial regions 54 to merge with each other. Voids (air gaps) 56 may be generated. According to some embodiments of the present disclosure, the formation of the epitaxial regions 54 may be completed while the top surfaces of the epitaxial regions 54 are still wavy, or after the top surfaces of the merged epitaxial regions 54 have become flat (as shown by Figure 6 This is shown to be completed when further growth is achieved on the epitaxial region 54).

[0028] After the epitaxial growth step, the epitaxial region 54 may be further implanted with P-type or N-type impurities to form source and drain regions, which are also denoted by reference numeral 54. According to an alternative embodiment of the present disclosure, when the epitaxial region 54 is in-situ doped with P-type or N-type impurities during epitaxy, the implantation step is omitted.

[0029] Figure 7A FIG. 1 shows a perspective view of the structure after forming a contact etch stop layer (CESL) 58 and an interlayer dielectric (ILD) 60. Figure 23 The process flow 200 is shown as process 214. The CESL 58 can be formed of silicon nitride, silicon oxide, silicon carbonitride, etc., and can be formed using CVD, ALD, etc. The ILD 60 can include a dielectric material formed using, for example, FCVD, spin coating, CVD, or other deposition methods. The ILD 60 can be formed of an oxygen-containing dielectric material, which can be a silicon oxide-based material such as silicon oxide, phosphosilicate glass (PSG), borosilicate glass (BSG), boron-doped phosphosilicate glass (BPSG), etc. A planarization process such as a CMP process or a mechanical grinding process can be performed to make the top surfaces of the ILD 60, the dummy gate stack 38, and the gate spacers 46 flush with each other. Figure 7B According to some embodiments, Figure 7AReferring to cross section 7B- 7B, a dummy gate stack 38 is shown.

[0030] In the formation Figure 7A and Figure 7B After the structure shown, Figure 8A 、 Figure 8B as well as Figures 9-12 As shown, dummy gate stack 38 is replaced with a metal gate and a replacement gate dielectric. In subsequent figures, top surface 24A of STI region 24 is shown to illustrate the location of semiconductor fin 36, which protrudes higher than top surface 24A of STI region 24.

[0031] To form a replacement gate, first remove the Figure 7B The hard mask layer 44, the dummy gate electrode 42 and the dummy gate dielectric 40 are formed as shown. Figure 8A and Figure 8B The opening 59 shown. Figure 23 This is shown as process 216 in the illustrated process flow 200 . The top surface and sidewalls of the protruding fin 36 are exposed to the opening 59 .

[0032] Next, refer to Figure 9 , forming a gate dielectric 61, which extends into the opening 59. The corresponding process is Figure 23 This is shown as process 218 in the illustrated process flow 200. According to some embodiments of the present disclosure, gate dielectric 61 includes an interfacial layer (IL) 62, which is formed on the exposed top and sidewall surfaces of protruding fin 36. IL 62 may include an oxide layer, such as a silicon oxide layer, formed by thermal oxidation, chemical oxidation, or deposition of the surface portion of protruding fin 36. Gate dielectric 61 may also include a high-k dielectric layer 64 located above IL 62. High-k dielectric layer 64 may be formed from a high-k dielectric material (e.g., hafnium oxide, lanthanum oxide, aluminum oxide, zirconium oxide, combinations thereof, multilayers thereof, etc.). The dielectric constant (k value) of the high-k dielectric material is greater than 3.9, may be greater than approximately 7.0, and may sometimes be as high as 21.0 or higher. High-k dielectric layer 64 covers IL 62 and may be in contact with IL 62. High-k dielectric layer 64 is formed as a conformal layer and extends over the sidewalls of protruding fins 36 and the top surfaces and sidewalls of gate spacers 46. According to some embodiments of the present disclosure, high-k dielectric layer 64 is formed using ALD, CVD, or the like.

[0033] According to some embodiments, an adhesion layer (also a diffusion barrier layer) 65 is formed on top of the high-k dielectric layer 64. Figure 23The process flow 200 is shown as process 220. The adhesion layer 65 can be formed of TiN or titanium silicon nitride (TSN). The TiN layer can be formed using ALD or CVD, and the TSN layer can include alternating deposited TiN layers and SiN layers, which are formed using ALD, for example. Because the TiN and SiN layers are very thin, these layers may not be distinguishable from each other and are therefore referred to as TSN layers. According to an alternative embodiment, the adhesion layer 65 is not formed, and the subsequently formed work function layer is in contact with the high-k dielectric layer 64. Therefore, Figure 23 Process 220 in FIG. 1 is shown using a dotted box to indicate that it may be performed or may be skipped. In subsequent figures, the adhesion layer 65 is not shown, although it may or may not be formed.

[0034] refer to Figure 10 and Figure 11 , a work function layer 66 is formed by deposition. The corresponding process is Figure 23 The process flow 200 is shown as process 222. The work function layer 66 includes at least one homogeneous layer (eg, Figure 10 ), or may include multiple sublayers formed of materials different from each other. The material of (one or more) layers in the work function layer 66 may be selected according to whether the corresponding FinFET to be formed is an n-type FinFET or a p-type FinFET. For example, when the FinFET is an n-type FinFET, the work function layer 66 may include an n work function layer, which may be an Al-based layer (for example, formed of TiAl, TiAlN, TiAlC, TaAlN, TaAl, TaAlC, etc. or a multilayer thereof). If the adhesion layer 65 is not formed, a titanium nitride (TiN) layer (not shown) may be formed between the n work function layer and the high-k dielectric layer 64 (and in contact with it) or not to adjust the work function. When the FinFET is a p-type FinFET, the corresponding work function layer 66 may include a p work function layer, such as a TiN layer, a tungsten carbonitride (WCN) layer, etc.

[0035] According to some embodiments, the work function layer 66 may include a sublayer 66A and a sublayer 66B, such as Figure 11 For example, the work function layer 66 of the n-type FinFET may include an n work function layer (denoted as 66A) and a p work function layer (denoted as 66B) located above the n work function layer, wherein the n work function layer dominates the work function of the corresponding FinFET, and the p work function layer is formed at the same time as the p work function layer of the p-type FinFET is formed.

[0036] According to an alternative embodiment, Figure 11As shown, the work function layer of the p-type FinFET may further include a p work function layer (denoted as 66A) and an n work function layer (denoted as 66B) located above the p work function layer, wherein the p work function layer dominates the work function of the corresponding FinFET, and the n work function layer is formed at the same time as the n work function layer of the n-type FinFET. In subsequent example figures, both work function layers 66A and 66B are shown, but according to some embodiments, a single work function layer may be used instead.

[0037] According to some embodiments of the present disclosure, a barrier layer 70 (which is an adhesion layer) is formed on the work function layer 66. Figure 23 This is shown as process 224 in the illustrated process flow 200. According to some embodiments, the barrier layer 70 may be a metal-containing layer, which may be formed of TiN. Other materials, such as TaN, may also be used. According to some embodiments, the barrier layer 70 is formed using ALD, CVD, etc. According to some embodiments, the barrier layer 70 completely fills the remaining opening 59 ( Figure 8B According to an alternative embodiment, a gap-fill process is performed to fill the remaining opening 59 with a fill metal, which may be formed of tungsten, cobalt, or the like.

[0038] After the opening 59 is completely filled, a planarization process such as a chemical mechanical polishing (CMP) process or a mechanical polishing process is performed to remove Figure 11 The excess portion of the deposited layer is removed to form a gate stack 76, as shown. Figure 12 The corresponding process is shown in Figure 23 This is shown as process 226 in the illustrated process flow 200 . The gate stack 76 includes a gate dielectric 61 and a gate electrode 74 .

[0039] Figure 13 and Figure 14 The process for recessing the gate stack 76 is shown in FIG. Figure 23 This is shown as process 228 in the illustrated process flow 200 . Figure 13A first etch-back process 78 is shown performed on the gate stack 76 and gate spacers 46, where etching is indicated by arrows. Recesses 80 are accordingly generated. The first etch-back process may include a dry etching process and / or a wet etching process. Furthermore, the etching may be isotropic or anisotropic. According to some embodiments of the present disclosure, the first etch-back process is performed using an etchant that etches the gate spacers 46 and gate stack 76 without etching the CESLs 58 and 60. According to some embodiments, when a dry etching process is used, the etching gas includes a fluorine-based etchant, such as CF4, C2F6, NF3, or the like, or a combination thereof. According to some embodiments, when a wet etching process is used, the etching chemistry may include a diluted HF solution, NH4OH (ammonia solution), or a combination thereof. According to some embodiments, after the first etch-back process, the height of the gate stack 76 is H1, which may be in a range between approximately 10 nm and approximately 40 nm. The vertical distance from the top surface of the protruding fin 136 (or 236) to the top surface of the ILD 60 is denoted as H2. The ratio of H1 / H2 may be in a range between about 1 / 3 and about 1 / 2. The recess depth D1 may be in a range between about 50 nm and about 80 nm. It should be understood that the value of the recess depth D1 cannot be too high or too low. If the value is too high, some portions of the gate stack 76 (e.g., the portion directly above the protruding fin 36) may be removed, thereby causing device failure. If the value is too low, sufficient recesses will not be generated in subsequent processes to accommodate the self-aligned hard mask.

[0040] According to Figure 13 In some embodiments shown, the gate spacers 46 are recessed by the first etch-back process 78. According to alternative embodiments, the gate spacers 46 are not recessed by the first etch-back process 78, where dashed lines 46' are shown to illustrate the top portions of the gate spacers 46 that remain after the first etch-back process.

[0041] In such Figure 13 After the first etch-back process shown, a second etch-back process 78' may be performed, as shown in FIG. Figure 14As shown. Consequently, a recess 81 is formed between opposing portions of the corresponding high-k dielectric layer 64. A second etch-back process 78' is performed using an etching gas or etching chemical solution different from that used in the first etch-back process 78. The second etch-back process 78' may include a dry etching process and / or a wet etching process. Furthermore, the etching may be isotropic or anisotropic. According to some embodiments of the present disclosure, the second etch-back process is performed using an etchant that etches the gate electrode 74 without etching the gate spacers 46, the high-k dielectric layer 64, the CESL 58, and the ILD 60. According to some embodiments, when a dry etching process is used, the etching gas may include BCl3, Cl2, WF6, or a combination thereof. According to some embodiments in which a wet etching process is used, the etching chemical may include NH4OH, etc. According to some embodiments, the recess depth D2 may be within a range between approximately 4 nm and approximately 8 nm. It should be understood that the value of the recess depth D2 should not be too high or too low. If the value is too high, portions of the gate electrode 74 may be removed, thereby causing device failure. If the value is too low, then not enough recesses are generated to accommodate the subsequently filled low-resistivity conductive layer. According to some embodiments, after the second etch-back process 78 ′, the height H3 of the gate stack 76 is in a range between about 5 nm and about 30 nm.

[0042] Since the etchant has selectivity to different materials, the top surface 46TS of the gate spacer 46 may be flush with, higher than, or lower than the top surface 64TS of the high-k dielectric layer 64 .

[0043] Figure 15 FIG. 8 shows a passivation process 82 performed according to some embodiments. Figure 23 This is shown as process 230 in the illustrated process flow 200. According to some embodiments, when dry etching is used in etching processes 78 and 78', material of gate electrode 74 may be re-sputtered onto high-k dielectric layer 64, gate spacer 46, CESL 58, and ILD 60. This may cause some problems. For example, the re-sputtered material may become a seed layer for the subsequently selectively deposited low-resistivity layers 84A and 84B. Figure 18 ), causing low resistivity layers 84A and 84B to grow in undesirable locations. In addition, these materials may cause electrical shorts ( Figure 20A ). Therefore, the passivation process is performed to improve the selectivity in the subsequent deposition process and convert the re-sputtered material (if any) into dielectric material. According to other embodiments, when the intensity of the re-sputtering is not enough to affect the selectivity of the deposition, the passivation process 82 is skipped. Figure 23The passivation process 230 is shown in FIG. 2 using a dashed box.

[0044] According to some embodiments, the passivation process 82 is performed by annealing the wafer 10 in an environment containing oxygen (O2) or performing a plasma treatment on the wafer 10 using O2 as a process gas. According to some embodiments, the oxygen annealing is performed at a temperature in a range between about 200°C and about 350°C for a period of time, for example, in a range between about 10 seconds and about 60 seconds. As a result, the gate electrode 74 and the surface layer of the re-sputtered material will be oxidized to form an oxide. According to an alternative embodiment, the passivation process 82 is performed by treating the wafer 10 in an environment containing nitrogen (N2) and hydrogen (H2). As a result, the gate electrode 74 and the surface layer of the re-sputtered material will be converted to a nitride. It should be understood that the gate electrode 74 may already include a metal nitride, and nitridation will still improve selectivity because the damaged sidewalls of the SiN are passivated and the metal residues are also passivated, thereby improving selectivity. According to yet another alternative embodiment, the passivation process 82 is performed by hot-dip ing the wafer 10 in an environment containing NF3 or performing a plasma treatment using NF3 as a process gas on the wafer 10. According to some embodiments, the hot-dip is performed at a temperature in a range between about 250° C. and about 400° C. for a period of time, for example, in a range between about 1 minute and about 10 minutes.

[0045] refer to Figure 16 , a selective deposition process is used to form a first low resistivity conductive layer 84A which may be a metal layer. Hereinafter, the low resistivity conductive layer 84A is also referred to as the bottom sub-(metal) layer 84A. The corresponding process is Figure 23 The process flow 200 is shown as process 232. Throughout the specification, the bottom sublayer 84A may also be considered to be part of the corresponding gate electrode. According to some embodiments of the present disclosure, the bottom sublayer 84A is formed of tungsten (W). The resistivity of the bottom sublayer 84A may be lower than the resistivity of the layers in the gate electrode 74 (which include layers 66 and 70). The bottom sublayer 84A is formed on the gate electrode 74, rather than on the exposed surfaces of the dielectric material (including the gate spacer 46, the high-k dielectric layer 64, the CESL 58, and the ILD 60). According to some embodiments, the deposition is performed using ALD. The precursor may include WCl5 and a reducing agent, such as H2. The deposition process includes multiple ALD cycles, each ALD cycle including applying WCl5, purging WCl5, introducing H2, and purging H2. The deposition process may be performed at a high temperature (e.g., in a range between about 400°C and about 500°C).

[0046] It should be understood that WCl5 has the function of etching metal oxides. Therefore, if oxygen is used to perform the first passivation process 82, the resulting metal oxide formed by oxidation of the gate electrode 74 and the surface layer of the re-sputtered material of the gate electrode 74 is etched before the bottom sub-layer 84A is grown.

[0047] refer to Figure 17 After depositing the bottom sub-layer 84A, a passivation process 86 is performed. Figure 23 This is shown as process 234 in the illustrated process flow 200. According to an alternative embodiment, the passivation process 86 is skipped. Thus, Figure 23 Step 234 in FIG. 8 is shown using a dashed box to indicate that it can be performed or skipped. The passivation process 86 can be performed using a method and a process gas selected from the same candidate group of methods and process gases used for the passivation process 82 ( Figure 15 ). Therefore, the details thereof will not be repeated here. In addition, the passivation process 86 can be performed using the same method and process gas or different methods and process gases.

[0048] refer to Figure 18 After forming the bottom sub-layer 84A and a possible passivation process 86, a metal layer 84B (hereinafter referred to as the top sub-(metal) layer 84B) is selectively deposited on the bottom sub-layer 84A. Figure 23 This is shown as process 236 in the illustrated process flow 200. The resistivity of the bottom sublayer 84A is also lower than the resistivity of the layers in the gate electrode 74 (including layers 66 and 70). The bottom sublayer 84A is used as a seed layer to form the top sublayer 84B and is therefore not deposited on exposed surfaces of the dielectric material (e.g., gate spacer 46, high-k dielectric layer 64, CESL 58, and ILD 60). According to some embodiments, the deposition of the top sublayer 84B is performed using ALD. The precursor is different from the precursor used to deposit the bottom sublayer 84A. For example, the precursor used to form the top sublayer 84B may include WF6 and a reducing agent, such as H2. The process may include multiple ALD cycles, each ALD cycle including applying WF6, purging the WF6, introducing H2, and purging the H2. The deposition process may be a thermal process performed at a high temperature (e.g., in a range between about 250° C. and about 400° C.).

[0049] Sublayers 84A and 84B have different functions. The bottom sublayer 84A (which can be formed using WCl5) can be selectively grown on the gate electrode 74 (e.g., TiN) without being deposited on the exposed dielectric layer. However, the bottom sublayer 84A cannot be deposited too thick because, as the bottom sublayer 84A is continuously deposited, the bottom sublayer 84A will eventually be deposited on the exposed dielectric layer. Therefore, the deposition of the bottom sublayer 84A is stopped before deposition on the exposed dielectric layer begins. According to some embodiments, the thickness of the bottom sublayer 84A is less than about 3 nm to ensure that it is not deposited on the exposed dielectric layer. On the other hand, the bottom sublayer 84A serves as a seed layer for selectively growing the top sublayer 84B, which is not grown on the gate electrode 74. Therefore, the bottom sublayer 84A has a sufficiently high thickness to ensure that it completely covers the exposed gate electrode 74, and therefore the thickness of the bottom sublayer 84A is greater than about 1 nm. Therefore, the thickness T1 of the bottom sub-layer 84A may be in a range between about 1 nm and about 3 nm.

[0050] The top sublayer 84B (which can be formed using WF6) is deposited on a metal such as the bottom sublayer 84A, and will not be deposited on the exposed dielectric layer even if the deposition of the top sublayer 84B continues for a long time. Therefore, by forming the bottom sublayer 84A as a seed layer, the top sublayer 84B is selectively deposited on the bottom sublayer 84A. When the thickness T2 of the top sublayer 84B is high, it still will not grow on the exposed dielectric layer. Therefore, the thickness T2 of the top sublayer 84B can be increased without worrying about growth on the exposed dielectric layer. The thickness T2 of the top sublayer 84B can be greater than approximately 1 nm, and can be greater than approximately 3 nm, greater than approximately 5 nm, or greater. According to some embodiments, the thickness T2 is in a range between approximately 1 nm and approximately 5 nm. The top surface of the top sublayer 84B can be flush with or slightly lower than the top of the high-k dielectric layer 64. The bottom sublayers 84A and 84B are collectively referred to as the low-resistivity conductive layer 84. Throughout the specification, low-resistivity conductive layer 84 is considered to be part of the gate electrode denoted by 74 ′. The combination of low-resistivity conductive layers 84A and 84B can achieve a sufficiently high thickness and thus can reduce the overall resistivity of gate electrode 74 (which includes low-resistivity conductive layer 84 ).

[0051] Due to the selective deposition, sublayers 84A and 84B can be conformal layers. Furthermore, if the top surface of the underlying portion of gate electrode 74' is planar, sublayers 84A and 84B can be substantially planar. Alternatively, sublayers 84A and 84B can be curved and have a topology that follows the contour of the top surface of the corresponding underlying portion of gate electrode 74'.

[0052] Next, refer to Figure 19, the remaining recesses 80 and 81 (if any) are filled with dielectric material to form a self-aligned hard mask 88. Figure 23 This is shown as process 238 in the illustrated process flow 200. The self-aligned hard mask 88 can be formed from a non-low-k dielectric material (e.g., silicon nitride, silicon oxynitride, silicon oxycarbide, etc.). The self-aligned hard mask 88 can also be formed from a homogeneous low-k dielectric material, which can be formed from porous silicon nitride, porous silicon oxynitride, porous silicon oxycarbide, etc. The self-aligned hard mask 88 is also planarized so that its top surface is coplanar with the top surface of the ILD 60. According to some embodiments, the sidewalls of the self-aligned hard mask 88 contact the sidewalls of the CESL 58. According to other embodiments in which the gate spacers 46 are not recessed, the sidewalls of the self-aligned hard mask 88 contact the sidewalls of the top portion of the gate spacers 46 (shown by dashed line 46').

[0053] Figure 20A The formation of gate contact plug 90, source / drain silicide region 92 and source / drain contact plug 94 is shown. Figure 23 This is shown as process 240 in the illustrated process flow 200. The formation of source / drain contact plugs 94 includes forming contact openings by etching ILD 60 to expose the underlying portion of CESL 58, and then etching the exposed portion of CESL 58 to expose source / drain regions 54. In a subsequent process, a metal layer (e.g., a titanium layer) is deposited to extend into the contact openings. A metal nitride barrier layer (e.g., a TiN layer) may be formed. An annealing process is then performed to react the metal layer with the top portion of the source / drain regions 54 to form silicide regions 92. Next, the previously formed metal nitride layer is either retained without being removed, or removed, and then a new metal nitride layer (e.g., a titanium nitride layer) is deposited. A fill metal material such as tungsten, cobalt, etc. is then filled into the contact openings, followed by a planarization process to remove excess material, thereby producing source / drain contact plugs 94. The formation of gate contact plug 90 may include etching self-aligned hard mask 88 to expose top sublayer 84B and forming gate contact plug 90 in the corresponding opening. Gate contact plug 90 may also include a diffusion barrier layer (e.g., titanium nitride) and a metal (e.g., copper, tungsten, cobalt, etc.) located above the diffusion barrier layer. FinFET 100 is thus formed. Figure 20B A perspective view of FinFET 100 is shown.

[0054] exist Figure 20AIn the embodiment, the thickness ratio T2 / T1 is designed to be within a range that is neither too large nor too small. When the ratio T2 / T1 is too large, the thickness T1 is too small, and / or the thickness T2 is too large. If the thickness T1 is too small, the bottom sublayer 84A may not completely cover the gate electrode 66 and may not serve as an effective seed layer. If the thickness T2 is too large, the top surface of the top sublayer 84B may be higher than the top of the high-k dielectric layer 64, causing problems in the subsequent formation of the self-aligned hard mask 88. On the other hand, when the ratio T2 / T1 is too small, the thickness T1 is too large, and / or the thickness T2 is too small. If the thickness T1 is too large, the bottom sublayer 84A may grow on a dielectric material such as the ILD 60, and the deposition of the bottom sublayer 84A and the top sublayer 84B is not selective. If the thickness T2 is too small, the resistance of the layer 84B (and therefore the total resistance of the layers 84A and 84B) is high, thereby defeating the purpose of forming the low-resistivity conductive layers 84A and 84B. According to some embodiments, the ratio T2 / T1 is in a range between 1 and about 5.

[0055] According to some embodiments, to ensure that top sublayer 84B does not grow on top of high-k dielectric layer 64 and gate spacer 46, the top surface of top sublayer 84B may be flush with the top end of high-k dielectric layer 64 and / or the top end of gate spacer 46. According to alternative embodiments, the top surface of top sublayer 84B is lower than the top end of high-k dielectric layer 64 and / or the top end of gate spacer 46 by a difference to provide process margin. The difference may be less than about 1 nm.

[0056] like Figure 20A As shown, the bottom surface of gate contact plug 90 may extend from the left edge shown to the right edge shown of top sublayer 84B. Alternatively, as shown Figure 20A As shown, the bottom surface of the gate contact plug 90 may be laterally recessed from the left edge and / or right edge of the top sublayer 84B. According to yet another alternative embodiment, the bottom surface of the gate contact plug 90 may extend over and contact the top end of the high-k dielectric layer and may or may not extend over and contact the top end of the gate spacer 46.

[0057] Figure 21 A top view of portions of FinFET 100 is shown. A gate electrode 74' and overlying low-resistivity conductive layers 84A and 84B are shown. Vertical portions of high-k dielectric layer 64 may form a ring around the respective gate electrode 74' (including the respective overlying low-resistivity conductive layer 84). Also shown are gate contact plug 90, protruding fin 36, and source / drain regions 54.

[0058] like Figure 21As shown, low-resistivity conductive layers 84A and 84B can completely cover work function layer 66, and the edges of conductive layers 84A and 84B can be flush with the corresponding edges of work function layer 66. High-k gate dielectric 64 can form a ring that contacts the sidewalls of low-resistivity conductive layers 84A and 84B and work function layer 66. Hard mask 88 can be completely surrounded by the vertical portion of CESL 58. Gate contact plug 90 can contact part, but not all, of top sublayer 84B, with low-resistivity conductive layers 84A and 84B extending beyond left and right sidewalls 90C and 90D of gate contact plug 90. It should be understood that although sidewalls 90A and 90B of gate contact plug 90 are shown as being directly on top sublayer 84B, sidewalls 90A and 90B can extend in the direction of arrow 95 and can be located anywhere along the path of arrow 95.

[0059] Figure 22 Schematic distribution of some elements is shown, wherein the atomic percentages of the elements F, Cl and N are shown as a function of the height in the gate electrode 74, wherein the height is Figure 20A Measured in the direction of arrow 108 in FIG. Lines 102, 104, and 106 illustrate example atomic percentages of chlorine, fluorine, and nitrogen, respectively. As shown by line 102, when WCl5 is used as a process gas to form bottom sub-layer 84A, the peak atomic percentage of Cl is in bottom sub-layer 84A, and the Cl atomic percentage gradually decreases in top sub-layer 84B (and dielectric hard mask 88) and work function layer 66. As shown by line 104, since WF6 can be used as a process gas to form top sub-layer 84B, the peak atomic percentage of F is in top sub-layer 84B, and the F atomic percentage gradually decreases in bottom sub-layer 84A, dielectric hard mask 88, and gate contact plug 90. The distributions of lines 102 and 104 can be observed using X-ray photoelectron spectroscopy (XPS). According to some embodiments, the peak atomic percentage of F in top sub-layer 84B is greater than approximately 12% and can be in a range between approximately 5% and approximately 20%. The peak atomic percentage of Cl in the bottom sub-layer 84A is higher than about 10% and may be in a range between about 5% and about 20%.

[0060] Line 106 shows an embodiment in which a passivation process 86 is performed using N2 after depositing layer 84A and before depositing layer 84B. According to some embodiments, the peak nitrogen atomic percentage is at the interface between layers 84A and 84B, and the nitrogen atomic percentage decreases in both sub-layers 84A and 84B. The distribution of line 106 can be observed using energy dispersive X-ray spectroscopy (EDS or EDX). Moreover, the two layers 84A and 84B can be distinguished from each other using EDX. Experiments also revealed that sub-layers 84A and 84B can be distinguished from each other using transmission electron microscopy (TEM) due to their differences in crystallinity.

[0061] Embodiments of the present disclosure have several advantageous features. By forming a first low-resistivity conductive layer, selective deposition of the first low-resistivity conductive layer on the gate electrode, rather than on the exposed dielectric layer, can be achieved. By stopping deposition of the first low-resistivity conductive layer and depositing a second low-resistivity conductive layer that is selectively deposited on the metal, the loss of selectivity caused by the extended placement of the low-resistivity conductive layer is addressed. As the thickness of the second low-resistivity conductive layer increases, there is no loss in deposition selectivity.

[0062] According to some embodiments of the present disclosure, a method includes: forming a gate electrode on a semiconductor region; recessing the gate electrode to generate a recess; performing a first deposition process to form a first metal layer on the gate electrode and in the recess, wherein the first deposition process is performed using a first precursor; performing a second deposition process using a second precursor different from the first precursor to form a second metal layer on the first metal layer, wherein the first metal layer and the second metal layer include the same metal; forming a dielectric hard mask over the second metal layer; and forming a gate contact plug through the dielectric hard mask, wherein the gate contact plug contacts a top surface of the second metal layer. In an embodiment, the first precursor includes tungsten chloride (WCl5) and the second precursor includes tungsten fluoride (WF6). In an embodiment, during the first deposition process, a surface of a dielectric material adjacent to the gate electrode is exposed, and the first deposition process stops before the first metal layer begins to grow on the exposed dielectric material adjacent to the gate electrode. In an embodiment, each of the first deposition process and the second deposition process includes an atomic layer deposition process. In one embodiment, recessing the gate electrode includes a first recessing process for recessing the gate electrode, the gate dielectric, and the gate spacers, wherein the gate dielectric includes a first sidewall portion located on the sidewall of the gate electrode, and the gate electrode and the gate dielectric are located between the gate spacers; and a second recessing process for recessing the gate electrode to be lower than a top edge of the gate dielectric. In one embodiment, the first metal layer has a first thickness of less than approximately 3 nm. In one embodiment, the second metal layer has a second thickness of greater than approximately 3 nm.

[0063] According to some embodiments of the present disclosure, a device includes: a semiconductor region; a gate dielectric located above the semiconductor region; a gate electrode including a first portion including a work function layer located in the first portion; and a second portion overlying and contacting the first portion, wherein the second portion includes fluorine and chlorine, and wherein the second portion includes a bottom sublayer, wherein a first peak atomic percentage of chlorine is in the bottom sublayer; and a top sublayer located above and in contact with the bottom sublayer, wherein a second peak atomic percentage of fluorine is in the top sublayer, and wherein the bottom sublayer and the top sublayer include the same metal; and a gate contact plug located above and in contact with the top sublayer. In an embodiment, the first portion includes titanium and the second portion includes tungsten. In an embodiment, the bottom sublayer and the top sublayer are distinguishable by transmission electron microscopy (TEM). In an embodiment, the gate dielectric includes a sidewall portion and a bottom portion located below and connected to the sidewall portion, and wherein the first and second portions of the gate electrode are located between the sidewall portions. In one embodiment, a top surface of the top sublayer is flush with or lower than a top edge of a sidewall portion of the gate dielectric. In one embodiment, the device further comprises a gate spacer located on opposite sides of the gate dielectric and the gate electrode; and an interlayer dielectric, wherein the gate spacer is located in the interlayer dielectric, wherein a first top surface of the gate dielectric is recessed below a second top surface of the interlayer dielectric. In one embodiment, the gate spacer is recessed to have a third top surface that is lower than the second top surface.

[0064] According to some embodiments of the present disclosure, a device includes: a semiconductor substrate; an isolation region extending into the semiconductor substrate; a semiconductor fin protruding above a portion of the isolation region located on an opposite side of the semiconductor fin; and a gate stack including a high-k gate dielectric located on the semiconductor fin; a work function layer located on the high-k gate dielectric; a barrier layer; a first tungsten layer located above and in contact with the work function layer and the barrier layer; and a second tungsten layer located above and in contact with the first tungsten layer, wherein the first tungsten layer and the second tungsten layer are distinguishable from each other. In an embodiment, both the first tungsten layer and the second tungsten layer contain fluorine and chlorine, and wherein a first peak atomic percentage of chlorine is in the first tungsten layer. In an embodiment, a second peak atomic percentage of fluorine is in the second tungsten layer. In an embodiment, both the first tungsten layer and the second tungsten layer include nitrogen, and wherein the atomic percentage of nitrogen in the gate stack has a peak at an interface between the first tungsten layer and the second tungsten layer. In an embodiment, the high-k gate dielectric includes sidewall portions located on opposite sides of the first tungsten layer and the second tungsten layer, and a top surface of the second tungsten layer is located between top edges of the sidewall portions of the high-k gate dielectric and is flush with or lower than the top edges of the sidewall portions of the high-k gate dielectric. In an embodiment, the barrier layer includes titanium nitride.

[0065] The features of several embodiments are summarized above so that those skilled in the art can better understand the various aspects of the present disclosure. Those skilled in the art will appreciate that they can easily use this disclosure as a basis to design or modify other processes and structures for achieving the same purpose and / or achieving the same advantages as the embodiments described herein. Those skilled in the art will also appreciate that such equivalent constructions do not depart from the spirit and scope of the present disclosure, and that they can make various changes, substitutions, and modifications herein without departing from the spirit and scope of the present disclosure.

[0066] Example 1 is a method for forming a semiconductor device, comprising: forming a gate electrode over a semiconductor region; recessing the gate electrode to generate a groove; performing a first deposition process to form a first metal layer over the gate electrode and in the groove, wherein the first deposition process is performed using a first precursor; performing a second deposition process using a second precursor different from the first precursor to form a second metal layer on the first metal layer, wherein the first metal layer and the second metal layer contain the same metal; forming a dielectric hard mask over the second metal layer; and forming a gate contact plug through the dielectric hard mask, wherein the gate contact plug contacts the top surface of the second metal layer.

[0067] Example 2 is the method of Example 1, wherein the first precursor includes tungsten chloride (WCl5) and the second precursor includes tungsten fluoride (WF6).

[0068] Example 3 is the method described in Example 1, wherein, in the first deposition process, the surface of the dielectric material adjacent to the gate electrode is exposed, and the first deposition process stops before the first metal layer begins to grow on the exposed dielectric material adjacent to the gate electrode.

[0069] Example 4 is the method of Example 1, wherein each of the first deposition process and the second deposition process includes an atomic layer deposition process.

[0070] Example 5 is the method described in Example 1, wherein recessing the gate electrode includes: a first recessing process for recessing the gate electrode, gate dielectric and gate spacer, wherein the gate dielectric includes a first sidewall portion located on the sidewall of the gate electrode, and the gate electrode and the gate dielectric are located between the gate spacers; and a second recessing process for recessing the gate electrode to be lower than the top edge of the gate dielectric.

[0071] Example 6 is the method of Example 1, wherein the first metal layer has a first thickness of less than about 3 nm.

[0072] Example 7 is the method of Example 6, wherein the second metal layer has a second thickness greater than about 3 nm.

[0073] Example 8 is a semiconductor device comprising: a semiconductor region; a gate dielectric located above the semiconductor region; a gate electrode comprising: a first portion comprising a work function layer located in the first portion; and a second portion overlying and in contact with the first portion, wherein the second portion comprises fluorine and chlorine, and wherein the second portion comprises: a bottom sublayer, wherein a first peak atomic percentage of chlorine is in the bottom sublayer; and a top sublayer located above and in contact with the bottom sublayer, wherein a second peak atomic percentage of fluorine is in the top sublayer, and wherein the bottom sublayer and the top sublayer comprise the same metal; and a gate contact plug located above and in contact with the top sublayer.

[0074] Example 9 is the device of Example 8, wherein the first portion comprises titanium and the second portion comprises tungsten.

[0075] Example 10 is the device of Example 8, wherein the bottom sublayer and the top sublayer are distinguishable by transmission electron microscopy (TEM).

[0076] Example 11 is the device of Example 8, wherein the gate dielectric includes a sidewall portion and a bottom portion located below and connected to the sidewall portion, and wherein the first and second portions of the gate electrode are located between the sidewall portions.

[0077] Example 12 is the device of Example 11, wherein a top surface of the top sublayer is flush with or lower than a top edge of a sidewall portion of the gate dielectric.

[0078] Example 13 is the device of Example 8, further comprising: a gate spacer located on opposite sides of the gate dielectric and the gate electrode; and an interlayer dielectric, wherein the gate spacer is located in the interlayer dielectric, wherein the first top surface of the gate dielectric is recessed below the second top surface of the interlayer dielectric.

[0079] Example 14 is the device of Example 13, wherein the gate spacer is recessed to have a third top surface lower than the second top surface.

[0080] Example 15 is a semiconductor device comprising: a semiconductor substrate; an isolation region extending into the semiconductor substrate; a semiconductor fin protruding higher than a portion of the isolation region located on an opposite side of the semiconductor fin; and a gate stack comprising: a high-k gate dielectric located on the semiconductor fin; a work function layer located on the high-k gate dielectric; a barrier layer; a first tungsten layer located above and in contact with the work function layer and the barrier layer; and a second tungsten layer located above and in contact with the first tungsten layer, wherein the first tungsten layer and the second tungsten layer are distinguishable from each other.

[0081] Example 16 is the device of Example 15, wherein the first tungsten layer and the second tungsten layer both contain fluorine and chlorine, and wherein a first peak atomic percentage of chlorine is in the first tungsten layer.

[0082] Example 17 is the device of Example 16, wherein the second peak atomic percentage of fluorine is in the second tungsten layer.

[0083] Example 18 is the device of Example 15, wherein both the first tungsten layer and the second tungsten layer include nitrogen, and wherein the atomic percentage of nitrogen in the gate stack has a peak at an interface between the first tungsten layer and the second tungsten layer.

[0084] Example 19 is a device described in Example 15, wherein the high-k gate dielectric includes sidewall portions located on opposite sides of the first tungsten layer and the second tungsten layer, and the top surface of the second tungsten layer is located between the top edges of the sidewall portions of the high-k gate dielectric, and the top surface of the second tungsten layer is flush with or lower than the top edge of the sidewall portions of the high-k gate dielectric.

[0085] Example 20 is the device of Example 15, wherein the barrier layer comprises titanium nitride.

Claims

1. A method for forming a semiconductor device, comprising: forming a gate electrode over the semiconductor region; recessing the gate electrode to form a groove; performing a first deposition process to form a first metal layer on the gate electrode and in the groove, wherein the first deposition process is performed using a first precursor; performing a second deposition process using a second precursor different from the first precursor to form a second metal layer on the first metal layer, wherein both the first metal layer and the second metal layer contain fluorine and chlorine, a first peak atomic percentage of chlorine is in the first metal layer, and a second peak atomic percentage of fluorine is in the second metal layer; forming a dielectric hard mask over the second metal layer; and forming a gate contact plug through the dielectric hard mask, wherein the gate contact plug contacts a top surface of the second metal layer, The step of making the gate electrode recessed comprises: a first recessing process for recessing the gate electrode, the gate dielectric, and the gate spacers, wherein the gate dielectric includes a first sidewall portion located on a sidewall of the gate electrode, and the gate electrode and the gate dielectric are located between the gate spacers; and A second recessing process is used to recess the gate electrode to be lower than a top edge of the gate dielectric.

2. The method according to claim 1, wherein The first precursor includes tungsten chloride WCl 5 , and the second precursor includes tungsten fluoride WF 6 .

3. The method according to claim 1, wherein During the first deposition process, a surface of the dielectric material adjacent to the gate electrode is exposed, and the first deposition process is stopped before the first metal layer begins to grow on the exposed dielectric material adjacent to the gate electrode.

4. The method according to claim 1, wherein Each of the first deposition process and the second deposition process includes an atomic layer deposition process.

5. The method according to claim 1, wherein The first metal layer has a first thickness less than 3 nm.

6. The method according to claim 5, wherein: The second metal layer has a second thickness greater than 3 nm.

7. A semiconductor device comprising: semiconductor region; a gate dielectric located above the semiconductor region; A gate electrode comprising: a first portion, comprising a work function layer located in the first portion; and a second portion overlying and in contact with the first portion, wherein the second portion comprises fluorine and chlorine, and wherein the second portion comprises: a bottom sublayer, wherein a first peak atomic percentage of chlorine is in the bottom sublayer; and a top sublayer overlying and contacting the bottom sublayer, wherein a second peak atomic percentage of fluorine is in the top sublayer, and wherein both the bottom sublayer and the top sublayer comprise fluorine and chlorine; and A gate contact plug is located above the top sub-layer and contacts the top sub-layer.

8. The device according to claim 7, wherein The first portion includes titanium, and the second portion includes tungsten.

9. The device according to claim 7, wherein The bottom sublayer and the top sublayer can be distinguished by transmission electron microscopy TEM.

10. The device according to claim 7, wherein The gate dielectric includes a sidewall portion and a bottom portion below and connected to the sidewall portion, and wherein the first and second portions of the gate electrode are located between the sidewall portions.

11. The device according to claim 10, wherein A top surface of the top sublayer is flush with or lower than a top edge of a sidewall portion of the gate dielectric.

12. The device according to claim 7, further comprising: gate spacers on opposite sides of the gate dielectric and the gate electrode; as well as An interlayer dielectric, wherein the gate spacer is located in the interlayer dielectric, wherein a first top surface of the gate dielectric is recessed below a second top surface of the interlayer dielectric.

13. The device according to claim 12, wherein The gate spacer is recessed to have a third top surface lower than the second top surface.

14. A semiconductor device comprising: semiconductor substrates; an isolation region extending into the semiconductor substrate; a semiconductor fin protruding higher than portions of the isolation region located on opposite sides of the semiconductor fin; as well as Gate stack, including: a high-k gate dielectric located on the semiconductor fin; a work function layer located on the high-k gate dielectric; barrier layer; a first tungsten layer overlying and contacting the work function layer and the barrier layer; and A second tungsten layer is located above and in contact with the first tungsten layer, wherein the first tungsten layer and the second tungsten layer are distinguishable from each other, wherein both the first tungsten layer and the second tungsten layer contain fluorine and chlorine, and wherein a first peak atomic percentage of chlorine is in the first tungsten layer and a second peak atomic percentage of fluorine is in the second tungsten layer.

15. The device according to claim 14, wherein The first tungsten layer and the second tungsten layer both include nitrogen, and wherein an atomic percentage of nitrogen in the gate stack has a peak at an interface between the first tungsten layer and the second tungsten layer.

16. The device according to claim 14, wherein The high-k gate dielectric includes sidewall portions located on opposite sides of the first tungsten layer and the second tungsten layer, and a top surface of the second tungsten layer is located between top edges of the sidewall portions of the high-k gate dielectric, and a top surface of the second tungsten layer is flush with or lower than the top edges of the sidewall portions of the high-k gate dielectric.

17. The device according to claim 14, wherein The barrier layer includes titanium nitride.

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