Semiconductor device and method

Abstract

The present application discloses a semiconductor device and a method thereof. A semiconductor device and a method for forming the same are disclosed, the semiconductor device including a source / drain contact extending into a source / drain region below a topmost surface of the source / drain region. In one embodiment, a semiconductor device includes: a semiconductor substrate; a first channel region above the semiconductor substrate; a first gate stack above the semiconductor substrate and surrounding four sides of the first channel region; a first epitaxial source / drain region adjacent to the first gate stack and the first channel region; and a first source / drain contact coupled to the first epitaxial source / drain region, the bottommost surface of the first source / drain contact extending below a topmost surface of the first channel region.

Description

Technical Field

[0001] The present disclosure relates generally to semiconductor devices and methods. Background Art

[0002] Semiconductor devices are used in a variety of electronic applications, such as personal computers, cell phones, digital cameras, and other electronic devices. Semiconductor devices are typically manufactured by sequentially depositing insulating or dielectric layers, conductive layers, and semiconductor material layers over a semiconductor substrate, and patterning the various material layers using photolithography to form circuit components and elements thereon.

[0003] The semiconductor industry continues to improve the integration density of various electronic components (e.g., transistors, diodes, resistors, capacitors, etc.) by continuously reducing the minimum feature size, which allows more components to be integrated into a given area. However, as the minimum feature size decreases, other problems arise that should be addressed. Summary of the invention

[0004] According to one aspect of the present disclosure, a semiconductor device is provided, comprising: a semiconductor substrate; a first channel region above the semiconductor substrate; a first gate stack above the semiconductor substrate and surrounding four sides of the first channel region; a first epitaxial source / drain region adjacent to the first gate stack and the first channel region; and a first source / drain contact coupled to the first epitaxial source / drain region, the bottommost surface of the first source / drain contact extending below the topmost surface of the first channel region.

[0005] According to another aspect of the present disclosure, a method for forming a semiconductor device is provided, comprising: forming a gate stack on a semiconductor substrate; epitaxially growing a first source / drain region in the semiconductor substrate adjacent to the gate stack, wherein the epitaxial growth of the first source / drain region comprises: epitaxially growing a first semiconductor material; epitaxially growing a second semiconductor material on the first semiconductor material; and epitaxially growing a third semiconductor material on the second semiconductor material, wherein the atomic concentration of the dopant in the first semiconductor material is between the atomic concentration of the dopant in the third semiconductor material and the atomic concentration of the dopant in the second semiconductor material. ; etching the first source / drain region to form a first recess in the first source / drain region, wherein the first recess extends through the third semiconductor material and partially through the second semiconductor material, and a bottommost surface of the first recess is disposed above a bottommost surface of the second semiconductor material, wherein etching the first source / drain region comprises iteratively etching the first source / drain region using a first etching process and a second etching process having an etchant different from that of the first etching process; and forming a first source / drain contact in the first recess, the first source / drain contact being coupled to the first source / drain region.

[0006] According to another aspect of the present disclosure, a semiconductor device is provided, comprising: a fin on a semiconductor substrate; a gate stack on the fin; an epitaxial source / drain region on the fin adjacent to the gate stack; and a source / drain contact coupled to the epitaxial source / drain region, wherein a bottommost surface of the source / drain contact extends to a first distance below a top surface of the fin, wherein a ratio of the first distance to a height of the epitaxial source / drain region is 1:3 to 1:2. BRIEF DESCRIPTION OF THE DRAWINGS

[0007] Various aspects of the present disclosure may be best understood from the following detailed description when read in conjunction with the accompanying drawings. It should be noted that, in accordance with standard industry practice, various features are not drawn to scale. In fact, the size of various features may be arbitrarily increased or decreased for clarity of discussion.

[0008] Figure 1 An example of a semiconductor device including a nanostructure field effect transistor (NSFET) in a three-dimensional view is shown in accordance with some embodiments.

[0009] Figure 2 , Figure 3 , Figure 4 , Figure 5 , Fig. 6A , Figure 6B , Fig. 7A, Figure 7B , Fig. 8A , Figure 8B , Fig. 9A , Fig. 9B , Fig. 10A , Fig. 10B , Fig.11A , Fig. 11B , Fig. 11C , Fig. 12A , Fig. 12B , Fig. 12C , Fig.12D , Fig.13A , Fig. 13B , Fig. 13C , Fig.14A , Fig. 14B , Fig.15A , Fig. 15B , Fig.16A , Fig. 16B , Fig.17A , Fig. 17B , Fig.18A , Fig.18B , Fig. 18C , Fig.19A , Fig.19B , Fig. 20A , Fig. 20B , Fig.21A , Fig.21B , Fig. 21C , Fig.21D , Fig.21E , Fig.22A , Fig. 22B , Fig. 22C , Fig.22D , Fig.22E , Fig.22F , Fig.23A and Fig. 23B is a cross-sectional view of an intermediate stage in the fabrication of a semiconductor device according to some embodiments.

[0010] Fig.24 An example of a semiconductor device including a fin field effect transistor (FinFET) in a three-dimensional view is shown in accordance with some embodiments.

[0011] Fig.25 , Fig.26 , Fig. 27 , Fig.28 , Fig.29A , Fig.29B , Fig. 30A , Fig. 30B , Fig.31A , Fig.31B , Fig.32A , Fig.32B , Fig.33A , Fig.33B , Fig.33C , Fig.34A , Fig.34B, Fig.34C , Fig.35A , Fig.35B , Fig.36A , Fig.36B , Fig.37A , Fig.37B , Fig.38A , Fig.38B , Fig.38C , Fig.39A , Fig.39B , Fig.39C , Fig.40A , Fig.40B , Fig.40C , Fig.41A and Fig.41B is a cross-sectional view of an intermediate stage in the fabrication of a semiconductor device according to some embodiments. DETAILED DESCRIPTION

[0012] The following disclosure provides many different embodiments or examples for realizing different features of the present invention. Specific examples of components and arrangements are described below to simplify the present disclosure. Of course, these are merely examples and are not intended to be limiting. For example, in the following description, forming a first feature above or on a second feature may include an embodiment in which the first feature and the second feature are formed in direct contact, and may also include an embodiment in which additional features may be formed between the first feature and the second feature so that the first feature and the second feature may not be in direct contact. In addition, the present disclosure may repeat reference numerals and / or letters in various examples. This repetition is for the purpose of simplicity and clarity, and does not itself indicate the relationship between the various embodiments and / or configurations discussed.

[0013] Additionally, spatially relative terms (e.g., "below," "beneath," "below," "above," "upper," etc.) may be used herein to facilitate describing the relationship of one element or feature illustrated in the figures relative to another element(s) or feature(s). These spatially relative terms are intended to encompass different orientations of the device in use or operation in addition to the orientation depicted in the figures. The device may be otherwise oriented (rotated 90 degrees or at other orientations) and the spatially relative descriptors used herein may likewise be interpreted accordingly.

[0014] Various embodiments provide semiconductor devices and methods for forming the same, wherein source / drain contacts extend beyond the top surface of an epitaxial source / drain region and into the epitaxial source / drain region. In a specific embodiment, a first recess may be formed through an interlayer dielectric to expose the top surface of the epitaxial source / drain region. A two-cycle plasma etching process may then be used to etch a second recess in the epitaxial source / drain region having a depth greater than about 15 nm from the top surface of an adjacent channel region. The first recess and the second recess may then be filled with a conductive material to form a source / drain contact. Forming a source / drain contact extending into the epitaxial source / drain region may reduce the distance between the source / drain contact and the channel region of the semiconductor device, which may reduce the source / drain contact resistance (R csd ) and improve the electrical performance of semiconductor devices.

[0015] Figure 1 An example of a nanostructure (e.g., nanosheet, nanowire, full gate, etc.) field effect transistor (NSFET) according to some embodiments is shown. The NSFET includes a nanostructure 55 on a substrate 50 (e.g., a semiconductor substrate). The nanostructure 55 includes a second semiconductor layer 54A-54C, which serves as a channel region of the nanostructure 55. Shallow trench isolation (STI) regions 58 are disposed in the substrate 50, and the nanostructures 55 are disposed on and between adjacent STI regions 58. Although the STI regions 58 are described / illustrated as being separate from the substrate 50, as used herein, the term "substrate" may refer to a semiconductor substrate alone or a combination of a semiconductor substrate and an STI region.

[0016] The gate dielectric layer 100 is along the top surface, sidewalls, and bottom surface of the nanostructure 55, for example, on the top surface, sidewalls, and bottom surface of each of the second semiconductor layers 54A-54C, and along the top surface and sidewalls of a portion of the substrate 50. The gate electrode 102 is on the gate dielectric layer 100. The epitaxial source / drain regions 92 are disposed on opposite sides of the nanostructure 55, the gate dielectric layer 100, and the gate electrode 102. Figure 1 Reference cross sections used in subsequent figures are further illustrated. Cross section AA' is along the longitudinal axis of gate electrode 102 and in a direction perpendicular to the direction of current flow, e.g., between epitaxial source / drain regions 92 of the NSFET. Cross section BB' is perpendicular to cross section AA' and along the longitudinal axis of nanostructure 55 and in the direction of current flow, e.g., between epitaxial source / drain regions 92 of the NSFET. Cross section CC' is parallel to cross section AA' and extends through epitaxial source / drain regions 92 of the NSFET. For clarity, subsequent figures refer to these reference cross sections.

[0017] Some embodiments discussed herein are discussed in the context of NSFETs and fin field effect transistors (FinFETs) formed using a gate-last process. In other embodiments, a gate-first process may be used. In addition, some embodiments contemplate aspects used in planar devices such as planar FETs.

[0018] Figures 2 to 23B is a cross-sectional view of an intermediate stage in the fabrication of a NSFET according to some embodiments. Figures 2 to 5 , Fig. 6A , Fig.13A , Fig.14A , Fig.15A , Fig.16A , Fig.17A , Fig.18A , Fig.22A and Fig.23A Shows Figure 1 Reference cross section AA' is shown. Figure 6B , Figure 7B , Figure 8B , Fig. 9B , Fig. 10B , Fig. 11B , Fig. 11C , Fig. 12B , Fig.12D , Fig. 13B , Fig. 14B , Fig. 15B , Fig. 16B , Fig. 17B , Fig.18B , Fig.19B , Fig. 20B , Fig.21B , Fig.21D , Fig.21E , Fig. 22B , Fig.22F and Fig. 23B Shows Figure 1 Reference cross section BB' is shown. Fig. 7A , Fig. 8A , Fig. 9A , Fig. 10A , Fig.11A , Fig. 12A , Fig. 12C , Fig. 13C , Fig. 18C , Fig.19A , Fig. 20A , Fig.21A , Fig. 21C , Fig. 22C , Fig.22D and Fig.22E Shows Figure 1 Reference cross section CC' shown.

[0019] exist Figure 2In the invention, a substrate 50 for forming a NSFET is provided. The substrate 50 may be a semiconductor substrate, such as a bulk semiconductor, a semiconductor on insulator (SOI) substrate, etc., which may be doped (e.g., with a p-type or n-type dopant) or undoped. The substrate 50 may be a wafer, such as a silicon wafer. Typically, an SOI substrate is a semiconductor material layer formed on an insulator layer. The insulator layer may be, for example, a buried oxide (BOX) layer, a silicon oxide layer, etc. The insulator layer is disposed on a substrate, which is typically a silicon or glass substrate. Other substrates may also be used, such as multilayer or gradient substrates. In some embodiments, the semiconductor material of the substrate 50 may include: silicon; germanium; compound semiconductors, including silicon carbide, gallium arsenide, gallium phosphide, indium phosphide, indium arsenide, and / or indium antimonide; alloy semiconductors, including silicon-germanium, gallium arsenide phosphide, aluminum indium arsenide, aluminum gallium arsenide, gallium indium arsenide, gallium indium phosphide, and / or gallium indium arsenide; or combinations thereof.

[0020] Substrate 50 has region 50N and region 50P. Region 50N can be used to form an n-type device, for example, an NMOS transistor, such as an n-type NSFET. Region 50P can be used to form a p-type device, for example, a PMOS transistor, such as a p-type NSFET. Region 50N can be physically separated from region 50P (as shown by separator 51), and any number of device features (e.g., other active devices, doped regions, isolation structures, etc.) can be disposed between region 50N and region 50P.

[0021] Substrate 50 may be lightly doped with p-type or n-type impurities. An anti-punch-through (APT) implant may be performed on an upper portion of substrate 50 to form APT region 53. During the APT implant, dopants may be implanted in regions 50N and 50P. The dopants may have a similar polarity to the source / drain regions (e.g., epitaxial source / drain regions 92, referred to below) to be formed in each of regions 50N and 50P. Figures 12A-12C The APT region 53 may extend below the subsequently formed source / drain regions in the resulting NSFET, which will be formed in a subsequent process. The APT region 53 may be used to reduce leakage from the source / drain regions to the substrate 50. In some embodiments, the doping concentration in the APT region 53 may be from about 1×10 18 Atom / cm 3 To about 1×10 19 Atom / cm 3 For the sake of simplicity and clarity, the APT region 53 is not shown in subsequent figures.

[0022] Further in Figure 2In the embodiment of the present invention, a multilayer stack 56 is formed on a substrate 50. The multilayer stack 56 includes alternating first semiconductor layers 52 and second semiconductor layers 54 of different semiconductor materials. The first semiconductor layer 52 may be formed of a first semiconductor material, which may include, for example, silicon germanium (SiGe), etc. The second semiconductor layer 54 may be formed of a second semiconductor material, which may include, for example, silicon (Si), silicon carbon (SiC), etc. In other embodiments, the first semiconductor layer 52 may be formed of a second semiconductor material, and the second semiconductor layer 54 may be formed of a first semiconductor material. For the purpose of illustration, the multilayer stack 56 includes three first semiconductor layers 52 (e.g., first semiconductor layers 52A-52C) and three second semiconductor layers 54 (e.g., second semiconductor layers 54A-54C). In other embodiments, the multilayer stack 56 may include any number of first semiconductor layers 52 and second semiconductor layers 54. Each layer of the multilayer stack 56 may be epitaxially grown using processes such as chemical vapor deposition (CVD), atomic layer deposition (ALD), vapor phase epitaxy (VPE), molecular beam epitaxy (MBE), etc.

[0023] For purposes of illustration, the second semiconductor layer 54 will be described as forming a channel region in a complete NSFET device. The first semiconductor layer 52 may be a sacrificial layer that may be subsequently removed. However, in some embodiments, the second semiconductor layers 54A-54C may form a channel region in a complete NSFET device, and the first semiconductor layers 52A-52D may be sacrificial layers.

[0024] exist Figure 3 In the embodiment of the present invention, nanostructures 55 are formed in multilayer stack 56, and substrate 50 is etched. In some embodiments, nanostructures 55 may be formed by etching trenches in multilayer stack 56 and substrate 50. Etching may be any acceptable etching process, such as reactive ion etching (RIE), neutral beam etching (NBE), etc., or a combination thereof. Etching may be anisotropic.

[0025] The nanostructure 55 and the substrate 50 may be patterned by any suitable method. For example, one or more photolithography processes may be used to pattern the nanostructure 55 and the substrate 50, including double patterning or multiple patterning processes. Typically, the double patterning or multiple patterning process combines photolithography and self-alignment processes, allowing the creation of patterns having, for example, a smaller spacing than that obtainable using a single direct photolithography process. For example, in one embodiment, a sacrificial layer is formed over the substrate and patterned using a photolithography process. A spacer is formed next to the patterned sacrificial layer using a self-alignment process. The sacrificial layer is then removed, and the remaining spacers may then be used to pattern the nanostructure 55 and the substrate 50. In some embodiments, after the nanostructure 55 and the substrate 50 are patterned, the mask (or other layer) may remain on the nanostructure 55.

[0026] exist Figure 4 In the embodiment, a shallow trench isolation (STI) region 58 is formed adjacent to the patterned portion of the substrate 50 and the nanostructure 55. The STI region 58 can be formed by forming an insulating material (not shown separately) on the substrate 50 and between the adjacent nanostructures 55 / patterned portions of the substrate 50. The insulating material can be an oxide (e.g., silicon oxide), a nitride, etc., or a combination thereof, and can be formed by high-density plasma chemical vapor deposition (HDP-CVD), flowable CVD (FCVD) (e.g., CVD-based material deposition in a remote plasma system and post-curing to convert the deposited material into another material, such as oxide), etc., or a combination thereof. Other insulating materials formed by any acceptable process can be used. In the embodiment shown, the insulating material is silicon oxide formed by an FCVD process. Once the insulating material is formed, an annealing process can be performed. In an embodiment, the insulating material is formed so that an excess of the insulating material covers the nanostructure 55. The insulating material can include a single layer or multiple layers can be used. For example, in some embodiments, a liner (not shown separately) can be first formed along the surface of the substrate 50 and the nanostructure 55. Thereafter, a fill material such as described above may be formed over the liner.

[0027] Then, a removal process is applied to the insulating material to remove excess insulating material above the nanostructure 55. In some embodiments, a planarization process may be employed, such as chemical mechanical polishing (CMP), an etch-back process, a combination thereof, etc. The planarization process may planarize the insulating material and the nanostructure 55. The planarization process exposes the nanostructure 55 so that the top surfaces of the nanostructure 55 and the insulating material are flush after the planarization process is completed.

[0028] The insulating material is then recessed to form a Figure 4The STI regions 58 shown. The insulating material is recessed so that the upper portions of the nanostructures 55 and the substrate 50 protrude from between adjacent STI regions 58. In addition, the top surface of the STI region 58 can have a flat surface (as shown), a convex surface, a concave surface (e.g., a dish), or a combination thereof. The top surface of the STI region 58 can be formed to be flat, convex, and / or concave by appropriate etching. The STI region 58 can be recessed using an acceptable etching process, for example, an etching process that is selective to the material of the insulating material (e.g., etching the material of the insulating material at a faster rate than the material of the nanostructures 55 and the substrate 50). For example, oxide removal using an acid such as dilute hydrofluoric acid (dHF) can be employed.

[0029] about Figure 2-4 The process described is only one example of how to form the nanostructure 55. In some embodiments, the nanostructure 55 can be formed by an epitaxial growth process. For example, a dielectric layer can be formed above the top surface of the substrate 50, and a groove can be etched through the dielectric layer to expose the substrate 50 below. The epitaxial structure can be epitaxially grown in the groove, and the dielectric layer can be recessed so that the epitaxial structure protrudes from the dielectric layer to form the nanostructure 55. In the nanostructure 55, the epitaxial structure can include alternating layers of a first semiconductor material and a second semiconductor material. The substrate 50 can include an epitaxial structure, which can be a homoepitaxial structure or a heteroepitaxial structure. The dielectric layer can then be recessed so that portions of the substrate 50 and the nanostructure 55 protrude from the dielectric layer. In embodiments in which portions of the substrate 50 and the nanostructure 55 are epitaxially grown, the epitaxially grown material can be doped in situ during growth, which can avoid implantation before and after, but in situ doping and implantation doping can be used together.

[0030] Furthermore, it may be advantageous to epitaxially grow a different material in region 50N (eg, NMOS region) than in region 50P (eg, PMOS region). In various embodiments, the upper portion of substrate 50 may be formed of: silicon germanium (Si x Ge 1-x , where x can be in the range of 0 to 1), silicon carbide, pure or substantially pure germanium, III-V compound semiconductors, II-VI compound semiconductors, etc. For example, available materials for forming III-V compound semiconductors include, but are not limited to, indium arsenide, aluminum arsenide, gallium arsenide, indium phosphide, gallium nitride, indium gallium arsenide, indium aluminum arsenide, gallium antimonide, aluminum antimonide, aluminum phosphide, gallium phosphide, etc.

[0031] Further in Figure 4In the embodiment of the present invention, appropriate wells (not shown separately) may be formed in the nanostructure 55 and / or the substrate 50. In some embodiments, a P-well may be formed in the region 50N, and an N-well may be formed in the region 50P. In further embodiments, a P-well or an N-well may be formed in each of the region 50N and the region 50P.

[0032] In embodiments including different well types, a photoresist or other mask (not shown separately) may be used to implement different implantation steps for region 50N and region 50P. For example, a photoresist may be formed over nanostructure 55, substrate 50, and STI region 58 in region 50N. The photoresist is patterned to expose region 50P of substrate 50. The photoresist may be formed using a spin coating technique and may be patterned using an acceptable photolithography technique. Once the photoresist is patterned, an n-type impurity implantation is performed in region 50P, and the photoresist may be used as a mask to substantially prevent n-type impurities from being implanted into region 50N. The n-type impurity may be phosphorus, arsenic, antimony, etc., implanted into the region at a concentration equal to or less than 1×10 18 Atom / cm 3 , for example, about 1×10 16 Atom / cm 3 About 1×10 18 Atom / cm 3 After implantation, the photoresist is removed, for example, by an acceptable ashing process.

[0033] After the implantation of region 50P, a photoresist is formed over nanostructure 55, substrate 50, and STI region 58 in region 50P. The photoresist is patterned to expose region 50N of substrate 50. The photoresist may be formed using a spin coating technique and may be patterned using an acceptable photolithography technique. Once the photoresist is patterned, a p-type impurity implantation may be performed in region 50N, and the photoresist may be used as a mask to substantially prevent the p-type impurity from being implanted into region 50P. The p-type impurity may be boron, boron fluoride, indium, etc., implanted into the region at a concentration equal to or less than 1×10 18 Atom / cm 3 , for example, about 1×10 16 Atom / cm 3 About 1×10 18 Atom / cm 3 After implantation, the photoresist may be removed, for example, by an acceptable ashing process.

[0034] After implantation of regions 50N and 50P, annealing may be performed to repair implant damage and activate the implanted p-type and / or n-type impurities. In some embodiments, the growth material of the epitaxial fins may be in-situ doped during growth, which may eliminate implantation, but in-situ doping and implantation doping may be used together.

[0035] exist Figure 5 In the process, a dummy dielectric layer 60 is formed on the nanostructure 55 and the substrate 50. The dummy dielectric layer 60 may be, for example, silicon oxide, silicon nitride, a combination thereof, etc., and may be deposited or thermally grown according to an acceptable technique. A dummy gate layer 62 is formed on the dummy dielectric layer 60, and a mask layer 64 is formed on the dummy gate layer 62. The dummy gate layer 62 may be deposited on the dummy dielectric layer 60 and then planarized by a process such as CMP. The mask layer 64 may be deposited on the dummy gate layer 62. The dummy gate layer 62 may be a conductive material or a non-conductive material, and may be selected from the group consisting of amorphous silicon, polycrystalline silicon (polysilicon), polycrystalline silicon germanium (poly-SiGe), metal nitride, metal silicide, metal oxide, and metal. The dummy gate layer 62 may be deposited by physical vapor deposition (PVD), CVD, sputtering deposition, or other techniques known in the art and used to deposit the selected material. The dummy gate layer 62 may be made of other materials with high etching selectivity relative to the material of the STI region 58. The mask layer 64 may include, for example, silicon nitride, silicon oxynitride, etc. In this example, a single dummy gate layer 62 and a single mask layer 64 are formed across the region 50N and the region 50P. It should be noted that the dummy dielectric layer 60 is shown as covering only the nanostructure 55 and the substrate 50 for illustration purposes only. In some embodiments, the dummy dielectric layer 60 may be deposited so that the dummy dielectric layer 60 covers the STI region 58, extending between the dummy gate layer 62 and the STI region 58.

[0036] FIG. 6A to FIG. 23B Various additional steps in the fabrication of example devices are shown. FIG. 6B to FIG. 23B Features in region 50N or region 50P are shown. For example, FIG. 6B to FIG. 23B The structure shown may apply to both region 50N and region 50P. Differences in the structures of region 50N and region 50P, if any, are described in the text accompanying each figure.

[0037] exist Fig. 6A and Figure 6B In the embodiment, the mask layer 64 (see Figure 5) is patterned to form a mask 74. The pattern of the mask 74 can be transferred to the dummy gate layer 62 using an acceptable etching technique to form the dummy gate 72. In some embodiments, the pattern of the mask 74 can also be transferred to the dummy dielectric layer 60. The dummy gate 72 covers the corresponding channel region of the nanostructure 55. In an embodiment, the channel region can be formed in the second semiconductor layer 54A-54C including the second semiconductor material. The pattern of the mask 74 can be used to physically separate each dummy gate 72 from the adjacent dummy gate 72. The dummy gate 72 can have a length direction substantially perpendicular to the length direction of the corresponding nanostructure 55.

[0038] exist Fig. 7A and Figure 7B in Fig. 6A and Figure 6B A first spacer layer 80 and a second spacer layer 82 are formed over the structure shown. Fig. 7A and Figure 7B , a first spacer layer 80 is formed on the top surface of the STI region 58, the top surface and sidewalls of the nanostructure 55 and the mask 74, and the sidewalls of the substrate 50, the dummy gate 72, and the dummy dielectric layer 60. A second spacer layer 82 is deposited on the first spacer layer 80. The first spacer layer 80 can be formed by thermal oxidation, or deposited by CVD, ALD, etc. The first spacer layer 80 can be formed of silicon oxide, silicon nitride, silicon oxynitride, etc. The second spacer layer 82 can be deposited by CVD, ALD, etc. The second spacer layer 82 can be formed of silicon oxide, silicon nitride, silicon oxynitride, etc.

[0039] exist Fig. 8A and Figure 8B In the embodiment, the first spacer layer 80 and the second spacer layer 82 are etched to form the first spacer 81 and the second spacer 83. The first spacer layer 80 and the second spacer layer 82 may be etched using a suitable etching process, for example, an isotropic etching process (for example, a wet etching process), an anisotropic etching process (for example, a dry etching process), etc. Fig. 8A As shown, the first spacer 81 and the second spacer 83 are disposed on the sidewalls of the nanostructure 55 and the substrate 50. Figure 8B As shown, the second spacer layer 82 may be removed from over the first spacer layer 80 adjacent to the mask 74 , the dummy gate 72 , and the dummy dielectric layer 60 , and the first spacer 81 is disposed on the sidewalls of the mask 74 , the dummy gate 72 , and the dummy dielectric layer 60 .

[0040] After forming the first spacer 81 and the second spacer 83, an implantation for lightly doped source / drain (LDD) regions (not shown separately) may be performed. In embodiments with different device types, similar to the above, Figure 4As discussed in the implantation described above, a mask (e.g., a photoresist) may be formed over region 50N, leaving region 50P exposed, and impurities of an appropriate type (e.g., p-type) may be implanted into exposed nanostructures 55 and substrate 50 in region 50P. The mask may then be removed. Subsequently, a mask (e.g., a photoresist) may be formed over region 50P, leaving region 50N exposed, and impurities of an appropriate type (e.g., n-type) may be implanted into exposed nanostructures 55 and substrate 50 in region 50N. The mask may then be removed. The n-type impurity may be any of the n-type impurities discussed previously, and the p-type impurity may be any of the p-type impurities discussed previously. The lightly doped source / drain regions may have a doping density of approximately 1×10 15 Atom / cm 3 About 1×10 19 Atom / cm 3 Annealing can be used to repair implant damage and activate the implanted impurities.

[0041] Note that the above disclosure generally describes the process of forming spacers and LDD regions. Other processes and sequences may be used. For example, fewer or additional spacers may be used, a different sequence of steps may be used, for example, the first spacer 81 may be formed before forming the second spacer 83, additional spacers may be formed and removed, etc. In addition, different structures and steps may be used to form n-type devices and p-type devices.

[0042] exist Fig. 9A and Fig. 9B In the embodiment, a first groove 86 is formed in the nanostructure 55 and the substrate 50. The first groove 86 can extend through the first semiconductor layer 52A-52C and the second semiconductor layer 54A-54C and extend into the substrate. Fig. 9A As shown, the top surface of the STI region 58 can be flush with the top surface of the substrate 50. In various embodiments, the first recess 86 can extend to the top surface of the substrate 50 without etching the substrate 50; the substrate 50 can be etched so that the bottom surface of the first recess 86 is disposed below the top surface of the STI region 58, etc. The first recess 86 can be formed by etching the nanostructure 55 and the substrate 50 using an anisotropic etching process such as RIE, NBE, etc. During the etching process for forming the first recess 86, the first spacer 81, the second spacer 83, and the mask 74 mask portions of the nanostructure 55 and the substrate 50. A single etching process can be used to etch each layer of the multilayer stack 56. In other embodiments, multiple etching processes can be used to etch the layers of the multilayer stack 56. A timed etching process can be used to stop etching the first recess 86 after the first recess 86 reaches a desired depth.

[0043] exist Fig. 10A and Fig. 10BIn the embodiment of the present invention, portions of the sidewalls of the layers of the multilayer stack 56 formed of the first semiconductor material (e.g., the first semiconductor layers 52A-52C) exposed by the first recess 86 are etched to form sidewall recesses 88. Although the sidewalls of the first semiconductor layers 52A-52C are Fig. 10B 52A-52C, but the sidewalls may be concave or convex. The sidewalls may be etched using an isotropic etching process such as wet etching or the like. The etchant used to etch the first semiconductor layer 52A-52C may be selective to the first semiconductor material so that the second semiconductor layer 54A-54C and the substrate 50 remain relatively unetched compared to the first semiconductor layer 52A-52C. In an embodiment in which the first semiconductor layer 52A-52C includes, for example, SiGe and the second semiconductor layer 54A-54C includes, for example, Si or SiC, the sidewalls of the multilayer stack 56 may be etched using tetramethylammonium hydroxide (TMAH), ammonium hydroxide (NH4OH), or the like. In other embodiments, a dry etching process may be used to etch the layers of the multilayer stack 56. The sidewalls of the multilayer stack 56 may be etched using hydrogen fluoride, another fluorine-based gas, or the like.

[0044] exist Figures 11A-11C In the embodiment, a first inner spacer 90 is formed in the sidewall groove 88. Fig. 10A and Fig. 10B An inner spacer layer (not separately shown) is deposited over the structure shown to form a first inner spacer 90. The inner spacer layer may be deposited by a conformal deposition process such as CVD, ALD, or the like. The inner spacer layer may include a material such as silicon nitride or silicon oxynitride, but any suitable material may be utilized, for example, a low dielectric constant (low-k) material having a k value of less than about 3.5. The inner spacer layer may then be etched to form the first inner spacer 90. Although in Fig. 11B The outer sidewalls of the first inner spacer 90 are shown as being flush with the sidewalls of the second semiconductor layers 54A-54C, but the outer sidewalls of the first inner spacer 90 may extend beyond the sidewalls of the second semiconductor layers 54A-54C or be recessed from the sidewalls of the second semiconductor layers 54A-54C. Fig. 11B The outer sidewall of the first inner spacer 90 is shown as straight, but the outer sidewall of the first inner spacer 90 can be concave or convex. As an example, Fig. 11C An embodiment is shown in which the sidewalls of the first semiconductor layer 52A-52C are concave, the outer sidewalls of the first inner spacer 90 are concave, and the first inner spacer is recessed from the sidewalls of the second semiconductor layer 54A-54C. The inner spacer layer can be etched by an anisotropic etching process such as RIE, NBE, etc. The first inner spacer 90 can be used to prevent the source / drain region (e.g., epitaxial source / drain region 92, which will be described below) formed by a subsequent etching process. FIG. 12A to FIG. 12C discussion) damage.

[0045] exist Figure 12A-12C In the embodiment, an epitaxial source / drain region 92 is formed in the first recess 86 to apply stress to the second semiconductor layer 54A-54C of the nanostructure 55, thereby improving performance. Fig. 12B As shown, an epitaxial source / drain region 92 is formed in the first recess 86 so that each dummy gate 72 is disposed between a corresponding adjacent pair of epitaxial source / drain regions 92. The height H1 of the epitaxial source / drain region 92 is about 40 nm to about 60 nm, for example, about 50 nm. In some embodiments, the first spacer 81 is used to separate the epitaxial source / drain region 92 from the dummy gate 72 by an appropriate lateral distance so that the epitaxial source / drain region 92 does not short-circuit the gate of the resulting NSFET formed subsequently. The first internal spacer 90 can be used to separate the epitaxial source / drain region 92 from the first semiconductor layer 52A-52C by an appropriate lateral distance to prevent short circuits between the epitaxial source / drain region 92 and the gate of the resulting NSFET formed subsequently.

[0046] The epitaxial source / drain regions 92 in the region 50N (e.g., NMOS region) can be formed by masking the region 50P (e.g., PMOS region). The epitaxial source / drain regions 92 are then epitaxially grown in the first recess 86. The epitaxial source / drain regions 92 can include any acceptable material, such as a material suitable for an n-type NSFET. For example, if the second semiconductor layers 54A-54C are silicon, the epitaxial source / drain regions 92 can include a material that applies tensile strain to the second semiconductor layers 54A-54C, such as silicon, silicon carbide, silicon carbide doped with phosphorus, silicon phosphorus, etc. The epitaxial source / drain regions 92 can have surfaces that protrude from corresponding surfaces of the multilayer stack 56 and can have small facets.

[0047] The epitaxial source / drain regions 92 in the region 50P (e.g., a PMOS region) can be formed by masking the region 50N (e.g., an NMOS region). The epitaxial source / drain regions 92 are then epitaxially grown in the first recess 86. The epitaxial source / drain regions 92 can include any acceptable material, such as a material suitable for a p-type NSFET. For example, if the second semiconductor layers 54A-54C are silicon, the epitaxial source / drain regions 92 can include a material that applies compressive strain on the second semiconductor layers 54A-54C, such as silicon germanium, boron-doped silicon germanium, germanium, germanium tin, etc. The epitaxial source / drain regions 92 can also have surfaces that protrude from corresponding surfaces of the multilayer stack 56 and can have small facets.

[0048] The epitaxial source / drain regions 92, the second semiconductor layers 54A-54C, and / or the substrate 50 may be implanted with dopants to form source / drain regions, similar to the process previously discussed for forming lightly doped source / drain regions, followed by annealing. In some embodiments, the epitaxial source / drain regions 92 may be doped with dopants in situ during growth. The impurity concentration of the source / drain regions may be about 1×10 19 Atom / cm 3 and about 1×10 21 Atom / cm 3 The n-type and / or p-type impurities used for the source / drain regions may be any of the impurities discussed previously.

[0049] As a result of the epitaxial process used to form epitaxial source / drain regions 92 in regions 50N and 50P, the top surfaces of epitaxial source / drain regions 92 have facets that extend laterally outward beyond the sidewalls of nanostructures 55. In some embodiments, these facets cause adjacent epitaxial source / drain regions 92 of the same NSFET to merge, such as Fig. 12A In other embodiments, adjacent epitaxial source / drain regions 92 remain separated after the epitaxial process is completed, such as Fig. 12C As shown. Fig. 12A and Fig. 12C In the illustrated embodiment, first spacers 81 may be formed to cover the sidewalls of nanostructures 55 and portions of substrate 50 extending over STI regions 58, thereby preventing epitaxial growth. In some other embodiments, the spacer etch used to form first spacers 81 may be adjusted to remove spacer material to allow the region of epitaxial growth to extend to the surface of STI regions 58.

[0050] The epitaxial source / drain region 92 may include one or more semiconductor material layers. For example, the epitaxial source / drain region 92 may include a first semiconductor material layer 92A, a second semiconductor material layer 92B, and a third semiconductor material layer 92C. Any number of semiconductor material layers may be used for the epitaxial source / drain region 92. Each of the first semiconductor material layer 92A, the second semiconductor material layer 92B, and the third semiconductor material layer 92C may be formed of a different semiconductor material and may be doped to a different dopant concentration. In some embodiments, the first semiconductor material layer 92A may have a dopant concentration that is less than the second semiconductor material layer 92B and greater than the third semiconductor material layer 92C. In an embodiment in which the epitaxial source / drain region 92 includes three semiconductor material layers, the first semiconductor material layer 92A may be deposited, the second semiconductor material layer 92B may be deposited on the first semiconductor material layer 92A, and the third semiconductor material layer 92C may be deposited on the second semiconductor material layer 92B.

[0051] Fig.12D An embodiment is shown in which the sidewalls of the first semiconductor layers 52A-52C are concave, the outer sidewalls of the first inner spacer 90 are concave, and the first inner spacer is recessed from the sidewalls of the second semiconductor layers 54A-54C. Fig.12D As shown, epitaxial source / drain regions 92 may be formed in contact with the first inner spacers 90 and may extend beyond the sidewalls of the second semiconductor layers 54A- 54C.

[0052] exist Figure 13A-13C In the embodiment, the first interlayer dielectric (ILD) 96 is deposited on Fig. 6A , Fig. 12B and Fig. 12A On top of the structure shown ( Figures 7A-12C The process will not change Fig. 6A ). The first ILD 96 may be formed of a dielectric material and may be deposited by any suitable method such as CVD, plasma enhanced CVD (PECVD), or FCVD. The dielectric material may include phosphosilicate glass (PSG), borosilicate glass (BSG), boron-doped phosphosilicate glass (BPSG), undoped silicate glass (USG), etc. Other insulating materials formed by any acceptable process may be used. In some embodiments, a contact etch stop layer (CESL) 94 is disposed between the first ILD 96 and the epitaxial source / drain regions 92, the mask 74, and the first spacer 81. The CESL 94 may include a dielectric material having an etch rate different from that of the material of the first ILD 96 above, for example, silicon nitride, silicon oxide, silicon oxynitride, etc.

[0053] exist Figure 14A-14B In the process, a planarization process such as CMP may be performed to make the top surface of the first ILD 96 flush with the top surface of the dummy gate 72 or the mask 74. The planarization process may also remove the mask 74 on the dummy gate 72, and the portion of the first spacer 81 along the sidewall of the mask 74. After the planarization process, the top surfaces of the dummy gate 72, the first spacer 81, and the first ILD 96 are flush. Therefore, the top surface of the dummy gate 72 is exposed through the first ILD 96. In some embodiments, the mask 74 may remain, in which case the planarization process makes the top surface of the first ILD 96 flush with the top surfaces of the mask 74 and the first spacer 81.

[0054] exist Fig.15A and Fig. 15BIn the embodiment of the present invention, the dummy gate 72 and the mask 74 (if present) are removed in the etching step(s) to form the second recess 98. The portion of the dummy dielectric layer 60 in the second recess 98 may also be removed. In some embodiments, only the dummy gate 72 is removed, and the dummy dielectric layer 60 remains and is exposed by the second recess 98. In some embodiments, the dummy dielectric layer 60 is removed from the second recess 98 in the first region of the die (e.g., the core logic region) and remains in the second recess 98 in the second region of the die (e.g., the input / output region). In some embodiments, the dummy gate 72 is removed by an anisotropic dry etching process. For example, the etching process may include a dry etching process using (one or more) reactive gases that selectively etches the dummy gate 72 at a faster rate than the first ILD 96 or the first spacer 81. Each second recess 98 exposes and / or covers portions of the multilayer stack 56 that serve as channel regions in a subsequently completed NSFET. Portions of the multilayer stack 56 that function as channel regions are disposed between adjacent pairs of epitaxial source / drain regions 92. During removal, the dummy dielectric layer 60 may function as an etch stop layer when etching the dummy gate 72. The dummy dielectric layer 60 may then be optionally removed after the dummy gate 72 is removed.

[0055] exist Fig.16A and Fig. 16B , the first semiconductor layers 52A-52C are removed, and the second recess 98 is extended. The first semiconductor layers 52A-52C can be removed by an isotropic etching process (e.g., wet etching, etc.). The first semiconductor layers 52A-52C can be removed using an etchant that is selective to the material of the first semiconductor layers 52A-52C, while the second semiconductor layers 54A-54C, the substrate 50, and the STI regions 58 remain relatively unetched compared to the first semiconductor layers 52A-52C. In embodiments where the first semiconductor layers 52A-52C include, for example, SiGe, and the second semiconductor layers 54A-54C include, for example, Si or SiC, tetramethylammonium hydroxide (TMAH), ammonium hydroxide (NH4OH), etc. can be used to remove the first semiconductor layers 52A-52C.

[0056] exist Fig.17A and Fig. 17B, a gate dielectric layer 100 and a gate electrode 102 are formed for replacing the gate. The gate dielectric layer 100 is conformally deposited in the second groove 98, for example, on the top surface and sidewalls of the substrate 50, and on the top surface, sidewalls and bottom surface of the second semiconductor layer 54A-54C. The gate dielectric layer 100 may also be deposited on the top surface of the first ILD 96, the CESL 94, the first spacer 81 and the STI region 58. According to some embodiments, the gate dielectric layer 100 includes silicon oxide, silicon nitride, or multiple layers thereof. In some embodiments, the gate dielectric layer 100 includes a high-k dielectric material, and in these embodiments, the gate dielectric layer 100 may have a k value greater than about 7.0, and may include metal oxides or silicates of hafnium, aluminum, zirconium, lanthanum, manganese, barium, titanium, lead, and combinations thereof. The formation method of the gate dielectric layer 100 may include molecular beam deposition (MBD), ALD, PECVD, etc.

[0057] The gate electrode 102 is deposited on the gate dielectric layer 100 and fills the remaining portion of the second recess 98. The gate electrode 102 may include a metal-containing material, such as titanium nitride, titanium oxide, tantalum nitride, tantalum carbide, cobalt, ruthenium, aluminum, tungsten, combinations thereof, or multiple layers thereof. Fig.17A and Fig. 17B , but the gate electrode 102 may include any number of liner layers, any number of work function adjustment layers, and fill materials. Any combination of layers constituting the gate electrode 102 may be deposited in the region between each of the second semiconductor layers 54A-54C and between the second semiconductor layer 54A and the substrate 50. After filling the second recess 98, a planarization process such as CMP may be performed to remove the material of the gate electrode 102 and the excess portion of the gate dielectric layer 100 that is above the top surface of the first ILD 96. The material of the gate electrode 102 and the remaining portion of the gate dielectric layer 100 thereby form a replacement gate of the resulting NSFET. The gate electrode 102 and the gate dielectric layer 100 may be collectively referred to as a "gate stack."

[0058] The formation of the gate dielectric layer 100 in the region 50N and the region 50P may occur simultaneously, such that the gate dielectric layer 100 in each region is formed of the same material, and the formation of the gate electrode 102 may occur simultaneously, such that the gate electrode 102 in each region is formed of the same material. In some embodiments, the gate dielectric layer 100 in each region may be formed by a different process, such that the gate dielectric layer 100 may be a different material, and / or the gate electrode 102 in each region may be formed by a different process, such that the gate electrode 102 may be a different material. When different processes are used, various masking steps may be used to mask and expose the appropriate regions.

[0059] exist Figures 18A-18C In some embodiments, a second ILD 106 is deposited over the first ILD 96. In some embodiments, the second ILD 106 is a flowable film formed by FCVD. In some embodiments, the second ILD 106 is formed of a dielectric material such as PSG, BSG, BPSG, USG, etc., and may be deposited by any suitable method such as CVD, PECVD, etc. According to some embodiments, before forming the second ILD 106, the gate stack (including the gate dielectric layer 100 and the corresponding overlying gate electrode 102) is recessed to form a groove directly above the gate stack and between the opposing portions of the first spacer 81. A gate mask 104 is filled in the groove, which includes one or more layers of dielectric material (e.g., silicon nitride, silicon oxynitride, etc.), and a planarization process is then performed to remove excess portions of the dielectric material extending over the first ILD 96. A gate contact (e.g., described below with respect to Fig.23A and Fig. 23B A gate contact 114 is discussed to penetrate the gate mask 104 to contact the top surface of the recessed gate electrode 102 .

[0060] exist Fig.19A and Fig.19B , the second ILD 106, the first ILD 96, and the CESL 94 are etched to form a third recess 108, which exposes the surface of the epitaxial source / drain region 92. The third recess 108 may be formed by etching using an anisotropic etching process (e.g., RIE, NBE, etc.). In some embodiments, the third recess 108 may be etched through the second ILD 106 and the first ILD 96 using a first etching process, and then may be etched through the CESL 94 using a second etching process. A mask (e.g., photoresist) may be formed over the second ILD 106 and patterned to mask portions of the second ILD 106 from the first etching process and the second etching process.

[0061] exist Fig. 20A and Fig. 20B , a third spacer 110 is formed on the sidewalls of the third recess 108. A third spacer layer (not shown separately) may be formed on the top surfaces of the second ILD 106 and the epitaxial source / drain regions 92, and on the sidewalls of the second ILD 106, the first ILD 96, and the CESL 94. The third spacer layer may be formed by thermal oxidation, or deposited by CVD, ALD, etc. The third spacer layer may be formed of silicon oxide, silicon nitride, silicon oxynitride, etc. The third spacer layer may be etched using a suitable etching process such as anisotropic etching (e.g., a dry etching process), etc. to form the third spacer 110. Fig. 20A and Fig. 20B As shown, the third spacer 110 may remain on the sidewalls of the second ILD 106, the first ILD 96, and the CESL 94 in the third recess 108. The third spacer 110 may have a thickness from about 2 nm to about 5 nm, for example, about 3 nm, and may be used to protect the sidewalls of the second ILD 106, the first ILD 96, and the CESL 94 from subsequent etching performed on the epitaxial source / drain regions 92. In some embodiments, the third spacer 110 may be formed of silicon nitride and may be used to prevent the subsequent formation of source / drain contacts (for example, as described below). Figure 22A-22F The source / drain contacts 112 discussed above can be used to reduce leakage and can be used to improve the breakdown voltage (V bd ) reliability issues, thereby improving performance and reducing device defects.

[0062] exist Figure 21A-Figure 21E, the epitaxial source / drain region 92 is etched to extend the third recess 108. The epitaxial source / drain region 92 may be etched by an anisotropic etching process such as RIE, NBE, etc. The epitaxial source / drain region 92 may be etched by an iterative etching process, wherein each iteration includes a third etching process followed by a fourth etching process. The third etching process and the fourth etching process may be different from the first etching process and the second etching process used to etch the first ILD 96, the second ILD 106, and the CESL 94. The iterative etching process may be repeated from 5 iterations to 20 iterations, for example, 10 iterations. The iterative etching process may be repeated until the depth D1 of the third recess 108 below the top surface of the second semiconductor layer 54C is greater than about 15 nm or from about 10 nm to about 20 nm, for example, about 15 nm. The depth D2 of the third recess 108 below the top surface of the epitaxial source / drain region 92 may be greater than about 18 nm or from about 13 nm to about 23 nm, for example, about 18 nm. The ratio of the depth D2 of the third recess 108 to the height H1 of the epitaxial source / drain region 92 may be about 1:3 to about 1:2, for example, about 2:5. The bottommost surface of the third recess 108 may be disposed above, below, or flush with the bottommost surface of the second semiconductor layer 54A. Portions of the gate dielectric layer 100 and the gate electrode 102 may extend below the bottommost surface of the third recess 108. For example, Fig.21B , Fig.21D and Fig.21E As shown, the portion of the gate dielectric layer 100 and the gate electrode 102 formed between the substrate 50 and the second semiconductor layer 54A can extend below the bottommost surface of the third recess 108. In some embodiments, the portion of the gate dielectric layer 100 and the gate electrode 102 formed between the second semiconductor layer 54A and the second semiconductor layer 54B can extend below the bottommost surface of the third recess 108. Etching the third recess 108 to the described depth reduces the subsequent formation of source / drain contacts (e.g., as described below with reference to Figures 22B-22F The source / drain contact 112 discussed above) and the distance between the second semiconductor layers 54A-54C reduce the source / drain contact resistance (R csd ), and improves the device performance of the NSFET. Etching the third groove 108 to too great a depth may affect the performance of the epitaxial source / drain region 92, reduce device performance and cause device defects. Fig.21A and Fig.21B As shown, the sidewalls of the epitaxial source / drain regions 92 may abut against the sidewalls of the third spacer 110. In other embodiments, as shown in FIG. Fig. 21C and Fig.21D As shown, the third recess 108 may undercut the epitaxial source / drain regions 92 beneath the third spacers 110 .

[0063] Fig.21E FIG. 1 shows the profile of the third groove 108 according to some embodiments. Fig.21E In the illustrated embodiment, the sidewalls of the epitaxial source / drain region 92 adjacent to the third recess 108 may abut against the sidewalls of the third spacer 110. Portions of the sidewalls of the epitaxial source / drain region 92 adjacent to the third recess 108 may be substantially straight and may be sloped to rounded corners. Fig.21E As further shown in FIG. 1 , the third recess 108 may extend through the third semiconductor material layer 92C and partially through the second semiconductor material layer 92B. However, in some embodiments, the third recess 108 may extend partially through the third semiconductor material layer 92C; through the third semiconductor material layer 92C, through the second semiconductor material layer 92B, and partially through the first semiconductor material layer 92A, etc.

[0064] The third etching process may use a third etchant gas and a fourth etchant gas. The third etchant gas may include fluoromethane (CH3F), difluoromethane (CH2F2), etc., and the fourth etchant gas may include hydrogen (H2), etc. The flow rate of the third etchant gas may be about 10sccm to about 40sccm, for example, about 15sccm, and the flow rate of the fourth etchant gas may be about 150sccm to about 300sccm, for example, about 200sccm. The third etching process may be performed at a pressure of about 10mTorr to about 30mTorr (for example, about 15mTorr) and a temperature of about 30°C to about 60°C (for example, about 40°C). A plasma generator may be used at a power of about 100W to about 300W (for example, about 200W) to generate plasma from the third etchant gas and the fourth etchant gas. The substrate holder on which the substrate 50 is arranged during the third etching process may be biased with a voltage of about 200V to about 400V (for example, about 300V).

[0065] The fourth etching process may use a fifth etchant gas and a sixth etchant gas. The fifth etchant gas may include nitrogen (N2), argon (Ar), etc., and the sixth etchant gas may include hydrogen (H2), etc. The flow rate of the fifth etchant gas may be about 100 sccm to about 300 sccm, for example, about 150 sccm, and the flow rate of the sixth etchant gas may be about 150 sccm to about 300 sccm, for example, about 200 sccm. The fourth etching process may be performed at a pressure of about 10 mTorr to about 30 mTorr (for example, about 15 mTorr) and a temperature of about 30°C to about 60°C (for example, about 40°C). A plasma generator may be used at a power of about 100 W to about 300 W (for example, about 150 W) to generate plasma from the fifth etchant gas and the sixth etchant gas. The substrate holder on which the substrate 50 is arranged during the fourth etching process may be biased with a voltage of about 200 V to about 400 V (for example, about 250 V).

[0066] Etching the epitaxial source / drain region 92 using the third etching process may cause byproduct polymers to be formed at the bottom of the third recess 108 adjacent to the epitaxial source / drain region 92. The byproduct polymers may then be removed using a fourth etching process. The fourth etching process may be anisotropic and may remove byproduct polymers from the bottom surface of the third recess 108 at a higher rate than the second etching process, which removes byproduct polymers from the side surfaces of the third recess 108. Thus, the third etching process and the fourth etching process may be used to anisotropically etch the epitaxial source / drain region 92.

[0067] exist Figures 22A-22F In the third recess 108, a source / drain contact 112 is formed. The source / drain contact 112 is formed in the third recess 108. A liner such as a diffusion barrier layer, an adhesion layer, etc., and a conductive material are formed in the third recess 108. The liner may include titanium, titanium nitride, tantalum, tantalum nitride, etc. The liner may be deposited by a conformal deposition process, such as atomic layer deposition (ALD), chemical vapor deposition (CVD), physical vapor deposition (PVD), etc. In some embodiments, the liner may include an adhesion layer, and at least a portion of the adhesion layer may be processed to form a diffusion barrier layer. For example, a nitridation process may be performed on the adhesion layer, such as a nitrogen plasma process, to convert at least a portion of the adhesion layer into a diffusion barrier layer. In some embodiments, the adhesion layer may be completely converted so that no adhesion layer remains and the diffusion barrier layer is an adhesion / barrier layer. In some embodiments, a portion of the adhesion layer remains unconverted so that a portion of the adhesion layer remains and the diffusion barrier layer is on the adhesion layer.

[0068] A silicide region may be formed adjacent epitaxial source / drain region 92 by reacting a portion of epitaxial source / drain region 92 adjacent to the liner with the liner. An anneal such as a rapid thermal anneal (RTA) may be performed to promote the reaction of epitaxial source / drain region 92 with the liner.

[0069] The conductive material may be copper, copper alloy, silver, gold, tungsten, cobalt, aluminum, nickel, etc. The conductive material may be deposited by ALD, CVD, PVD, etc. After forming the liner and the conductive material, a planarization process such as CMP may be performed to remove excess material from the surface of the second ILD 106. The remaining liner and conductive material form source / drain contacts 112 in the third recess 108. The source / drain contacts 112 are physically and electrically coupled to the epitaxial source / drain regions 92.

[0070] The bottom surface of the source / drain contact 112 may be flush with, disposed above, or disposed below the bottom surface of the second semiconductor layer 54A. The bottom surface of the source / drain contact 112 may also be disposed below the bottom surfaces of the second semiconductor layers 54B and 54C, and below the top surfaces of the second semiconductor layers 54A-54C. The vertical distance D3 between the bottom surface of the source / drain contact 112 and the bottom surface of the second semiconductor layer 54A may be about 10 nm to about 14 nm, for example, about 12 nm. The source / drain contact 112 may be laterally spaced from the second semiconductor layers 54A-54C by a distance D4 of about 4 nm to about 8 nm, for example, about 6 nm. The bottom surface of the source / drain contact 112 may extend into the epitaxial source / drain region 92 to a depth D9 below the top surface of the epitaxial source / drain region 92, which may be greater than about 18 nm or from about 13 nm to about 23 nm, for example, about 18 nm. The ratio of the depth D9 of the source / drain contact 112 to the height H1 of the epitaxial source / drain region 92 may be about 1:3 to about 1:2, for example, about 2:5. Forming the epitaxial source / drain region 92 and the source / drain contact 112 according to this ratio makes the source / drain contact resistance (R csd ) while ensuring that enough material of the epitaxial source / drain regions 92 remains to effectively function as source / drain regions. Portions of the gate dielectric layer 100 and gate electrode 102 may extend below the bottom surface of the source / drain contact 112. For example, Fig. 22B and Fig.22FAs shown, portions of the gate dielectric layer 100 and the gate electrode 102 formed between the substrate 50 and the second semiconductor layer 54A may extend below the bottom surface of the source / drain contact 112. In some embodiments, portions of the gate dielectric layer 100 and the gate electrode 102 formed between the second semiconductor layer 54A and the second semiconductor layer 54B may extend below the bottom surface of the source / drain contact 112.

[0071] Etching the epitaxial source / drain regions 92 to form the third recess 108 and forming the source / drain contacts 112 in the third recess 108 reduces the distance between the source / drain contacts 112 and the second semiconductor layers 54A-54C (which serve as the channel in the completed NSFET). For example, the maximum distance between any one of the second semiconductor layers 54A-54C and the source / drain contacts 112 can be about 4 nm to about 8 nm, for example, about 6 nm. This reduces the source / drain contact resistance (R csd ), thereby improving the device performance of the NSFET formed by the above method.

[0072] Fig.22D and Fig.22E A cross section CC' of an alternative embodiment with source / drain contacts 112 is shown. Fig.22D and Fig.22E As shown, source / drain contacts 112 may contact adjacent pairs of merged epitaxial source / drain regions 92. Source / drain contacts 112 may contact epitaxial source / drain regions 92 and may extend to a greater depth between the pairs of merged epitaxial source / drain regions 92. Source / drain contacts 112 may have a more square profile, such as Fig.22D or a more wavy profile, such as Fig.22E . The bottom surface of source / drain contact 112 may be disposed above STI region 58 or may extend to STI region 58. Epitaxial source / drain regions 92 may contact the above-mentioned silicide regions of source / drain contact 112. Forming source / drain contact 112 to contact adjacent pairs of merged epitaxial source / drain regions 92 creates a large contact area between source / drain contact 112 and epitaxial source / drain regions 92, which further reduces the source / drain contact resistance (R csd ).

[0073] Fig.22F Shown according to Fig.21E The third recessed source / drain contact 112 of the embodiment shown in FIG. Fig.22FAs shown in the illustrated embodiment, the source / drain contact 112 can have an inclined sidewall that is substantially straight adjacent to the third spacer 110 and adjacent to the epitaxial source / drain region 92, the sidewall extending to a round point. The epitaxial source / drain region can be in contact with the silicide region of the source / drain contact 112. In some embodiments, the source / drain contact 112 can extend through the third semiconductor material layer 92C and partially through the second semiconductor material layer 92B. However, in some embodiments, the source / drain contact can extend only partially through the third semiconductor material layer 92C; through the third semiconductor material layer 92C, through the second semiconductor material layer 92B, and partially through the first semiconductor material layer 92A, etc.

[0074] exist Fig.23A and Fig. 23B , a gate contact 114 is formed. An opening for the gate contact 114 is formed through the second ILD 106 and the gate mask 104. Acceptable photolithography and etching techniques may be used to form the opening. A liner such as a diffusion barrier layer, an adhesion layer, etc., and a conductive material are formed in the opening. The liner may include titanium, titanium nitride, tantalum, tantalum nitride, etc. The conductive material may be copper, a copper alloy, silver, gold, tungsten, cobalt, aluminum, nickel, etc. A planarization process such as CMP may be performed to remove excess material from the surface of the second ILD 106. The remaining liner and conductive material form a gate contact 114 in the opening. The gate contact 114 is physically and electrically coupled to the gate electrode 102. In different embodiments, the gate contact 114 may be formed simultaneously by the same process as the source / drain contact 112, or may be formed by a different process and before or after the source / drain contact 112. Although shown as being formed in the same cross-section, it is understood that each of the source / drain contacts 112 and the gate contact 114 may be formed in different cross-sections, which may avoid shorting of the contacts.

[0075] Figure 24-41B An embodiment is shown that applies the above teachings to a fin field effect transistor (FinFET). Fig.24An example of a FinFET according to some embodiments is shown. The FinFET includes a fin 255 on a substrate 250 (e.g., a semiconductor substrate). A shallow trench isolation (STI) region 258 is disposed in the substrate 250, and the fin 255 protrudes above and between adjacent STI regions 258. Although the STI regions 258 are described / illustrated as being separated from the substrate 250, as used herein. The term "substrate" may be used to refer to only a semiconductor substrate, or a semiconductor substrate including an STI region. In addition, although the fin 255 is shown as a single continuous material with the substrate 250, the fin 255 and / or the substrate 250 may include a single material or multiple materials. In this context, the fin 255 refers to a portion extending between adjacent STI regions 258.

[0076] The gate dielectric layer 300 is located along the sidewalls of the fin 255 and on the top surface of the fin 255, and the gate electrode 302 is located on the gate dielectric layer 300. The epitaxial source / drain regions 292 are disposed on the opposite sides of the fin 255, the gate dielectric layer 300 and the gate electrode 302. Fig.24 Reference cross sections used in subsequent figures are further illustrated. Cross section AA' is along the longitudinal axis of the gate electrode 302 and in a direction, for example, perpendicular to the direction of current flow between the epitaxial source / drain regions 292 of the FinFET. Cross section BB' is perpendicular to cross section AA' and along the longitudinal axis of the fin 255 and in a direction of current flow, for example, between the epitaxial source / drain regions 292 of the FinFET. Cross section CC' is parallel to cross section AA' and extends through the epitaxial source / drain regions 292 of the FinFET. For clarity, subsequent figures refer to these reference cross sections.

[0077] Figures 25 to 41B is a cross-sectional view of an intermediate stage in the fabrication of a FinFET according to some embodiments. Figure 25 to Figure 28 Shows Fig.24 Reference cross section AA' is shown. Fig.29A , Fig.34A , Fig.35A , Fig.36A , Fig.37A , Fig.38A and Fig.41A Along Fig.24 The reference cross section AA' is shown. Fig.29B , Fig. 30B , Fig.31B , Fig.32B , Fig.33B , Fig.34B , Fig.35B , Fig.36B , Fig.37B , Fig.38B , Fig.39B , Fig.39C , Fig.40B , Fig.40C and Fig.41B Along Fig.24 A similar cross section BB' is shown in FIG. Fig. 30A , Fig.31A , Fig.32A , Fig.33A , Fig.33C , Fig.34C , Fig.38C , Fig.39A and Fig.40A Along Fig.24 The reference cross section CC' is shown.

[0078] exist Fig.25 In the embodiment, a substrate 250 is provided. The substrate 250 may be a semiconductor substrate, such as a bulk semiconductor, a semiconductor on insulator (SOI) substrate, etc., which may be doped (e.g., with a p-type or n-type dopant) or undoped. The substrate 250 may be a wafer, such as a silicon wafer. Typically, an SOI substrate is a semiconductor material layer formed on an insulator layer. The insulator layer may be, for example, a buried oxide (BOX) layer, a silicon oxide layer, etc. The insulator layer is disposed on a substrate, which is typically a silicon or glass substrate. Other substrates may also be used, such as multilayer or gradient substrates. In some embodiments, the semiconductor material of the substrate 250 may include: silicon; germanium; compound semiconductors, including silicon carbide, gallium arsenide, gallium phosphide, indium phosphide, indium arsenide, and / or indium antimonide; alloy semiconductors, including silicon-germanium, gallium arsenide phosphide, aluminum indium arsenide, aluminum gallium arsenide, gallium indium arsenide, gallium indium phosphide, and / or gallium indium arsenide; or combinations thereof.

[0079] The substrate 250 has a region 250N and a region 250P. The region 250N can be used to form an n-type device, for example, an NMOS transistor, such as an n-type FinFET. The region 250P can be used to form a p-type device, for example, a PMOS transistor, such as a p-type FinFET. The region 250N can be physically separated from the region 250P (as shown by the separator 251), and any number of device features (e.g., other active devices, doped regions, isolation structures, etc.) can be set between the region 250N and the region 250P.

[0080] exist Fig.26 In the embodiment of the present invention, fins 255 are formed in substrate 250. Fins 255 are semiconductor strips. In some embodiments, fins 255 can be formed in substrate 250 by etching trenches in substrate 250. Etching can be any acceptable etching process, such as reactive ion etching (RIE), neutral beam etching (NBE), etc., or a combination thereof. Etching can be anisotropic.

[0081] The fin 255 may be patterned by any suitable method. For example, the fin 255 may be patterned using one or more photolithography processes, including double patterning or multi-patterning processes. Typically, the double patterning or multi-patterning process combines photolithography and self-alignment processes, allowing the creation of patterns having, for example, a smaller spacing than that obtainable using a single direct photolithography process. For example, in one embodiment, a sacrificial layer is formed over a substrate and patterned using a photolithography process. Spacers are formed next to the patterned sacrificial layer using a self-alignment process. The sacrificial layer is then removed, and the remaining spacers may then be used to pattern the fin 255. In some embodiments, the mask (or other layer) may remain on the fin 255.

[0082] exist Fig. 27 In the embodiment, a shallow trench isolation (STI) region 258 is formed adjacent to the fin 255. The STI region 258 can be formed by forming an insulating material (not shown separately) over the substrate 250 and between adjacent fins 255. The insulating material can be an oxide such as silicon oxide, a nitride, or the like, or a combination thereof, and can be formed by high-density plasma chemical vapor deposition (HDP-CVD), flowable CVD (FCVD) (e.g., CVD-based material deposition in a remote plasma system, and post-curing to convert the deposited material into another material, such as an oxide), or the like, or a combination thereof. Other insulating materials formed by any acceptable process can be used. In the illustrated embodiment, the insulating material is silicon oxide formed by an FCVD process. Once the insulating material is formed, an annealing process can be performed. In an embodiment, the insulating material is formed so that an excess of the insulating material covers the fin 255. The insulating material can include a single layer, or multiple layers can be used. For example, in some embodiments, a liner (not shown separately) can be first formed along the surface of the substrate 250 and the fin 255. Thereafter, a filling material such as discussed above can be formed over the liner.

[0083] Then, a removal process is applied to the insulating material to remove excess insulating material on the fin 255. In some embodiments, a planarization process such as chemical mechanical polishing (CMP), an etch-back process, a combination thereof, etc. may be used. The planarization process may planarize the insulating material and the fin 255. The planarization process exposes the fin 255 so that the top surfaces of the fin 255 and the insulating material are flush after the planarization process is completed.

[0084] The insulating material is then recessed to form STI regions 258, as shown. Fig. 27As shown. The insulating material is recessed so that the upper portions of the fins 255 and the substrate 250 protrude from between adjacent STI regions 258. In addition, the top surface of the STI region 258 can have a flat surface (as shown), a convex surface, a concave surface (e.g., a dished shape), or a combination thereof. The top surface of the STI region 258 can be formed to be flat, convex, and / or concave by appropriate etching. The STI region 258 can be recessed using an acceptable etching process, for example, an etching process that is selective to the material of the insulating material (e.g., etching the material of the insulating material at a faster rate than the material of the fins 255 and the substrate 250). For example, oxide removal using, for example, dilute hydrofluoric acid (dHF) acid can be used.

[0085] about Figure 25-27 The process described is only one example of how the fin 255 may be formed. In some embodiments, the fin 255 may be formed by an epitaxial growth process. For example, a dielectric layer may be formed over the top surface of the substrate 250, and a trench may be etched through the dielectric layer to expose the substrate 250 below. A homoepitaxial structure may be epitaxially grown in the trench, and the dielectric layer may be recessed such that the homoepitaxial structure protrudes from the dielectric layer to form the fin. Additionally, in some embodiments, a heteroepitaxial structure may be used for the fin 255. For example, Fig. 27 The fin 255 in the substrate 250 may be recessed, and a material different from the fin 255 may be epitaxially grown over the recessed fin 255. In such an embodiment, the fin 255 includes a recessed material, and an epitaxially grown material arranged over the recessed material. In another embodiment, a dielectric layer may be formed over the top surface of the substrate 250, and a trench may be etched through the dielectric layer. A heteroepitaxial structure may then be epitaxially grown in the trench using a material different from the substrate 250, and the dielectric layer may be recessed so that the heteroepitaxial structure protrudes from the dielectric layer to form the fin 255. In some embodiments in which a homoepitaxial structure or a heteroepitaxial structure is epitaxially grown, the epitaxially grown material may be in-situ doped during growth, which may eliminate previous and subsequent implants, but in-situ doping and implant doping may be used together.

[0086] In addition, it may be advantageous to epitaxially grow a different material in region 250N (eg, NMOS region) than in region 250P (eg, PMOS region). In various embodiments, the upper portion of fin 255 may be made of silicon germanium (SiGe). x Ge 1-x, where x can be in the range of 0 to 1), silicon carbide, pure or substantially pure germanium, III-V compound semiconductors, II-VI compound semiconductors, etc. For example, available materials for forming III-V compound semiconductors include, but are not limited to, indium arsenide, aluminum arsenide, gallium arsenide, indium phosphide, gallium nitride, indium gallium arsenide, indium aluminum arsenide, gallium antimonide, aluminum antimonide, aluminum phosphide, gallium phosphide, etc.

[0087] Further in Fig. 27 In the embodiment of the present invention, appropriate wells (not separately shown) may be formed in the fin 255 and / or the substrate 250. In some embodiments, a P-well may be formed in the region 250N, and an N-well may be formed in the region 250P. In some embodiments, a P-well or an N-well is formed in both the region 250N and the region 250P.

[0088] In embodiments with different well types, a photoresist or other mask (not shown separately) may be used to implement different implantation steps for region 250N and region 250P. For example, a photoresist may be formed over the fin 255 and STI region 258 in region 250N. The photoresist is patterned to expose region 50P of substrate 250, for example, a PMOS region. The photoresist may be formed using a spin coating technique and may be patterned using acceptable photolithography techniques. Once the photoresist is patterned, an n-type impurity implantation is performed in region 250P, and the photoresist may be used as a mask to substantially prevent n-type impurities from being implanted into region 250N, for example, an NMOS region. The n-type impurity may be phosphorus, arsenic, antimony, etc., implanted into the region at a concentration equal to or less than 1×10 18 Atom / cm 3 , for example, at about 1×10 16 Atom / cm 3 and about 1×10 18 Atom / cm 3 After implantation, the photoresist is removed, for example, by an acceptable ashing process.

[0089] After the implantation of region 250P, a photoresist is formed over the fin 255 and STI region 258 in region 250P. The photoresist is patterned to expose region 250N of substrate 250, for example, an NMOS region. The photoresist may be formed using a spin coating technique and may be patterned using an acceptable photolithography technique. Once the photoresist is patterned, a p-type impurity implantation may be performed in region 250N, and the photoresist may be used as a mask to substantially prevent the p-type impurity from being implanted into region 250P, for example, a PMOS region. The p-type impurity may be boron, boron fluoride, indium, etc., implanted into the region at a concentration equal to or less than 1×10 18Atom / cm 3 , for example, at about 1×10 16 Atom / cm 3 and about 1×10 18 Atom / cm 3 After implantation, the photoresist may be removed, for example, by an acceptable ashing process.

[0090] After implantation of regions 250N and 250P, annealing may be performed to repair implant damage and activate the implanted p-type and / or n-type impurities. In some embodiments, the growth material of the epitaxial fins may be in-situ doped during growth, which may eliminate implantation, but in-situ doping and implantation doping may be used together.

[0091] exist Fig.28 In the embodiment of the present invention, a dummy dielectric layer 260 is formed on the fin 255 and the substrate 250. The dummy dielectric layer 260 may be, for example, silicon oxide, silicon nitride, a combination thereof, etc., and may be deposited or thermally grown according to an acceptable technique. A dummy gate layer 260 is formed on the dummy dielectric layer 260, and a mask layer 264 is formed on the dummy gate layer 262. The dummy gate layer 262 may be deposited on the dummy dielectric layer 260, and then planarized, for example, by a process such as implantation CMP. The mask layer 264 may be deposited on the dummy gate layer 262. The dummy gate layer 262 may be a conductive material or a non-conductive material, and may be selected from the group consisting of amorphous silicon, polycrystalline silicon (polysilicon), polycrystalline silicon germanium (poly-SiGe), metal nitride, metal silicide, metal oxide, and metal. The dummy gate layer 262 may be deposited by physical vapor deposition (PVD), CVD, sputtering deposition, or other known and in the art techniques for depositing selected materials. The dummy gate layer 262 may be made of other materials with high etching selectivity relative to the material of the STI region 258. The mask layer 264 may include, for example, silicon nitride, silicon oxynitride, etc. In this example, a single dummy gate layer 262 and a single mask layer 264 are formed across the region 250N and the region 250P. Note that the dummy dielectric layer 260 is shown as covering only the fin 255 and the substrate 250 for illustration purposes only. In some embodiments, the dummy dielectric layer 260 may be deposited such that the dummy dielectric layer 260 covers the STI region 258 and extends between the dummy gate layer 262 and the STI region 258.

[0092] FIG. 29A to FIG. 41B Various additional steps in the fabrication of example devices are shown. FIG. 29B to FIG. 41B Features in region 250N or region 250P are shown. For example, FIG. 29B to FIG. 41BThe structure shown may apply to both region 250N and region 250P. Differences in the structure of region 250N and region 250P, if any, are described in the text accompanying each figure.

[0093] exist Fig.29A and Fig.29B In the embodiment, the mask layer 264 (see Fig.28 ) is patterned to form a mask 274. The pattern of the mask 274 can be transferred to the dummy gate layer 262 using an acceptable etching technique to form a dummy gate 272. In some embodiments, the pattern of the mask 274 can also be transferred to the dummy dielectric layer 260. The dummy gate 272 covers the corresponding channel region 268 of the fin 255. The pattern of the mask 274 can be used to physically separate each dummy gate 272 from an adjacent dummy gate. The dummy gate 272 can also have a length direction that is substantially perpendicular to the length direction of the corresponding epitaxial fin 255.

[0094] exist Fig. 30A and Fig. 30B in Fig.29A and Fig.29B A first spacer layer 280 and a second spacer layer 282 are formed over the structure shown. Fig. 30A and Fig. 30B In the embodiment, the first spacer layer 280 is formed on the top surface of the STI region 258, the top surface and sidewalls of the fin 255 and the mask 274, and the sidewalls of the dummy gate 272 and the dummy dielectric layer 260. The second spacer layer 282 is deposited on the first spacer layer 280. The first spacer layer 280 can be formed by thermal oxidation, or deposited by CVD, ALD, etc. The first spacer layer 280 can be formed of silicon oxide, silicon nitride, silicon oxynitride, etc. The second spacer layer 282 can be deposited by CVD, ALD, etc. The second spacer layer 282 can be formed of silicon oxide, silicon nitride, silicon oxynitride, etc.

[0095] exist Fig.31A and Fig.31B In the embodiment, the first spacer layer 280 and the second spacer layer 282 are etched to form the first spacer 281 and the second spacer 283. The first spacer layer 280 and the second spacer layer 282 may be etched using a suitable etching process, for example, an isotropic etching process (for example, a wet etching process), an anisotropic etching process (for example, a dry etching process), etc. Fig.31A As shown, the first spacer 281 and the second spacer 283 are disposed on the sidewalls of the fin 255. Fig.31BAs shown, the second spacer layer 282 may be removed from over the first spacer layer 280 adjacent to the mask 274 , the dummy gate 272 , and the dummy dielectric layer 260 , and the first spacer 281 is disposed on the sidewalls of the mask 274 , the dummy gate 272 , and the dummy dielectric layer 260 .

[0096] After forming the first spacer 281 and the second spacer 283, an implantation for lightly doped source / drain (LDD) regions (not shown separately) may be performed. In embodiments with different device types, similar to the above, Fig. 27 , a mask (e.g., a photoresist) may be formed over region 250N, leaving region 250P exposed, and impurities of an appropriate type (e.g., p-type) may be implanted into the exposed fins 255 and substrate 250 in region 250P. The mask may then be removed. Subsequently, a mask (e.g., a photoresist) may be formed over region 250P, leaving region 250N exposed, and impurities of an appropriate type (e.g., n-type) may be implanted into the exposed fins 255 and substrate 250 in region 250N. The mask may then be removed. The n-type impurity may be any of the n-type impurities discussed previously, and the p-type impurity may be any of the p-type impurities discussed previously. The lightly doped source / drain regions may have a doping capacity of approximately 1×10 15 Atom / cm 3 About 1×10 19 Atom / cm 3 Annealing can be used to repair implant damage and activate the implanted impurities.

[0097] Note that the above disclosure generally describes the process of forming spacers and LDD regions. Other processes and sequences may be used. For example, fewer or additional spacers may be used, a different sequence of steps may be used, for example, the first spacer 281 may be formed before forming the second spacer 283, additional spacers may be formed and removed, etc. In addition, different structures and steps may be used to form n-type devices and p-type devices.

[0098] exist Fig.32A and Fig.32B In the embodiment, a first groove 286 is formed in the fin 255 and the substrate 250. Fig.32AAs shown, the top surface of the STI region 258 can be flush with the top surface of the substrate 250. The substrate 250 can be etched so that the bottom surface of the first recess 286 is disposed above or below the top surface of the STI region 258. The first recess 286 can be formed by etching the fin 255 and the substrate 250 using an anisotropic etching process such as RIE, NBE, etc. During the etching process for forming the first recess 286, the first spacer 281, the second spacer 283, and the mask 274 mask portions of the fin 255 and the substrate 250. The first recess 286 can be formed using a single etching process or multiple etching processes. A timed etching process can be used to stop etching the first recess 286 after the first recess 286 reaches a desired depth.

[0099] exist Figures 33A-33C In the embodiment, an epitaxial source / drain region 292 is formed in the first recess 286 to apply stress on the channel region 268 of the fin 255, thereby improving performance. Fig.33B As shown, an epitaxial source / drain region 292 is formed in the first recess 286 so that each dummy gate 272 is disposed between a corresponding adjacent pair of epitaxial source / drain regions 292. The height H2 of the epitaxial source / drain region 292 is about 40 nm to about 60 nm, for example, about 50 nm. In some embodiments, the first spacer 281 is used to separate the epitaxial source / drain region 292 from the dummy gate 272 by an appropriate lateral distance so that the epitaxial source / drain region 292 does not short-circuit the gate of the resulting FinFET formed subsequently.

[0100] The epitaxial source / drain region 292 in the region 250N (e.g., NMOS region) can be formed by masking the region 250P (e.g., PMOS region). The epitaxial source / drain region 292 is then epitaxially grown in the first recess 286. The epitaxial source / drain region 292 may include any acceptable material, for example, a material suitable for an n-type FinFET. For example, if the fin 255 is silicon, the epitaxial source / drain region 292 may include a material that applies tensile strain to the fin 255, for example, silicon, silicon carbide, phosphorus-doped silicon carbide, silicon phosphorus, etc. The epitaxial source / drain region 292 may have a surface that protrudes from a corresponding surface of the fin 255 and may have a small facet.

[0101] The epitaxial source / drain regions 292 in the region 250P (e.g., a PMOS region) can be formed by masking the region 250N (e.g., an NMOS region). The epitaxial source / drain regions 292 are then epitaxially grown in the first recess 286. The epitaxial source / drain regions 292 can include any acceptable material, for example, a material suitable for a p-type FinFET. For example, if the fin 255 is silicon, the epitaxial source / drain regions 292 can include a material that applies compressive strain on the fin 255, such as silicon germanium, boron-doped silicon germanium, germanium, germanium tin, etc. The epitaxial source / drain regions 292 can also have surfaces that protrude from the corresponding surfaces of the fin 255 and can have small facets.

[0102] The epitaxial source / drain regions 292, fins 255, and / or substrate 250 may be implanted with dopants to form source / drain regions, similar to the process previously discussed for forming lightly doped source / drain regions, followed by annealing. In some embodiments, the epitaxial source / drain regions 292 may be doped with dopants in situ during growth. The impurity concentration of the source / drain regions may be about 1×10 19 Atom / cm 3 and about 1×10 21 Atom / cm 3 The n-type and / or p-type impurities used for the source / drain regions may be any of the impurities discussed previously.

[0103] As a result of the epitaxial process used to form epitaxial source / drain regions 292 in regions 250N and 250P, the top surfaces of epitaxial source / drain regions 292 have facets that extend laterally outward beyond the sidewalls of fins 255. In some embodiments, these facets cause adjacent epitaxial source / drain regions 292 of the same FinFET to merge, such as Fig.33A In other embodiments, adjacent epitaxial source / drain regions 292 remain separated after the epitaxial process is completed, such as Fig.33C As shown. Fig.33A and Fig.33C In the illustrated embodiment, the first spacer 281 can be formed to cover the portion of the sidewall of the fin 255 that extends over the STI region 258, thereby preventing epitaxial growth. In some other embodiments, the spacer etch used to form the first spacer 281 can be adjusted to remove the spacer material to allow the epitaxial growth area to extend to the surface of the STI region 258.

[0104] The epitaxial source / drain region 292 may include one or more semiconductor material layers. For example, the epitaxial source / drain region 292 may include a first semiconductor material layer 292A, a second semiconductor material layer 292B, and a third semiconductor material layer 292C. Any number of semiconductor material layers may be used for the epitaxial source / drain region 292. Each of the first semiconductor material layer 292A, the second semiconductor material layer 292B, and the third semiconductor material layer 292C may be formed of a different semiconductor material and may be doped to a different dopant concentration. In some embodiments, the first semiconductor material layer 292A may have a dopant concentration that is less than the second semiconductor material layer 292B and greater than the third semiconductor material layer 292C. In an embodiment in which the epitaxial source / drain region 292 includes three semiconductor material layers, the first semiconductor material layer 292A may be deposited, the second semiconductor material layer 292B may be deposited on the first semiconductor material layer 292A, and the third semiconductor material layer 292C may be deposited on the second semiconductor material layer 292B.

[0105] exist Figures 34A-34C In the embodiment, the first interlayer dielectric (ILD) 296 is deposited on Fig.29A , Fig.33B and Fig.33A On top of the structure shown ( Figures 30A-33C The process will not change Fig.29A 296). The first ILD 296 may be formed of a dielectric material and may be deposited by any suitable method such as CVD, plasma enhanced CVD (PECVD), or FCVD. The dielectric material may include phosphosilicate glass (PSG), borosilicate glass (BSG), boron-doped phosphosilicate glass (BPSG), undoped silicate glass (USG), etc. Other insulating materials formed by any acceptable process may be used. In some embodiments, a contact etch stop layer (CESL) 294 is disposed between the first ILD 296 and the epitaxial source / drain regions 292, the mask 274, and the first spacer 281. The CESL 294 may include a dielectric material having an etch rate different from that of the material of the first ILD 296 above, for example, silicon nitride, silicon oxide, silicon oxynitride, etc.

[0106] exist Figures 35A-35BIn the process, a planarization process such as CMP may be performed to make the top surface of the first ILD 296 flush with the top surface of the dummy gate 272 or the mask 274. The planarization process may also remove the mask 274 on the dummy gate 272, and the portion of the first spacer 281 along the sidewall of the mask 274. After the planarization process, the top surfaces of the dummy gate 272, the first spacer 281, and the first ILD 296 are flush. Therefore, the top surface of the dummy gate 272 is exposed through the first ILD 296. In some embodiments, the mask 274 may remain, in which case the planarization process makes the top surface of the first ILD 296 flush with the top surfaces of the mask 274 and the first spacer 281.

[0107] exist Fig.36A and Fig.36B In the embodiment of the present invention, the dummy gate 272 and the mask 274 (if present) are removed in the etching step(s) to form the second recess 298. The portion of the dummy dielectric layer 260 in the second recess 298 may also be removed. In some embodiments, only the dummy gate 272 is removed, and the dummy dielectric layer 260 remains and is exposed by the second recess 298. In some embodiments, the dummy dielectric layer 260 is removed from the second recess 298 in the first region of the die (e.g., the core logic region) and remains in the second recess 298 in the second region of the die (e.g., the input / output region). In some embodiments, the dummy gate 272 is removed by an anisotropic dry etching process. For example, the etching process may include a dry etching process using (one or more) reactive gases that selectively etches the dummy gate 272 at a faster rate than the first ILD 296 or the first spacer 281. Each second recess 298 exposes and / or covers the channel region 268 of the corresponding fin 255. Each channel region 268 is disposed between adjacent pairs of epitaxial source / drain regions 292. During removal, the dummy dielectric layer 260 may serve as an etch stop layer when etching the dummy gate 272. The dummy dielectric layer 260 may then be optionally removed after the dummy gate 272 is removed.

[0108] exist Fig.37A and Fig.37B, a gate dielectric layer 300 and a gate electrode 302 are formed for replacing the gate. The gate dielectric layer 300 is conformally deposited in the second groove 298, for example, on the top surface and sidewalls of the fin 255. The gate dielectric layer 300 may also be deposited on the top surfaces of the first ILD 296, the CESL 294, the first spacer 281, and the STI region 258. According to some embodiments, the gate dielectric layer 300 includes silicon oxide, silicon nitride, or multiple layers thereof. In some embodiments, the gate dielectric layer 300 includes a high-k dielectric material, and in these embodiments, the gate dielectric layer 300 may have a k value greater than about 7.0, and may include metal oxides or silicates of hafnium, aluminum, zirconium, lanthanum, manganese, barium, titanium, lead, and combinations thereof. The formation method of the gate dielectric layer 300 may include molecular beam deposition (MBD), ALD, PECVD, etc.

[0109] The gate electrode 302 is deposited on the gate dielectric layer 300 and fills the remaining portion of the second recess 298. The gate electrode 302 may include a metal-containing material, such as titanium nitride, titanium oxide, tantalum nitride, tantalum carbide, cobalt, ruthenium, aluminum, tungsten, combinations thereof, or multiple layers thereof. Fig.37A and Fig.37B 296 , a single layer gate electrode 302 is shown, but the gate electrode 302 may include any number of liner layers, any number of work function adjustment layers, and fill materials. After filling the second recess 298, a planarization process such as CMP may be performed to remove the material of the gate electrode 302 and the excess portion of the gate dielectric layer 300 that is above the top surface of the first ILD 296. The material of the gate electrode 302 and the remaining portion of the gate dielectric layer 300 thereby form a replacement gate of the resulting FinFET. The gate electrode 302 and the gate dielectric layer 300 may be collectively referred to as a "gate stack."

[0110] The formation of the gate dielectric layer 300 in the region 250N and the region 250P may occur simultaneously, such that the gate dielectric layer 300 in each region is formed of the same material, and the formation of the gate electrode 302 may occur simultaneously, such that the gate electrode 302 in each region is formed of the same material. In some embodiments, the gate dielectric layer 300 in each region may be formed by a different process, such that the gate dielectric layer 300 may be a different material, and / or the gate electrode 302 in each region may be formed by a different process, such that the gate electrode 302 may be a different material. When different processes are used, various masking steps may be used to mask and expose the appropriate regions.

[0111] exist Figure 38A-Figure 38C, a second ILD 306 is deposited over the first ILD 296. In some embodiments, the second ILD 306 is a flowable film formed by FCVD. In some embodiments, the second ILD 306 is formed of a dielectric material such as PSG, BSG, BPSG, USG, etc., and may be deposited by any suitable method such as CVD, PECVD, etc. According to some embodiments, before forming the second ILD 306, the gate stack (including the gate dielectric layer 300 and the corresponding overlying gate electrode 302) is recessed to form a groove directly above the gate stack and between the opposing portions of the first spacer 281. A gate mask 304 is filled in the groove, which includes one or more layers of dielectric material (e.g., silicon nitride, silicon oxynitride, etc.), and a planarization process is then performed to remove excess portions of the dielectric material extending over the first ILD 296. A gate contact (e.g., described below with respect to Fig.41A and Fig.41B A gate contact 314 is discussed to pass through the gate mask 304 to contact the top surface of the recessed gate electrode 302 .

[0112] exist Figures 39A-39C , the second ILD 306, the first ILD 296, and the CESL 294 are etched to form a third recess 308, which exposes the surface of the epitaxial source / drain region 292. The third recess 308 may be formed by etching using an anisotropic etching process (e.g., RIE, NBE, etc.). In some embodiments, the third recess 308 may be etched through the second ILD 306 and the first ILD 296 using a first etching process, and then may be etched through the CESL 294 using a second etching process. A mask (e.g., photoresist) may be formed over the second ILD 306 and patterned to mask portions of the second ILD 306 from the first etching process and the second etching process.

[0113] Further in Figures 39A-39C , a third spacer 310 is formed on the sidewalls of the third recess 308. A third spacer layer (not shown separately) may be formed on the top surfaces of the second ILD 306 and the epitaxial source / drain regions 292, and on the sidewalls of the second ILD 306, the first ILD 296, and the CESL 294. The third spacer layer may be formed by thermal oxidation, or deposited by CVD, ALD, etc. The third spacer layer may be formed of silicon oxide, silicon nitride, silicon oxynitride, etc. The third spacer layer may be etched using a suitable etching process such as anisotropic etching (e.g., a dry etching process) to form the third spacer 310. Figures 39A-39CAs shown, the third spacer 310 may remain on the sidewalls of the second ILD 306, the first ILD 296, and the CESL 294 in the third recess 308. The third spacer 310 may have a thickness from about 2 nm to about 5 nm, for example, about 3 nm, and may be used to protect the sidewalls of the second ILD 306, the first ILD 296, and the CESL 294 from subsequent etching performed on the epitaxial source / drain region 292. In some embodiments, the third spacer 310 may be formed of silicon nitride and may be used to prevent the subsequent formation of source / drain contacts (for example, as described below). Figures 40A-40C The source / drain contacts 312 discussed above) can be used to reduce leakage and can be used to improve the breakdown voltage (V bd ) reliability issues, thereby improving performance and reducing device defects.

[0114] Further in Figures 39A-39C , the epitaxial source / drain region 292 is etched to extend the third recess 308. The epitaxial source / drain region 292 may be etched by an anisotropic etching process such as RIE, NBE, etc. The epitaxial source / drain region 292 may be etched by an iterative etching process, wherein each iteration includes a third etching process followed by a fourth etching process. The third etching process and the fourth etching process may be different from the first etching process and the second etching process used to etch the first ILD 296, the second ILD 306, and the CESL 294. The iterative etching process may be repeated for 5 to 20 iterations, for example, 10 iterations. The iterative etching process may be repeated until the depth D5 of the third recess 308 below the top surface of the channel region 258 of the fin 255 is greater than about 13 nm or from about 8 nm to about 18 nm, for example, about 14 nm. The depth D6 of the third recess 308 below the top surface of the epitaxial source / drain region 292 can be greater than about 15 nm or from about 10 nm to about 20 nm, for example, about 15 nm. The ratio of the depth D6 of the third recess 308 to the height H2 of the epitaxial source / drain region 292 can be about 1:3 to about 1:2, for example, about 2:5. Etching the third recess 308 to the described depth reduces the source / drain contact formed subsequently (for example, as described below with reference to FIG. 1 ). Figures 40A-40C The distance between the source / drain contact 312 discussed above and the fin 255 reduces the source / drain contact resistance (R csd ), and improves the device performance of the FinFET. Etching the third groove 308 to too great a depth may affect the performance of the epitaxial source / drain region 292, reduce device performance and cause device defects. Fig.39A and Fig.39BAs shown, the sidewalls of the epitaxial source / drain regions 292 may abut against the sidewalls of the third spacer 310. In other embodiments (not separately shown), the third recess 308 may undercut the epitaxial source / drain regions 292 below the third spacer 310, similar to Fig. 21C and Fig.21D The embodiment shown.

[0115] Fig.39C FIG. 3 shows an outline of the third groove 308 according to some embodiments. Fig.39C In the illustrated embodiment, the sidewalls of the epitaxial source / drain region 292 adjacent to the third recess 308 may abut against the sidewalls of the third spacer 310. Portions of the sidewalls of the epitaxial source / drain region 292 adjacent to the third recess 308 may be substantially straight and may be sloped to rounded corners. Fig.39C As further shown in FIG. 3 , the third recess 308 may extend through the third semiconductor material layer 292C and partially through the second semiconductor material layer 292B. However, in some embodiments, the third recess 308 may extend partially through the third semiconductor material layer 292C; through the third semiconductor material layer 292C, through the second semiconductor material layer 292B, and partially through the first semiconductor material layer 292A, etc.

[0116] The third etching process may use a third etchant gas and a fourth etchant gas. The third etchant gas may include fluoromethane (CH3F), difluoromethane (CH2F2), etc., and the fourth etchant gas may include hydrogen (H2), etc. The flow rate of the third etchant gas may be about 10sccm to about 40sccm, for example, about 15sccm, and the flow rate of the fourth etchant gas may be about 150sccm to about 300sccm, for example, about 200sccm. The third etching process may be performed at a pressure of about 10mTorr to about 30mTorr (for example, about 15mTorr) and a temperature of about 30°C to about 60°C (for example, about 40°C). A plasma generator may be used at a power of about 150W to about 300W (for example, about 200W) to generate plasma from the third etchant gas and the fourth etchant gas. The substrate holder on which the substrate 50 is arranged during the third etching process may be biased with a voltage of about 200V to about 400V (for example, about 300V).

[0117] The fourth etching process may use a fifth etchant gas and a sixth etchant gas. The fifth etchant gas may include nitrogen (N2), argon (Ar), etc., and the sixth etchant gas may include hydrogen (H2), etc. The flow rate of the fifth etchant gas may be about 100 sccm to about 300 sccm, for example, about 150 sccm, and the flow rate of the sixth etchant gas may be about 150 sccm to about 300 sccm, for example, about 200 sccm. The fourth etching process may be performed at a pressure of about 10 mTorr to about 30 mTorr (for example, about 15 mTorr) and a temperature of about 30°C to about 60°C (for example, about 40°C). A plasma generator may be used at a power of about 100 W to about 300 W (for example, about 150 W) to generate plasma from the fifth etchant gas and the sixth etchant gas. The substrate holder on which the substrate 50 is arranged during the fourth etching process may be biased with a voltage of about 200 V to about 400 V (for example, about 250 V).

[0118] Etching the epitaxial source / drain region 292 using the third etching process may cause byproduct polymers to be formed at the bottom of the third recess 308 adjacent to the epitaxial source / drain region 292. The byproduct polymers may then be removed using a fourth etching process. The fourth etching process may be anisotropic and may remove byproduct polymers from the bottom surface of the third recess 308 at a higher rate than the second etching process, which removes byproduct polymers from the side surfaces of the third recess 308. Thus, the third etching process and the fourth etching process may be used to anisotropically etch the epitaxial source / drain region 292.

[0119] exist Figures 40A-40C In the third recess 308, a source / drain contact 312 is formed. The source / drain contact 312 is formed in the third recess 308. A liner such as a diffusion barrier layer, an adhesion layer, etc., and a conductive material are formed in the third recess 308. The liner may include titanium, titanium nitride, tantalum, tantalum nitride, etc. The liner may be deposited by a conformal deposition process, such as atomic layer deposition (ALD), chemical vapor deposition (CVD), physical vapor deposition (PVD), etc. In some embodiments, the liner may include an adhesion layer, and at least a portion of the adhesion layer may be processed to form a diffusion barrier layer. For example, a nitridation process may be performed on the adhesion layer, such as a nitrogen plasma process, to convert at least a portion of the adhesion layer into a diffusion barrier layer. In some embodiments, the adhesion layer may be completely converted so that no adhesion layer remains and the diffusion barrier layer is an adhesion / barrier layer. In some embodiments, a portion of the adhesion layer remains unconverted so that a portion of the adhesion layer remains and the diffusion barrier layer is on the adhesion layer.

[0120] A silicide region may be formed adjacent to epitaxial source / drain region 292 by reacting a portion of epitaxial source / drain region 292 adjacent to the liner with the liner. An anneal such as a rapid thermal anneal (RTA) may be performed to promote the reaction of epitaxial source / drain region 292 with the liner.

[0121] The conductive material may be copper, copper alloy, silver, gold, tungsten, cobalt, aluminum, nickel, etc. The conductive material may be deposited by ALD, CVD, PVD, etc. After forming the liner and the conductive material, a planarization process such as CMP may be performed to remove excess material from the surface of the second ILD 306. The remaining liner and conductive material form a source / drain contact 312 in the third recess 308. The source / drain contact 312 is physically and electrically coupled to the epitaxial source / drain region 292. Although the source / drain contact 312, the third spacer 310, and the epitaxial source / drain region 292 are shown as having the same Fig. 22B and Fig. 22C The source / drain contacts 112, the third spacer 110 and the epitaxial source / drain regions 92 shown in FIG. 1 have the same structure, but the source / drain contacts 312, the third spacer 310 and the epitaxial source / drain regions 292 may have Figures 21A-22F Any of the structures of source / drain contacts 112, third spacers 110, and epitaxial source / drain regions 92 as shown, or any other suitable structure.

[0122] The bottom surface of the source / drain contact 312 can be disposed below the top surface of the fin 255 by a distance D7 of about 8 nm to about 18 nm, for example, about 14 nm. The source / drain contact 312 can be laterally spaced from the fin 255 by a distance D8 of about 4 nm to about 8 nm, for example, about 6 nm. The bottom surface of the source / drain contact 312 can extend into the epitaxial source / drain region 292 to a depth D below the top surface of the epitaxial source / drain region 292. 10 , which may be greater than about 18 nm or from about 13 nm to about 23 nm, for example, about 18 nm. The depth D of the source / drain contact 312 10 The ratio of the height H2 of the epitaxial source / drain region 292 may be about 1:3 to about 1:2, for example, about 2:5. The epitaxial source / drain region 292 and the source / drain contact 312 are formed according to the ratio so that the source / drain contact resistance (R csd) while ensuring that enough material of the epitaxial source / drain region 292 remains to effectively function as a source / drain region. Etching the epitaxial source / drain region 292 to form the third recess 308 and forming the source / drain contact 312 in the third recess 308 reduces the distance between the source / drain contact 312 and the channel region 268 of the fin 255. For example, the maximum distance between any one of the fins 255 and the source / drain contact 312 can be about 4 nm to about 8 nm, for example, about 6 nm. This reduces the source / drain contact resistance (R csd ), thereby improving the device performance of the FinFET formed by the above method.

[0123] exist Fig.41A and Fig.41B , a gate contact 314 is formed. An opening for the gate contact 314 is formed through the second ILD 306 and the gate mask 304. The opening can be formed using acceptable photolithography and etching techniques. A liner such as a diffusion barrier layer, an adhesion layer, etc., and a conductive material are formed in the opening. The liner may include titanium, titanium nitride, tantalum, tantalum nitride, etc. The conductive material may be copper, a copper alloy, silver, gold, tungsten, cobalt, aluminum, nickel, etc. A planarization process such as CMP may be performed to remove excess material from the surface of the second ILD 306. The remaining liner and conductive material form a gate contact 314 in the opening. The gate contact 314 is physically and electrically coupled to the gate electrode 302. In different embodiments, the gate contact 314 may be formed simultaneously with the source / drain contact 312 by the same process, or may be formed by a different process and before or after the source / drain contact 312. Although shown as being formed in the same cross-section, it is understood that each of the source / drain contacts 312 and the gate contact 314 may be formed in different cross-sections, which may avoid shorting of the contacts.

[0124] As described above, etching the epitaxial source / drain regions 92 and the epitaxial source / drain regions 292, respectively, and forming the source / drain contacts 112 and the source / drain contacts 312 extending into the epitaxial source / drain regions 92 and the epitaxial source / drain regions 292, respectively, reduces the source / drain contact resistance (R csd ), which improves the device performance of NSFET and FinFET formed by the above method.

[0125] According to one embodiment, a semiconductor device includes: a semiconductor substrate; a first channel region, above the semiconductor substrate; a first gate stack, above the semiconductor substrate and surrounding four sides of the first channel region; a first epitaxial source / drain region, adjacent to the first gate stack and the first channel region; and a first source / drain contact, coupled to the first epitaxial source / drain region, the bottommost surface of the first source / drain contact extending below the topmost surface of the first channel region. In one embodiment, the bottommost surface of the first source / drain contact extends more than 15nm below the topmost surface of the first channel region. In one embodiment, the semiconductor device further includes: a second channel region, below the first channel region, the bottommost surface of the first source / drain contact extending below the topmost surface of the second channel region. In one embodiment, the first source / drain contact extends through a first interlayer dielectric, and a spacer separates the first source / drain contact from the first interlayer dielectric. In one embodiment, the topmost surface of the first epitaxial source / drain region is 10nm to 20nm above the bottommost surface of the first source / drain contact. In one embodiment, a bottommost surface of the first gate stack extends below a bottommost surface of the first source / drain contact.

[0126] According to another embodiment, a method includes: forming a gate stack above a semiconductor substrate; epitaxially growing a first source / drain region in the semiconductor substrate adjacent to the gate stack, the epitaxially growing the first source / drain region including epitaxially growing a first semiconductor material; epitaxially growing a second semiconductor material above the first semiconductor material; and epitaxially growing a third semiconductor material above the second semiconductor material, the atomic concentration of a dopant in the first semiconductor material being between the atomic concentration of a dopant in the third semiconductor material and the atomic concentration of a dopant in the second semiconductor material; etching the first source / drain region to form a first recess in the first source / drain region, the first recess extending through the third semiconductor material and partially through the second semiconductor material, the bottommost surface of the first recess being disposed above the bottommost surface of the second semiconductor material, etching the first source / drain region including iteratively etching the first source / drain region using a first etching process and a second etching process having an etchant different from the first etching process; and forming a first source / drain contact in the first recess, the first source / drain contact being coupled to the first source / drain region. In one embodiment, etching the first source / drain region using a first etching process includes generating a first plasma from fluoromethane (CH3F) and hydrogen (H2). In one embodiment, etching the first source / drain region using a second etching process includes generating a second plasma from nitrogen (N2) and hydrogen (H2). In one embodiment, the first etching process and the second etching process are repeated 5 to 20 iterations. In one embodiment, the first etching process etches the first source / drain region and forms polymer byproducts along the surface of the first source / drain region, and the second etching process etches the polymer byproducts. In one embodiment, the method further includes: forming an interlayer dielectric above the gate stack and the first source / drain region; and before etching the first source / drain region to form the first groove, etching the interlayer dielectric to form a second groove exposing the first source / drain region. In one embodiment, the first groove has straight sidewalls, and the distance between the opposite sidewalls of the first groove decreases from the top of the first groove to the bottommost surface of the first groove.

[0127] According to yet another embodiment, a semiconductor device includes: a fin on a semiconductor substrate; a gate stack on the fin; an epitaxial source / drain region on the fin adjacent to the gate stack; and a source / drain contact coupled to the epitaxial source / drain region, the bottommost surface of the source / drain contact extending to a first distance below the top surface of the fin, the ratio of the first distance to the height of the epitaxial source / drain region being 1:3 to 1:2. In one embodiment, the semiconductor device further includes: a gate spacer adjacent to the gate stack; and a first interlayer dielectric (ILD) surrounding the gate stack and the gate spacer, the top surface of the first ILD being flush with the top surfaces of the gate stack and the gate spacer, the source / drain contact extending through the first ILD. In one embodiment, the semiconductor device further includes: a second ILD on the first ILD, the source / drain contact extending through the second ILD. In one embodiment, the semiconductor device further includes: an ILD spacer separating the source / drain contact from the first ILD and the second ILD, the ILD spacer comprising silicon oxide, silicon nitride, or silicon oxynitride. In one embodiment, the bottommost surface of the source / drain contact extends to a distance in the range of 10 nm to 20 nm below the top surface of the epitaxial source / drain region. In one embodiment, the semiconductor device further comprises: a second fin above the semiconductor substrate; and a second epitaxial source / drain region above the second fin, the second epitaxial source / drain region being separate from the epitaxial source / drain region, the epitaxial source / drain contact being coupled to the second epitaxial source / drain region. In one embodiment, the epitaxial source / drain region is a merged epitaxial source / drain region above the fin and the third fin, and the second epitaxial source / drain region is a second merged epitaxial source / drain region above the second fin and the fourth fin.

[0128] The features of several embodiments are summarized above so that those skilled in the art can better understand the various aspects of the present disclosure. Those skilled in the art should understand that they can easily use the present disclosure as a basis for designing or modifying other processes and structures to achieve the same purpose of the embodiments introduced herein and / or achieve the same advantages of the embodiments introduced herein. Those skilled in the art should also recognize that such equivalent constructions do not depart from the spirit and scope of the present disclosure, and they can make various changes, substitutions and modifications herein without departing from the spirit and scope of the present disclosure.

[0129] Example 1. A semiconductor device comprising: a semiconductor substrate; a first channel region above the semiconductor substrate; a first gate stack above the semiconductor substrate and surrounding four sides of the first channel region; a first epitaxial source / drain region adjacent to the first gate stack and the first channel region; and a first source / drain contact coupled to the first epitaxial source / drain region, the bottommost surface of the first source / drain contact extending below the topmost surface of the first channel region.

[0130] Example 2. The semiconductor device of Example 1, wherein the bottommost surface of the first source / drain contact extends more than 15 nm below the topmost surface of the first channel region.

[0131] Example 3. The semiconductor device of Example 1, further comprising: a second channel region below the first channel region, wherein the bottommost surface of the first source / drain contact extends below a topmost surface of the second channel region.

[0132] Example 4. The semiconductor device of Example 1, wherein the first source / drain contact extends through a first interlayer dielectric, wherein a spacer separates the first source / drain contact from the first interlayer dielectric.

[0133] Example 5. The semiconductor device of Example 4, wherein a topmost surface of the first epitaxial source / drain region is 10 nm to 20 nm above the bottommost surface of the first source / drain contact.

[0134] Example 6. The semiconductor device of Example 1, wherein a bottommost surface of the first gate stack extends below the bottommost surface of the first source / drain contact.

[0135] Example 7. A method for forming a semiconductor device, comprising: forming a gate stack on a semiconductor substrate; epitaxially growing a first source / drain region in the semiconductor substrate adjacent to the gate stack, epitaxially growing the first source / drain region comprising: epitaxially growing a first semiconductor material; epitaxially growing a second semiconductor material on the first semiconductor material; and epitaxially growing a third semiconductor material on the second semiconductor material, wherein an atomic concentration of a dopant in the first semiconductor material is between an atomic concentration of a dopant in the third semiconductor material and an atomic concentration of a dopant in the second semiconductor material; etching the first source / drain region to form a first recess in the first source / drain region, wherein the first recess extends through the third semiconductor material and partially through the second semiconductor material, a bottommost surface of the first recess being disposed above a bottommost surface of the second semiconductor material, wherein etching the first source / drain region comprises iteratively etching the first source / drain region using a first etching process and a second etching process having an etchant different from the first etching process; and forming a first source / drain contact in the first recess, the first source / drain contact being coupled to the first source / drain region.

[0136] Example 8. The method of Example 7, wherein etching the first source / drain region using the first etching process includes generating a first plasma from fluoromethane (CH3F) and hydrogen (H2).

[0137] Example 9. The method of Example 8, wherein etching the first source / drain region using the second etching process includes generating a second plasma from nitrogen (N2) and hydrogen (H2).

[0138] Example 10. The method of Example 7, wherein the first etching process and the second etching process are repeated 5 to 20 iterations.

[0139] Example 11. The method of Example 7, wherein the first etching process etches the first source / drain region and forms polymer byproducts along a surface of the first source / drain region, wherein the second etching process etches the polymer byproducts.

[0140] Example 12. The method according to Example 7 further includes: forming an interlayer dielectric above the gate stack and the first source / drain region; and before etching the first source / drain region to form the first groove, etching the interlayer dielectric to form a second groove exposing the first source / drain region.

[0141] Example 13. The method of Example 7, wherein the first groove has straight sidewalls, wherein a distance between opposing sidewalls of the first groove decreases from a top of the first groove to the bottommost surface of the first groove.

[0142] Example 14. A semiconductor device comprising: a fin on a semiconductor substrate; a gate stack on the fin; an epitaxial source / drain region on the fin adjacent to the gate stack; and a source / drain contact coupled to the epitaxial source / drain region, wherein a bottommost surface of the source / drain contact extends to a first distance below a top surface of the fin, wherein a ratio of the first distance to a height of the epitaxial source / drain region is 1:3 to 1:2.

[0143] Example 15. The semiconductor device according to Example 14 further includes: a gate spacer adjacent to the gate stack; and a first interlayer dielectric (ILD) surrounding the gate stack and the gate spacer, the top surface of the first ILD being flush with the top surfaces of the gate stack and the gate spacer, and the source / drain contact extending through the first ILD.

[0144] Example 16 The semiconductor device of Example 15, further comprising: a second ILD, above the first ILD, the source / drain contacts extending through the second ILD.

[0145] Example 17 The semiconductor device of Example 16, further comprising: an ILD spacer separating the source / drain contacts from the first ILD and the second ILD, the ILD spacer comprising silicon oxide, silicon nitride, or silicon oxynitride.

[0146] Example 18. The semiconductor device of Example 14, wherein the bottommost surface of the source / drain contact extends to a distance in a range of 10 nm to 20 nm below a top surface of the epitaxial source / drain region.

[0147] Example 19. The semiconductor device according to Example 14 further includes: a second fin, above the semiconductor substrate; and a second epitaxial source / drain region, above the second fin, the second epitaxial source / drain region is separated from the epitaxial source / drain region, and the epitaxial source / drain contact is coupled to the second epitaxial source / drain region.

[0148] Example 20. A semiconductor device according to Example 19, wherein the epitaxial source / drain region is a merged epitaxial source / drain region over the fin and a third fin, and wherein the second epitaxial source / drain region is a second merged epitaxial source / drain region over the second fin and a fourth fin.

Claims

1. A semiconductor device, comprising: Semiconductor substrate; a first channel region, on the semiconductor substrate; a first gate stack on the semiconductor substrate and surrounding four sides of the first channel region; A first epitaxial source / drain region, adjacent to the first gate stack and the first channel region, the first epitaxial source / drain region comprising: a first semiconductor material; a second semiconductor material overlying the first semiconductor material; and a third semiconductor material overlying the second semiconductor material, wherein an atomic concentration of the dopant in the first semiconductor material is between an atomic concentration of the dopant in the third semiconductor material and an atomic concentration of the dopant in the second semiconductor material; and A first source / drain contact is coupled to the first epitaxial source / drain region, the first source / drain contact extends through the third semiconductor material and partially through the second semiconductor material, the bottommost surface of the first source / drain contact is arranged above the bottommost surface of the second semiconductor material, and the bottommost surface of the first source / drain contact extends below the topmost surface of the first channel region. 2 . The semiconductor device of claim 1 , wherein the bottommost surface of the first source / drain contact extends more than 15 nm below the topmost surface of the first channel region.

3. The semiconductor device according to claim 1, further comprising: A second channel region is below the first channel region, wherein the bottommost surface of the first source / drain contact extends below a topmost surface of the second channel region. 4 . The semiconductor device of claim 1 , wherein the first source / drain contact extends through a first interlayer dielectric, wherein a spacer separates the first source / drain contact from the first interlayer dielectric. 5 . The semiconductor device of claim 4 , wherein a topmost surface of the first epitaxial source / drain region is 10 nm to 20 nm above the bottommost surface of the first source / drain contact. 6 . The semiconductor device of claim 1 , wherein a bottommost surface of the first gate stack extends below the bottommost surface of the first source / drain contact.

7. A method for forming a semiconductor device, comprising: forming a gate stack on a semiconductor substrate; Epitaxially growing a first source / drain region in the semiconductor substrate adjacent to the gate stack, wherein the epitaxially growing the first source / drain region comprises: epitaxially growing a first semiconductor material; epitaxially growing a second semiconductor material on the first semiconductor material; and epitaxially growing a third semiconductor material on the second semiconductor material, wherein an atomic concentration of a dopant in the first semiconductor material is between an atomic concentration of a dopant in the third semiconductor material and an atomic concentration of a dopant in the second semiconductor material; etching the first source / drain region to form a first recess in the first source / drain region, wherein the first recess extends through the third semiconductor material and partially through the second semiconductor material, a bottommost surface of the first recess being disposed above a bottommost surface of the second semiconductor material, wherein etching the first source / drain region comprises iteratively etching the first source / drain region using a first etching process and a second etching process having an etchant different from the first etching process; and A first source / drain contact is formed in the first recess, the first source / drain contact being coupled to the first source / drain region.

8. The method of claim 7, wherein etching the first source / drain region using the first etching process comprises generating a first plasma from fluoromethane (CH3F) and hydrogen (H2). 9 . The method of claim 8 , wherein etching the first source / drain region using the second etching process comprises generating a second plasma from nitrogen (N 2 ) and hydrogen (H 2 ). 10 . The method of claim 7 , wherein the first etching process and the second etching process are repeated 5 to 20 times.

11. The method of claim 7, wherein the first etching process etches the first source / drain region and forms polymer byproducts along surfaces of the first source / drain region, wherein the second etching process etches the polymer byproducts.

12. The method according to claim 7, further comprising: forming an interlayer dielectric over the gate stack and the first source / drain region; as well as Before etching the first source / drain region to form the first recess, the interlayer dielectric is etched to form a second recess exposing the first source / drain region.

13. The method of claim 7, wherein the first groove has straight sidewalls, wherein a distance between opposing sidewalls of the first groove decreases from a top of the first groove to the bottommost surface of the first groove.

14. A semiconductor device comprising: Fins, on top of a semiconductor substrate; a gate stack over the fin; An epitaxial source / drain region adjacent to the gate stack above the fin, the epitaxial source / drain region comprising: a first semiconductor material; a second semiconductor material overlying the first semiconductor material; and a third semiconductor material overlying the second semiconductor material, wherein an atomic concentration of the dopant in the first semiconductor material is between an atomic concentration of the dopant in the third semiconductor material and an atomic concentration of the dopant in the second semiconductor material; and A source / drain contact coupled to the epitaxial source / drain region, wherein the source / drain contact extends through the third semiconductor material and partially through the second semiconductor material, a bottommost surface of the source / drain contact is disposed above a bottommost surface of the second semiconductor material, and the bottommost surface of the source / drain contact extends a first distance below a top surface of the fin, wherein a ratio of the first distance to a height of the epitaxial source / drain region is 1:3 to 1:

2.

15. The semiconductor device according to claim 14, further comprising: a gate spacer adjacent to the gate stack; as well as A first interlayer dielectric ILD surrounds the gate stack and the gate spacer, a top surface of the first ILD is flush with top surfaces of the gate stack and the gate spacer, and the source / drain contacts extend through the first ILD.

16. The semiconductor device according to claim 15, further comprising: A second ILD is above the first ILD, and the source / drain contacts extend through the second ILD.

17. The semiconductor device according to claim 16, further comprising: An ILD spacer separates the source / drain contacts from the first ILD and the second ILD, wherein the ILD spacer comprises silicon oxide, silicon nitride, or silicon oxynitride. 18 . The semiconductor device of claim 14 , wherein the bottommost surface of the source / drain contact extends to a distance in the range of 10 nm to 20 nm below a top surface of the epitaxial source / drain region.

19. The semiconductor device according to claim 14, further comprising: a second fin on the semiconductor substrate; as well as A second epitaxial source / drain region is above the second fin, the second epitaxial source / drain region is separated from the epitaxial source / drain region, and the source / drain contact is coupled to the second epitaxial source / drain region.

20. The semiconductor device of claim 19, wherein the epitaxial source / drain region is a merged epitaxial source / drain region over the fin and a third fin, and wherein, The second epitaxial source / drain region is a second merged epitaxial source / drain region over the second and fourth fins.

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