Transistor device and method of forming a field plate in an elongated active trench of a transistor device

Abstract

Transistor devices and methods of forming a field plate in an elongate active trench of a transistor device. In embodiments, a method of forming a field plate in an elongate active trench of a transistor device is provided. The elongate active trench includes a first insulating material lining the elongate active trench and surrounding a gap, and a first conductive material filling the gap. The method includes selectively removing a first portion of the first insulating material using a first etching process, selectively removing a portion of the first conductive material using a second etching process and forming the field plate in a lower portion of the elongate active trench, and selectively removing a second portion of the first insulating material using a third etching process. The first etching process, the second etching process, and the third etching process are performed in that order.

Description

Background Technology

[0001] Transistors used in power electronics applications can be fabricated using silicon semiconductor materials. Common transistor devices for power applications include silicon CoolMOS®, silicon power MOSFETs, and silicon insulated-gate bipolar transistors (IGBTs). Transistor devices for power applications can be based on the charge compensation principle and can include an active cell field comprising multiple elongated trenches, each elongated trench including a field plate for charge compensation. Each trench and each mesa formed between adjacent trenches has an elongated strip-like structure. DE 102011054372 B4 discloses a method for fabricating a transistor structure comprising multiple trenches, the trenches including a field plate and a gate electrode located above the field plate in the trench. However, further improvements are desired to further enhance the reliability of these types of transistor devices. Summary of the Invention

[0002] In an embodiment, the transistor device includes a semiconductor substrate having a first main surface, a cell field, and an edge-terminating region laterally surrounding the cell field. The cell field includes a plurality of elongated active trenches extending from the first main surface into the semiconductor substrate, wherein a field plate and a gate electrode are located in each elongated active trench, the gate electrode being disposed above and electrically insulated from the field plate. The cell field also includes at least one elongated mesa, each mesa formed between adjacent elongated active trenches. The elongated mesa includes a drift region, a body region on the drift region, and a source region on the body region. The lower surface of the gate electrode is disposed at a position above the field plate at a depth d1 from the first main surface and at a position laterally adjacent to the field plate at a depth d2 from the first main surface, wherein d2 > d1 and d2 / d1 is in the range of 1.005:1 to 2:1.

[0003] In some embodiments, the lower surface of the gate electrode includes a profile containing a ridge formed between two grooves.

[0004] In some embodiments, the gate electrode is electrically insulated from the field plate by an insulating layer having a thickness d3 in the vertical direction above the field plate and a thickness d4 at an angle relative to the vertical direction, wherein d3 > d4 and d3 / d4 is in the range of 1.01:1 to 3:1.

[0005] In some embodiments, the elongated active trench includes a width w t ,in, Furthermore, the field plate has a width w fp ,in, .

[0006] In some embodiments, the depth d2 of the gate electrode is equal to the width w of the active elongation active trench 15. t The ratio between them can be in the range of 1:2 to 2:1, that is... .

[0007] In some embodiments, the edge termination region includes an edge termination structure comprising at least one elongated groove, the at least one elongated groove comprising an edge field plate. The edge field plate has a depth d located at a distance from the first main surface. efp The top surface of the active trench has a depth d at a distance from the first main surface. fp The top surface at the location and d efp <d fp ,in, and .

[0008] In some embodiments, the transistor device further includes a distance d extending from the first main surface into the gate electrode. c The gate contact, and It is at least 50 nm.

[0009] In one embodiment, a method is provided for forming a field plate in an extended active trench of a transistor device. The extended active trench includes a first insulating material lining the extended active trench and surrounding a gap, and a first conductive material filling the gap. The method includes selectively removing a first portion of the first insulating material using a first etching process, selectively removing a portion of the first conductive material using a second etching process and forming a field plate in the lower portion of the extended active trench, and selectively removing a second portion of the first insulating material using a third etching process. The first, second, and third etching processes are performed in this order.

[0010] In some embodiments, after the first etching process, the upper sidewalls of the elongated active trench remain covered by the first insulating material, and after the third etching process, the upper sidewalls of the elongated active trench are exposed from the first insulating material.

[0011] In some embodiments, selectively removing a first portion of the first insulating material using a first etching process includes forming a first recess in the first insulating material and an exposed portion of the first conductive material. The exposed portion of the first conductive material protrudes over the base of the first recess and is spaced apart from the sidewalls of the first recess. During a second etching process, at least the exposed portion of the first conductive material is removed such that the position of the top surface of the field plate relative to the first main surface is set.

[0012] In some embodiments, the method further includes removing a first portion of the first conductive material using an initial etching process prior to the first etching process. The initial etching process and a second etching process are used to position the top surface of the field plate relative to the first main surface.

[0013] In some embodiments, the first insulating material is also positioned on the first main surface. After the first etching process, the first main surface of the semiconductor substrate remains covered by the remaining portion of the first insulating material, and after the third etching process, the first main surface of the semiconductor substrate is exposed from the first insulating material.

[0014] In some embodiments, the method further includes insulating the field plate after a third etching process, forming a gate oxide on the sidewalls of the trench, and forming a gate electrode over the insulating field plate in the elongated active trench.

[0015] In some embodiments, insulating the field plate includes forming a second insulating material on the sidewalls of the trench and on the top and side surfaces of the exposed portion of the field plate, removing the second insulating material from at least the upper portion of the sidewalls of the trench and exposing the upper portion of the sidewalls of the trench, and forming a gate oxide on the second insulating material and on the sidewalls of the trench.

[0016] In some embodiments, a second insulating material is nonconformally deposited on the top and side surfaces of the exposed portion of the field plate. The second insulating material has a top surface with a profile including a ridge formed between two grooves. The base of the grooves may be located at a greater depth than the top surface of the field plate from the first main surface.

[0017] In some embodiments, the transistor device includes a cell field comprising a plurality of elongated active trenches and an edge termination region laterally surrounding the cell field and including at least one edge termination trench. The method further includes, in the edge termination region, using a single etch process to position the top surface of the edge field plate relative to the edge termination trench in the first main surface, the single etch process being a second etch process.

[0018] Those skilled in the art will recognize the additional features and advantages when reading the following detailed description and viewing the accompanying drawings. Attached Figure Description

[0019] The elements in the accompanying drawings are not necessarily proportional to each other. The same reference numerals denote corresponding similar parts. Features of the various illustrated embodiments can be combined unless they are mutually exclusive. Exemplary embodiments are described in the accompanying drawings and in detail in the following description.

[0020] Figure 1a A cross-sectional view of a portion of the cell field of a transistor device including elongated trenches is shown.

[0021] Figure 1b It shows Figure 1a An enlarged view of a portion of the trench in a transistor device.

[0022] Figure 1c It shows Figure 1b Enlarged cross-sections of different parts of the trench.

[0023] Figure 1d It shows Figure 1a A top view of a transistor device.

[0024] include Figures 2a to 2i Figure 2 illustrates a method for forming a field plate in an elongated active trench of a transistor device.

[0025] Figure 3 A flowchart illustrating a method for forming a field plate in an elongated active trench of a transistor device is shown. Detailed Implementation

[0026] In the following detailed description, reference is made to the accompanying drawings, which form a part of the detailed description and illustrate specific embodiments in which the invention can be practiced. In this regard, directional terms such as “top,” “bottom,” “front,” “rear,” “leading,” and “trailing” are used to refer to the orientation of the described drawings(s). Because components of the embodiments can be positioned in multiple different orientations, the directional terms are for illustrative purposes and are by no means limiting. It should be understood that other embodiments can be utilized, and structural or logical changes can be made without departing from the scope of the invention. The following detailed description should not be construed as limiting, and the scope of the invention is defined by the appended claims.

[0027] Several exemplary embodiments will now be explained. In this context, the same structural features are identified by the same or similar reference numerals in the accompanying drawings. In the context of this specification, "lateral" or "lateral direction" should be understood to mean a direction or extent that extends substantially parallel to the lateral extent of the semiconductor material or semiconductor carrier. Thus, the lateral direction extends substantially parallel to these surfaces or sides. In contrast, the term "vertical" or "vertical direction" is understood to mean a direction that extends substantially perpendicular to these surfaces or sides and therefore perpendicular to the lateral direction. Thus, the vertical direction extends in the thickness direction of the semiconductor material or semiconductor carrier.

[0028] As used in this specification, when an element such as a layer, region, or substrate is referred to as being "on" or "extending" "on" another element, it may be directly on or directly extending onto the other element, or there may be intermediate elements present. Conversely, when an element is referred to as being "directly on" another element or "directly" extending "on" another element, no intermediate elements are present.

[0029] As used in this specification, when an element is referred to as "connected" or "coupled" to another element, it can be directly connected or coupled to other elements, or intermediate elements may exist. Conversely, when an element is referred to as "directly connected" or "directly coupled" to another element, no intermediate elements exist.

[0030] As used herein, various device types and / or doped semiconductor regions may be identified as n-type or p-type, but this is merely for ease of description and not intended to be limiting, and such identification may be replaced by a more general description of “first conductivity type” or “second opposite conductivity type”, wherein the first type may be n-type or p-type and the second type may be p-type or n-type.

[0031] The accompanying diagram illustrates relative doping concentrations by indicating "-" or "+" next to the doping type "n" or "p". For example, "n-" means a lower doping concentration than the "n" doped region, while "n+" has a higher doping concentration than the "n" doped region. Doped regions with the same relative doping concentration do not necessarily have the same absolute doping concentration. For example, two different "n" doped regions can have the same or different absolute doping concentrations.

[0032] include Figures 1a to 1d Figure 1 shows a cross-sectional view and a top view of the transistor device 10, and in particular a portion of the cell field 11 of the transistor device 10.

[0033] The transistor device 10 includes a semiconductor substrate 12 having a first main surface 13. The semiconductor substrate 12 comprises silicon and may include an epitaxially deposited silicon layer, which may be formed on a separate silicon substrate or may be formed from single-crystal silicon, such as a single-crystal silicon wafer. The transistor device 10 includes a cell field 11 and an edge-terminating region 14 laterally surrounding the cell field 11, such as... Figure 1d This is what you see in the top view.

[0034] The cell field 11 provides the active region of the transistor device 10 and includes a plurality of elongated active trenches 15 extending from the first main surface 13 into the semiconductor substrate 12. Each trench 15 includes a sidewall 17 and a base 28. Typically, the elongated active trenches 15 extend substantially perpendicularly from the first main surface 13 into the semiconductor substrate 12, and each has the form of an elongation having a length l.t Width w t and depth d t The length of the extended active trench 15 extends to... Figures 1a to 1c The cross-sectional view shown is in the plane of the attached figure.

[0035] The unit field 11 also includes a plurality of elongated terraces 16, each terrace formed between adjacent elongated active trenches 15. Thus, each terrace 16 is defined by two sidewalls 17 of two adjacent elongated trenches 15 facing each other, and has a top surface formed by a first main surface 13. Each terrace 16 has an elongated strip structure extending to... Figures 1a to 1c The length in the plane of the accompanying cross-sectional view. The width of the platform 16 is determined by the spacing between the two sidewalls 17 of two adjacent elongated trenches 15 facing each other.

[0036] A field plate 18 and a gate electrode 19 are located in each elongated active trench 15. The gate electrode 19 is disposed above and electrically insulated from the field plate 18 within each trench 15. The field plate 18 and the gate electrode 19 are formed of a conductive material, each of which may be formed of polysilicon, for example. Each of the field plate 18 and the gate electrode 19 has an elongated structure having a length substantially corresponding to the length of the elongated active trench 15 and extending into the plane of the drawing.

[0037] Each of the elongated platforms 16 includes a drift region 20, a body region 21 on the drift region 20, and a source region 22 on the body region 21. The drift region 20 has a first conductivity type, the body region 21 has a second conductivity type opposite to the first conductivity type, and the source region 22 has a first conductivity type. For example, the first conductivity type may be n-type and the second conductivity type may be p-type.

[0038] The base 28 and sidewall 17 of each active trench 15 are lined with a thickness w i The insulating material 27. The gate electrode 19 is electrically insulated from the field plate 18 by an insulating layer 26 located between the lower surface 23 of the gate electrode 19 and the upper surface 30 of the field plate 18. The gate oxide 29 is located between the sidewall 17 of the elongated active trench 15 and the sidewall of the gate electrode 19, and the gate oxide 29 has a thickness less than that of the insulating material 28 located between the sidewall of the field plate 18 and the sidewall 17 of the elongated active trench 15.

[0039] The gate electrode 19 has a lower surface 23, which is not flat but has a profile including a ridge 24 formed between two elongated recesses 25. The gate electrode 19 has a lower surface 23 disposed above the field plate 18 at a depth d1 from the first main surface 13 and laterally adjacent to the field plate 18 at a depth d2 from the first main surface 13. The lower surface 23 of the gate electrode may be disposed at a depth d2 laterally adjacent to two opposite sides of the field plate 18. The depth d2 is greater than the depth d1, such that the ratio of depth d2 to d1 (d2 / d1) is in the range of 1.005:1 to 2:1, i.e. or d1 is the distance between the first main surface 13 and the ridge 24, and d2 is the distance between the first main surface 13 and the groove 25.

[0040] The width w of the extended active trench 15 t This can depend on the voltage class of the transistor device. In some embodiments, the elongated active trench 15 has a width w between 1400 nm and 1900 nm. t The field plate 18 can have a width w fp And w fp It can be located in the range of 175 nm to 325 nm. The width w of the extended active trench 15 is... t and the width w of the field plate 18 fp This particular combination can be used in transistor devices with a 120 V rating.

[0041] The depth d2 of the position of the lowest surface 23 of the gate electrode 19 from the first main surface 13 and the width w of the active elongated active trench 15 t The ratio between them can be in the range of 1:2 to 2:1, that is... .

[0042] The thickness of the insulating material 26 located between the lower surface 23 of the gate electrode 19 and the upper surface 30 of the field plate 18 spans the width w of the elongated active trench 15. t The thickness of the insulating material 26 varies at different locations along the length l of the trench 15. t The variation on the surface can be significantly smaller than the width w of the elongated active trench 15. t Changes in. For example, in Figure 1b and 1c As can be more easily seen in the enlarged cross-sectional view, the insulating layer 26 has a thickness d3 in the vertical direction above the field plate 15, perpendicular to the first main surface 13 of the semiconductor substrate 12 and the base 28 of the elongated active trench 15. The insulating layer 26 has a thickness d4 as an angle of inclination relative to the vertical direction, such as... Figure 1c As shown in the enlarged cross-sectional view, d4 is therefore less than d3, i.e., d4 < d3. In some embodiments, d3 / d4 is in the range of 1.9:1 to 3:1.

[0043] The first main surface 13 of the semiconductor substrate 12, and therefore the top surface of the platform 16, can be covered by an insulating layer 32. One or more additional insulating layers 33 can be disposed on top of the insulating layer 31. A metallization structure is located on the first main surface 13 of the transistor device 10, which provides source pads 35 and gate pads 36, which can... Figure 1d Seen in the top view.

[0044] Figure 1c A cross-sectional view of the location of the elongated active trench 15 is shown, in which the gate contact 31 to the gate electrode 19 can be seen in the upper part of the elongated active trench 15. The gate contact 31 is typically positioned toward one end of the elongated gate electrode 19 and one end of the elongated active trench 15, such that a single vertical via structure provides electrical connection to the elongated gate electrode 19.

[0045] The gate contact 31 may comprise one or more metals or alloys. The gate contact 31 may have a depth d from the first main surface 13 to the gate electrode 19. c The depth d of gate contact 31 c The value of dc may depend on the voltage level of the transistor device 10 and also on the depth d1 of the gate electrode 19. In some embodiments, dc may be in the range of 400 nm to 700 nm, for example for a transistor device with a voltage level of 120 V. For other types of voltage levels, such as transistor devices with voltage levels of 15 V or 20 V, dc may be smaller, for example, 150 nm to 200 nm.

[0046] like Figure 1a As shown, each platform 16 is provided with a source contact 34 in the form of a conductive via. The source contact 34 extends through insulating layers 32, 33 located on the first main surface 13 and has a base located in the body region 21 of each platform 16. The source contacts 34 in each platform 16 are electrically coupled to each other via source metallization to source pads 35 on the first main surface 13, which allows for… Figure 1d As seen in the top view. The transistor device 10 also includes a gate pad 36 on the first main surface 13, which is electrically coupled to the gate electrode 19 located in the active trench 15 via a gate contact 31 and a gate runner 37 extending between the gate contacts 31.

[0047] like Figure 1aAs shown, the transistor device 10 also includes a drain pad 38 located on a second main surface 39 of the semiconductor substrate 12 opposite to the first main surface 13. Therefore, the transistor device 10 is a vertical transistor device because it has a vertical drift path. The source pad 35, gate pad 36, and drain pad 38 can be formed of metal or alloy and can include one or two or more sublayers.

[0048] Now we will refer to including Figures 2a to 2i Figure 2 illustrates a method for forming a field plate in an extended active trench of a transistor device. This method can be used to manufacture, for example, the transistor device 10 shown in Figure 1, and the method is described with reference to that particular transistor device, but the use of this method is not limited to manufacturing that particular transistor structure.

[0049] Figure 2 shows a cross-sectional view of a semiconductor substrate 12 including a first main surface 13. The semiconductor substrate 12 may include a Si epitaxial layer or a single-crystal silicon wafer. The semiconductor substrate 12 is processed to form a transistor device 10 having a cell field 11 laterally surrounded by an edge-terminating region 14. The cell field 11 includes a plurality of elongated active trenches 15 and the edge-terminating region 14 includes one or more edge-terminating trenches 40. In Figure 2, two elongated active trenches 15 and one edge-terminating trench 40 are shown. The elongated active trenches 15 and the edge-terminating trench 40 extend from the first main surface 13 into the semiconductor substrate 12 and are defined by sidewalls 17 extending substantially perpendicular to the first main surface 13 and bases 28 extending between the sidewalls 17. The lengths of the trenches 15, 40 extend into the plane of the diagram in Figure 2.

[0050] Typically, the semiconductor substrate 12 is in the form of a semiconductor wafer, including a large number of device locations, each forming a transistor device 10. After the transistor devices 10 are fabricated at the wafer level, individual transistor devices 10 are singled out from the wafer.

[0051] The platform 16 is formed between two adjacent elongated active trenches 15 and has an elongated strip shape with a depth d corresponding to the elongated active trenches 15. t The height, and the length l corresponding to the elongated active trench 15 t The length of the platform 16 and the width of the platform 16 correspond to the spacing between the sidewalls 17 of two adjacent elongated active trenches 15 facing each other.

[0052] In some embodiments, the edge termination trench 40 has a depth d greater than that of the elongated active trench 15 in the unit field 11. t Greater depth d edge The width w of the edge termination groove 40 edgeThe width w can also be different from that of the elongated active trench 15. t And it can be wider.

[0053] refer to Figure 2a Each of the elongated active trenches 15 and edge-terminating trenches 40 is lined with a first insulating material 41. The first insulating material 41 also extends over the first main surface 13, and thus over the top surface of the terraces 16 formed between the elongated active trenches 15, forming a continuous layer. The first insulating material 41 surrounds a gap formed toward the center of each elongated active trench 15 and edge-terminating trench 40. This gap is filled with a conductive material 42, which extends to the uppermost surface 43 of the first insulating material 41 located on the first main surface 13. The first insulating material 41 may be silicon oxide and the conductive material 42 may be polycrystalline silicon.

[0054] In some embodiments, the first insulating material 41 comprises two sublayers of silicon oxide manufactured using different methods. For example, the first insulating material 41 may comprise a first sublayer formed by thermal oxidation of the semiconductor substrate 12 and a second sublayer formed on the first sublayer by a TEOS (tetraethyl orthosilicate) deposition process. After depositing the first insulating material 41 and the conductive material 42, a planarization process may be performed to form a planarized upper surface 43, wherein the conductive material 42 is coplanar with the first insulating material 41.

[0055] Figure 2b The diagram shows a semiconductor substrate 12 after an initial etching process has been performed to selectively remove some conductive material 42 from the upper region of the elongated active trench 15, resulting in an indentation 44 in the upper part of the active elongated trench 15 within a first insulating material 41. The indentation 44 has sidewalls formed by the first insulating material 41 located on the sidewalls 17 of the elongated active trench 15 and a base formed by the remaining portion of the conductive material 42. The base of the indentation 44 is located within the semiconductor substrate 12 at a depth from the first main surface 13. The first insulating material 41 remains on the first main surface 13 and forms a continuous layer.

[0056] Compared to the first insulating material 41, the conductive material 42 can be selectively removed from the elongated active trench 15 by an etching process such as, for example, a wet etching process. However, the conductive material 42' located in the edge-terminating trench 40 has not been removed, such that the conductive material 42' in the edge-terminating trench 40 is coplanar with the upper surface 43 of the first insulating layer 41. The edge-terminating trench 40 can be covered by a mask to prevent the removal of the conductive material 42' in the edge-terminating trench 40 during the initial etching process for removing the conductive material 42 from the elongated active trench 15.

[0057] The selectivity of the material of the conductive material 42 relative to the material of the first insulating material 41 can be, for example, at least about 100:1, or about 10:1 for dry etching.

[0058] like Figure 2c As shown, a first etching process is then performed to remove a portion of the first insulating material 41 from the upper part of the elongated active trench 15 and from the first main surface 13 of the semiconductor substrate 12. The first insulating material 41 can be selectively removed relative to the conductive material 42. A first recess 45 is formed in the insulating material 41 in the elongated active trench 15, having sidewalls 47 and a base 46.

[0059] The first etching process exposes a portion of the conductive material 42 from the first insulating material, which protrudes over the base 46 of the first recess 45 and is spaced apart from the sidewall 47 of the first recess 45. After the first etching process, the sidewall 17 of the active trench 15 and the first main surface 13 of the semiconductor substrate 12 remain covered by a portion of the first insulating layer 41. The first insulating material 41 retained on the sidewall 17 and base 28 of the elongated active trench 15 provides the field oxide 27 of the transistor device 10.

[0060] The first insulating material 41 is also selectively removed from the area above the edge termination trench 40, such that a portion of the conductive material 42' is exposed from the first insulating material 41 and protrudes above the remaining portion of the first insulating layer 41 in the edge termination trench 40.

[0061] For example, the first insulating layer 41 above the conductive materials 42, 42' can be selectively removed by wet etching. The material selectivity of the first insulating material 41 relative to the conductive material 42 can be at least about 100 to 1. The first insulating layer 41 may include silicon oxide and can be removed by wet etching. For example, after the first etching process, silicon oxide with a thickness of about 100 nm can remain on the first main surface 13 and sidewalls 17 in the upper part of the elongated active trench 15, forming a continuous layer.

[0062] refer to Figure 2d A second etching process is performed to selectively remove a portion of the first conductive material 42 to form a field plate 18 in the lower portion of the extended active trench 15. Following the first etching process in which a first portion of the first insulating layer 41 is removed, the remaining portion of the first insulating layer 41 can be used as a mask when the conductive material 42, 42' is removed not only from the extended active trench 15 but also from the edge-terminating trench 40. For example, the conductive material 42 is selectively removed over the first insulating layer 41 by wet etching. The selectivity of the material of the conductive material 42 relative to the material of the first insulating layer 27 can be approximately 100:1, or approximately 5:1 for dry etching.

[0063] After the second etching process, the upper surface 30 of the field plate 18 is located at a depth d from the first main surface 13. fp In place, and using as referenced Figure 2b The initial etching process for removing the first portion of the conductive material 42 is shown and as referenced. Figure 2d The depth is set by a combination of the second etching process shown, which removes the exposed portion of the conductive material 42.

[0064] like Figure 2c As shown, the first etching process, which removes the first insulating material 41 and forms the first recess 45, exposes a portion of the conductive material 42 protruding from the base 46 of the recess 45. The first etching process is performed between the initial etching process and the second etching process. Therefore, during the initial etching process, the etching solution only contacts the upper surface of the conductive material 42, as the sides of the conductive material 42 are in contact with the first insulating layer 41, such as... Figure 2b As shown in the diagram. Conversely, in situations such as... Figure 2d In the second etching process shown, the etching solution can come into contact with the sides and top surface of the exposed portion of the conductive material 42.

[0065] refer to Figure 2e The third etching process can be used to selectively remove a second portion of the first insulating layer 41, exposing the upper portion of the sidewall 17 of the elongated active trench 15 from the first insulating material 41. The conductive material 42 forming the field plate 18 protrudes from the remaining portion of the first insulating material 41 in the elongated active trench 15 because, except for the sidewall 47, the first insulating material 41 is removed from the base 46 of the first recess 45.

[0066] In some embodiments, the first main surface 13 may also be exposed from the first insulating material 41, such that the first insulating material 41 no longer forms a continuous layer. In some embodiments, the uppermost portion of the first insulating layer 41 located in the edge termination trench may also be removed, such that the conductive material 42' in the edge termination trench 40 protrudes above the top surface of the insulating material 41 retained in the edge termination trench 40.

[0067] Therefore, the first insulating material 41 is removed from the upper part of the sidewall 17 of the elongated active trench 15 using the first etching process and the third etching process, thereby performing a second etching process that selectively removes the conductive material 42 after the first etching process and before the third etching process.

[0068] For example, the first insulating material 41 on top of the conductive material 42 is selectively removed by wet etching. In the third etching process, the selectivity of the material of the first insulating material 41 relative to the material of the conductive material 42 can be approximately at least 100 to 1.

[0069] Therefore, the depth d of the upper surface 30 of the field plate 18 is set relative to the first main surface 13 through an initial selective removal process and a second etching process. fp In the initial selective removal process, conductive material 42 is selectively removed over the first insulating layer 41 to provide a field oxide. In the second etching process, conductive material 42 is selectively removed over the remaining portion of the first insulating layer 41. The first insulating material 41 is also removed in two stages by the first and third etching processes, such that at least at the uppermost portion of the trench 15, the sidewalls 17 of the trench 15 and the crystalline material of the semiconductor substrate 12 are exposed after the third etching process.

[0070] refer to Figure 2f A second insulating layer 50 is formed, which covers the exposed portions of the sidewall 17, the first main surface 13, and the exposed portions of the field plate 18 in the extended active trench 15, as well as the conductive material 42' forming the edge-terminating field plate 51 in the edge-terminating trench 40. The second insulating layer 50 can be formed as a continuous layer such that it also extends over the first insulating material 41 located in the trenches 15, 40, and can serve as a portion of the electrical insulation 26 between the field plate 18 and the gate electrode 19 to be formed in each extended active trench 15.

[0071] After the second removal process of the first insulating layer 41 in the third etching process, the freestanding conductive material forming the upper part of the field plate 18 can have an aspect ratio that can be up to a maximum of one.

[0072] Because the wet etching material contacts both the top and side surfaces of the exposed portion of the conductive material 42 during the third etching process, the conductive material 42 can be removed more isotopically, i.e., removed from both the top and side surfaces, resulting in a lower aspect ratio and greater stability of the remaining structure. This also allows the freestanding exposed portions to be more easily oxidized to form the second insulating layer 50 and the electrical insulation 26 between the field plate 18 and the subsequently formed gate electrode 19, and also results in a free-lying structure that is mechanically more stable than structures with a larger aspect ratio.

[0073] In some embodiments, the second insulating layer 50 has a greater thickness on the polycrystalline silicon material of the field plate 18 than on the silicon of the semiconductor substrate 12. In some embodiments, the second insulating layer 50 may be nonconformally formed on the top surface and side surfaces of the exposed portion of the field plate 18, such that the thickness of the second insulating layer 50 in the vertical direction is greater than the thickness of the second insulating layer 50 deposited on the side surfaces of the exposed portion of the field plate 18, the vertical direction being substantially perpendicular to the first main surface 13 and perpendicular to the length of the field plate 18. In some embodiments, the second insulating layer 50 may be conformally deposited on the top surface and side surfaces of the exposed portion of the field plate 18, such that the thickness of the second insulating layer 50 is substantially uniform.

[0074] After the second insulating layer 50 is formed, the second insulating layer 50 has a top surface having a profile 52 including a ridge 53 or a raised region formed between two recesses 54. The ridge 53 is formed vertically above the field plate 18, and the recesses 54 are formed laterally adjacent to the opposite sides of the field plate 18 within the extended active trench 15. In some embodiments, the base of the recess 54 is located at a greater depth than the top surface 30 of the field plate 18 from the first main surface 13.

[0075] refer to Figure 2g The second insulating layer 50 can then be removed to expose the sides 17 of the elongated active trench 15 in the upper portion. The second insulating material 50 can also be completely removed from the sidewalls in the upper portion of the edge-terminating trench 40. The second insulating layer 50 may be referred to as a sacrificial oxide.

[0076] In some embodiments, in addition to the top and side surfaces of the exposed portion of the field plate 18, a second insulating layer 50 is formed on the sidewalls 17 of the trench 15 and the top surface of the platform 16. The second insulating layer 50 may be formed of silicon oxide produced by thermal oxidation and may be referred to as POLOX. Compared to the sidewalls 17 and the first main surface 13 of the elongated active trench 15, this material is grown to a greater thickness on the top and side surfaces of the field plate 18 because the silicon material of the field plate 18 is more highly doped with the first conductivity type than the silicon material of the semiconductor substrate 12 that forms the sidewalls 17 of the elongated active trench 15 and also the top surface of the platform 16. Therefore, in reference Figure 2g After the second insulating layer 50 is removed from at least the upper part of the sidewall 17 of the trench 15 during the third etching process shown, a portion of the second insulating layer 50 located on the top and side surfaces of the field plate 18 can be retained due to the larger initial thickness.

[0077] In some embodiments, the field plate 18 remains covered by the remaining portion of the second insulating layer 50, such that the top surface 52 of the second insulating layer 50 has a profile including a ridge 53 formed above the field plate 18, the ridge 53 being defined by two recesses 54 located on either side of the field plate 18. This arrangement may result from a different thickness of the second insulating layer 50 on the polycrystalline silicon material of the field plate 18 compared to the first insulating material 41.

[0078] refer to Figure 2h Then, a third insulating layer 55 is formed on at least the exposed portion of the sidewall 17 of the elongated active trench 15 to form the gate oxide 29. In some embodiments, the third insulating layer 55 is formed as a continuous layer over the first main surface 13, the sidewall 17 of the elongated active trench 15, the second insulating layer 50 retained in the elongated active trench and the edge-terminating trench 40. The total thickness of the insulating material 26 located on the field plate 18 and insulating the field plate 18 from the gate electrode 19 may be formed by the remaining portions of the second and third insulating layers 50, 55.

[0079] refer to Figure 2i Then, conductive material for forming the gate electrode 19 is deposited into the active elongation active trench 15. The conductive material may be polysilicon or may be a metal or alloy. The lower surface 23 of the gate electrode 19 has a profile including a ridge 24 located between two recesses 25. The profile of the lower surface 23 of the gate electrode 19 conforms to the profile of the lower surface of the third insulating layer 55, and subsequently conforms to the profile of the lower surface of the second insulating layer 50 covering the field plate 18. The upper surface of the ridge 24 is located at a distance d1 from the first main surface 13, and the deepest point of the recess 25 is located at a distance d2 from the first main surface 13, where d2 is greater than d1.

[0080] In the edge termination region 14, the position d of the top surface 56 of the edge field plate 57 in the edge termination trench 40 is set relative to the first main surface 13 using a single etching process. efp This single etching process is the second etching process, and in the unit field 11, the position d of the top surface 30 of the field plate 18 is set relative to the first main surface 13 using the initial etching process and the second etching process. fp Therefore, the top surface 30 of the field plate 18 in the active trench 15 is located at a greater depth from the first main surface 13 than the top surface 56 of the conductive material 42' providing the edge field plate 57 in the edge termination trench 40, such that d fp >d efp .

[0081] In some embodiments, the upper surface of the gate electrode 19 may be located below the level of the first main surface 13, such that the minimum height of the gate electrode 19 is slightly less than d1. After depositing the conductive material of the gate electrode 19, a planarization process, such as chemical mechanical polishing, may be performed, followed by dry etching.

[0082] The method can continue by forming a body region 21 in the platform 16 by implanting a dopant of a second conductivity type, forming a source region 22 on the body region 21 by implanting a dopant of a first conductivity type, applying one or more insulating layers 32, 33 to the first main surface 13, forming conductive vias to form source contacts 34 and gate contacts 31, and forming subsequent metallization structures to electrically couple the source contacts 34 to source pads 35 and the gate contacts 31 to gate pads 36. A drain pad 38 can be formed on the second main surface 31 of the semiconductor substrate 12.

[0083] exist Figure 1a In this process, the insulating layer 32 can be a thermally grown oxide, which can have a thickness of approximately 15 nm. Figure 1b In this process, insulating layer 32 is a deposited oxide layer, such as a TEOS layer, which may have a thickness of about 250 nm.

[0084] In some embodiments, before applying the conductive layer to the back surface 39 to form the drain pad 38, the thickness of the substrate 12 is reduced by removing a portion of the back surface of the semiconductor substrate 12, for example by grinding and / or chemical mechanical polishing. In some embodiments, a drain region is formed in the semiconductor substrate 12 at or near the second main surface 39. This drain region is highly doped with a first conductivity type and is electrically connected to the drain pad 38.

[0085] Figure 3 A flowchart 100 is shown for a method of forming a field plate in an extended active trench of a transistor device. The extended active trench includes a first insulating material and a first conductive material, the first insulating material lining the extended active trench and surrounding a gap, and the first conductive material filling the gap.

[0086] In block 101, a first portion of the first insulating material is selectively removed, for example, using a first etching process. In block 102, a portion of the first conductive material is selectively removed, for example, using a second etching process, and a field plate is formed in the lower portion of the elongated active trench. In block 103, a second portion of the first insulating material is selectively removed, for example, using a third etching process. As shown in flowchart 100, the first, second, and third etching processes are performed in this sequence.

[0087] For ease of description, spatial relative terms such as "below," "under," "lower part," "above," "upper part," and the like are used to explain the positioning of one element relative to a second element. These terms are intended to cover different orientations of the device other than those depicted in the figures. Furthermore, terms such as "first," "second," and the like are also used to describe various elements, sections, parts, etc., and are not intended to be limiting. Throughout the specification, the same terms refer to the same elements.

[0088] As used herein, the terms “having,” “containing,” “comprising,” “including,” and the like are open-ended terms that indicate the presence of an element or feature described, but do not exclude additional elements or features. The articles “a,” “an,” and “the” are intended to include both plural and singular forms unless the context clearly indicates otherwise. It should be understood that, unless otherwise specifically indicated, features of the various embodiments described herein can be combined with each other.

[0089] Although specific embodiments have been shown and described herein, those skilled in the art will understand that various alternatives and / or equivalent implementations may be made in place of the specific embodiments shown and described without departing from the scope of the invention. This application is intended to cover any modifications or variations of the specific embodiments discussed herein. Therefore, the invention is intended to be limited only by the claims and their equivalents.

Claims

1. A transistor device, comprising: a semiconductor substrate having a first main surface, a cell field, and an edge termination region laterally surrounding the cell field, wherein the cell field comprises: a plurality of elongated active trenches extending into the semiconductor substrate from the first main surface, wherein a field plate and a gate electrode are located in each elongated active trench, the gate electrode being arranged above the field plate and electrically insulated therefrom, an elongated mesa, each elongated mesa being formed between adjacent elongated active trenches, wherein the elongated mesa comprises a drift region, a body region on the drift region, and a source region on the body region, wherein a lower surface of the gate electrode is arranged at a depth di from the first main surface at a location above the field plate and at a depth d2 from the first main surface at a location laterally adjacent to the field plate, wherein d2 > di and d2 / di is in a range of 1.005:1 to 2:1, wherein the edge termination region comprises at least one edge trench extending into the semiconductor substrate from the first main surface, wherein an edge field plate is located in the at least one edge trench, wherein the at least one edge trench extends deeper into the semiconductor substrate than the plurality of elongated active trenches.

2. The transistor device of claim 1, the lower surface of the gate electrode comprising a profile including a ridge formed between two grooves.

3. The transistor device of claim 1 or claim 2, wherein, the gate electrode is electrically insulated from the field plate by an insulating layer having a thickness d3 above the field plate in a vertical direction and a thickness d4 at an inclination angle with respect to the vertical direction, wherein d3 > d4 and d3 / d4 is in a range of 1.01:1 to 3:

1.

4. The transistor device according to one of claims 1 to 2, wherein The elongated active trench includes a width w t where 600 nm ≤ w t ≤ 3500 nm, and the field plate has a width w fp where 175 nm ≤ w fp ≤ 325 nm.

5. The transistor device according to one of claims 1 to 2, wherein, The edge termination region includes an edge termination structure including at least one elongated trench including an edge field plate, wherein the edge field plate has a top surface located at a depth d efp from the first major surface, and a field plate in the active trench has a top surface located at a depth d fp from the first major surface and d efp <d fp wherein 0 nm < d efp ≤ 1500 nm and 800 nm < d fp ≤ 1600 nm.

6. The transistor device according to one of claims 1 to 2, further comprising a distance d c a gate contact extending from the first main surface into the gate electrode, and d c - dl is at least 50 nm.

7. A method of forming a field plate in an elongated active trench of a transistor device, wherein, the elongated active trench comprises a first insulating material lining the elongated active trench and surrounding a gap and a first conductive material filling the gap, the method comprising: selectively removing a first portion of the first insulating material using a first etching process; selectively removing a portion of the first conductive material to form the field plate in a lower portion of the elongated active trench using a second etching process; and selectively removing a second portion of the first insulating material using a third etching process, wherein the first etching process is performed prior to the second etching process and the second etching process is performed prior to the third etching process, wherein the transistor device comprises a cell field comprising the plurality of elongated active trenches formed in the first main surface of the semiconductor substrate and an edge termination region laterally surrounding the cell field and comprising at least one edge termination trench, the method further comprising:

8. The method of claim 7, wherein, setting a position of a top surface of the edge field plate in the edge termination trench relative to the first main surface using a single etching process, the single etching process being the second etching process.

9. The method of claim 7, wherein, after the first etching process, sidewalls of an upper portion of the elongated active trench remain covered by the first insulating material, and wherein after the third etching process, the sidewalls of the upper portion of the elongated active trench are exposed from the first insulating material. selectively removing the first portion of the first insulating material using the first etching process comprises: forming a first recess in the first insulating material that exposes a portion of the first conductive material, wherein the exposed portion of the first conductive material protrudes above the base of the first recess and is spaced apart from the sidewall of the first recess, wherein the exposed portion of the first conductive material is at least partially removed during the second etching process such that the location of the top surface of the field plate is set.

10. The method of claim 7, further comprising: prior to the first etching process, removing a first portion of the first conductive material using an initial etching process, wherein the location of the top surface of the field plate is set using the initial etching process and the second etching process.

11. The method of claim 7, wherein, The first insulating material is also positioned on the first major surface of the semiconductor substrate in which the elongated active trench is formed, and after the first etching process, the first major surface of the semiconductor substrate remains covered by the remaining portion of the first insulating material, and wherein after the third etching process, the first major surface of the semiconductor substrate is exposed from the first insulating layer.

12. The method of claim 7, further comprising after the third etching process: insulating the field plate; forming a gate oxide on the sidewall of the trench; and forming a gate electrode in the elongated active trench over the insulated field plate.

13. The method of claim 12, wherein, insulating the field plate includes: forming a second insulating material on the sidewall of the trench and on the top surface and the sides of the exposed portion of the field plate; removing the second insulating material from at least the upper portion of the sidewall of the trench to expose the upper portion of the sidewall of the trench; and forming a gate oxide on the second insulating material and on the sidewall of the trench.

14. The method of claim 13, wherein, The elongated active trench is formed in the first major surface of the semiconductor substrate, wherein the second insulating material is deposited non-conformally on the top surface and the sides of the exposed portion of the field plate, wherein the second insulating material has a top surface having a profile including a ridge formed between two grooves, and wherein the base of the two grooves are located at a greater depth from the first major surface than the top surface of the field plate.

15. The method of claim 7, wherein, The first portion of the first insulating layer over the first conductive material is selectively removed by wet etching, and wherein the selectivity of the material of the first insulating material relative to the material of the first conductive material is at least 100 to 1.

16. The method of claim 7, wherein, The first recess is formed in the first insulating material by the first etching process, the first recess having a sidewall and a base, and wherein the first etching process exposes a portion of the first conductive material from the first insulating material, the portion protruding above the base of the first recess and being spaced apart from the sidewall of the first recess.

17. The method of claim 16, wherein, The second etching process removes the exposed portion of the first conductive material protruding above the base of the first recess and being spaced apart from the sidewall of the first recess, and wherein the remaining portion of the first insulating layer is used as a mask when the first conductive material is selectively removed during the second etching process.

18. A method of forming a field plate in an elongated active trench of a transistor device, wherein, The elongated active trench includes the first insulating material lining the elongated active trench and surrounding the gap and the first conductive material filling the gap, the method comprising: selectively removing a first portion of the first insulating material using the first etching process; after the first etching process, selectively removing a portion of the first conductive material to form the field plate in a lower portion of the elongated active trench using the second etching process; after the second etching process, a third etching process is used to selectively remove a second portion of the first insulating material; and after the third etching process: insulating the field plate; forming a gate oxide on the sidewalls of the trench; and forming a gate electrode over the insulating field plate in the elongated active trench, wherein insulating the field plate comprises: forming a second insulating material on the sidewalls of the trench and on the top surface and the sides of the exposed portion of the field plate; removing the second insulating material from at least an upper portion of the sidewalls of the trench to expose an upper portion of the sidewalls of the trench; and forming a gate oxide on the second insulating material and on the sidewalls of the trench.

19. The method of claim 18, wherein, The elongated active trench is formed in the first major surface of the semiconductor substrate, wherein the second insulating material is deposited non-conformally on the top surface and the sides of the exposed portion of the field plate, wherein the second insulating material has a top surface having a profile comprising a ridge formed between two grooves, and wherein the base of the two grooves is located at a greater depth from the first major surface than the top surface of the field plate.

20. The method of claim 18, wherein, The selectively removing a first portion of the first insulating material using the first etching process comprises: forming a first recess in the first insulating material that exposes a portion of the first conductive material, wherein the exposed portion of the first conductive material protrudes above the base of the first recess and is spaced apart from the sidewalls of the first recess, wherein the exposed portion of the first conductive material is at least partially removed during the second etching process such that the position of the top surface of the field plate is set.

21. The method of claim 18, further comprising: prior to the first etching process, removing a first portion of the first conductive material using an initial etching process, wherein the position of the top surface of the field plate is set using the initial etching process and the second etching process.

22. The method of claim 18, wherein, The first recess is formed in the first insulating material by the first etching process, the first recess having sidewalls and a base, and wherein the first etching process exposes a portion of the first conductive material from the first insulating material, the portion protruding above the base of the first recess and being spaced apart from the sidewalls of the first recess.

23. The method of claim 18, wherein, The second etching process removes the exposed portion of the first conductive material, the exposed portion protruding above the base of the first recess and being spaced apart from the sidewalls of the first recess, and wherein a remaining portion of the first insulating layer acts as a mask when the first conductive material is selectively removed during the second etching process.

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