Sampling switch circuit

Abstract

A sampling switch circuit includes: an input node connected to receive an input voltage signal to be sampled; a sampling transistor including a gate terminal, a source terminal and a drain terminal, the source terminal being connected to the input node; a voltage divider circuit connected to the input node and a tracking-control node to provide a tracking-control voltage signal at the tracking-control node that depends on the input voltage signal; a hold-control node connected to receive the hold-control voltage signal; an output node connected to the drain terminal of the sampling transistor; and a switching circuit system configured to connect the gate terminal of the sampling transistor to the tracking-control node or the hold-control node according to a clock signal.

Description

Technical Field

[0001] The present invention relates to a sampling switch circuit and a circuit system which can be referred to as a sampling circuit system. The sampling switch circuit according to the present invention can be referred to as a sample-and-hold circuit or a sample-and-hold switch circuit. Background Art

[0002] In general, voltage mode sampling and current mode sampling are known, and a sample-and-hold circuit may be considered an example of a voltage mode sampling circuit.The previously considered bootstrapping method will now be explored by way of introduction.

[0003] In a typical voltage-mode sampler, a sampling transistor, such as a field-effect transistor (FET), acts as a simple switch that is turned ON during the sampling (tracking) phase and turned OFF during the holding phase. The on-resistance of the device (sampling transistor) depends on the input voltage (e.g., the gate-source voltage in the case of a FET), which in turn produces harmonic distortion, i.e., distortion that is related to the input. In the case where the voltage-mode sampler is located at the front end of an analog-to-digital converter (ADC), the harmonic distortion may limit the dynamic range of the ADC.

[0004] The bootstrap circuit can be used to provide or apply a constant voltage on the gate-source of the switch (during the sampling phase or tracking phase) that is, at least in theory, independent of the input signal. This minimizes the input-dependent on-resistance variation of the sampling switch.

[0005] Figure 1 Figure 1 is a schematic diagram of the sampling switch circuit 1, which is used to fully understand the concept of bootstrapping. The input signal V IN Applied to the sampling switch M S Then, a voltage source V0 (e.g., a battery) is connected between the source and the gate (gate terminal) via a clock-controlled switch, so that during the tracking phase, the voltage V0+V IN Applied to the sampling switch M S The gate of the sampling capacitor C is connected to the ground (ground supply voltage) via another clock-controlled switch. S Connect to sampling switch M S The drain (drain terminal) of the sampling switch M S The drain of the circuit 1 serves as the output node, generating an output signal V at the output node. OUT . Sampling capacitor C S Connect between the drain and ground.

[0006] Typically, as shown, V0 = V DD , where VDD is the supply voltage, and this enables the device M S The maximum possible gate-source voltage is obtained on the MOSFET, resulting in the minimum on-resistance. Figure 1 In the example, CLK is of frequency f s The sampling clock (clock signal) of

[0007] The operation of circuit 1 is as follows. When CLK is high (and -CLK is low), sampling switch M S The gate of is connected to ground (ground supply voltage). The terms "high" and "low" may refer to voltage levels, such as digital voltage levels, for example, V DD voltage level and GND (0V) voltage level. Therefore, transistor M S The circuit 1 is in the state of sampling capacitor C S The sampled value (voltage) on V is held during the hold phase. When CLK is low (and -CLK is high), V IN +V DD is applied to the gate of the switch. Therefore, transistor M S turns on and circuit 1 enters tracking mode, and the sampling capacitor C S The voltage across the terminals tracks the input signal V IN Therefore, the gate-source voltage in tracking mode is V IN +V DD –V IN =V DD , that is, with the input signal V IN Not relevant.

[0008] Figure 2 The previously considered bootstrap circuit 10 is shown as a detailed implementation of the circuit 1, in which the voltage source V0 (in other words, Figure 1 The battery in the B accomplish.

[0009] The operation of circuit 10 is as follows.

[0010] When the sampling clock is high (ie, CLK=high), transistors M5 and M 5t Turn on, transistors M5 and M 5t The conduction makes the node G (i.e., the sampling switch M S The voltage at the gate of the sampling switch M S Turn off and start sampling capacitor C SThe sampled value on is held during the hold phase. During this phase (i.e., the hold phase), transistors M2 and M7 are also turned off. The clock signal "-CLK" (which is an inverted version of the clock signal CLK) is low (i.e., -CLK = low). This turns off transistor M6 and turns on transistor M8. This raises the voltage at node Z to the supply voltage, i.e., V DD Since node Z is now connected to V DD , so transistor M4 is off. At the same time, since the voltage at node G is at ground voltage (i.e., has the ground supply voltage), transistor M3 is on. Transistor M1 is also on (due to CLK=high). In this case, capacitor C B Connect to ground (GND) at its bottom plate and to V at its top plate DD Therefore, this is also called the pre-charge phase because the sample is held on the sampling capacitor C S When the capacitor C B is precharged to store voltage V DD .

[0011] When the sampling clock is low (ie, CLK = low), transistors M5 and M 5t is switched off and thus node G is disconnected from ground. Transistor M8 quickly turns off, and transistor M6 quickly turns on (-CLK = high) and connects node X (whose voltage level is at ground voltage at the beginning of this phase) to node Z, which in turn causes the voltage on node Z to rise from V DD This turns on transistor M4 and connects node Y to node G. In this case, the voltage on node G starts to rise (because node Y was charged to V during the precharge / hold phase). DD ). As the voltage on node G increases, transistors M2 and M7 begin to conduct (in other words, they turn on). This causes the voltage at nodes Z and X to increase toward the input signal V IN The voltage at node Y increases. At this time, the voltage at node Y increases to V DD +V IN (Because V DD is the capacitor C B The voltage (V DD +V IN ) is transmitted to node G (ie, sampling switch M S In this case, the gate-source voltage of the switch is V DD +V IN -V IN =V DD , the gate-source voltage is constant and proportional to the input signal V IN As mentioned above, this phase is called the tracking phase, during which the sampling switch MS is turned on, and the sampling capacitor C S The voltage across the terminals tracks the input signal V IN .

[0012] In addition, Figure 2 In the circuit, the voltage across the terminals of all switches (transistors) is always equal to or less than the supply voltage V DD This ensures stress-free operation of the transistor circuit system.

[0013] To better understand Figure 2 The speed of the bootstrap circuit in Figure 10 is analyzed in more detail during the precharge phase and in tracking mode.

[0014] Figure 3 is a schematic diagram of circuit 10 in which certain elements are highlighted (not shown in dashed form) and other elements are not highlighted (shown in dashed form) to aid in understanding the precharge / hold phase (when CLK=high).

[0015] As described previously, during this phase, capacitor C B is precharged to V through transistors M1 and M3 DD (i.e., for storing voltage V DD ). At the same time, M5 and M 5t M S The gate of the sampling transistor M is forced to ground and pushes S Enter the off state. Transistor M8 also keeps M4 in the off region. All other transistors are off, such as Figure 3 Indicated by grey in the figure.

[0016] First, the following time constant is used to convert Figure 3 Node G in the circuit is discharged to ground:

[0017] T 1，1 =(R on，M5 +R on，M5t )×C G (1)

[0018] Then, the capacitor C is B Charge:

[0019] T 1，2 =(R on，M1 +R on，M3 )×C B (2)

[0020] Among them, R on,M5 , R on,M5t , R on,M1and R on,M3 Respectively refer to devices M5, M 5t , the on-resistance of M1 and M3, and C G is the sum of all parasitic capacitances at node G:

[0021] C G =C gsS +C gdS +C db5t +C db4 +C gs3 +C gd3 +C gs2 +C gd2 +C gs7 +C gd7 (3)

[0022] Other transistor pairs M S The contribution of the gate capacitance can be seen in (3). The precharge time constant can be calculated as the sum of the two time constants calculated in (1) and (2):

[0023] T 预充电 =T 1，1 +T 1，2 (4)

[0024] Typically, the discharge of node G occurs much faster than the precharge (due to the switches M5 and M 5t The strength is relatively high). Therefore, (4) can be simplified as follows:

[0025] T 预充电 ~T 1，2 (5)

[0026] Figure 4A and Figure 4B is a schematic diagram of circuit 10 in which certain elements are highlighted (not shown in dashed lines) and other elements are not highlighted (shown in dashed lines) to aid understanding of the tracking phase (when CLK=low).

[0027] When the clock signal CLK goes low, transistor M6 quickly switches to conduction. This occurs with the following time constant:

[0028] T 2，1 =R on，M6 ×C Z (6)

[0029] Among them, R on,M6 is the on-resistance of device M6, and C Z is the total capacitance on node Z:

[0030] C Z =C gs4 +Cgd4 +C db6 +C db7 +C db8 (7)

[0031] Next, and when M4 is already turned on, C B The voltage level at the top plate of the MOSFET is precharged to the voltage level V DD ——The on-resistance of M4 appears at M S At the gate. V G (i.e., the voltage level at the gate node G) starts to increase, and once V G When the threshold voltage of M2 is reached, the transistor turns on and C B The bottom plate is connected to the input voltage V IN . After that, V X and V Y (i.e., the voltage at node X and the voltage at node Y) increases with a time constant of V IN :

[0032] T 2，2 =(R on，M2 +R on，M4 )×C G (8)

[0033] Among them, R on,M2 and R on,M4 are the on-resistances of devices M2 and M4 respectively.

[0034] Figure 4A and Figure 4B The time constant T 2,1 and T 2,2 During the bootstrap circuit 10.

[0035] The total tracking time constant can be calculated as:

[0036] T 跟踪 =T 2，1 +T 2，2 (9)

[0037] Therefore, the maximum sampling clock frequency can be calculated using the sum of the time constants calculated above as follows:

[0038] ω s，max =2π×f s，max =1 / (T 预充电 +T 跟踪 ) (10)

[0039] Due to C B Ratio of total parasitic capacitance C G and C Z is much larger, so (10) can be simplified to:

[0040] ω s，max =2π×f s，max ~1 / [(R on，M1 +R on，M3 )×C B ] (11)

[0041] In practice, several time constants are needed to achieve an appropriate settling time, depending on the required resolution. Therefore, the maximum sampling frequency is usually the estimated f in (11) s,max However, this is used to compare the speed of the embodiments of the present invention (described later) with Figure 2 A simple guideline for comparing the speed of the bootstrap structures of circuit 10 is shown in FIG.

[0042] It should be noted that the circuit 10 is Figure 4A The status shown in Figure 4B The transition of states shown in includes a time interval during which the voltage on node G rises above the threshold voltages of M2 and M7. This time interval acts like an intrinsic delay that ultimately slows down the operation of circuit 10.

[0043] The inventors also considered the above Figure 2 The circuit 10 in FIG. 1 is about the operation of ultra-high sampling frequency. In particular, in practice, the circuit 10 has the following three main problems that limit its maximum frequency operation.

[0044] First, there is a relatively large capacitor C B (acts as a battery during the tracking phase), capacitor C B It switches on / off (charges / discharges) at the same rate as the sampling frequency (as it does in the switching path). Since the charge is shared with the parasitic capacitor at node G (which occurs during the tracking phase), a relatively large capacitance value can be chosen for this capacitor so that it substantially maintains V DD voltage. This becomes very difficult as the sampling frequency increases, since a large capacitor then needs to be pre-charged and switched to the sampling switch M S on the gate-source.

[0045] Second, due to the large number of transistors (such as Figure 2 As shown in Figure 1, a lot of parasitic capacitance will be generated, so the number of transistors is very important at ultra-high sampling frequencies. Figure 2 In the example, for the sampling switch M S , there are nine devices (transistors) that can be designed to have the same S As explained above, the total capacitance at node G determines the capacitance of the sampling switch M. SThe time constant of the on / off state. S , M2, M3 and M7. Therefore, Figure 2 The bootstrap circuit 10 in the embodiment of the present invention handles approximately four times the number of sampling switches M. S of the gate capacitance (rather than just twice), which causes the time constant of the circuit to increase during the tracking phase.

[0046] Third, when the clock signal changes its state (from high to low or from low to high), transistors M5, M 5t , M1, M6 and M8 change their states quickly, while transistors M2, M3 and M7 change their states according to the voltage change on node G. This acts as an inherent delay in the structure where the states of the three devices do not change quickly with the clock signal. Increasing the area of ​​the device can reduce its on-resistance to make the time constant smaller. However, on the other hand, this will generate more parasitic capacitance, which will contribute to the parasitic capacitance C G / C Z And thus offset the lower on-resistance effect.

[0047] Therefore, with the above in mind, when pushing the sampling frequency toward higher frequencies, three destructive / failure mechanisms begin to emerge that can undermine high frequency operation of the circuit 10 as follows.

[0048] First, due to the relatively large time constant of the precharge time (see equation (2)), the capacitor C B Therefore, as the sampling frequency increases, the stored charge may decrease so that the capacitor C B The voltage across the terminals changes from V DD As mentioned above, this charge (and the resulting voltage) is the voltage that switches the sampling switch M S configuration is required at its maximum on-state (minimum on-resistance).

[0049] Secondly, the current stored in capacitor C B The charge on the capacitor (and the B The voltage generated across the two terminals is also used to turn M2 on. Therefore, as the sampling frequency increases, M2 will eventually only be partially turned on. As mentioned earlier, it is necessary to turn M2 on to make C B The bottom plate is V IN Thus, V is reconstructed on node G IN +V DD . This is the second failure mechanism.

[0050] The third failure mechanism is due to the voltage on node Z. As mentioned earlier, at the beginning of the tracking phase, the voltage on node Z increases from V DDThen, as transistor M7 turns on, the voltage rises to V IN As the sampling frequency increases (decreasing the clock period), the voltage at node Z drops to ground, but does not have enough time to rise toward V IN Increase.

[0051] Voltage-mode ADCs (with such a sampling switch circuit as a voltage-mode sampler front end) often use bootstrapping techniques to enhance the dynamic range of the converter. For networking applications, this can most likely be avoided due to the low-resolution nature of applications in this technology area. However, for 5G applications that require high speed and high resolution, as mentioned above, current bootstrapping techniques seem impractical.

[0052] It is desirable to address one or more of the above problems, and in particular, to provide a sampling switch circuit having improved performance, for example at higher operating speeds.It is desirable to provide an improved sampling switch circuit that can be used as a voltage mode sampler front end for an ADC, for example in direct RF applications. Summary of the invention

[0053] According to an embodiment of the first aspect of the present invention, there is provided a sampling switch circuit, comprising: an input node connected to receive an input voltage signal to be sampled; a sampling transistor comprising a gate terminal, a source terminal and a drain terminal, the source terminal being connected to the input node; a voltage divider circuit connected to the input node and a tracking-control node to provide a tracking-control voltage signal at the tracking-control node that depends on the input voltage signal; a hold-control node connected to receive the hold-control voltage signal; an output node connected to the drain terminal of the sampling transistor; and a switching circuit system configured to connect the gate terminal of the sampling transistor to the tracking-control node or the hold-control node according to a clock signal.

[0054] Such a sampling switch circuit may be referred to as, for example, a sampling circuit, a sampler circuit, a sampler front-end circuit, an ADC front-end circuit, a sample-and-hold circuit, or a sample-and-hold switch circuit. The voltage divider circuit provides a tracking-control voltage signal at least at a tracking-control node based on an input voltage signal, such that the tracking-control voltage signal may be used to control a sampling transistor (e.g., without requiring a capacitor such as Figure 2 C in the circuit system B when charging).

[0055] It will be appreciated that a connection herein may be a circuit connection, such as a conductive connection (and may include a DC (direct current) connection and / or an AC (alternating current) connection via a capacitor).A voltage provided at a node may be applied to or generated at the node.

[0056] The voltage divider circuit may be configured such that when the gate terminal of the sampling transistor is connected to the tracking-control node, the sampling transistor is turned on and the voltage at the drain terminal of the sampling transistor and / or at the output node tracks the voltage at the source terminal of the sampling transistor.

[0057] The sampling switch circuit may include a sampling capacitor connected to the output node, optionally connected between the output node and a ground supply node. Such a sampling capacitor may be used to maintain a voltage level at the output node. When the gate terminal of the sampling transistor is connected to the hold-control node, the sampling transistor may be turned off and the voltage at the drain terminal of the sampling transistor and / or the output node may be maintained or held at least temporarily.

[0058] The voltage divider circuit may be at least one of: an impedance circuit; a resistor circuit; a resistor network; a passive circuit; and a linear circuit. The resistor circuit / resistor network may include resistors (among other components) or its components may all be resistors.

[0059] The tracking-control voltage signal may have a tracking-control AC component defined at least by the input voltage signal and a tracking-control DC component defined at least by the voltage divider circuit. The voltage divider circuit may be configured to maintain the tracking-control voltage signal at the tracking-control node, wherein the tracking-control AC component is optionally maintained to be defined at least by the input voltage signal and the tracking-control DC component is maintained to be defined at least by the voltage divider circuit, the tracking-control voltage signal is optionally maintained as a continuous signal and is optionally independent of the clock signal.

[0060] The voltage divider circuit can be connected to the sampling node to provide a sampled voltage signal at the sampling node, the sampled voltage signal having a sampled AC component defined at least by the input voltage signal and a sampled DC component defined at least by the voltage divider circuit, the source terminal of the sampling transistor being connected to the sampling node and connected to the input node via the sampling node. The sampled voltage signal can represent the input voltage signal, for example (e.g., directly) being proportional to the input voltage signal. The voltage divider circuit can be configured to maintain the sampled voltage signal at the sampling node, optionally maintaining the sampled AC component to be defined at least by the input voltage signal and maintaining the sampled DC component to be defined at least by the voltage divider circuit, optionally maintaining the sampled voltage signal as a continuous signal and optionally being independent of the clock signal.

[0061] The voltage divider circuit may be configured such that the tracking-control DC component and the sampling DC component differ from each other in voltage level. The difference between the voltage level of the tracking-control DC component and the voltage level of the sampling DC component may be greater than or equal to a threshold voltage of the sampling transistor. When the gate terminal is connected to the tracking-control node, the difference between the voltage level of the tracking-control DC component and the voltage level of the sampling DC component may be sufficient to turn on the sampling transistor, optionally fully.

[0062] The voltage divider circuit may be connected to a first reference node and a second reference node, the first reference node being connected to receive a first reference voltage signal having a first reference DC component, and the second reference node being connected to receive a second reference voltage signal having a second reference DC component. The first reference DC component and the second reference DC component may be configured such that a difference between a voltage level of the tracking-controlling DC component and a voltage level of the sampling DC component is greater than or equal to a threshold voltage of the sampling transistor.

[0063] The first reference voltage signal and / or the second reference voltage signal may be a DC voltage signal. The first reference node may be connected to a voltage supply node, which may have a voltage different from (higher than) V DD The second reference node may be connected to a voltage supply node, such as a ground supply node or a voltage supply node having a voltage level different from the voltage level of the ground supply node.

[0064] The voltage divider may include a first impedance connected between the input node and the tracking-control node, a second impedance connected between the tracking-control node and the first reference node, a third impedance connected between the input node and the sampling node, and a fourth impedance connected between the sampling node and the second reference node.

[0065] The first to fourth impedances may be composed of resistors, may be resistors, or may include resistors.

[0066] The first impedance may be implemented as a resistor or a series connection of a resistor and a capacitor, or as a parallel connection of a resistor and a capacitor, or as a parallel connection of a parallel combination of impedances and a capacitor, the parallel combination of impedances including a parallel connection of a resistor and a capacitor.

[0067] The second impedance may be implemented as a resistor, or as a series connection of a resistor and an inductor.

[0068] The third impedance may be implemented as a resistor, or as a parallel connection of a resistor and a capacitor.

[0069] The fourth impedance may be implemented as a resistor, or as a series connection of a parallel combination of impedances and a resistor, the parallel combination of impedances comprising a parallel connection of a resistor and a capacitor, optionally wherein the parallel combination of impedances is connected to the second reference node.

[0070] The hold-control voltage signal may have a hold-control DC component, and the difference between the voltage level of the hold-control DC component and the voltage level of the sampling DC component may be less than the threshold voltage of the sampling transistor. When the gate terminal is connected to the hold-control node, the difference between the voltage level of the hold-control DC component and the voltage level of the sampling DC component may be sufficient to turn off the sampling transistor. The hold-control voltage signal may be a DC voltage signal. The hold-control voltage signal may be a ground supply signal. The hold-control node may be connected to a voltage supply node, such as a ground supply node.

[0071] The switching circuit system may include: a first switch connected between a gate terminal of the sampling transistor and a tracking-control node; and a second switch connected between a gate terminal of the sampling transistor and a holding-control node. The first switch and the second switch may be connected to be controlled by the clock signal so that when one of the two switches is turned on, the other switch is turned off. The first switch and the second switch may be implemented by transistors.

[0072] The first switch may be connected in series with a resistor between the gate terminal of the sampling transistor and the tracking-control node, optionally wherein the resistor is implemented by one or more transistors. The second switch may be connected in series with a resistor between the gate terminal of the sampling transistor and the holding-control node, optionally wherein the resistor is implemented by one or more transistors.

[0073] The sampling switch circuit can be configured to have multiple channels (each channel can correspond to a different phase of the multi-phase clock signal). Each channel can include its own sampling transistor, output node, switching circuit system and clock signal. For each channel, the source terminal of the sampling transistor can be connected to the input node, the output node can be connected to the drain terminal of the sampling transistor, and the switching circuit system can be configured to connect the gate terminal of the sampling transistor to the tracking-control node or the holding-control node according to the clock signal.

[0074] According to an embodiment of a second aspect of the present invention, a sampling switch circuit is provided, the sampling switch circuit comprising: a sampling switch transistor connected between an input node and an output node; a sampling capacitor connected between the output node and a ground node; a first transistor connected between a gate of the sampling switch transistor and an intermediate node; a second transistor arranged between the gate of the sampling switch transistor and the ground node; and a resistor circuit connected between an input node and a reference voltage node and configured to generate a voltage for driving the sampling switch transistor based on an input voltage and a reference voltage at the intermediate node, wherein a gate of the first transistor and a gate of the second transistor are respectively connected to a clock input node, so that the first transistor and the second transistor are alternately turned on and off.

[0075] According to an embodiment of the third aspect of the present invention, there is provided an analog-to-digital converter, the analog-to-digital converter comprising the sampling switch circuit according to the aforementioned first aspect or second aspect of the present invention.

[0076] According to an embodiment of the fourth aspect of the present invention, an integrated circuit system, such as an IC (integrated circuit) chip, is provided, which includes a sampling switch circuit according to the aforementioned first aspect or second aspect of the present invention or an analog-to-digital converter according to the aforementioned third aspect of the present invention. BRIEF DESCRIPTION OF THE DRAWINGS

[0077] Reference will now be made by way of example to the accompanying drawings, in which:

[0078] Figure 1 As shown above is a schematic diagram of the sampling switch circuit previously considered;

[0079] Figure 2 shows the previously considered bootstrap circuit as Figure 1 Detailed implementation of the circuit;

[0080] Figure 3 yes Figure 2 Schematic diagram of the circuit for understanding the pre-charge phase / hold phase;

[0081] Figure 4A and Figure 4B yes Figure 2 Schematic diagram of the circuit for understanding the tracking phase;

[0082] Figure 5 is a schematic diagram of a sampling switch circuit embodying the present invention;

[0083] Figure 6 Shown Figure 5 A simplified circuit model of the voltage at node A of the circuit in;

[0084] Figure 7 is with Figure 6 Equivalent schematic diagrams indicating AC (alternating current) power flow and DC (direct current) power flow;

[0085] Figure 8 Shown Figure 5 A simplified circuit model of the voltage on node B of the circuit in;

[0086] Fig. 9 Yes means Figure 5 A schematic diagram of a simplified circuit model focusing on its voltage divider circuit;

[0087] Fig.10 is with Fig. 9 A similar schematic diagram but with parasitic capacitance explicitly shown;

[0088] Fig.11 is with Figure 5 Equivalent but schematic diagrams indicating the corresponding power flows;

[0089] Fig.12 and Fig.13 It helps to better understand Figure 5 A schematic diagram of the equivalent circuit of the circuit;

[0090] Fig.14 is a schematic diagram of a sampling switch circuit embodying the present invention;

[0091] Fig.15 is a schematic diagram of a sampling switch circuit embodying the present invention;

[0092] Fig.16 is a schematic diagram of a sampling switch circuit embodying the present invention;

[0093] Fig.17 is a schematic diagram of a sampling switch circuit embodying the present invention;

[0094] Fig.18 is a schematic diagram of a sampling switch circuit embodying the present invention;

[0095] Fig.19 is a schematic diagram of a sampling switch circuit embodying the present invention;

[0096] Fig. 20 It is used to Figure 2 The operation of the circuit is Fig.18 a schematic diagram of a test bench for comparing the operation of the circuit;

[0097] Fig.21 It is shown Figure 2 The circuit and Fig.18 A graph showing the change in on-resistance of a circuit;

[0098] Fig. 22 It is shown Figure 2 The circuit and Fig.18 A graph of the effective bandwidth (EBW) of the sampling switch of the circuit;

[0099] Fig.23 is a schematic diagram of a sampling switch circuit embodying the present invention for simulation;

[0100] Fig.24 is with Fig.23 Schematic diagram of the corresponding clock signal;

[0101] Figure 25 to Figure 27 Node A ( Fig.25 ) and node G( Fig.26 ) and the waveform on Fig.23 The simulation of the circuit is concerned with the output of all four phases ( Fig. 27 );

[0102] Fig.28 Shown with Fig. 27 The corresponding FFT spectrum;

[0103] Fig.29 is a schematic diagram of an ADC embodying the present invention; and

[0104] Fig.30 is a schematic diagram of an integrated circuit system embodying the present invention. DETAILED DESCRIPTION

[0105] Embodiments of the present invention attempt to solve the above problems.

[0106] In particular, by outlining and reviewing Figure 2 4, in an embodiment, by removing the large capacitor C from the switching path B The precharge phase becomes unnecessary. By removing the precharge phase, the maximum operating frequency of the clock circuit is greatly increased. In addition, the state of the device (transistor) depends on the clock signal or input voltage, not on the sampling device M. S The voltage at the gate of the sampling switch M S The total capacitance at the gate of is also reduced (eg, by reducing the number of devices - transistors - connected to that node), which results in an enhancement (ie, reduction) of the tracking time constant.

[0107] Figure 51 is a schematic diagram of a sampling switch circuit 100 embodying the present invention. The sampling switch circuit 100 may be referred to as, for example, a sampling circuit, a sampler circuit, a sampler front-end circuit, an ADC front-end circuit, a sample-and-hold circuit, or a sample-and-hold switch circuit, and the present disclosure will be understood accordingly. Variations of the sampling switch circuit 100 that also embody the present invention will be considered later below. Compared to the sampling switch circuit 10, the need for a relatively large capacitor (i.e., C B ) and reduces the number of transistors.

[0108] The sampling switch circuit 100 includes an input node (labeled as V IN )、Sampling transistor (sampling switch) M S , potential divider circuit 110, tracking-control node (node ​​A), sampling node (node ​​B), holding-control node (node ​​C), switching circuit system 120 and output node (labeled as V OUT ).

[0109] The input node is connected to receive the input voltage signal V to be sampled IN . Sampling transistor M S The voltage divider circuit 110 is connected to the input node and the tracking-control node (node ​​A) to provide a voltage at the tracking-control node that depends on the input voltage signal V IN The holding-control node (node ​​C) is connected to receive the holding-control voltage signal, which in this case is a ground supply voltage signal. The switching circuit system 120 is configured to connect the gate terminal of the sampling transistor (or) to the tracking-control node (node ​​A) or the holding-control node (node ​​C) according to the (sampling) clock signal CLK.

[0110] exist Figure 5 In FIG. 1 , the voltage divider circuit 110 includes resistors R1 to R4 (in later variations, other components are provided). Resistor R1 is connected between the input node and node A. Resistor R2 is connected between node A and a first reference node (labeled V REF ), the first reference node is connected to receive the first reference signal V REF In this case, the first reference signal V REF is a DC (power supply) voltage signal (DC reference voltage), which can be assumed to have a voltage level higher than the (core) power supply voltage V DD The third resistor R3 is connected between the input node and the node B, and the node B is connected to the sampling transistor M SA fourth resistor R4 is connected between node B and a second reference node, the second reference node being connected to receive a second reference signal, which in this case is a ground supply voltage signal.

[0111] Therefore, the voltage divider circuit 110 is connected to the tracking-control node (node ​​A) to provide a tracking-control voltage signal having a voltage at least equal to the input voltage signal V IN The voltage divider circuit 110 is connected to the sampling node (node ​​B) to provide a sampled voltage signal at the node (node ​​B), the sampled voltage signal having a voltage component at least equal to the input voltage signal V IN The sampling transistor M S The source terminal of is connected to the sampling node (node ​​B) and is connected to the input node via the sampling node (node ​​B).

[0112] The switching circuit system 120 includes transistors M1 and M2, which act as switches of the switching circuit system 120 and are controlled by the clock signal CLK at their gate terminals. S between the gate terminal of M2 (labeled as node G′) and node A, and M2 is connected with its channel between node G′ and node C.

[0113] Transistor M S , M1 and M2 are shown as FETs, such as MOSFETs, where M S and M2 are NMOS (n-channel) devices, and M1 is a PMOS (p-channel) device. Therefore, when CLK is low, M1 connects node A to M S The gate node G' and the sampling switch M S is turned on (as explained below), and M2 connects node C to M when CLK is high. S The gate node G' and the sampling switch M S Shut down.

[0114] The output node is connected to the sampling transistor M S The drain terminal of the sampling capacitor C S Connect between the output node and ground.

[0115] To better understand the operation of circuit 100, the voltages at node A and node B will be considered in more detail.

[0116] First, the voltage on node A (tracking-controlling voltage signal) will be considered. Figure 6A simplified circuit model representing the voltage at node A of circuit 100 is shown. Figure 6 In, R eqA is seen at node A due to the switching activity of transistors M1, M2 and M S The gate capacitance on the G The equivalent resistance caused by this.

[0117] C' G =C gsS +C gdS +C db1 +C db2 (12)

[0118] At first glance, as seen in (12), the capacitance (C') at node G' G ) only involves M S The gate capacitance (which is the same as C in (3) G different).

[0119] Equivalent resistance R eqA It can be expressed as (approximately on average):

[0120] R eqA ~1 / (f s ×C' G ) (13)

[0121] Among them, f s is the sampling frequency (ie, the frequency of the CLK signal). Resistors R1 and R2 may advantageously be designed such that:

[0122] R eqA >>R1||R2 (14)

[0123] Here, >> is the symbol for "much larger" and || means parallel.

[0124] Equation (14) confirms that Figure 5 It is advantageous to make the resistance values ​​of resistors R1 and R2 small enough to allow sufficient AC power to flow from the input node and DC power to flow from the reference voltage toward node A. Figure 7 As schematically shown in Figure 7 and Figure 6 Equivalent but indicating AC power flow and DC power flow.

[0125] according to Figure 6 The circuit we have is:

[0126] V A =(g1 / ∑g A )×V IN +(g2 / ∑g A )×VREF (15)

[0127] Among them, g1=1 / R1, g2=1 / R2, g eqA =1 / R eqA ,and

[0128] ∑g A =g1+g2+g eqA (16)

[0129] You can Figure 8 The equivalent circuit shown is calculated Figure 5 The voltage on node B (sampling voltage signal), where R eqB is from the sampling switch M S The switching activity and capacitor C S Look at the equivalent impedance.

[0130] according to Figure 8 , the voltage at node B can be estimated as:

[0131] V B =g3 / (g3+∑g B )×V IN (17)

[0132] Among them, g3=1 / R3, g4=1 / R4, g eqB =1 / R eqB ,and

[0133] ∑g B =g4+g eqB (18)

[0134] During the tracking mode or tracking phase, the sampling switch M S The effective gate-source voltage V GS (i.e., V GS,MS ) can be calculated as the difference between the voltage at node A and the voltage at node B:

[0135] V GS，MS =V A -V B =(g1 / ∑g A -g3 / (g3+∑g B ))×V IN +(g2 / ∑g A )×V REF (19)

[0136] The same concept as the bootstrap switch is used, i.e., in order to have a linear sampling switch M S , the first term in (19) (i.e., the term that depends on the input signal) should be designed to be at least approximately equal to zero:

[0137] g1 / ∑g A -g3 / (g3+∑g B )=0 (20)

[0138] In this case, the gate-source voltage in (19) is reduced to (at least approximately):

[0139] V GS，MS =(g2 / ∑g A )×V REF (twenty one)

[0140] The gate-source voltage is constant and proportional to the input signal V IN Not relevant.

[0141] It should be noted that the combination Figures 5 to 8 , assuming the input signal V IN is assumed to be DC connected at the input node so that it applies both a DC component and an AC component. Thus, for example, assuming that equation (17) includes V IN , then equation (17) implicitly includes a DC component term. However, it is possible to pass the input signal V IN (ie, via a decoupling capacitor) AC connection.

[0142] From the perspective of input impedance matching, Figure 5 The circuit 100 also has advantages.

[0143] In particular, the voltage divider circuit 100 implemented as a resistor network or resistor circuit as previously described provides an equivalent input impedance that can be used for impedance matching in high speed applications. Fig. 9 , Fig. 9 is a schematic diagram showing a simplified circuit model representing circuit 100 with emphasis on voltage divider circuit 110 .

[0144] The equivalent input impedance Z seen at the input node IN can be calculated as:

[0145] Z IN =(R1+R2||R eqA )||(R3+R4||R eqB ) (twenty two)

[0146] As the input frequency (f in ) increases, that is, check the input signal V IN The frequency of the parasitic capacitance on node B (which is mainly due to the sampling switch M S The drain-to-body capacitance) intervenes or becomes dominant and reduces the effective impedance seen by node B.

[0147] refer to Fig.10 , Fig.10 is with Fig. 9 Similar but explicitly showing the parasitic capacitance C at node B p1 Considering the parasitic capacitance C at higher input frequencies p1 , the equivalent input impedance Z seen at the input node IN It can be calculated as:

[0148] Z IN =(R1+R2||R eqA )||(R3+R4||R eqB ||(1 / 2×π×f in ×C p1 )) (twenty three)

[0149] In order to account for reflections in the example design without losing any generality, it will be assumed in the example application that the resistors designed for the clock branch (i.e., R1+R2||R eqA ) is higher than the resistance seen from the signal path:

[0150] (R1+R2||R eqA )>>[R3+R4||R eqB ||(1 / 2×π×f in ×C p1 )] (twenty four)

[0151] This means

[0152] Z IN ~R3+R4||R eqB ||(1 / 2×π×f in ×C p1 )) (25)

[0153] At low input frequencies, the input impedance in (25) is reduced to:

[0154] Z IN，L ~R3+R4||R eqB (26)

[0155] At high input frequencies:

[0156] Z IN，H ~R3 (27)

[0157] At low input frequencies, the input impedance in (26) is designed to be equal to the characteristic impedance Z0 (e.g., 50 ohms) in the example application:

[0158] Z IN，L ~R3+R4||R eqB =Z0 (28)

[0159] In this case, at high input frequencies, the reflectance metric / reflection coefficient or S parameter S 11 It can be calculated as:

[0160] S 11 =20×log 10 (|Z IN，H -Z0| / (Z IN，H +Z0)) (29)

[0161] Substituting (27) and (28) into (29) yields:

[0162] S 11 =20×log 10 ((R4||R eqB ) / (2R3+R4||R eqB )) (30)

[0163] The interesting aspect of the voltage division between R3 and R4 is related to the reflection coefficient (i.e., S 11 If R4 is much larger than R3, most of the input power (V IN ) will pass through the sampling switch M S , but this will make S 11 On the other hand, according to (30), losing a part of the input power can help improve S 11 For example, in 5G applications, where the input signal from an LNA (low noise amplifier) ​​may produce a very large blocker (a high power signal in the same frequency range), this voltage division can actually help increase the linear range of the ADC (including circuit 100 in its front end) while also improving S 11 .

[0164] S calculated in (30) 11 The assumptions made in (24) are used. Therefore, S 11 It depends on the design and how the power flowing from the input node towards the clock path and sampling switch (i.e., signal path) is controlled. Fig.11 This concept is schematically shown in FIG. Fig.11 and Figure 5 Equivalent but indicates the corresponding power flow. Different designs require different output signal swings, S 11 , clock accuracy (and ultimately effective number of bits (ENOB), spurious-free dynamic range (SFDR) in ADC implementations), etc.

[0165] and Figure 2 Compared with the bootstrap circuit 10 of FIG. 1 , the speed of the circuit 100 will now be considered. In the circuit 100, the main capacitor in the clock path is the sampling switch M SThe gate capacitance (i.e., C' in (12) G ). On the other hand, in the bootstrap circuit 10, as described above, the capacitor C B In the clock path, C B Usually higher than C' G Much bigger.

[0166] During the tracking mode / tracking phase, Figure 5 In this case, the M1 in Fig.12 The equivalent circuit is calculated from the capacitance C' G Based on this circuit, the equivalent time constant can be calculated as follows:

[0167] T 跟踪，2 =(R on，M1 +R1||R2)×C' G (31)

[0168] Similarly, in the hold phase (no pre-charge phase), the Fig.13 Calculate the equivalent RC time constant.

[0169] T 保持，2 =R on，M2 ×C' G (32)

[0170] Similar to (10), the maximum sampling frequency can be calculated as:

[0171] ω s，max，2 =2π×f s，max，2 =1 / (T 保持，2 +T 跟踪，2 ) (33)

[0172] Substituting (31) and (32) into (33), we obtain:

[0173] ω s，max，2 =2π×f s，max，2 =1 / [(R on，M1 +R on，M2 +R1||R2)×C' G ] (34)

[0174] To compare the velocities of the two structures, divide (34) by (11) to obtain:

[0175] f s，max，2 / f s，max =[(R on，M1 +R on，M3 )×C B ] / [(R on，M1 +R on，M2 +R1||R2)×C'G ] (35)

[0176] according to Figure 7 and Fig.11 , resistors R1 and R2 are advantageously designed to be small enough to allow sufficient AC power to be shunted from the input node and flow toward the switch path. This means that R1||R2 will be small and of the same order of magnitude as the on-resistance of the device (transistor). For simplicity, as an example of a rule of thumb (without any loss of generality), assume that R1||R2 ~ R on , which means that (35) is reduced to:

[0177] f s，max，2 / f s，max ~[2R on ×C B ] / [3R on ×C' G ]=C B / (3C' G ) (36)

[0178] It is assumed that the on-resistance of all devices is also equal to R on As explained before, C B will be designed to be larger than C G On the other hand, C' G Even better than C G Small (compare (12) with (3)). Therefore, according to (36), the maximum sampling frequency of circuit 100 is much higher than that of bootstrap circuit 10.

[0179] It is expected that for the sampling switch M S The input signal has a well-defined common-mode voltage. Figure 5 This is the first reference signal V REF (DC reference voltage), a second reference signal (ground), and a DC current through resistors R1 to R4 of the voltage divider circuit 110. In this case, the common mode voltage can be calculated as:

[0180] V IN，CM ~[(R4||R eqB ) / (R2||R eqA +R1+R3+R4||R eqB )]×V REF (37)

[0181] exist Fig.14 As schematically shown in Figure 5 In another circuit arrangement 100A of a variation of the circuit 100, as shown, the reference voltage V applied as the second reference signal can be IN,CMAnd the decoupling capacitor C1 placed in series with the resistor R1 generates the common mode voltage. This can lead to a better defined common mode voltage but at the expense of adding the decoupling capacitor C1.

[0182] In such Fig.15 As an alternative to the circuit arrangement 100A, which is schematically shown in FIG. Figure 5 In another circuit arrangement 100B of a variation of the circuit 100, it is possible to Fig.15 Shown in Figure 5 A resistor R0 is added in series with the resistor R4 (between R4 and ground) in the structure of the circuit 100 of FIG. 100B to add another degree of freedom in the design of the common mode voltage. In the arrangement 100B, the resistor R0 is connected in parallel with a relatively large capacitor C0, so that in the equivalent AC model, Figure 5 That is, at high frequencies (of the input signal), capacitor C0 dominates and causes resistor R0 to be effectively bypassed.

[0183] Fig.16 is a schematic diagram of another circuit arrangement 100C configured to include multiple channels arranged for time interleaved operation. It should be understood that such a configuration may be used as a front end of a time interleaved ADC.

[0184] For simplicity, Figure 5 The circuit 100 has been used as a basis for an arrangement 100C, wherein the input node, nodes A and B, the first and second reference signal nodes, and the voltage divider circuit 110 are common to different channels (ie, shared between different channels).

[0185] Each channel then has its own transistors M1, M2, and M S , transistors M1, M2 and M S like Figure 5 and are controlled by their own clock signal CLK, and then these components are Figure 5 The channels are effectively connected in parallel as shown, each channel having its own output node and corresponding sampling capacitor C S The components in each channel are labeled accordingly to identify which of the n channels they are in. For example, CLK1 is the clock signal for channel 1, and CLK n is the clock signal for channel n. Similarly, M S,1 belongs to channel 1, and M S,n Belongs to channel n.

[0186] It should be understood that if the clock signals CLK1 to CLK nis a set of time-interleaved clock signals, then channels 1 to n will respond to the input signal V in a time-interleaved manner. IN That is, multiple sampling switches (M S,1 , M S,2 , ..., M S,n ) is driven by n clock circuits (switching circuit 120), and n clock circuits are driven by n sampling clocks (CLK1, CLK2, ..., CLK n ) drive. It can be seen that the circuit of four transistors per channel repeats itself according to the number of channels and all circuits are powered by node A.

[0187] Of course, although Figure 5 Circuit 100 is used as the basis for arrangement 100C, but it should be understood that any other single-channel arrangement disclosed herein (e.g., 100A or 100B described above, or 100D, 100E, or 100F described below) can be used as the basis for a multi-channel arrangement in a similar manner.

[0188] In order to use the sampling switch M S In order to maximize power (in other words, to minimize on-resistance), the gate-source voltage in (21) is preferably designed to be equal to the core supply voltage (i.e., V DD ):

[0189] V GS，MS =(g2 / ∑g A )×V REF =V DD (38)

[0190] This means that the reference voltage V REF It should preferably be designed so that:

[0191] V REF =∑g A ×V DD / g2 (39)

[0192] Substituting (38) into (15) yields:

[0193] V A =(g1 / ∑g A )×V IN +V DD (40)

[0194] This means that the voltage on node A will exceed the core supply voltage. In this case, Figure 5 Devices M1 and M2 will withstand more than V DD This can cause excessive stress on the transistor and shorten its useful life.

[0195] Fig.17 As Figure 5 100D is a schematic diagram of another circuit arrangement 100D of a variation of circuit 100, which is configured to address the overstress problem. Transistor M3 is added to protect M2 when CLK is low. This ensures that the drain voltage of M2 remains at V when it is turned off. DD Similarly, the transistor M p4 and transistor M n4 Added to this circuit to protect transistor M when CLK is high p1 , transistor M n1 . M p4 The gate and M n4 The gate is properly common-mode voltage V CM3,4 In addition, the DC voltage V is biased by resistor R5 and decoupling capacitor C1. CM1,2 Added to the sampling clocks (ie, CLK and -CLK). It should be noted that these capacitors are added only to AC couple the clock signal to the transmission gate M p1,n1 gate, and with Figure 2 Unlike the bootstrap circuit 10, they are not turned on / off in the circuit. All the voltages V CM1 To V CM4 In this example, both are DC voltages and can be obtained (e.g., via a voltage divider) from a reference voltage V REF generate.

[0196] Fig.17 The circuit 100D can also be used in conjunction with the previously described Fig.16 The time-interleaved structure shown in is equivalent to the time-interleaved structure.

[0197] It should be noted that when CLK is low, Fig.17 The transmission gate (i.e., transistor M p1,n1 and M p4,n4 ) has a fairly constant on-resistance. In this case, the circuit can be simplified.

[0198] Fig.18 As Figure 5 FIG. 1 is a schematic diagram of another circuit arrangement 100E of a variation of the circuit 100 , the circuit arrangement 100E being configured as a simplified version of the circuit arrangement 100D. Fig.18 In the circuit 100E, the gate of transistor M4 is connected to node B. In this case, when CLK is low, the sampling switch M S Similarly, the gate-source voltage on transistor M4 is constant. This eliminates the need for a transmission gate (such as Fig.17 M P4 and M n4 ) and DC voltage VCM3,4 needs.

[0199] Fig.18 The circuit 100E can also be used in conjunction with the previously mentioned Fig.16 The time-interleaved structure shown in is equivalent to the time-interleaved structure.

[0200] At high input frequencies, the pass through the sampling switch (via Fig.18 The amount of input signal power transmitted through the clock path (via node A) is reduced by the sampling circuit 100E. This limits the bandwidth of the sampling circuit 100E and ultimately the bandwidth of the ADC including the sampling circuit 100E.

[0201] Fig.19 As Fig.17 100D, which is configured to compensate for this bandwidth limitation. As shown, two capacitors (C2 and C3) have been added to Fig.17 (Similarly, they can be added to, for example, Figure 5 or Fig.18 C2 is connected in parallel with R1 and C3 is connected in parallel with R3. Inductor L1 is also added to the circuit structure, inductor L1 is connected in series with R2 to increase the voltage from the reference branch (i.e., connected to V REF The impedance seen by resistor R2) and helps capacitor C2 increase the signal level at node A.

[0202] In this case, the voltage on node A (in the s-domain) can be calculated by modifying (15) as follows:

[0203] V A =V IN ×(g1+sC2)×(R2+sL1) / [1+(g eqA +g1+sC2)×(R2+sL1)]+V REF / [1+(g eqA +g1+sC2)×(R2+sL1)] (41)

[0204] On the other hand, we can calculate it by modifying (17) as follows Fig.19 The voltage on node B (in the s domain) is:

[0205] V B =(g3+sC3) / (g3+∑g B +sC3)×V IN (42)

[0206] Among them, Σg B Defined in (18).

[0207] At high input frequencies (ie, s = ∞), equations (41) and (42) are simplified to:

[0208] V A ~V B ~V IN (43)

[0209] Replace V in (43) B Comparing the high-frequency values ​​of with (17) shows that the amount of high-frequency "boost" in the signal compared to its low-frequency value can be calculated by dividing (43) by (17):

[0210] G=(g3+∑g B ) / g3=1+∑g B / g3 (44)

[0211] This gain amount acts as an equalizer that enhances Fig.19 The bandwidth of the sampler circuit 100F in FIG. 100B and thus enhances the bandwidth of the ADC including the sampler circuit 100E.

[0212] Of course, C2, C3, and L1 may be employed in a similar manner in any of the circuits 100 and 100A to 100E (or 100G described below).

[0213] Depending on the actual implementation and the specifications required for the sampling switch circuit, it may be necessary to set the reference voltage V REF Designed to have a voltage higher than the core supply voltage (i.e., V DD ) (see equation (39)). The IO supply voltage may be, for example, a reference voltage to be used in sampling switch M S The upper generation is close to V DD As another option, the reference voltage can be generated using, for example, a step-up DC-DC converter.

[0214] Fig. 20 is a circuit 100E ( Fig.18 ) and circuit 10( Figure 2 ) is a schematic diagram of a test bench for comparing the operation of the circuit 100E and the circuit 10 in 7nM FinFet CMOS technology. S The on-resistance of is calculated and compared between the two "clock methods" (i.e., circuit 10 and circuit 100E). Fig.21 and Fig. 22 The results are shown with those items related to circuit 10 labeled as "conventional" and those items related to circuit 100E labeled as "proposed."

[0215] Fig.21 is a graph showing the on-resistance change (due to input voltage swing) versus sampling clock frequency for two clocking methods (i.e., circuit 10 and circuit 100E). Fig. 20 As shown, the clock frequency is f s And the duty cycle is 0.25. This means the tracking time is 0.25 / f s In the four-phase sampler front-end structure (later in Fig.23 This corresponds to 4×f s The sampling frequency of Fig.21 As can be seen in FIG. 1 , the performance of circuit 10 saturates very quickly and reaches a relatively large Ron (on resistance) variation with respect to the sampling frequency. On the other hand, the performance of circuit 100 maintains reasonable performance at very high sampling frequencies.

[0216] It is worth mentioning that Fig.21 The variation shown in is for different sampling frequencies with respect to the input voltage. Larger variations result in higher harmonic distortion and ultimately lower effective number of bits (ENOB), spurious free dynamic range (SFDR), and overall degradation of the dynamic performance of the ADC with associated circuitry.

[0217] Fig. 22 The sampling switch M S The effective bandwidth (EBW) (relative to Fig. 20 The sampling frequency f defined in s ), the EBW is defined as follows:

[0218] FBW=(1 / 2π)×1 / (R on，ave ×C S ) (45)

[0219] Among them, R on,ave is the average on-resistance (relative to the input signal amplitude), and C S is the sampling capacitor.

[0220] like Fig. 22 It can be seen from the results that Figure 2 Compared with the techniques of Fig.18 ) shows a better effective bandwidth. It is worth mentioning that, depending on the required resolution (and ENOB), the effective bandwidth (which represents the switch M S The RC time constant of the sampling clock should be several times higher than the sampling clock frequency. Figure 2 For sampling frequencies above about 14 GHz, the ratio of effective bandwidth to sampling frequency (i.e., EBW / f s ) drops below 1, and Fig.18 The method proposed in maintains a ratio greater than 2 for sampling frequencies up to over 30 GHz.

[0221] Fig.23 is a schematic diagram of another circuit arrangement 100G, the circuit arrangement 100G and Fig.16 The circuit arrangement is equivalent, but based on Fig.18 Rather than Figure 5 The circuit 100G is used for further simulation. Fig.18 A four-phase structure configured in (for example, used as a time-interleaved sampler front-end structure), where <3:0> represents an array of four components in a channel subcircuit connected in parallel. Fig.16 As in FIG. 1 , the input node, the nodes A and B, the first reference signal node and the second reference signal node, and the voltage divider circuit 110 are common to different channels (ie, shared between different channels).

[0222] exist Fig.23 In the example, CLK<3:0> and CLKN<3:0> are four-phase clocks, where the duty cycle of CLKN<3:0> is 0.25 and the duty cycle of CLK<3:0> is 0.75. Fig.24 (CLK<3:0> are the same but inverted). In this case, V DD =0.9V, and the frequency of each clock is f s / 4, where f s is the sampling frequency. In this example simulation, the circuit is designed for f s =100GSa / s or 100GHz (i.e., each clock phase is 25GHz). In addition, the output voltage swing is set to 0.5V peak-to-peak differential. Fig.23 The circuit in Fig.23 (depicted as single-ended in FIG.

[0223] Figure 25 to Figure 27 Node A ( Fig.25 ) and node G( Fig.26 ) and the output V of all four phases OUT ( Fig. 27 ). The circuit is designed for a characteristic impedance of (as an example) 50 ohms. In addition, the input frequency is set to about 1 GHz.

[0224] Will Fig. 27 The four phase output signals in are recombined into a single signal and its FFT spectrum is calculated, and then Fig.28In this example simulation, the ENOB is found to be about 10 bits, which shows that the proposed technique ( Fig.18 ) is effective at high sampling frequencies.

[0225] In summary, the embodiments disclosed herein enable: removing the large capacitor C from the switch path B (In other words, by removing the pre-charge stage) to speed up clock control, remove intrinsic delays and control all switches through the clock signal to speed up clock control, provide power to the clock path by dividing the power between the clock path and the input signal path, and introduce equalization and enhance the bandwidth of the circuit by boosting the input signal (power flowing through the clock path and the signal path) at high input frequencies.

[0226] It is advantageous to remove the precharge phase. The voltage V used in the tracking phase IN +V DD is always available (ie, maintained at node A). The number of transistors is significantly reduced (e.g., Figure 5 and Figure 2 In addition, the clock circuit system only processes the sampling switch M S In addition, the states of all devices are directly controlled by the clock, and Figure 2 The inherent delays are removed from the structure.

[0227] As described above, the sampling switch circuit embodying the present invention can be implemented as a part of an ADC, for example, as a front end of an ADC, so as to generate an input signal V at a sampling rate defined by a clock signal CLK as described above. IN Voltage mode sample V OUT . Fig.29 1 is a schematic diagram of such an ADC 1000 embodying the present invention. The ADC 1000 includes the sampling switch circuit 100 disclosed herein and any of the sampling switch circuits 100A to 100G, which are shown in FIG. Fig.29 As shown, ADC 1000 can be based on the voltage mode sample V OUT Output digital signals in sequence.

[0228] Any circuit system disclosed herein may be implemented as an integrated circuit system or integrated circuit, for example, as (or as a part of) an IC chip such as a flip chip. Fig.30 2 is a schematic diagram of an integrated circuit system 2000 embodying the present invention. The integrated circuit system 2000 may include the ADC 1000 and / or the sampling switch circuit 100 disclosed herein and any sampling switch circuits 100A to 100G. Fig.30The indication is 100.

[0229] Integrated circuit system 2000 may represent some or all of an IC chip. The present invention extends to integrated circuit systems and IC chips as described above, circuit boards including such IC chips, and communication networks (e.g., Internet fiber networks and wireless networks) including such circuit boards and network devices of such networks.

[0230] The invention can be embodied in many different ways in light of the above disclosure within the spirit and scope of the appended claims.

Claims

1. A sampling switch circuit, comprising: an input node connected to receive an input voltage signal to be sampled; a sampling transistor including a gate terminal, a source terminal and a drain terminal, the source terminal being connected to the input node; a voltage divider circuit connected to the input node and a tracking-control node to provide a tracking-control voltage signal at the tracking-control node that is dependent on the input voltage signal; a hold-control node connected to receive a hold-control voltage signal; an output node connected to a drain terminal of the sampling transistor; and a switching circuit system configured to connect a gate terminal of the sampling transistor to the tracking-control node or the holding-control node according to a clock signal; in: The voltage divider circuit comprises: a first impedance connected between the input node and the tracking-control node; a second impedance connected between the tracking-control node and a first reference node connected to receive a first reference voltage signal having a first reference DC component; A third impedance connected between the input node and the sampling node; and a fourth impedance connected between the sampling node and a second reference node, the second reference node being connected to receive a second reference voltage signal having a second reference DC component; a source terminal of the sampling transistor being connected to the sampling node and connected to the input node via the sampling node; The voltage divider circuit is configured such that: when the gate terminal of the sampling transistor is connected to the tracking-control node, the sampling transistor is turned on and the voltage at the output node tracks the voltage at the source terminal of the sampling transistor; and When the gate terminal of the sampling transistor is connected to the hold-control node, the sampling transistor is turned off and the voltage at the output node is at least temporarily maintained or held.

2. The sampling switch circuit according to claim 1, wherein: The tracking-control voltage signal has a tracking-control AC component defined by at least the input voltage signal and a tracking-control DC component defined by at least the voltage divider circuit.

3. The sampling switch circuit according to claim 2, wherein: The voltage divider circuit is configured to maintain the tracking-control voltage signal at the tracking-control node, wherein the tracking-control AC component is optionally maintained to be at least defined by the input voltage signal and the tracking-control DC component is maintained to be at least defined by the voltage divider circuit, the tracking-control voltage signal is optionally maintained as a continuous signal and is optionally independent of the clock signal.

4. The sampling switch circuit according to claim 2 or 3, wherein: The voltage divider circuit is connected to the sampling node to provide a sampled voltage signal at the sampling node, the sampled voltage signal having at least a sampled AC component defined by the input voltage signal and at least a sampled DC component defined by the voltage divider circuit.

5. The sampling switch circuit according to claim 4, wherein: The voltage divider circuit is configured to maintain the sampled voltage signal at the sampling node, wherein the sampled AC component is optionally maintained to be at least defined by the input voltage signal and the sampled DC component is maintained to be at least defined by the voltage divider circuit, optionally maintained as a continuous signal and optionally independent of the clock signal.

6. The sampling switch circuit according to claim 4, wherein: The voltage divider circuit is configured such that the tracking-controlling DC component and the sampling DC component are different in voltage level from each other.

7. The sampling switch circuit according to claim 4, wherein: The first reference DC component and the second reference DC component are configured such that a difference between a voltage level of the tracking-controlling DC component and a voltage level of the sampling DC component is greater than or equal to a threshold voltage of the sampling transistor.

8. The sampling switch circuit according to claim 7, wherein: The first impedance is implemented as a resistor or a series connection of a resistor and a capacitor, or is implemented as a parallel connection of a resistor and a capacitor, or is implemented as a series connection of a parallel combination of impedances and a capacitor, wherein the parallel combination of impedances includes a parallel connection of a resistor and a capacitor; and / or The second impedance is implemented as a resistor, or as a series connection of a resistor and an inductor; and / or The third impedance is implemented as a resistor, or as a parallel connection of a resistor and a capacitor; and / or The fourth impedance is implemented as a resistor, or as a series connection of a parallel combination of impedances and a resistor, wherein the parallel combination of impedances comprises a parallel connection of a resistor and a capacitor, and optionally, wherein the parallel combination of impedances is connected to the second reference node.

9. The sampling switch circuit according to claim 4, wherein: The hold-control voltage signal has a hold-control DC component, and a difference between a voltage level of the hold-control DC component and a voltage level of the sampling DC component is smaller than a threshold voltage of the sampling transistor.

10. The sampling switch circuit according to any one of claims 1 to 3, wherein: The switching circuit system includes: a first switch connected between the gate terminal of the sampling transistor and the tracking-control node; and a second switch connected between the gate terminal of the sampling transistor and the holding-control node, Optionally, the first switch and the second switch are implemented by transistors, Optionally, where: A resistor between the first switch and the gate terminal of the sampling transistor and the tracking-control node is connected in series, optionally wherein the resistor is implemented by one or more transistors; and / or The second switch and a resistor between the gate terminal of the sampling transistor and the hold-control node are connected in series, optionally wherein the resistor is implemented by one or more transistors.

11. The sampling switch circuit according to any one of claims 1 to 3, configured to have a plurality of channels, wherein: Each of said channels includes its own sampling transistor, output node, switching circuitry, and clock signal; and For each of the channels, a source terminal of a sampling transistor is connected to an input node, an output node is connected to a drain terminal of the sampling transistor, and a switching circuit system is configured to connect a gate terminal of the sampling transistor to the tracking-control node or the holding-control node according to a clock signal.

12. An analog-to-digital converter comprising a sampling switch circuit according to any one of the preceding claims. 13 . An integrated circuit system, comprising the sampling switch circuit according to claim 1 or the analog-to-digital converter according to claim 12 .

14. The integrated circuit system according to claim 13, wherein: The integrated circuit system is an IC chip.

Images