Interconnect structure and method of manufacturing the same

Abstract

Disclosed herein are interconnect structures and methods of manufacturing that exhibit reduced copper vacancy accumulation along an interface between a contact etch stop layer (CESL) and an interconnect. The method includes: forming a copper interconnect in a dielectric layer; and depositing a metal nitride CESL over the copper interconnect and the dielectric layer. The interface between the metal nitride CESL and the copper interconnect has a first surface nitrogen concentration, a first nitrogen concentration, and / or a first amount of nitrogen-nitrogen combinations. A nitrogen plasma treatment is performed to modify the interface between the metal nitride CESL and the copper interconnect. The nitrogen plasma treatment increases the first surface nitrogen concentration to a second surface nitrogen concentration, increases the first nitrogen concentration to a second nitrogen concentration, and / or increases the first amount of nitrogen-nitrogen combinations to a second amount of nitrogen-nitrogen combinations, each of which can minimize the accumulation of copper vacancies at the interface.

Description

Technical Field

[0001] Embodiments of the present application relate to an interconnect structure and a method for manufacturing the same. Background Art

[0002] The integrated circuit (IC) industry has experienced exponential growth. Technological advances in IC materials and design have produced multiple generations of ICs, each with smaller and more complex circuits than the previous generation. In the process of IC development, functional density (i.e., the number of interconnected IC devices per chip area) has generally increased, while geometric dimensions (i.e., the size and / or size of IC components and / or the spacing between these IC components) have decreased. Typically, scaling down is limited by the ability of ICs to be defined by photolithography with ever-decreasing geometric dimensions. However, as reduced geometric dimensions are implemented to achieve ICs with faster operating speeds (e.g., by reducing the distance that electrical signals propagate), resistance-capacitance (RC) delays have become significant challenges, thereby offsetting some of the advantages obtained by scaling down and limiting further scaling down of ICs. RC delays generally represent the product of resistance (R) (i.e., the reaction of the material to the flow of current) and capacitance (C) (i.e., the ability of the material to store charge) resulting in a delay in the speed of electrical signals passing through the IC. Therefore, it is desirable to reduce resistance and capacitance to reduce RC delays and optimize the performance of scaled-down ICs. IC interconnects that physically and / or electrically connect IC components and / or IC parts of an IC are particularly problematic in their effect on RC delay. Interconnect solutions that can reduce the effect of interconnects on RC delay present new challenges. For example, improved interconnect structures sometimes fail to adequately prevent metal from diffusing from the interconnect into surrounding dielectric materials, which results in the formation of undesirable voids in the interconnect, thereby degrading IC performance. Therefore, there is a need for improved interconnects for ICs and / or methods of making interconnects. Summary of the invention

[0003] Some embodiments of the present application provide an interconnect structure of a multilayer interconnect component of an integrated circuit device, the interconnect structure comprising: a first interlayer dielectric (ILD) layer; a second interlayer dielectric layer, disposed above the first interlayer dielectric layer; a first copper interconnect, disposed in the first interlayer dielectric layer; a second copper interconnect, disposed in the second interlayer dielectric layer; and an aluminum nitride contact etch stop layer (CESL), disposed between a portion of the first copper interconnect and the second interlayer dielectric layer and between the first interlayer dielectric layer and the second interlayer dielectric layer, wherein the second copper interconnect extends through the aluminum nitride contact etch stop layer to physically contact the first copper interconnect, and further wherein a surface nitrogen concentration at an interface between the aluminum nitride contact etch stop layer and the first copper interconnect is greater than or equal to approximately 20 at%.

[0004] Some other embodiments of the present application provide an interconnect structure of a multilayer interconnect component of an integrated circuit device, the interconnect structure comprising: a first interconnect, arranged in a dielectric layer, wherein the first interconnect has: a copper main layer, a first metal nitride layer, arranged along the sidewall of the copper main layer, wherein the first metal nitride layer is arranged between the copper main layer and the dielectric layer, a second metal nitride layer, arranged along the top of the copper main layer, wherein the first metal nitride layer includes a first metal and the second metal nitride layer includes a second metal, and a third metal nitride layer, arranged above the second metal nitride layer, wherein the third metal nitride layer includes a third metal, wherein the third metal, the second metal and the first metal are different; and a second interconnect, arranged in the dielectric layer and extending through the third metal nitride layer to the first interconnect.

[0005] Still other embodiments of the present application provide a method for manufacturing an interconnect structure, comprising: forming a copper interconnect in an interlayer dielectric (ILD) layer; depositing a metal nitride contact etch stop layer (CESL) over the copper interconnect and the interlayer dielectric layer, wherein an interface region between the metal nitride contact etch stop layer and the copper interconnect has a first surface nitrogen concentration; and performing a nitrogen plasma treatment to modify the interface region between the metal nitride contact etch stop layer and the copper interconnect, wherein the nitrogen plasma treatment increases the first surface nitrogen concentration to a second surface nitrogen concentration that minimizes accumulation of copper vacancies in the interface region. BRIEF DESCRIPTION OF THE DRAWINGS

[0006] The present invention can be best understood from the following detailed description when read in conjunction with the accompanying drawings. It should be emphasized that, in accordance with standard practice in the industry, the various components are not drawn to scale and are only used for illustration purposes. In fact, the size of the various components can be arbitrarily increased or reduced for clarity of discussion.

[0007] Figure 1 is a flow chart of a method for fabricating a portion of a multi-layer interconnect component according to various aspects of the present invention.

[0008] FIG. 2A to FIG. 2I According to various aspects of the present invention, at various stages of manufacture (such as Figure 1 A partial schematic diagram of a portion of a multi-layer interconnect component (those related to the method).

[0009] Figure 3 is a partially schematic diagram of a portion of a multi-layer interconnect component according to various aspects of the present invention.

[0010] Figure 4 is a flow chart of a deposition process for an etch stop layer for forming a multi-layer interconnect structure according to various aspects of the present invention.

[0011] Figure 5 is a flow chart of a nitrogen plasma treatment process for an interface region between an etch stop layer and an interconnect of a multi-level interconnect structure according to various aspects of the present invention.

[0012] Figure 6 ] are Fourier transform infrared (FTIR) spectra obtained by performing FTIR spectroscopy on an AlN bulk film before and after nitrogen plasma treatment according to various aspects of the present invention.

[0013] Fig. 7A and Figure 7B According to various aspects of the present invention Fig.2I and Figure 3 A partial schematic top view of a portion of some or all of a multi-layer interconnect component.

[0014] Figure 8 is a partial schematic diagram of a portion or all of an integrated circuit device according to various aspects of the present invention. DETAILED DESCRIPTION

[0015] The present invention relates generally to integrated circuit (IC) devices and, more particularly, to interconnect structures for IC devices.

[0016] The following disclosure provides many different embodiments or examples for realizing different features of the present invention. Specific examples of components and arrangements are described below to simplify the present invention. Of course, these are only examples and are not intended to limit the present invention. For example, in the following description, forming a first component above or on a second component may include an embodiment in which the first component and the second component are directly contacted and formed, and may also include an embodiment in which an additional component may be formed between the first component and the second component, so that the first component and the second component may not be directly contacted. In addition, spatial relative terms such as, for example, "lower", "upper", "horizontal", "vertical", "above", "above", "below", "below", "under", "upward", "downward", "top", "bottom" and their derivatives (e.g., "horizontal", "downward", "upward", etc.) are used to facilitate the present invention to disclose the relationship between one component and another component. Spatial relative terms are intended to cover different orientations of devices including components. In addition, when describing a numerical value or a numerical range with "about", "roughly", etc., it is considered that the term is intended to cover a numerical value within a reasonable range considering the inherent changes during manufacturing, as understood by those of ordinary skill in the art. For example, based on known manufacturing tolerances associated with manufacturing components having properties associated with the values, the values ​​or ranges of values ​​encompass a reasonable range including the described values, such as within + / -10% of the described values. For example, a material layer having a thickness of "about 5 nm" may encompass a size range from 4.5 nm to 5.5 nm, where the manufacturing tolerance associated with deposited material layers known to those of ordinary skill in the art is + / -10%. In addition, the present invention may repeat reference numerals and / or characters in various instances. This repetition is for the purpose of simplicity and clarity and does not in itself indicate a relationship between the various embodiments and / or configurations discussed.

[0017] Typically, scaling down is limited only by the ability of lithography to define ICs with ever-decreasing geometries. However, as reduced geometries are implemented to achieve ICs with faster operating speeds (e.g., by reducing the distance that electrical signals propagate), resistance-capacitance (RC) delays have become significant challenges, offsetting some of the advantages gained from scaling down and limiting further scaling down of ICs. For example, as IC technology nodes extend to 20nm and below, the reduction in critical dimensions (CD) at IC device layers (e.g., gate length, gate spacing, fin spacing, etc.) results in a corresponding reduction in the interconnect CD (e.g., device-level contact dimensions, via dimensions, metal line dimensions, device-level contact spacing, via spacing, metal line spacing, etc.) of the multi-layer interconnect (MLI) functions of the IC. When considering their impact on RC delays, shrinking interconnects are increasingly becoming a problem. Therefore, solutions for reducing the resistance and capacitance associated with interconnects are desired to reduce RC delays and optimize the performance of scaled-down ICs.

[0018] RC delay generally refers to the delay in the speed of electrical signals through an IC, which is caused by the product of resistance (R), the material's reaction to current flow, and capacitance (C), the material's ability to store charge. For any two adjacent interconnects, capacitance is a function of the dielectric constant of the dielectric material surrounding the two interconnects and the distance between the interconnects. Because the reduced distance (spacing) between interconnects is caused by scaling down the IC (and thus resulting in increased capacitance), capacitance reduction techniques have focused on reducing the dielectric constant of the insulating material of the interconnects. For example, low dielectric constant materials that reduce parasitic capacitance and / or capacitive coupling between interconnects and adjacent conductive components (such as adjacent interconnects or adjacent device components (e.g., gates)) have been developed, such as dielectric materials having a dielectric constant less than that of silicon oxide (e.g., SiO2). Reduced resistance associated with interconnects has been achieved by implementing interconnect materials and / or interconnect structures that exhibit reduced resistance and promote increased current flow. For example, because copper interconnects exhibit lower resistance, higher conductivity, and higher electromigration resistivity than aluminum interconnects, copper interconnects are often used to replace aluminum interconnects to reduce RC delay and thereby increase IC speed. However, because the copper ions / atoms of the copper interconnects easily diffuse into the low-k dielectric material (which has been implemented to reduce capacitance), a diffusion / barrier layer is typically integrated into the copper interconnects to separate the copper layer of the copper interconnect from the surrounding low-k dielectric material and reduce (or prevent) the diffusion of copper atoms / ions from the copper layer into the surrounding low-k dielectric material.

[0019] During the process, undesirable copper diffusion is also observed at the interface between the copper interconnect and the layer above, such as the contact etch stop layer (CESL). The CESL is typically implemented in copper interconnect manufacturing to prevent accidental etching and / or over-etching of the underlying interconnect. Therefore, the interconnect manufacturing can include a two-step etching process to form an interconnect opening, such as a first etching process that etches the dielectric layer until the CESL is formed between the dielectric layer and the underlying interconnect (in other words, the CESL serves as a stop member for the first etching process), and a second etching process that etches the CESL until (exposes) the underlying interconnect, wherein the parameters of the first etching process are adjusted to selectively etch the dielectric layer (e.g., relative to the CESL), and the parameters of the second etching process are adjusted to selectively remove the CESL (e.g., relative to the dielectric layer and the underlying interconnect). The interconnect opening is then filled with one or more conductive materials, such as a copper bulk layer disposed above a diffusion barrier layer (including, for example, tantalum and nitrogen) to form a copper interconnect to the underlying interconnect.

[0020] Stress-induced voids (also referred to as stress migration) at the interface between CESL and copper interconnects (hereinafter referred to as CESL / copper interface) have become a major factor in IC device reliability. For example, mechanical stresses in MLI components can cause copper ions / atoms and copper vacancies to migrate to the CESL / copper interface along grain boundaries in the copper interconnects. As copper atoms / ions diffuse into the MLI components (e.g., into the CESL and / or surrounding dielectric layers) and copper vacancies accumulate at the CESL / copper interface, voids are formed at the CESL / copper interface, which increases the resistance of the copper interconnects and degrades IC performance. These voids can lead to open circuits, depending on location and / or size, and in some cases lead to copper interconnect failure and / or IC device failure. These mechanical stresses often occur during MLI component manufacturing (referred to as back-end of line (BEOL) processes) because of the mismatch in thermal expansion coefficients between the copper interconnect and the dielectric material surrounding it. For example, because the copper interconnect and the surrounding dielectric material have different coefficients of thermal expansion, the copper interconnect and the surrounding dielectric material will expand and contract at different rates during each BEOL thermal cycle, resulting in stress differences in the MLI features, causing copper ions / atoms and / or copper vacancies to migrate to the CESL / copper interface.

[0021] To address these challenges, the present invention proposes an interconnect manufacturing method for inhibiting copper diffusion at the CESL / copper interface, thereby preventing copper vacancies from accumulating at the CESL / copper interface, and reducing (and even eliminating) void formation in the copper interconnect at the CESL / copper interface. For example, the present invention proposes subjecting the CESL to a nitrogen plasma treatment before forming the upper ILD layer, wherein the nitrogen plasma treatment is configured to increase the concentration of nitrogen and / or increase and / or enhance (strengthen) nitrogen bonding at the CESL / copper interface. Increasing the nitrogen concentration and / or nitrogen bonding at the CESL / copper interface prevents (or limits) the diffusion of copper ions / atoms, and reduces copper vacancies along the CESL / copper interface, thereby preventing the accumulation of copper vacancies at the CESL / copper interface and limiting the formation of stress-induced voids in the copper interconnect. In some embodiments, it has been observed that the proposed nitrogen plasma treatment not only increases the nitrogen concentration of the CESL, but also increases the dielectric constant, reflectivity and / or density of the CESL. The following is a detailed description of a method for manufacturing an interconnect structure including the proposed nitrogen plasma treatment process, and the resulting interconnect structure. Different embodiments may have different advantages, and no particular advantage is required of any embodiment.

[0022] Go to Figure 1 , Figure 11 is a flow chart of a method 100 for manufacturing a portion of an MLI component according to various aspects of the present invention. At blocks 110 and 120, the method 100 includes: forming a first dielectric layer over a device substrate; and forming a first interconnect opening in the first dielectric layer to expose an underlying conductive feature, such as an interconnect of the MLI component or a conductive feature of the device substrate (e.g., a gate or source / drain feature). In some embodiments, the dielectric layer includes an interlayer dielectric layer disposed over an etch stop layer. At block 130, a first interconnect is formed in the first interconnect opening. For example, at block 132, a diffusion barrier layer is formed over a sidewall surface (e.g., defined by the dielectric layer) and a bottom surface (e.g., defined by the underlying conductive feature) defining the interconnect opening; at block 134, a bulk layer is formed over the diffusion barrier layer so that the diffusion barrier layer and the bulk layer fill the interconnect opening; and at block 136, a capping layer is formed over the bulk layer and, in some embodiments, over the diffusion barrier layer. In some embodiments, the bulk layer includes copper, the capping layer includes a metal such as cobalt and nitrogen, and the first interconnect is a copper interconnect. At block 140, an etch stop layer is deposited over the first interconnect. The etch stop layer includes a metal such as aluminum and nitrogen. The region near the interface between the etch stop layer and the first interconnect is referred to as an interface region, which includes the interface between the etch stop layer and the capping layer and the interface between the capping layer and the bulk layer. In some embodiments, the capping layer in the first interconnect is omitted, and the interface region includes the interface between the etch stop layer and the bulk layer. At block 150, a nitrogen plasma treatment is applied to the etch stop layer to increase the nitrogen concentration and / or nitrogen incorporation at the interface region, as described herein. Increasing the nitrogen concentration and / or nitrogen incorporation at the interface region can improve the metal diffusion barrier capability of the interface region, so that during subsequent processing of the MLI component (such as the component associated with blocks 160-180), the interface region can prevent metal ions / atoms and / or metal vacancies from diffusing from the bulk layer of the first interconnect through the interface region to the surrounding layers. It has been observed that improving the diffusion barrier capability of the interface region minimizes (and even eliminates) void formation at the interface region. The method 100 then continues with forming a second dielectric layer over the etch stop layer at block 160, forming a second interconnect opening in the second dielectric layer to expose the first interconnect at block 170, and forming a second interconnect (which may be similar to the first interconnect) in the second interconnect opening at block 180. Additional steps may be provided before, during, and after the method 100, and some of the steps described may be moved, replaced, or eliminated for additional embodiments of the method 100.

[0023] FIG. 2A to FIG. 2I is according to various aspects of the present invention at various stages of manufacture (such as with Figure 1 Multilayer interconnect (MLI) components (such as those related to method 100) Figure 42 is a partial schematic diagram of a portion 200 of an MLI component 400 as depicted in FIG. The MLI component 400 electrically couples various devices (e.g., transistors, resistors, capacitors, and / or inductors) and / or components (e.g., gates and / or source / drain components) of an IC device so that the various devices and / or components can operate in a manner specified by design requirements. The MLI component 400 includes a combination of dielectric layers and metal layers configured to form various interconnects. The metal layers are configured to form vertical interconnects (such as device-level contacts and / or vias) and horizontal interconnects (such as wires). The vertical interconnects typically connect horizontal interconnects in different layers (or different planes) of the MLI function 400. During operation of the IC device, the interconnects route signals between devices and / or components of the IC device and / or distribute signals (e.g., clock signals, voltage signals, and / or ground signals) to the devices and / or components, as well as route and distribute signals between devices and / or components of the IC device and devices and / or components external to the IC device. It should be noted that although the MLI component 400 will be depicted as having a given number of dielectric layers and metal layers, the present disclosure contemplates MLI components 400 having more or fewer dielectric layers and / or metal layers. FIG. 2A to FIG. 2I , to better understand the inventive concept of the present invention. Additional components may be added to the MLI component and / or the portion 200 of the MLI component 400, and some of the components described below may be replaced, modified, or eliminated in other embodiments of the MLI component and / or the portion 200 of the MLI component 400.

[0024] Go to Figure 2A, a dielectric layer 202 is formed over the device substrate 206. In the depicted embodiment, the dielectric layer 202 includes an interlayer dielectric (ILD) layer 210 disposed over a contact etch stop layer (CESL) 212. In some embodiments, the thickness of the ILD layer 210 is about 20 nm to about 30 nm, and the thickness of the CESL 212 is about 1 nm to about 3 nm. The ILD layer 210 and / or the CESL 212 are formed over the device substrate 206 by a deposition process such as chemical vapor deposition (CVD), physical vapor deposition (PVD), atomic layer deposition (ALD), high density plasma CVD (HDPCVD), metal organic CVD (MOCVD), remote plasma CVD (RPCVD), plasma enhanced CVD (PECVD), low pressure CVD (LPCVD), atomic layer CVD (ALCVD), atmospheric pressure CVD (APCVD), plasma enhanced ALD (PEALD), other suitable deposition methods, or combinations thereof. In some embodiments, the ILD layer 210 is formed by a high aspect ratio process (HARP), such as HDPCVD, which generally refers to a deposition process having parameters configured to achieve sufficient filling in high aspect ratio structures. In some embodiments, the ILD layer 210 is formed by a flowable CVD (FCVD) process, which includes, for example, depositing a flowable material (such as a liquid compound) over the device substrate 206, and converting the flowable material into a solid material by a suitable technique (such as thermal annealing) and / or treating the flowable material with ultraviolet radiation. After depositing the ILD layer 210 and / or CESL 212, a CMP process and / or other planarization process may be performed so that the ILD layer 210 and / or CESL 212 has a substantially flat surface.

[0025] The ILD layer 210 includes a dielectric material, which includes, for example, silicon oxide, carbon-doped silicon oxide, silicon nitride, silicon oxynitride, tetraethyl orthosilicate (TEOS), phosphosilicate glass (PSG), borosilicate glass (BSG), boron-doped phosphosilicate glass (BPSG), fluorine-doped silicate glass (FSG), (Applied Materials, Santa Clara, CA), xerogel, aerogel, amorphous fluorinated carbon, parylene, benzocyclobutene (BCB) based dielectric materials, SiLK (The Dow Chemical Company, Midland, MI), polyimide, other suitable dielectric materials, or combinations thereof. In some embodiments, the ILD layer 210 includes a low-k dielectric material, which generally refers to a dielectric material having a low dielectric constant relative to the dielectric constant of silicon dioxide (k≈3.9). For example, the low-k dielectric material has a dielectric constant of less than about 3.9. In some embodiments, the low-k dielectric material has a dielectric constant of less than about 2.5, which may be referred to as an extremely low-k (ELK) dielectric material. In the depicted embodiment, the ILD layer 210 includes an ELK dielectric material (and thus may be referred to as an ELK dielectric layer), such as silicon dioxide (SiO2) (e.g., porous silicon dioxide), silicon carbide (SiC), and / or a carbon-doped oxide (e.g., a SiCOH-based material (e.g., having a Si-CH3 bond)), each of which is tuned / configured to exhibit a dielectric constant of less than 2.5. The CESL 212 includes a material different from the ILD layer 210, such as a dielectric material different from the dielectric material of the ILD layer 210. For example, in the case where the ILD layer 210 includes silicon and oxygen (e.g., SiCOH, SiO x In some embodiments, the CESL 212 may include silicon and nitrogen and / or carbon (e.g., SiN, SiCN, SiCON, SiON, SiC, and / or SiCO) (and may therefore be referred to as a silicon nitride layer). In some embodiments, the CESL 212 is configured similarly to other CESLs described herein, such as metal nitride layers. The ILD layer 210 and / or the CESL 212 may include a multilayer structure having multiple dielectric materials.

[0026] Go to Figure 2B , an interconnect opening 220 is formed in the dielectric layer 202 by a patterning process. The interconnect opening 220 extends vertically through the ILD layer 210 and the CESL 212 to expose the underlying MLI components (e.g., device-level contacts, vias, or wires of the MLI component 400) and / or the underlying components of the device substrate 206 (e.g., gate or source / drain components). The interconnect opening 220 includes a sidewall 222 (defined by the dielectric layer 202), a sidewall 224 (defined by the dielectric layer 202), and a bottom 226 (defined by the underlying components) extending between the sidewall 222 and the sidewall 224. Figure 2B, the interconnect opening 220 has a trapezoidal shape, but the present invention contemplates that the interconnect opening 220 has other shapes, such as a rectangle. The sidewalls 222, 224 of the interconnect opening 220 are tapered so that the width of the interconnect opening 220 decreases along the thickness of the dielectric layer 202, and the width of the interconnect opening 220 that exposes the underlying components is smaller than the width of the interconnect opening 220 at the top surface of the ILD layer 210. In some embodiments, the patterning process includes: performing a photolithography process to form a patterned mask layer 228 having an opening 229 over the dielectric layer 202; and performing an etching process to transfer the pattern defined in the patterned mask layer 228 to the dielectric layer 202. The photolithography process may include: forming a resist layer on the dielectric layer 202 (e.g., by spin coating); performing a pre-exposure baking process; performing an exposure process using a mask; performing a post-exposure baking process; and performing a development process. During the exposure process, the resist layer is exposed to radiation energy (such as ultraviolet (UV), deep ultraviolet (DUV) or extreme ultraviolet (EUV)), wherein the mask blocks, transmits and / or reflects radiation to the resist layer, depending on the mask pattern (for example, binary mask, phase shift mask or EUV mask) of the mask and / or mask type, so that the image is projected on the resist layer corresponding to the mask pattern. Because the resist layer is sensitive to radiation energy, chemical changes occur in the exposed portion of the resist layer, and during the development process, the exposed (or non-exposed) portion of the resist layer dissolves, depending on the characteristic of the resist layer and the characteristic of the developer used in the development process. After development, the patterned resist layer comprises the resist pattern corresponding to the mask. Alternatively, the exposure process can be implemented or replaced by other methods such as maskless lithography, electron beam writing and / or ion beam writing.

[0027] In some embodiments, the patterned resist layer is a patterned mask layer 228. In such embodiments, the patterned resist layer is used as an etching mask to remove the portion of the dielectric layer 202 exposed by the opening 229. In some embodiments, before forming the resist layer, a patterned resist layer is formed over the mask layer formed over the dielectric layer 202, and the patterned resist layer is used as an etching mask to remove the portion of the mask layer formed over the dielectric layer 202, thereby forming the patterned mask layer 228. In such embodiments, the patterned mask layer is used as an etching mask to remove the portion of the dielectric layer 202 exposed by the opening 229. The etching process may include a dry etching process (e.g., a reactive ion etching (RIE) process), a wet etching process, other suitable etching processes, or a combination thereof. Each selective etching process may be performed to form the interconnect opening 220. For example, the etching process may include a first etch that selectively etches the ILD layer 210 relative to the patterned mask layer 228 and the CESL 212, so that the first etch stops when reaching the CESL 212, and a second etch that selectively etches the CESL 212 relative to the ILD layer 210 and the underlying components, so that the second etch stops when reaching the underlying components. In some embodiments, the first etch and / or the second etch may be configured to slightly overetch, so that the first etch may partially etch the CESL 212 and / or the second etch may partially etch the underlying components. In some embodiments, the first etch and the second etch are similar to the etching processes described herein for etching the ILD and CESL. In some embodiments, the etching process may include multiple steps (stages) for etching the CESL 212. In some embodiments, after the etching process, the patterned mask layer 228 is removed from the ILD layer 210 (in some embodiments, by a resist stripping process). In some embodiments, the patterned mask layer 228 is removed during etching the ILD layer 210 and / or the CESL 212.

[0028] Go to Figure 2C, a copper interconnect 230 is formed in the interconnect opening 220. The copper interconnect 230 includes a diffusion barrier layer 232 (having a first barrier layer 234A and a second barrier layer 234B) and a copper body layer 236 disposed over the diffusion barrier layer 232. The diffusion barrier layer 232 is disposed on the sidewalls 222, 224 and bottom 226 of the interconnect opening 220 defined by the ILD layer 210, the CESL 212 and the underlying components. For example, the first barrier layer 234A physically contacts the sidewalls 222, 224 and bottom 226 of the interconnect opening 220 defined by the ILD layer 210, the CESL 212 and the underlying components, and the second barrier layer 234B is disposed on and physically contacts the first barrier layer 234A, such that the second barrier layer 234B extends along the sidewalls 222, 224 and bottom 226 of the interconnect opening 220 defined by the ILD layer 210, the CESL 212 and the underlying components. In some embodiments, the thickness of the diffusion barrier layer 232 (the sum of the thickness t1 of the first barrier layer 234A and the thickness t2 of the second barrier layer 234B) is less than or equal to about 9 nm. For example, in some embodiments, the thickness t1 is about 2 nm to about 5 nm, and the thickness t2 is about 2 nm to about 4 nm. In some embodiments, the copper interconnect 230 is formed by the following steps: performing a first deposition process to form a first barrier material partially filling the interconnect opening 220 over the ILD layer 210; performing a second deposition process to form a second barrier material over the first barrier material, wherein the second barrier material partially fills the interconnect opening 220; and performing a third deposition process to form a copper body material over the second barrier material, wherein the copper body material fills the remaining portion of the interconnect opening 220. In such an embodiment, the first barrier material, the second barrier material, and the copper body material are disposed in the interconnect opening 220 and over the top surface of the ILD layer 210. The first deposition process, the second deposition process, and the third deposition process may include CVD, PVD, ALD, HDPCVD, MOCVD, RPCVD, PECVD, LPCVD, ALCVD, APCVD, PEALD, electroplating, chemical plating, other suitable deposition methods, or combinations thereof. In some embodiments, the first barrier layer 234A and the second barrier layer 234B have a substantially uniform thickness along the sidewalls 222, 224 and the bottom 226 of the interconnect opening 220. Therefore, the first barrier layer 234A and the second barrier layer 234B may be formed by a conformal deposition process. A CMP process and / or other planarization process is performed to remove excess copper body material, the second barrier material, and the first barrier material, for example, from above the top surface of the ILD layer 210, thereby obtaining the copper interconnect 230 (in other words, the diffusion barrier layer 232 and the copper body layer 236 fill the interconnect opening 220).The CMP process planarizes the top surface of the copper interconnect 230 , such that in some embodiments, the top surface of the ILD layer 210 and the top surface of the copper interconnect 230 form a substantially flat surface.

[0029] The diffusion barrier layer 232 is configured to promote adhesion between the dielectric layer 202 (here, the dielectric surface defining the interconnect opening 220) and the copper body layer 236, and prevent copper components (e.g., copper atoms / ions) from diffusing from the copper interconnect 230 into the dielectric layer 202. For example, the first barrier layer 234A includes a material that prevents copper from diffusing from the copper body layer 236 into the dielectric layer 202 and promotes adhesion between the copper body layer 236 and the dielectric layer 202, and the second barrier layer 234B includes a material that promotes adhesion between the first barrier layer 234A and the copper body layer 236 (thereby serving as a glue (adhesion) layer between the first barrier layer 234A and the copper body layer 236). The materials of the first barrier layer 234A and the second barrier layer 234B also exhibit low resistivity to maximize the conductivity of the copper interconnect 230. In some embodiments, the first barrier layer 234A includes tantalum, tantalum alloy, titanium, titanium alloy, tungsten, tungsten alloy, cobalt, cobalt alloy, molybdenum, molybdenum alloy, other suitable components configured to prevent copper from diffusing from the copper-based material into the dielectric material and promote adhesion between the copper-based material and the dielectric material, or a combination thereof. For example, the first barrier layer 234A includes tantalum, tantalum nitride, titanium, titanium nitride, tungsten, tungsten nitride, tantalum silicon nitride, titanium silicon nitride, tantalum carbide, titanium carbide, tungsten carbide, molybdenum nitride, or a combination thereof. In the depicted embodiment, the first barrier layer 234A includes tantalum and nitrogen and may be referred to as a tantalum nitride (TaN) barrier layer. Tantalum exhibits low resistance to current flow and adheres well to dielectric materials, such as those of the ILD layer 210 and / or the CESL 212, thereby enhancing the conductivity of the copper interconnect 230 and minimizing (or eliminating) gaps formed between the copper interconnect 230 and the dielectric layer 202. The combination of tantalum and nitrogen also exhibits desirable copper diffusion barrier properties. In some embodiments, the TaN barrier layer includes a tantalum concentration of about 55 atomic percent (at%) to about 60 at% and a nitrogen concentration of about 35 at% to about 40 at%. In some embodiments, the second barrier layer 234B includes tantalum, tantalum alloys, titanium, titanium alloys, tungsten, tungsten alloys, cobalt, cobalt alloys, ruthenium, ruthenium alloys, palladium, palladium alloys, molybdenum, molybdenum alloys, other suitable components configured to promote adhesion between a copper diffusion barrier material (such as tantalum nitride) and a copper-based material, or combinations thereof. For example, the second barrier layer 234B includes cobalt, cobalt nitride, ruthenium, palladium, tantalum, titanium, tungsten, tantalum silicon nitride, titanium silicon nitride, tantalum aluminum nitride, titanium aluminum nitride, or combinations thereof. In the depicted embodiment, the second barrier layer 234B includes cobalt and may be referred to as a cobalt (Co) layer. Cobalt exhibits low resistance to electric current and bonds well to tantalum nitride and copper-based materials, thereby enhancing the conductivity of copper interconnect 230 and minimizing (or eliminating) gaps formed between copper bulk layer 236 and first barrier layer 234A. In some embodiments, second barrier layer 234B includes a cobalt concentration greater than or equal to about 99 at %.

[0030] The copper main layer 236 includes copper or a copper alloy. In some embodiments, the copper main layer 236 includes a copper concentration greater than or equal to about 99at%, for example, about 99at% to about 99.5at%. The copper main layer 236 has grain boundaries 238, which generally represent interfaces between copper grains (or crystallites) of, for example, copper (or copper alloy) in polycrystalline form. The grain boundaries 238 provide paths for copper ions / atoms and copper vacancies to travel in the copper main layer 236, which allow copper ions / atoms and copper vacancies to migrate to the interface between the copper interconnect 230 and its surrounding layers. Such migration can cause copper ions / atoms to diffuse from the copper main layer 236 at the interface of the copper interconnect 230 with the surrounding dielectric material and / or accumulate copper vacancies at the interface, which can cause voids to form in the copper interconnect 230. As further described below, the present invention proposes solutions for addressing these challenges faced as ICs shrink to 20nm and beyond IC technology nodes. The copper body layer 236 has a thickness t3, which in some embodiments is about 20 nm to about 40 nm. In some embodiments, the copper body layer 236 includes a copper-containing seed (or liner) layer disposed between the second barrier layer 234B and the copper-containing body layer. In such embodiments, the copper-containing seed layer is disposed on the second barrier layer 234B so that the copper-containing seed layer extends along the sidewalls 222, 224 and the bottom 226 of the interconnect opening 220 defined by the ILD layer 210, the CESL 212 and the underlying components. In some embodiments, the copper-containing seed layer has a thickness of about 30 nm to about 40 nm, and the copper-containing body layer has a thickness of about 30 nm to about 40 nm. In some embodiments, the copper-containing seed layer is formed by an ALD process, and the copper-containing body layer is formed by a CVD process or a PVD process.

[0031] Go to Figure 2D , the process continues with a capping layer 240 being implemented to form the copper interconnect 230. The capping layer 240 covers the first barrier layer 234A, the second barrier layer 234B, and the copper body layer 236. In some embodiments, the capping layer 240 may only cover the copper body layer 236. The capping layer 240 has a thickness t4. In the depicted embodiment, the thickness t4 is less than or equal to about 4 nm. In some embodiments, the thickness t4 is about 2 nm to about 4 nm. The capping layer 240 includes a material that promotes adhesion between the copper interconnect 230 and a subsequently formed dielectric layer, such as CESL. For example, the capping layer 240 includes a metal (e.g., cobalt) and nitrogen, and therefore can be referred to as a metal nitride capping layer. In Figure 2DIn the embodiment, the capping layer 240 includes cobalt and nitrogen, and thus may be referred to as a cobalt nitride (CoN) capping layer. In some embodiments, the CoN capping layer includes a cobalt concentration of about 80 at % to about 90 at % and a nitrogen concentration of about 10 at % to about 20 at %. In some embodiments, the CoN layer is formed by depositing a cobalt layer over the copper interconnect 230, for example, by an ALD process and subjecting the cobalt layer to a nitrogen plasma treatment to incorporate (drive) nitrogen into the cobalt layer, thereby forming the CoN layer. In some embodiments, the ALD process or other suitable deposition process is performed with a cobalt-containing precursor such as biscyclopentadienyl cobalt (CoCp2), cyclopentadienyl cobalt dicarbonyl (CpCo(CO)2), bis(η-methylcyclopentadienyl) cobalt (Co(MeCp)2), dicobalt dicarbonyl hexacarbonyl tert-butyl acetylene (CCTBA), tricarbonyl nitroso cobalt (Co(CO)3NO), cyclopentadienyl isopropyl acetamido cobalt (Co(CpAMD)), bis(cyclopentadienyl) cobalt (Co(C5H5)2, CpCo(CO)2), bis(ethylcyclopentadienyl) cobalt (C 14 H 18 Cobalt tris(2,2,6,6-tetramethyl-3,5-heptanedioate), bis(pentamethylcyclopentadienyl)cobalt(C 20 H 30 Co), other suitable cobalt-containing precursors, or combinations thereof. In some embodiments, the nitrogen plasma treatment generates a nitrogen-containing plasma from a suitable nitrogen-containing precursor gas. The nitrogen-containing precursor may include nitrogen (N2), ammonia (NH3), hydrazine (N2H4), dimethylhydrazine, tert-butylhydrazine, tert-butylamine, other suitable nitrogen-containing precursors, or combinations thereof. In some embodiments, the nitrogen plasma treatment implements a flow rate of a nitrogen-containing precursor (e.g., NH3) of about 300sccm to about 5,000sccm. In some embodiments, the power used to generate the nitrogen-containing plasma is about 200W to about 700W. In some embodiments, the nitrogen plasma treatment is performed for about 3 seconds to about 100 seconds. In some embodiments, the pressure maintained in the process chamber during the nitrogen plasma treatment is about 1torr to about 15torr. In some embodiments, the temperature maintained in the process chamber during the nitrogen plasma treatment is about 150°C to about 450°C. In some embodiments, capping layer 240 may be formed by CVD, PVD, HDPCVD, MOCVD, RPCVD, PECVD, LPCVD, ALCVD, APCVD, PEALD, electroplating, electroless plating, other suitable deposition methods, or combinations thereof. The present invention further contemplates embodiments in which capping layer 240 includes other materials and / or combinations of materials that promote adhesion between copper interconnect 230 and subsequently formed dielectric layers, as well as embodiments in which copper interconnect 230 does not include capping layer 240 (in which case such process step is omitted from the fabrication of portion 200).

[0032] Go to Figure 2E, a CESL 250 is formed over the dielectric layer 202 and the copper interconnect 230 by a suitable deposition process such as CVD, PVD, ALD, HDPCVD, MOCVD, RPCVD, PECVD, LPCVD, ALCVD, APCVD, PEALD, electroplating, electroless plating, other suitable deposition methods, or combinations thereof. In the depicted embodiment, the CESL 250 is deposited on the ILD layer 210 and the capping layer 240 of the copper interconnect 230 such that the CESL 250 physically contacts the ILD layer 210 and the capping layer 240. The thickness t5 of the CESL 250 is greater than the thickness t4. In the depicted embodiment, the thickness t5 is less than or equal to about 3 nm. In some embodiments, the thickness t5 is about 1 nm to about 2.5 nm. In embodiments where the capping layer 240 is omitted from the copper interconnect 230, the CESL 250 physically contacts the copper body layer 236, the second barrier layer 234A, and the first barrier layer 234B. CESL 250 includes a material different from the material of copper interconnect 230 (e.g., the material of capping layer 240) and the material of a subsequently formed ILD layer to achieve etch selectivity during a subsequent etching process, such as those used to form interconnect openings that expose copper interconnect 230. In other words, CESL 250 and its surrounding layers will include materials with different etching sensitivities to a given etchant. For example, CESL 250 includes a material having an etch rate to the etchant that is less than the etch rate of the ILD layer to the etchant, so that the material of CESL 250 is used as an etch stop layer during etching of the upper ILD layer (including, for example, a low-k dielectric material). The material of CESL 250 is also selected to prevent copper from diffusing from the copper bulk layer 236 into surrounding layers, such as a subsequently formed ILD layer. In some embodiments, CESL 250 includes a metal and nitrogen, and thus may be referred to as a metal nitride CESL. The metal may include aluminum, hafnium, titanium, copper, manganese, vanadium, other suitable metals, or combinations thereof. In the depicted embodiment, the metal is aluminum and the CESL 250 is aluminum nitride (AlN) CESL. Aluminum in combination with nitrogen exhibits desirable copper diffusion barrier properties. The CESL 250 includes a nitrogen concentration that is greater than the nitrogen concentration of the capping layer 240. For example, the CESL 250 includes an aluminum concentration of about 52 at % to about 58 at % and a nitrogen concentration of about 42 at % to about 48 at %. As described below, as IC technology nodes shrink, the nitrogen concentration at the interface between the CESL 250 and the capping layer 240 may not adequately prevent copper diffusion, particularly copper diffusion associated with BEOL processes such as manufacturing portion 200. Therefore, the present invention provides an interconnect manufacturing process that increases the nitrogen concentration at the interface between the CESL 250 and the capping layer 240 and particularly increases the surface nitrogen concentration of the CESL 250 at the interface between the CESL 250 and the capping layer 240.

[0033] In some embodiments, ALD is performed to form the AlN CESL. Figure 4 According to various aspects of the present invention, Figure 1 FIG. 1 is a flow chart of an ALD process 300 performed at block 140 in FIG. At block 302, a workpiece is loaded into a process chamber, wherein the process chamber is prepared for an ALD process to form a contact etch stop layer, such as CESL 250, over a dielectric layer having interconnects disposed therein. At block 304, the workpiece is exposed to an aluminum-containing precursor (which may be referred to as an aluminum-containing pulse). At block 306, a purge process is performed to remove any remaining aluminum-containing precursor and any byproducts from the process chamber. At block 308, the workpiece is exposed to a nitrogen-containing precursor (which may be referred to as a nitrogen-containing pulse). At block 310, a purge process is performed to remove any remaining nitrogen-containing precursor and any byproducts from the process chamber. Blocks 304-310 constitute an ALD cycle, which includes two deposition phases (blocks 304 and 308) and two purge phases (blocks 306 and 310). Each ALD cycle is a self-limiting process, wherein less than or equal to about one monolayer comprising aluminum and nitrogen is deposited during each ALD cycle. The ALD cycle is repeated until the contact etch stop layer (such as CESL 250) reaches a desired (target) thickness. For example, at block 312, if the thickness of CESL 250 is equal to the target thickness (or within a given threshold of the target thickness), then the ALD process 300 ends at block 314. If the thickness of CESL 250 is not equal to the target thickness (or not within a given threshold of the target thickness), then the ALD process 300 returns to block 304 to begin another ALD cycle. In some embodiments, the ALD cycle (blocks 304-310) is repeated until CESL 250 has a thickness of about 1 nm to about 2.5 nm. Various parameters of the ALD process 300 may be adjusted to achieve desired growth characteristics, such as the flow rate of the deposition gas (including the aluminum-containing precursor gas, the nitrogen-containing precursor gas, and / or the carrier gas), the concentration (or dose) of the aluminum-containing precursor gas, the concentration (or dose) of the nitrogen-containing precursor gas, the concentration (or dose) of the carrier gas, the ratio of the concentration of the aluminum-containing precursor gas to the concentration of the carrier gas, the ratio of the concentration of the nitrogen-containing precursor gas to the concentration of the carrier gas, the power of a radio frequency (RF) source (e.g., used to generate a plasma during the deposition process), a bias voltage (e.g., applied to ignite a plasma during the deposition process), the pressure of the process chamber, the duration of the deposition process, other suitable deposition parameters, or combinations thereof. Additional steps may be provided before, during, and after the ALD process 300, and some of the steps described may be moved, replaced, or eliminated for additional embodiments of the ALD process 300.

[0034] At block 304, the aluminum-containing precursor may include trimethylaluminum (TMA), triethylaluminum (TEA), trimethylamine alane, aluminum chloride, dimethylaluminum hydride (DMAH), diethylaluminum ethoxide (DEAL), other aluminum-containing precursors, or combinations thereof. In such embodiments, during the aluminum-containing pulse, aluminum and / or other aluminum-containing precursors and / or reactive components are adsorbed onto the exposed surface of the ILD layer 210 and / or the capping layer 240 to form a layer including aluminum and / or other aluminum-containing precursors and / or reactive components. In some embodiments, the flow rate of the aluminum-containing precursor is about 6,000 sccm to about 8,000 sccm. In some embodiments, the duration of the aluminum-containing pulse is about 20 seconds to about 30 seconds. In some embodiments, the pressure maintained in the process chamber during the aluminum-containing pulse is about 2.0 torr to about 3.0 torr. In some embodiments, the temperature maintained in the process chamber during the aluminum-containing pulse is about 300° C. to about 350° C. In some embodiments, a carrier gas is used to deliver the aluminum-containing precursor to the process chamber. In some embodiments, the carrier gas is an inert gas, such as an argon-containing gas, a helium-containing gas, other suitable inert gases, or combinations thereof. In some embodiments, at block 306, the purge process is performed with an inert gas, such as an argon-containing gas, a helium-containing gas, other suitable inert gases, or combinations thereof. In some embodiments, the flow rate of the inert gas is about 4,000 sccm to about 5,000 sccm. In some embodiments, the duration of the purge process is about 20 seconds to about 30 seconds. In some embodiments, the pressure maintained in the process chamber during the purge process is about 2.0 torr to about 3.0 torr.

[0035] At block 308, the nitrogen-containing precursor may include nitrogen (N2), ammonia (NH3), hydrazine (N2H4), dimethylhydrazine, tert-butylhydrazine, tert-butylamine, other suitable nitrogen-containing precursors, or combinations thereof. In such embodiments, nitrogen and / or other nitrogen-containing precursors and / or reactive components interact with a layer including aluminum and / or other aluminum-containing precursors and / or reactive components to form less than or equal to about one monolayer including aluminum and nitrogen, such as an AlN layer (e.g., nitrogen adsorbed onto the layer including aluminum). In some embodiments, the flow rate of the nitrogen-containing precursor (e.g., NH3) is about 5,000 sccm to about 10,000 sccm. In some embodiments, the nitrogen-containing pulse duration is about 1 second to about 20 seconds. In some embodiments, the pressure maintained in the process chamber during the nitrogen-containing pulse is about 1 torr to about 3 torr. In some embodiments, the temperature maintained in the process chamber during the nitrogen-containing pulse is about 300°C to about 400°C. In some embodiments, a carrier gas is used to deliver the nitrogen-containing precursor to the process chamber. In some embodiments, the carrier gas is an inert gas, such as an argon-containing gas, a helium-containing gas, other suitable inert gases, or combinations thereof. In some embodiments, at block 310, the purge process is performed with an inert gas, such as an argon-containing gas, a helium-containing gas, other suitable inert gases, or combinations thereof. In some embodiments, the flow rate of the inert gas is about 2,000 sccm to about 7,000 sccm. In some embodiments, the purge process duration is about 1 second to about 10 seconds. In some embodiments, the pressure maintained in the process chamber during the purge process is about 1 torr to about 3 torr.

[0036] In some embodiments, CVD is performed to form the AlN CESL. For example, a workpiece is loaded into a process chamber, wherein the process chamber is prepared for a CVD process to form a contact etch stop layer, such as CESL250, over a dielectric layer in which an interconnect is disposed. In the process chamber, the workpiece is exposed to an aluminum-containing precursor and a nitrogen-containing precursor, which react with the exposed surfaces of the dielectric layer and the interconnect to form an aluminum- and nitrogen-containing layer. The workpiece is exposed to the aluminum-containing precursor and the nitrogen-containing precursor until the contact etch stop layer reaches a desired (target) thickness, such as a thickness of about 1 nm to about 2.5 nm. Thereafter, a purge process is performed to remove any remaining aluminum-containing precursors, nitrogen-containing precursors, and any byproducts from the process chamber. The aluminum-containing precursor may include TMA, TEA, trimethylamine aluminum alkane, aluminum chloride, DMAH, DEAL, other aluminum-containing precursors, or combinations thereof. The nitrogen-containing precursor may include N2, NH3, N2H4, dimethylhydrazine, tert-butylhydrazine, tert-butylamine, other suitable nitrogen-containing precursors, or combinations thereof. Various parameters of the CVD process may be adjusted to achieve desired growth characteristics (e.g., thickness of the AlN layer, aluminum concentration, and / or nitrogen concentration), such as the flow rate of the deposition gas (including the aluminum-containing precursor gas, the nitrogen-containing precursor gas, and / or the carrier gas), the concentration of the aluminum-containing precursor gas, the concentration of the nitrogen-containing precursor gas, the concentration of the carrier gas, the ratio of the concentration of the aluminum-containing precursor gas to the concentration of the nitrogen-containing precursor gas, the ratio of the concentration of the aluminum-containing precursor gas and / or the nitrogen-containing precursor gas to the concentration of the carrier gas, the power of the RF source, the bias voltage, the pressure of the process chamber, the duration of the deposition process, other suitable deposition parameters, or combinations thereof. In some embodiments, the flow rate of the aluminum-containing precursor is about 6,000 sccm to about 8,000 sccm, and the flow rate of the nitrogen-containing precursor is about 4,000 sccm to about 5,000 sccm. In some embodiments, the workpiece is exposed to the aluminum-containing precursor and the nitrogen-containing precursor for about 20 seconds to about 40 seconds. In some embodiments, the pressure maintained in the process chamber during the CVD process is about 2.0 torr to about 3.0 torr. In some embodiments, a nitrogen-containing precursor is used to generate a nitrogen-containing plasma that interacts with an aluminum-containing precursor and / or an exposed surface of the workpiece (e.g., when the CVD process is a PEALD process). In some embodiments, the nitrogen-containing plasma has a nitrogen concentration of about 70% to about 90%. In some embodiments, the power used to generate the low-frequency nitrogen-containing plasma is about 80 W to about 100 W. In some embodiments, the power used to generate the high-frequency nitrogen-containing plasma is 500 W to about 650 W. It should be noted that ALD is a type of CVD, except that ALD exposes the workpiece to an aluminum-containing precursor (or other metal-containing precursor depending on the desired composition of the CESL 250) and a nitrogen-containing precursor separately.

[0037] The interface region A between the CESL 250 and the copper interconnect 230 (hereinafter generally referred to as the CESL / copper interface A) includes the interface B between the CESL 250 and the capping layer 240 and the interface C between the capping layer 240 and the copper bulk layer 236. The present invention recognizes that stress-induced voids (stress migration) at the CESL / copper interface A have become a major factor in IC device reliability. For example, mechanical stress in the MLI component including the portion 200 can cause copper ions / atoms and copper vacancies to migrate along the grain boundaries 238 in the copper interconnect 230 to the CESL / copper interface A. As copper vacancies accumulate and copper atoms / ions diffuse into the MLI component (e.g., the dielectric layer of the MLI component), voids are formed at the CESL / copper interface A, which increases the resistance of the copper interconnect 230 and degrades IC performance. These voids can result in open circuits, depending on the location and / or size, and in some cases lead to copper interconnect failure and / or IC device failure. These mechanical stresses occur during the MLI component process (in other words, during the BEOL process) because of the mismatch in thermal expansion coefficients between the copper interconnect 230 and the surrounding dielectric materials. For example, because the copper interconnect 230 and the surrounding dielectric materials (e.g., the ILD layer 210, the CESL 212, and the subsequently formed ILD layer and / or CESL) have different thermal expansion coefficients, the copper interconnect 230 and the surrounding dielectric materials will expand and contract at different rates during the BEOL thermal cycle (e.g., heating cycle and / or cooling cycle), thereby causing stress differences in the portion 200 of the MLI component, thereby causing copper ions / atoms and / or copper vacancies to migrate to the CESL / copper interface A. Therefore, the present invention proposes to perform a nitrogen plasma treatment on the CESL 250 before forming the upper ILD layer, wherein the nitrogen plasma treatment is configured to increase the nitrogen concentration at the CESL / copper interface A and / or increase and / or enhance (strengthen) nitrogen bonding. Increasing the nitrogen concentration and / or nitrogen bonding at the CESL / copper interface A limits (and in some embodiments eliminates) the diffusion of copper ions / atoms and copper vacancies along the CESL / copper interface A, thereby preventing the accumulation of copper vacancies at the CESL / copper interface A and limiting the formation of stress-induced voids in the copper interconnect 230, as described in further detail below. In some embodiments, before the nitrogen plasma treatment, the CESL 250 may have a surface nitrogen concentration (e.g., at the interface B) of about 10 at % to about 15 at %, and it has been observed that with the scaling down of IC technology nodes, especially copper diffusion associated with BEOL processes (such as manufacturing portion 200), the CESL 250 does not provide sufficient copper diffusion barrier capabilities. In such embodiments, by performing the nitrogen plasma treatment described herein, the surface nitrogen concentration is increased to about 20 at % to about 30 at % after the nitrogen plasma treatment. It has been observed that such an increased surface nitrogen concentration can improve the copper diffusion barrier capabilities of the CESL 250 and reduce voids.

[0038] Go to Figure 2F , a nitrogen plasma treatment 255 is performed on the CESL 250, thereby obtaining a nitrogen-treated CESL 250'. The nitrogen-treated CESL 250' has a nitrogen concentration greater than the nitrogen concentration of the capping layer 240. For example, the nitrogen concentration is about 40 at%. In some embodiments, the ratio of the nitrogen concentration of the nitrogen-treated CESL 250' to the nitrogen concentration of the capping layer 240 is about 2:1 to about 5:1. In some embodiments, the nitrogen-treated CESL 250' has an aluminum concentration of about 52 at% to about 58 at% and a nitrogen concentration of about 42 at% to about 48 at%. It should be noted that in the depicted embodiment, the nitrogen concentration of the first barrier layer 234A (e.g., a TaN barrier layer) is less than the nitrogen concentration of the nitrogen-treated CESL 250' and greater than the nitrogen concentration of the capping layer 240. In some embodiments, the ratio of the nitrogen concentration of the nitrogen-treated CESL 250' to the nitrogen concentration of the first barrier layer 234A is about 1:1 to about 1.5:1. Figure 5 is a flow chart of a nitrogen plasma treatment process 350 according to various aspects of the present invention, which can be used as Figure 2F Neutralize and / or Figure 1 At block 352, a workpiece (including, for example, CESL 250 disposed above copper interconnect 230) is loaded into a process chamber, where the process chamber is prepared for a nitrogen plasma treatment process. In some embodiments, CESL 250 is deposited above copper interconnect 250 in the same process chamber, so that CESL deposition and nitrogen plasma treatment are performed in situ. At block 354, the workpiece is exposed to a nitrogen-containing plasma (which is referred to as a nitrogen-containing plasma pulse). The nitrogen-containing plasma bombards CESL 250 with plasma-excited nitrogen-containing species to drive nitrogen into CESL 250, particularly to CESL / copper interface A. Bombarding CESL 250 with plasma-excited nitrogen-containing species can also create, repair and / or enhance nitrogen bonds, such as NN bonds, Al-N bonds, Co-N bonds and / or Co-N-Al bonds. In some embodiments, the nitrogen-treated CESL 250' has more NN bonding, Al-N bonding, Co-N bonding, and / or Co-N-Al bonding than the CESL 250. For example, Figure 6Fourier transform infrared (FTIR) spectra obtained by performing FTIR spectroscopy on the AlN bulk film before and after a nitrogen plasma treatment, such as the nitrogen plasma treatment 255, are provided. In the FTIR spectrum, the absorption intensity of the absorption frequency / wavenumber corresponding to the Al-N bonding after the treatment (≈0.95) is greater than the absorption intensity of the absorption frequency / wavenumber corresponding to the Al-N bonding before the treatment (≈0.75), which indicates that the nitrogen plasma treatment increases the Al-N bonding in the AlN bulk film. Therefore, the nitrogen plasma treatment 255 can be performed to increase the Al-N bonding in the CESL 250. Various parameters of the nitrogen plasma treatment process 350 are adjusted to obtain a desired nitrogen concentration and / or nitrogen bonding in the CESL 250, such as the flow rate of the nitrogen-containing precursor gas, the flow rate of the carrier gas, the concentration of the nitrogen-containing precursor gas, the concentration of the carrier gas, the ratio of the concentration of the nitrogen-containing precursor gas to the concentration of the carrier gas, the power of the RF source, the bias voltage, the pressure of the process chamber, the duration of the nitrogen plasma treatment process, other suitable parameters, or combinations thereof. At block 356, if necessary, a purge process is performed to remove any remaining nitrogen-containing plasma and any byproducts from the process chamber. In some embodiments, at block 358, if the nitrogen-treated CESL 250' exhibits a target nitrogen concentration and / or target nitrogen incorporation characteristics, the nitrogen plasma treatment process 350 ends at block 360. If not, in some embodiments, blocks 354 and 356 may be repeated (i.e., one cycle) until the desired target nitrogen concentration and / or target nitrogen incorporation characteristics are achieved.

[0039] The nitrogen-containing plasma is generated from a nitrogen-containing precursor gas that includes diatomic nitrogen (N2) alone or includes diatomic nitrogen (N2) combined with NH3, other suitable nitrogen-containing precursor gases, or combinations thereof. In some embodiments, the nitrogen plasma treatment 255 may therefore be referred to as an N2 plasma treatment process. In such embodiments, the nitrogen-containing plasma includes nitrogen-excited neutral molecules (e.g., N2*), nitrogen-containing ionized molecules (e.g., N2+), nitrogen-containing atoms (e.g., N), ionized atoms (N+), or combinations thereof (generally collectively referred to as plasma-excited nitrogen-containing species). The nitrogen-containing plasma is "nitrogen-rich," generally referring to a nitrogen-containing plasma having a nitrogen concentration (N2) greater than about 50%. In some embodiments, the nitrogen-containing plasma includes a nitrogen concentration (N2) of about 70% to about 90% to effectively drive nitrogen into the CESL 250 toward interface B and / or drive nitrogen into the capping layer 240 toward interface B and / or interface C, thereby increasing the nitrogen concentration and / or nitrogen incorporation at the CESL / copper interface A. A nitrogen concentration in the nitrogen-containing plasma of less than or equal to about 30% may not sufficiently increase the nitrogen concentration and / or increase nitrogen incorporation at the CESL / copper interface A. In some embodiments, the power used to generate the low-frequency nitrogen-containing plasma is about 50 W to about 200 W. In some embodiments, the power used to generate the high-frequency nitrogen-containing plasma is about 500 W to about 650 W. In some embodiments, an RF bias voltage and / or a direct current (DC) bias voltage is applied to the workpiece to accelerate the nitrogen-containing plasma toward the workpiece. In some embodiments, the CESL 250 is exposed to the nitrogen-containing plasma for about 20 seconds to about 30 seconds. In some embodiments, the pressure maintained in the process chamber during the nitrogen plasma treatment 255 is about 1 torr to about 2 torr. In some embodiments, the temperature maintained in the process chamber during the nitrogen plasma treatment 255 is about 350° C. to about 450° C. In some embodiments, the workpiece is heated to a temperature of about 350° C. to about 450° C. during the nitrogen plasma treatment 255.

[0040] The nitrogen plasma treatment 255 drives nitrogen into the CESL 250, thereby increasing the surface nitrogen concentration and / or nitrogen incorporation at the CESL / copper interface A, particularly along the interface B. In some embodiments, after the nitrogen plasma treatment 255, the surface nitrogen concentration at the interface B of the nitrogen-treated CESL 250' is greater than the surface nitrogen concentration at the interface B of the CESL 250. For example, the nitrogen-treated CESL 250' has a surface nitrogen concentration at the interface B that is greater than or equal to about 20 at% (e.g., about 20 at% to about 30 at%), and the CESL 250 has a surface nitrogen concentration at the interface B that is less than about 20 at% (e.g., about 10 at% to about 15 at%), as shown in FIG. Figure 2FSurface nitrogen concentrations at interface B of less than about 20 at% may not adequately block copper diffusion, which has been observed to result in void formation within copper interconnect 230 during subsequent processing. In contrast, surface nitrogen concentrations at interface B of greater than or equal to about 20 at% may adequately reduce copper diffusion, and have been observed to reduce and in some cases eliminate void formation in copper interconnect 230 during subsequent processing. In some embodiments, the surface nitrogen concentration of CESL 250 at interface B is about 10 at% to about 15 at% before nitrogen plasma treatment 255, and the surface nitrogen concentration of nitrogen-treated CESL 250' at interface B is about 20 at% to about 25 at% after nitrogen plasma treatment 255. In some embodiments, the nitrogen concentration of nitrogen-treated CESL 250' has a gradient profile, wherein the nitrogen concentration increases along its thickness from the top surface of nitrogen-treated CESL 250' to interface B, such that nitrogen-treated CESL 250' has a maximum nitrogen concentration along interface B. In some embodiments, the nitrogen treated CESL 250' has other nitrogen concentration profiles, such as a gradient profile, a linear continuous profile, a nonlinear continuous profile, a bell-shaped curved profile, a sawtooth profile, or other suitable profiles. In some embodiments, the nitrogen plasma treatment 255 can increase the NN bonding and / or Al-N bonding such that the amount of NN bonding and / or Al-N bonding in the nitrogen treated CESL 250' (particularly along the interface B) is about 20% greater than the amount of NN bonding and / or Al-N bonding in the CESL 250. The nitrogen treated CESL 250' also exhibits different material properties than the CESL 250 (having a lower nitrogen concentration). For example, the dielectric constant and density of the nitrogen treated CESL 250' are greater than the dielectric constant and density of the CESL 250. In some embodiments, the nitrogen plasma treatment 255 increases the dielectric constant by about 0.2. For example, the nitrogen treated CESL 250' has a dielectric constant of about 7.2 to about 7.6 (e.g., about 7.4) compared to the CESL 250 having a dielectric constant less than or equal to about 7. In some embodiments, nitrogen plasma treatment 255 increases density by about 0.10. For example, nitrogen treated CESL 250' has a density of about 2.70 to about 2.80 (eg, about 2.75) compared to CESL 250 having a density of about 2.60 to about 2.70 (eg, about 2.65).

[0041] The nitrogen plasma treatment 255 may also drive nitrogen into the capping layer 240, thereby increasing the nitrogen concentration along the interface C. For example, in some embodiments, after the nitrogen plasma treatment 255, the capping layer 240 has a cobalt concentration of about 80 at % to about 90 at % and a nitrogen concentration of about 10 at % to about 20 at %. In some embodiments, after the nitrogen plasma treatment 255, the nitrogen concentration of the capping layer 240 has a gradient profile, wherein the nitrogen concentration decreases along its thickness from the interface B to the interface C, such that the capping layer 240 has a maximum nitrogen concentration along the interface B. In some embodiments, the capping layer 240 has other nitrogen concentration profiles, such as a gradient profile, a linear continuous profile, a nonlinear continuous profile, a bell-shaped curved profile, a sawtooth profile, or other suitable profiles. In some embodiments, the combined nitrogen concentration profile of the nitrogen treated CESL 250' and the capping layer 240 increases along the thickness of the CESL / copper interface A from the top surface of the nitrogen treated CESL 250' to a peak region near the interface B, and then decreases along the thickness of the CESL / copper interface A from the peak region to the bottom surface of the capping layer 240 at the interface C, such as Figure 2F 250′ and the capping layer 240. In such an embodiment, the nitrogen concentration at the CESL / copper interface A can be described as having a bell-shaped curved distribution, wherein the peak of the bell-shaped distribution is near the interface B. In some embodiments, the nitrogen plasma treatment 255 can increase NN bonding and / or Co-N bonding, such that the amount of NN bonding and / or Co-N bonding in the capping layer 240 after the nitrogen plasma treatment 255 (particularly along the interface B) is greater than the amount of NN bonding and / or Co-N bonding in the capping layer 240 before the nitrogen plasma treatment 255. In some embodiments, the nitrogen plasma treatment 255 creates, repairs, and / or enhances Co-N-Al bonding between the capping layer 240 and the nitrogen-treated CESL 250′, for example, increasing the amount of Co-N-Al bonding at the interface B in the nitrogen-treated CESL 250′ compared to the amount of Co-N-Al bonding at the interface B in the CESL 250.

[0042] It should be noted that the material of CESL 250 is selected to minimize metal diffusion while also providing sufficient etch stop functionality during the formation of the interconnect opening to expose the copper interconnect 230 during subsequent processing. The material of CESL 250 is also selected to minimize the parasitic capacitance effects caused by the MLI functional portion 200, which cannot be ignored in smaller IC technology nodes. The present invention has recognized that after a nitrogen plasma treatment such as nitrogen plasma treatment 255, when etching low-k dielectric materials, metal nitrides (in the depicted embodiment, aluminum nitride) perform well as etch stops while also providing excellent copper diffusion barrier properties at thicknesses desired for smaller IC technology nodes. For example, while silicon nitride can satisfactorily limit (or prevent) metal diffusion, such as copper diffusion, the thickness (e.g., about 10 nm to about 20 nm) desired for silicon nitride to achieve the desired metal diffusion barrier function and thus avoid the formation of voids at the CESL / interconnect interface is too large for IC technology nodes of 20 nm and below. In contrast, after nitrogen plasma treatment, metal nitrides can reliably provide the desired metal diffusion barrier and etch stop functions at a thickness of less than or equal to about 3 nm, which allows for seamless integration into IC technology nodes of 20 nm and below and minimizes the parasitic capacitance effects of ESL on MLI functions.

[0043] Go to Figure 2G, the process continues, CESL 260 is formed over CESL 250, and CESL 262 is formed over CESL 260, thereby forming a multilayer CESL 265 including CESL 250, CESL 260, and CESL 262. Then, an ILD layer 270 is formed over CESL 265, particularly on CESL 262. In some embodiments, CESL 260 has a thickness t6 of about 3 nm to about 9 nm, and CESL 262 has a thickness t7 of about 2 nm to about 5 nm. CESL 260 and CESL 262 include different materials from ILD layer 270 to achieve etching selectivity in subsequent etching processes (such as those used to form interconnect openings that expose copper interconnect 230). In other words, CESL 260 and CESL 262 and the layers surrounding them will include materials with different etching sensitivities to a given etchant. For example, CESL 260 and CESL 262 include a material having an etch rate to an etchant that is less than an etch rate to an etchant of a material of the ILD layer, such that the material of CESL 260 and / or CESL 262 serves as an etch stop layer during etching of an overlying ILD layer (including, for example, a low-k dielectric material). CESL 260 and CESL 262 also include a material that promotes adhesion between CESL 250 and ILD layer 270. In some embodiments, CESL 260 and CESL 262 include a material that is substantially free of nitrogen. For example, CESL 260 and CESL 262 include a material having a nitrogen concentration of less than about 1 at%. CESL 260 includes oxygen and / or carbon, and in some embodiments includes silicon. For example, CESL 260 includes SiO, SiC, SiCO, other materials containing oxygen and / or carbon, or combinations thereof. In the depicted embodiment, CESL 260 includes oxygen-doped silicon carbide (SiCO, also referred to as ODC). CESL 262 includes metal and oxygen, and thus may be referred to as a metal oxide layer. The metal may include aluminum, hafnium, titanium, copper, manganese, vanadium, other suitable metals, or combinations thereof. In the depicted embodiment, the metal is aluminum, and CESL 262 is an aluminum oxide (AlO) CESL. In some embodiments, CESL 262 includes an aluminum concentration of about 55 at % to about 65 at % and an oxygen concentration of about 35 at % to about 45 at %. CESL 260 and / or CESL 262 are formed by CVD, PVD, ALD, HDPCVD, MOCVD, RPCVD, PECVD, LPCVD, ALCVD, APCVD, PEALD, FCVD, other suitable deposition methods, or combinations thereof.After depositing CESL 260 and / or CESL 262 , a CMP process and / or other planarization process may be performed so that CESL 260 and / or CESL 262 have a substantially planar surface.

[0044] The ILD layer 270 is similar to the ILD layer 210. For example, the ILD layer 270 is formed by a deposition process such as CVD, PVD, ALD, HDPCVD, MOCVD, RPCVD, PECVD, LPCVD, ALCVD, APCVD, PEALD, FCVD, other suitable deposition methods, or combinations thereof. The ILD layer 270 includes a dielectric material including, for example, silicon oxide, carbon-doped silicon oxide, silicon nitride, silicon oxynitride, TEOS, PSG, BSG, BPSG, FSG, (Applied Materials, Santa Clara, California), xerogel, aerogel, amorphous fluorinated carbon, parylene, BCB-based dielectric materials, SiLK (Dow Chemical Company, Midland, Michigan), polyimide, other suitable dielectric materials, or combinations thereof. In some embodiments, the ILD layer 270 includes a low-k dielectric material. For example, in the depicted embodiment, the ILD layer 270 includes an ELK dielectric material, such as silicon dioxide (SiO2) (e.g., porous silicon dioxide), silicon carbide (SiC) and / or a carbon-doped oxide (e.g., a SiCOH-based material (having, for example, a Si-CH3 bond)), each of which is adjusted / configured to exhibit a dielectric constant of less than about 2.5. In some embodiments, the ILD layer 270 may include a multilayer structure having a plurality of dielectric materials. In some embodiments, the ILD layer 270 has a thickness t8 of about 60 nm to about 90 nm. After the ILD layer 270 is deposited, a CMP process and / or other planarization process may be performed so that the ILD layer 270 has a substantially flat surface.

[0045] Go to Figure 2H , an interconnect opening 280 is formed in the ILD layer 270 and the CESL 265 (which may be collectively referred to as a dielectric layer) by a patterning process. In the depicted embodiment, the interconnect opening 280 vertically extends through the ILD layer 270 and the CESL 265 to expose the copper interconnect 230, and in particular, the capping layer 240 of the copper interconnect 230. The interconnect opening 280 includes a sidewall 282 (defined by the ILD layer 270 and the CESL 265), a sidewall 284 (defined by the ILD layer 270 and the CESL 265), and a bottom 286 (defined by the copper interconnect 230) extending between the sidewall 282 and the sidewall 284. Figure 2H, the interconnect opening 280 has a trapezoidal shape, but the present invention contemplates interconnect openings 280 having other shapes (such as a rectangle). The sidewalls of the interconnect opening 280 are tapered so that the width of the interconnect opening 280 decreases along the thickness of the dielectric layer, and the width of the interconnect opening 280 exposing the copper interconnect 230 is less than the width of the interconnect opening 280 at the top surface of the ILD layer 270. The patterning process for forming the interconnect opening 280 can be similar to the patterning process for forming the interconnect opening 220. For example, the patterning process includes: performing a photolithography process to form a patterned mask layer 288 (having an opening 289 therein) over the ILD layer 270; and performing an etching process to transfer the pattern defined in the patterned mask layer 288 to the ILD layer 270 and the CESL 265. The photolithography process may include: forming a resist layer on the ILD layer 270 (e.g., by spin coating); performing a pre-exposure bake process; performing an exposure process using a mask; performing a post-exposure bake process; and performing a development process. During the exposure process, the resist layer is exposed to radiation energy, wherein the mask blocks, transmits and / or reflects radiation to the resist layer, depending on the mask and / or the mask pattern of the mask type, so that the image is projected onto the resist layer corresponding to the mask pattern. Because the resist layer is sensitive to radiation energy, the exposed portion of the resist layer undergoes chemical changes, and during the development process, the exposed (or non-exposed) portion of the resist layer dissolves, depending on the characteristics of the resist layer and the characteristics of the developer used in the development process. After development, the patterned resist layer includes a resist pattern corresponding to the mask. Optionally, the exposure process can be implemented or replaced by other methods such as maskless lithography, electron beam writing and / or ion beam writing. In some embodiments, the patterned resist layer is a patterned mask layer 288. In such an embodiment, the patterned resist layer is used as an etching mask to remove the portion of the ILD layer 270 and / or CESL 265 exposed by the opening 289, thereby exposing the copper interconnect 230. In some embodiments, before forming the resist layer, a patterned resist layer is formed over the mask layer formed over the ILD layer 270, and the patterned resist layer is used as an etching mask to remove portions of the mask layer forming the ILD layer 270, thereby forming a patterned mask layer 288. In such embodiments, the patterned mask layer is used as an etching mask to remove portions of the ILD layer 270 and / or the CESL 265 exposed by the opening 289, thereby exposing the copper interconnect 230. In some embodiments, after the etching process, the patterned mask layer 288 is removed from over the ILD layer 270 (in some embodiments, by a resist stripping process). In some embodiments, the patterned mask layer 288 is removed during etching of the ILD layer 270, the CESL 262, the CESL 260, and / or the nitrogen-treated CESL 250'.

[0046] In some embodiments, the etching process is a multi-step etching process including a first etching step for selectively etching the ILD 270 and a second etching step for selectively etching the CESL 265. For example, the first etching step is configured to remove the ILD layer 270 but not remove or substantially remove the CESL 265, so that the first etching stops when reaching the CESL 265, and the second etching step is configured to remove the CESL 265 but not remove or substantially remove the ILD 270 and the copper interconnect 230, so that the second etching stops when reaching the copper interconnect 230 (especially the capping layer 240). Various etching parameters may be adjusted to achieve selective etching of the ILD layer 270 and the CESL 265, such as etchant composition, etching temperature, etching solution concentration, etching time, etching pressure, source power, RF bias voltage, RF bias power, etchant flow rate, other suitable etching parameters, or combinations thereof. For example, for the first etching step, an etchant is selected for the etching process that etches the material of the ILD layer 270 (in the depicted embodiment, an ELK material including silicon and oxygen) at a higher rate than the material of the CESL 265 (in the depicted embodiment, a metal oxide, oxygen-doped silicon carbide, and a metal nitride) (i.e., the etchant has a high etching selectivity with respect to the material of the ILD layer 270). For the second etching step, an etchant is selected for the etching process that etches the material of the CESL 265 at a higher rate than the material of the ILD layer 270 (i.e., the etchant has a high etching selectivity with respect to the material of the CESL 265). In some embodiments, the first etching step and / or the second etching step can be configured to slightly overetch. In such an embodiment, the first etching step can partially etch the CESL 265 and / or the second etching step can partially etch the capping layer 240. In some embodiments, the second etching step may include multiple steps for selectively etching each layer of the CESL 265 (such as the CESL 262, the CESL 260, and the nitrogen-treated CESL 250'), wherein each step is configured to selectively etch a corresponding layer of the CESL 265. The etching process is a dry etching process, a wet etching process, other suitable etching processes, or a combination thereof. The dry etching process may be implemented with a hydrogen-containing etching gas, an oxygen-containing etching gas, a fluorine-containing etching gas (e.g., CF4, SF6, CH2F2, CHF3, and / or C2F6), a chlorine-containing etching gas (e.g., Cl2, CHCl3, CCl4, and / or BCl3), a bromine-containing etching gas (e.g., HBr and / or CHBr3), an iodine-containing etching gas, other suitable etching gases and / or etching plasmas, or a combination thereof. The wet etching process may be implemented with a wet etchant solution including DHF, KOH, NH4OH, NH3, HF, HNO3, CH3COOH, H2O, other suitable wet etchant solution components, or a combination thereof.In some embodiments, the first etching step is a dry etching process using an etching gas including C4F8 and Ar to selectively etch the ILD layer 270. In such embodiments, the ratio of C4F8 to Ar, the etching temperature, and / or the RF power may be adjusted to achieve a desired etching selectivity. In some embodiments, the first etching step is a wet etching process using a wet etchant solution including HF to selectively etch the ILD layer 270. In such embodiments, the etching temperature and / or the etching time may be adjusted to achieve a desired etching selectivity. In some embodiments, the second etching step is a dry etching process using an etching gas including Cl2, CHCl2, and / or N2 to selectively etch the CESL 265. In such embodiments, the ratio of Cl2 to CHCl2 and / or N2, the etching temperature, and / or the RF power may be adjusted to achieve a desired etching selectivity.

[0047] Go to Fig.2I , interconnect 290 is formed in interconnect opening 280. Because the nitrogen-treated CESL 250' of the CESL / copper interface A of portion 200 is larger than the CESL (such as CESL) not treated with nitrogen. Figure 3 The CESL 250 in the portion 200′ depicted in FIG. 2 has a higher surface nitrogen concentration and greater (stronger) nitrogen bonding, so the CESL / copper interface A of the portion 200 limits (or prevents) copper diffusion during the BEOL process, which typically causes copper vacancies to accumulate at the CESL / copper interface A, thereby preventing the formation of voids 298 at the CESL / copper interface A, such as Figure 3 This phenomenon is further described by Fig. 7A and Figure 7B It is shown that Fig. 7A is a partial schematic top view of a copper bulk layer 236 of a copper interconnect 230 when a nitrogen treated CESL 250' is formed over the copper interconnect 230, and Figure 7B 2 is a partial schematic top view of the copper bulk layer 236 of the copper interconnect 230 when the CESL 250 is formed over the copper interconnect 230 (without nitrogen plasma treatment). Without nitrogen treatment of the CESL located above the copper interconnect 230, copper diffusion that occurs during BEOL processing can lead to the accumulation of copper vacancies and Figure 7BA void is induced in the copper body layer 236 shown. In the depicted embodiment, the copper interconnect 230 is a through-hole of the MLI component (in other words, an interconnect that connects two different layers of the MLI component), and the interconnect 290 is a conductive line of the MLI component. For example, the copper interconnect 230 is a through-hole that connects the conductive line of the first metal layer of the MLI component (e.g., the metal one (M1) layer below the copper interconnect 230) to the interconnect 290 of the second metal layer of the MLI component (e.g., the metal two (M2) layer above the copper interconnect 230). In another example, the copper interconnect 230 is a through-hole that connects the source / drain contact or gate of the first metal layer of the MLI component (e.g., the device contact, the metal zero (M0) layer below the copper interconnect 230) to the interconnect 290 of the second metal layer of the MLI component (e.g., the metal one (M1) layer above the copper interconnect 230). In some embodiments, the interconnect 290 is similar to the copper interconnect 230. For example, the interconnect 290 may include a diffusion barrier layer 292 (having a first barrier layer 294A and a second barrier layer 294B) and a copper body layer 296 disposed over the diffusion barrier layer 292. The diffusion barrier layer 292 is disposed on the sidewalls 282, 284 and the bottom 286 of the interconnect opening 280 defined by the ILD layer 270, the CESL 265 and the copper interconnect 230. The diffusion barrier layer 292, the first barrier layer 294A, the second barrier layer 294B and the copper body layer 296 are similar to the diffusion barrier layer 232, the first barrier layer 234A, the second barrier layer 234B and the copper body layer 296, respectively, all of which have been described above. Optionally, the interconnect 290 is configured differently from the copper interconnect 230 and includes different layers and / or materials than the copper interconnect 230. Therefore, the present invention contemplates various material configurations and / or compositions of the interconnect 290. Thereafter, manufacturing can continue with manufacturing additional portions of the MLI functionality.

[0048] Go to Figure 8 , Figure 8is a partial schematic diagram of part or all of an IC device 500 according to various aspects of the present invention. The IC device 500 may be included in a microprocessor, a memory, and / or other integrated circuit devices. In some embodiments, the IC device 500 is part of an IC chip, part of a system on a chip (SoC), or part thereof, and includes various passive and active microelectronic devices, such as resistors, capacitors, inductors, diodes, p-type field effect transistors (PFETs), n-type field effect transistors (NFETs), metal oxide semiconductor field effect transistors (MOSFETs), complementary metal oxide semiconductor (CMOS) transistors, bipolar junction transistors (BJTs), laterally diffused MOS (LDMOS) transistors, high voltage transistors, high frequency transistors, other suitable components, or combinations thereof. The transistors may be planar transistors or multi-gate transistors, such as fin FETs (FinFETs). For clarity, the schematic diagram has been simplified. Figure 8 Additional components may be added to the IC device 500, and some of the components described below may be replaced, modified, or eliminated in other embodiments of the IC device 500.

[0049] IC device 500 includes device substrate 206, which includes substrate (wafer) 510. In the depicted embodiment, substrate 510 includes silicon. Alternatively or additionally, substrate 510 includes another element semiconductor, such as germanium; a compound semiconductor, such as silicon carbide, gallium arsenide, gallium phosphide, indium phosphide, indium arsenide and / or indium antimonide; an alloy semiconductor, such as silicon germanium (SiGe), GaAsP, AlInAs, AlGaAs, GaInAs, GaInP and / or GaInAsP; or a combination thereof. Optionally, substrate 510 is a semiconductor-on-insulator substrate, such as a silicon-on-insulator (SOI) substrate, a silicon-germanium-on-insulator (SGOI) substrate, or a germanium-on-insulator (GOI) substrate. The semiconductor-on-insulator substrate can be manufactured using isolation by implantation of oxygen (SIMOX), wafer bonding, and / or other suitable methods. Substrate 510 may include doped regions formed by ion implantation processes, diffusion processes, and / or other suitable doping processes, depending on the design requirements of IC device 500. In some embodiments, substrate 510 includes a p-type doped region (e.g., a p-type well) doped with a p-type dopant such as boron, indium, other p-type dopants, or a combination thereof. In some embodiments, substrate 510 includes an n-type doped region (e.g., an n-type well) doped with an n-type dopant such as phosphorus, arsenic, other n-type dopants, or a combination thereof. In some embodiments, substrate 510 includes a doped region formed by a combination of a p-type dopant and an n-type dopant. The various doped regions may be formed directly on and / or in substrate 510, for example, to provide a p-well structure, an n-well structure, a double-well structure, a raised structure, or a combination thereof.

[0050] Isolation components may be formed above and / or in the substrate 510 to isolate various regions of the IC device 500, such as device regions. For example, the isolation components define active device regions and / or passive device regions and electrically isolate the active device regions and / or passive device regions from each other. The isolation components include silicon oxide, silicon nitride, silicon oxynitride, other suitable isolation materials (e.g., including silicon, oxygen, nitrogen, carbon or other suitable isolation components) or a combination thereof. The isolation components may include different structures, such as shallow trench isolation (STI) structures, deep trench isolation (DTI) structures and / or local oxidation of silicon (LOCOS) structures. In some embodiments, the isolation components are formed by etching a trench (or multiple trenches) in the substrate 510 and filling the trenches with insulating materials (e.g., using a CVD process or a spin-on-glass process). A CMP process may be implemented to remove excess insulating materials and / or planarize the top surface of the isolation components. In some embodiments, the isolation feature may be formed by depositing an insulating material over the substrate 510 and etching back the insulating material layer after forming the fin structure (in some embodiments, such that the insulating material layer fills the gaps (trench) between the fin structures). In some embodiments, the isolation feature includes a multilayer structure filling the trench, such as a bulk dielectric layer disposed over a liner dielectric layer, wherein the bulk dielectric layer and the liner dielectric layer include materials depending on design requirements (e.g., a bulk dielectric layer including silicon nitride disposed over a liner dielectric layer including thermal oxide). In some embodiments, the isolation feature includes a dielectric layer disposed over a doped liner layer (including, for example, BSG or PSG).

[0051] The device substrate 206 also includes various gate structures, such as gate structure 520A, gate structure 520B, and gate structure 520C, disposed above the substrate 510. Each of the gate structures 520A-520C is bonded to a corresponding channel region defined between a corresponding source region and a corresponding drain region, so that during operation, current can flow between the corresponding source / drain regions. In some embodiments, the gate structures 520A-520C are formed above the fin structure, so that each of the gate structures 520A-520C wraps around a portion of the fin structure and is between a corresponding source region and a corresponding drain region (collectively referred to as a source / drain region) of the fin structure. Each of the gate structures 520A-520C includes a metal gate (MG) stack, such as a metal gate stack 522. The metal gate stack 522 is formed by a deposition process, a photolithography process, an etching process, other suitable processes, or a combination thereof. The metal gate stack 522 is manufactured according to a gate-last process, a gate-first process, or a hybrid gate-last / gate-first process. In a gate-last process embodiment, the gate structures 520A-520C include a dummy gate stack that is subsequently replaced with a metal gate stack 522. The dummy gate stack includes, for example, an interface layer (including, for example, silicon oxide) and a dummy gate electrode layer (including, for example, polysilicon). In such an embodiment, the dummy gate electrode layer is removed to form an opening (trench) that is subsequently filled with the metal gate stack 522.

[0052] The metal gate stack 522 is configured to achieve the desired function according to the design requirements of the IC device 500. In some embodiments, the metal gate stack 522 includes a gate dielectric (e.g., a gate dielectric layer) and a gate electrode (e.g., a work function layer and a bulk conductive layer). The metal gate stack 522 may include many other layers, for example, a capping layer, an interface layer, a diffusion layer, a barrier layer, a hard mask layer, or a combination thereof. In some embodiments, the gate dielectric layer is disposed above the interface layer (including a dielectric material such as silicon oxide), and the gate electrode is disposed above the gate dielectric layer. The gate dielectric layer includes a dielectric material such as silicon oxide, a high-k dielectric material, other suitable dielectric materials, or a combination thereof. Examples of high-k dielectric materials include hafnium dioxide (HfO2), HfSiO, HfSiON, HfTaO, HfTiO, HfZrO, zirconium oxide, aluminum oxide, hafnium dioxide-aluminum oxide (HfO2-Al2O3) alloy, other suitable high-k dielectric materials, or a combination thereof. High-k dielectric materials generally refer to dielectric materials with a high dielectric constant (k value) relative to the dielectric constant of silicon dioxide (k≈3.9). For example, a high-k dielectric material has a dielectric constant greater than about 3.9. In some embodiments, the gate dielectric layer is a high-k dielectric layer. The gate electrode includes a conductive material such as polysilicon, aluminum, copper, titanium, tantalum, tungsten, molybdenum, cobalt, TaN, NiSi, CoSi, TiN, WN, TiAl, TiAlN, TaCN, TaC, TaSiN, other conductive materials, or combinations thereof. In some embodiments, the work function layer is a conductive layer adjusted to have a desired work function (such as an n-type work function or a p-type work function), and the conductive body layer is a conductive layer formed above the work function layer. In some embodiments, the work function layer includes an n-type work function material, such as Ti, silver, manganese, zirconium, TaAl, TaAlC, TiAlN, TaC, TaCN, TaSiN, other suitable n-type work function materials, or combinations thereof. In some embodiments, the work function layer includes a p-type work function material, such as ruthenium, Mo, Al, TiN, TaN, WN, ZrSi2, MoSi2, TaSi2, NiSi2, WN, other suitable p-type work function materials, or combinations thereof. The bulk (or filler) conductive layer includes a suitable conductive material, such as Al, W, and / or Cu. The bulk conductive layer may additionally or jointly include polysilicon, Ti, Ta, metal alloys, other suitable materials, or combinations thereof.

[0053] The gate structures 520A-520C also include a gate spacer 236 disposed adjacent to the metal gate stack 522 (e.g., along its sidewalls). The gate spacer 236 is formed by any suitable process and includes a dielectric material. The dielectric material may include silicon, oxygen, carbon, nitrogen, other suitable materials, or combinations thereof (e.g., silicon oxide, silicon nitride, silicon oxynitride, or silicon carbide). For example, in the depicted embodiment, a dielectric layer including silicon and nitrogen (such as a silicon nitride layer) may be deposited over the substrate 510 and then anisotropically etched to form the gate spacer 236. In some embodiments, the gate spacer 236 includes a multilayer structure, such as a first dielectric layer including silicon nitride and a second dielectric layer including silicon oxide. In some embodiments, more than one set of spacers (such as sealing spacers, offset spacers, sacrificial spacers, dummy spacers, and / or main spacers) are formed adjacent to the metal gate stack 522. In such an embodiment, each set of spacers may include materials having different etching rates. For example, a first dielectric layer (e.g., silicon oxide) including silicon and oxygen may be deposited over the substrate 510 and then anisotropically etched to form a first spacer group adjacent to the metal gate stack 522 (or in some embodiments, a dummy metal gate stack), and a second dielectric layer (e.g., silicon nitride) including silicon and nitrogen may be deposited over the substrate 510 and then anisotropically etched to form a second spacer group adjacent to the first spacer group. Before and / or after forming the gate spacers 236, implantation, diffusion, and / or annealing processes may be performed to form lightly doped source and drain (LDD) features and / or heavily doped source and drain (HDD) features in the substrate 510, depending on the design requirements of the IC device 500.

[0054] Epitaxial source features and epitaxial drain features (referred to as epitaxial source / drain features) such as epitaxial source / drain features 530 are disposed in source / drain regions of substrate 510. Gate structures 520B are interposed between epitaxial source / drain features 530 such that a channel region is defined between epitaxial source / drain features 530. In some embodiments, gate structures 520B and epitaxial source / drain features 530 form part of a transistor of IC device 500. In some embodiments, semiconductor material is epitaxially grown on and / or from substrate 510 to form epitaxial source / drain features 530 over source / drain regions of substrate 510. In some embodiments, an etching process is performed on the source / drain regions of substrate 510 to form source / drain recesses, wherein epitaxial source / drain features 530 are grown to fill the source / drain recesses. In some embodiments, where the substrate 510 represents part of a fin structure, the epitaxial source / drain features 530 wrap around the source / drain regions of the fin structure and / or are disposed in source / drain recesses of the fin structure, depending on the design requirements of the IC device 500. The epitaxial process may implement a CVD deposition technique (e.g., vapor phase epitaxy (VPE), ultra-high vacuum CVD (UHV-CVD), LPCVD, and / or PECVD), molecular beam epitaxy, other suitable SEG processes, or combinations thereof. The epitaxial process may use gaseous and / or liquid precursors that interact with the components of the substrate 510. The epitaxial source / drain features 530 are doped with n-type dopants and / or p-type dopants. In some embodiments, the epitaxial source / drain features 530 are epitaxial layers including silicon and / or carbon, wherein the silicon-containing epitaxial layer or the silicon-carbon-containing epitaxial layer is doped with phosphorus, other n-type dopants, or combinations thereof. In some embodiments, the epitaxial source / drain component 530 is an epitaxial layer including silicon and germanium, wherein the epitaxial layer including silicon and germanium is doped with boron, other p-type dopants, or a combination thereof. In some embodiments, the epitaxial source / drain component 530 includes materials and / or dopants that achieve desired tensile stress and / or compressive stress in the channel region. In some embodiments, the epitaxial source / drain component 530 is doped by adding impurities to the source material of the epitaxial process during deposition. In some embodiments, the epitaxial source / drain component 530 is doped by an ion implantation process after the deposition process. In some embodiments, an annealing process is performed to activate dopants in the epitaxial source / drain component 530 and / or other source / drain regions (e.g., HDD regions and / or LDD regions) of the IC device 500.

[0055] The MLI component 400 is disposed over the device substrate 206 and includes one or more ILD layers and / or CESL. Figure 8, the MLI component 400 includes an ILD layer 552 (ILD-0) disposed over a substrate 510, an ILD layer 554 (ILD-1) disposed over the ILD layer 552, an ILD layer 556 (ILD-2) disposed over the ILD layer 554, and an ILD layer 558 (ILD-3) disposed over the ILD layer 556. The MLI component 400 also includes a CESL 562 disposed between the ILD layer 552 and the ILD layer 554, a CESL 564 disposed between the ILD layer 554 and the ILD layer 556, and a CESL 566 disposed between the ILD layer 556 and the ILD layer 558. Device-level contacts 570, device-level contacts 572, device-level contacts 574, vias 580, vias 582, vias 584, wires 590, wires 592, and wires 594 are disposed in the ILD layers 552-558 and the CESLs 562-566 to form an interconnect structure. One or more of the ILD layers 552-558 are configured and fabricated similarly to the ILD layers 210 and / or the ILD layers 270 described in detail above. One or more of the CESLs 562-566 are configured and fabricated similarly to the CESLs 265, the nitrogen-treated CESLs 250', the CESLs 260, the CESLs 262, and / or the CESLs 212 described in detail above. One or more of the device-level contacts 570-574, vias 580-584, and wires 590-594 are configured and fabricated similarly to the copper interconnects 230 and / or the interconnects 290. For example, in some embodiments, vias 580-584 are copper interconnects, such as copper interconnect 230, and CESL 566 is configured similar to CESL 265 and includes nitrogen treated CESL 250'. Thus, during fabrication of MLI component 400, the formation of voids is limited and / or prevented at the interface between vias 580-584 and CESL 566 and / or corresponding conductive lines 590-594. IC device 500, such as a transistor of IC device 500, exhibits improved performance.

[0056] Device-level contacts 570-574 (also referred to as local interconnects or local contacts) electrically and / or physically couple IC device components to other conductive components of the MLI component 400. For example, the device-level contact 570 is a metal-to-polysilicon (MP) contact, which generally refers to a contact to a gate structure, such as a polysilicon gate structure or a metal gate structure. In the depicted embodiment, the device-level contact 570 is disposed on the gate structure 520B (particularly the metal gate stack 522), such that the device-level contact 570 connects the gate structure 520B to the via 580. In a further example, the device-level contact 572 and the device-level contact 574 are metal-to-device (MD) contacts, which generally refer to contacts to conductive regions (such as source / drain regions) of the IC device 500. For example, device-level contacts 572 and device-level contacts 574 are disposed on respective epitaxial source / drain features 530 such that device-level contacts 572 and device-level contacts 574 connect epitaxial source / drain features 530 to vias 582 and 584, respectively. Vias 580-584 electrically and / or physically couple conductive features of MLI feature 400 to one another. For example, via 580 is disposed on device-level contact 570 such that via 580 connects device-level contact 570 to conductive line 590; via 582 is disposed on device-level contact 572 such that via 582 connects device-level contact 572 to conductive line 592; and via 584 is disposed on device-level contact 574 such that via 584 connects device-level contact 574 to conductive line 594.

[0057] The present invention provides many different embodiments. Disclosed herein is an interconnect structure exhibiting reduced copper vacancy accumulation along the interface between CESL and an interconnect and a method for manufacturing such an interconnect structure. An exemplary interconnect structure of a multilayer interconnect component of an integrated circuit device includes a first interlayer dielectric (ILD) layer, a second ILD layer disposed above the first ILD layer, a first copper interconnect disposed in the first ILD layer, and a second copper interconnect disposed in the second ILD layer. An aluminum nitride contact etch stop layer (CESL) is disposed between a portion of the first copper interconnect and the second ILD layer and between the first ILD layer and the second ILD layer. The surface nitrogen concentration at the interface between the aluminum nitride CESL and the first copper interconnect is greater than or equal to about 20at%. The second copper interconnect extends through the aluminum nitride CESL to physically contact the first copper interconnect. In some embodiments, the density of the aluminum nitride CESL is about 2.70g / cm 3 To about 2.80g / cm 3In some embodiments, the aluminum nitride CESL has a dielectric constant of about 7.2 to about 7.4. In some embodiments, the aluminum nitride CESL has a thickness of less than or equal to about 3 nm. In some embodiments, the aluminum nitride CESL has a nitrogen concentration of about 42 atomic percent (at%) to about 48 at%.

[0058] In some embodiments, the first copper interconnect includes a copper main layer and a cobalt nitride capping layer disposed between the aluminum nitride CESL and the copper main layer. The first nitrogen concentration of the aluminum nitride CESL is greater than the second nitrogen concentration of the cobalt nitride capping layer. In some embodiments, the first copper interconnect also includes a tantalum nitride diffusion barrier layer disposed between the copper main layer and the first ILD layer. The third nitrogen concentration of the tantalum nitride diffusion barrier layer is greater than the second nitrogen concentration of the cobalt nitride capping layer. In some embodiments, the interconnect structure also includes: an oxygen-doped silicon carbide CESL disposed above the aluminum nitride CESL; and an aluminum oxide CESL disposed above the oxygen-doped silicon carbide CESL. The second copper interconnect extends through the oxygen-doped silicon carbide CESL and the aluminum oxide CESL.

[0059] Another interconnect structure of a multilayer interconnect component of an integrated circuit device includes a first interconnect disposed in a dielectric layer. The first interconnect has: a copper body layer; a first metal nitride layer disposed along a sidewall of the copper body layer; and a second metal nitride layer disposed along a top of the copper body layer. The first metal nitride layer is disposed between the copper body layer and the dielectric layer. The first metal nitride layer includes a first metal, and the second metal nitride layer includes a second metal. The interconnect structure also includes a third metal nitride layer disposed above the second metal nitride layer. The third metal nitride layer includes a third metal. The third metal, the second metal, and the first metal are different. The interconnect structure also includes a second interconnect disposed in the dielectric layer and extending through the third metal nitride layer to the first interconnect. In some embodiments, the first metal is tantalum, the second metal is cobalt, and the third metal is aluminum. In some embodiments, the first metal nitride layer has a first nitrogen concentration, the second metal nitride layer has a second nitrogen concentration, and the third metal nitride layer has a third nitrogen concentration. The first nitrogen concentration, the second nitrogen concentration, and the third nitrogen concentration are different. In some embodiments, the third nitrogen concentration is greater than the first nitrogen concentration and the second nitrogen concentration. In some embodiments, the first nitrogen concentration is greater than the second nitrogen concentration. In some embodiments, the density of the third metal nitride layer is about 2.70 g / cm 3 To about 2.80g / cm 3In some embodiments, the dielectric constant of the third metal nitride layer is about 7.2 to about 7.4. In some embodiments, the interconnect structure further includes a metal oxide layer disposed above the third metal nitride layer. The metal oxide layer includes a third metal, and the second interconnect further extends through the metal oxide layer. In some embodiments, the first interconnect further has a metal layer disposed between the first metal nitride layer and the dielectric layer, wherein the metal layer includes a second metal.

[0060] An exemplary method for manufacturing an interconnect structure includes: forming a copper interconnect in an interlayer dielectric (ILD) layer; and depositing a metal nitride CESL over the copper interconnect and the ILD layer. An interface region between the metal nitride CESL and the copper interconnect has a first nitrogen concentration and / or a first amount of nitrogen-nitrogen bonding. The method also includes performing a nitrogen plasma treatment to modify the interface region between the metal nitride CESL and the copper interconnect. The nitrogen plasma treatment increases the first nitrogen concentration to a second nitrogen concentration and / or increases the first amount of nitrogen-nitrogen bonding to a second amount of nitrogen-nitrogen bonding, both of which minimize the accumulation of copper vacancies in the interface region.

[0061] An exemplary method includes forming an interconnect opening in a first dielectric layer to expose an underlying conductive component. The interconnect opening has a first sidewall defined by the first dielectric layer and a first bottom defined by the underlying conductive component. The method also includes: forming a first metal interconnect in the interconnect opening, which includes forming a diffusion barrier layer along the first sidewall defined by the first dielectric layer and the first bottom defined by the underlying conductive component; forming a metal body layer over the diffusion barrier layer; and forming a metal nitride capping layer over the metal body layer. The diffusion barrier layer partially fills the interconnect opening, and the metal body layer fills the remaining portion of the interconnect opening. The method also includes performing a deposition process to form a metal nitride etch stop layer (ESL) over the first metal interconnect and the first dielectric layer. An interface is defined between the metal nitride ESL of the first metal interconnect and the metal nitride capping layer. The method also includes performing a nitrogen plasma treatment on the metal nitride ESL to increase nitrogen-nitrogen bonding along the interface defined between the metal nitride ESL of the first metal interconnect and the metal nitride capping layer. The method also includes forming a second dielectric layer over the metal nitride ESL, and forming a second interconnect opening in the second dielectric layer to expose the first metal interconnect. The second interconnect opening has a second sidewall defined by the second dielectric layer and the metal nitride ESL and a second bottom defined by the first metal interconnect. The method also includes forming a second metal interconnect in the second interconnect opening.

[0062] In some embodiments, the metal nitride ESL includes aluminum, and the method further includes adjusting the parameters of the nitrogen plasma treatment to increase the number of Al-N bonds in the metal nitride ESL along the interface. In some embodiments, the metal nitride capping layer includes cobalt, and the method further includes adjusting the parameters of the nitrogen plasma treatment to increase the number of Co-N bonds in the metal nitride capping layer along the interface. In some embodiments, implementing the nitrogen plasma treatment includes generating an N2 plasma. In some embodiments, the metal body layer includes a first metal, the metal nitride capping layer includes a second metal, and the metal nitride ESL includes a third metal, wherein the first metal, the second metal, and the third metal are different. In some embodiments, the diffusion barrier layer includes a metal nitride diffusion barrier layer, which includes a fourth metal. In some embodiments, the fourth metal is different from the first metal, the second metal, and the third metal.

[0063] Some embodiments of the present application provide an interconnect structure of a multilayer interconnect component of an integrated circuit device, the interconnect structure comprising: a first interlayer dielectric (ILD) layer; a second interlayer dielectric layer disposed above the first interlayer dielectric layer; a first copper interconnect disposed in the first interlayer dielectric layer; a second copper interconnect disposed in the second interlayer dielectric layer; and an aluminum nitride contact etch stop layer (CESL) disposed between a portion of the first copper interconnect and the second interlayer dielectric layer and between the first interlayer dielectric layer and the second interlayer dielectric layer, wherein the second copper interconnect extends through the aluminum nitride contact etch stop layer to physically contact the first copper interconnect, and further wherein a surface nitrogen concentration at an interface between the aluminum nitride contact etch stop layer and the first copper interconnect is greater than or equal to about 20 at%. In some embodiments, the density of the aluminum nitride contact etch stop layer is about 2.70 g / cm 3 To about 2.80g / cm 3. In some embodiments, the dielectric constant of the aluminum nitride contact etch stop layer is about 7.2 to about 7.4. In some embodiments, the aluminum nitride contact etch stop layer has a thickness less than or equal to about 3 nm. In some embodiments, the nitrogen concentration of the aluminum nitride contact etch stop layer is about 42 atomic percent (at%) to about 48 at%. In some embodiments, the first copper interconnect includes a copper main layer and a cobalt nitride capping layer disposed between the aluminum nitride contact etch stop layer and the copper main layer, wherein the first nitrogen concentration of the aluminum nitride contact etch stop layer is greater than the second nitrogen concentration of the cobalt nitride capping layer. In some embodiments, the first copper interconnect also includes a tantalum nitride diffusion barrier layer disposed between the copper main layer and the first interlayer dielectric layer, wherein the third nitrogen concentration of the tantalum nitride diffusion barrier layer is greater than the second nitrogen concentration of the cobalt nitride capping layer. In some embodiments, the interconnect structure further includes: an oxygen-doped silicon carbide contact etch stop layer disposed above the aluminum nitride contact etch stop layer; and an aluminum oxide contact etch stop layer disposed above the oxygen-doped silicon carbide contact etch stop layer, wherein the second copper interconnect extends through the oxygen-doped silicon carbide contact etch stop layer and the aluminum oxide contact etch stop layer.

[0064] Some other embodiments of the present application also provide an interconnect structure of a multilayer interconnect component of an integrated circuit device, the interconnect structure comprising: a first interconnect, arranged in a dielectric layer, wherein the first interconnect has: a copper main layer, a first metal nitride layer, arranged along the sidewall of the copper main layer, wherein the first metal nitride layer is arranged between the copper main layer and the dielectric layer, a second metal nitride layer, arranged along the top of the copper main layer, wherein the first metal nitride layer includes a first metal, and the second metal nitride layer includes a second metal, and a third metal nitride layer, arranged above the second metal nitride layer, wherein the third metal nitride layer includes a third metal, wherein the third metal, the second metal and the first metal are different; and a second interconnect, arranged in the dielectric layer and extending through the third metal nitride layer to the first interconnect. In some embodiments, the first metal is tantalum, the second metal is cobalt, and the third metal is aluminum. In some embodiments, the first metal nitride layer has a first nitrogen concentration, the second metal nitride layer has a second nitrogen concentration, and the third metal nitride layer has a third nitrogen concentration; and the first nitrogen concentration, the second nitrogen concentration, and the third nitrogen concentration are different. In some embodiments, the third nitrogen concentration is greater than the first nitrogen concentration and the second nitrogen concentration. In some embodiments, the first nitrogen concentration is greater than the second nitrogen concentration. In some embodiments, the interconnect structure further includes: a metal oxide layer disposed above the third metal nitride layer, wherein the metal oxide layer includes the third metal, and the second interconnect further extends through the metal oxide layer. In some embodiments, the first interconnect also has a metal layer disposed between the first metal nitride layer and the dielectric layer, wherein the metal layer includes the second metal. In some embodiments, the density of the third metal nitride layer is approximately 2.70 g / cm 3 To about 2.80g / cm 3 ; and the dielectric constant of the third metal nitride layer is about 7.2 to about 7.4.

[0065] Still other embodiments of the present application provide a method, comprising: forming a copper interconnect in an interlayer dielectric (ILD) layer; depositing a metal nitride contact etch stop layer (CESL) over the copper interconnect and the interlayer dielectric layer, wherein an interface region between the metal nitride contact etch stop layer and the copper interconnect has a first surface nitrogen concentration; and performing a nitrogen plasma treatment to modify the interface region between the metal nitride contact etch stop layer and the copper interconnect, wherein the nitrogen plasma treatment increases the first surface nitrogen concentration to a second surface nitrogen concentration that minimizes accumulation of copper vacancies in the interface region. In some embodiments, performing the nitrogen plasma treatment comprises exposing the metal nitride contact etch stop layer to a nitrogen-containing plasma having a nitrogen concentration of about 70% to about 90%. In some embodiments, performing the nitrogen plasma treatment comprises exposing the metal nitride contact etch stop layer to the nitrogen-containing plasma for about 20 seconds to about 30 seconds. In some embodiments, after performing the nitrogen plasma treatment, the method further includes: forming an oxide-based contact etch stop layer above the metal nitride contact etch stop layer; forming a metal oxide contact etch stop layer above the oxide-based contact etch stop layer, wherein the metal oxide contact etch stop layer and the metal nitride contact etch stop layer include the same metal; forming a second interlayer dielectric layer above the metal oxide contact etch stop layer; and forming a metal interconnect in the second interlayer dielectric layer, wherein the metal interconnect extends through the second interlayer dielectric layer, the metal oxide contact etch stop layer, the oxide-based contact etch stop layer and the metal nitride contact etch stop layer to the copper interconnect.

[0066] The features of several embodiments are summarized above so that those skilled in the art can better understand aspects of the present invention. Those skilled in the art should understand that they can easily use the present invention as a basis to design or modify other processes and structures for implementing the same purpose and / or achieving the same advantages as the embodiments introduced herein. Those skilled in the art should also appreciate that such equivalent constructions do not deviate from the spirit and scope of the present invention, and that they can make various changes, substitutions and modifications herein without departing from the spirit and scope of the present invention.

Claims

1. An interconnect structure of a multi-layer interconnect component of an integrated circuit device, the interconnect structure comprising: a first interlayer dielectric (ILD) layer; a second interlayer dielectric layer, disposed above the first interlayer dielectric layer; a first copper interconnect disposed in the first interlayer dielectric layer; a second copper interconnect disposed in the second interlayer dielectric layer; an aluminum nitride contact etch stop layer (CESL) disposed between a portion of the first copper interconnect and the second interlayer dielectric layer and between the first interlayer dielectric layer and the second interlayer dielectric layer; an oxygen-doped silicon carbide contact etch stop layer, disposed above the aluminum nitride contact etch stop layer; as well as an aluminum oxide contact etch stop layer disposed above the oxygen-doped silicon carbide contact etch stop layer, wherein the second copper interconnect extends through the oxygen-doped silicon carbide contact etch stop layer and the aluminum oxide contact etch stop layer and the aluminum nitride contact etch stop layer to physically contact the first copper interconnect, and further wherein a surface nitrogen concentration at an interface between the aluminum nitride contact etch stop layer and the first copper interconnect is greater than or equal to 20±10% atomic percentage.

2. The interconnect structure according to claim 1, wherein: The density of the aluminum nitride contact etch stop layer is 2.70 g / cm 3 ±10% to 2.80g / cm 3 ±10%.

3. The interconnect structure according to claim 1, wherein: The dielectric constant of the aluminum nitride contact etch stop layer is 7.2±10% to 7.4±10%.

4. The interconnect structure according to claim 1, wherein: The aluminum nitride contact etch stop layer has a thickness less than or equal to 3 nm±10%.

5. The interconnect structure according to claim 1, wherein: The aluminum nitride contact etch stop layer has a nitrogen concentration of 42±10% atomic percent (at %) to 48±10% atomic percent.

6. The interconnect structure according to claim 1, wherein: The first copper interconnect includes a copper main layer and a cobalt nitride capping layer disposed between the aluminum nitride contact etch stop layer and the copper main layer, wherein a first nitrogen concentration of the aluminum nitride contact etch stop layer is greater than a second nitrogen concentration of the cobalt nitride capping layer.

7. The interconnect structure according to claim 6, wherein: The first copper interconnect further includes a tantalum nitride diffusion barrier layer disposed between the copper body layer and the first interlayer dielectric layer, wherein a third nitrogen concentration of the tantalum nitride diffusion barrier layer is greater than the second nitrogen concentration of the cobalt nitride capping layer.

8. The interconnect structure according to claim 1, wherein: The second copper interconnect includes a copper body layer and a diffusion barrier layer disposed between the copper body layer and the second interlayer dielectric layer.

9. An interconnect structure of a multi-layer interconnect component of an integrated circuit device, the interconnect structure comprising: A first interconnection is disposed in the dielectric layer, wherein the first interconnection has: Copper main layer, a first metal nitride layer disposed along a sidewall of the copper main layer, wherein the first metal nitride layer is disposed between the copper main layer and the dielectric layer, a second metal nitride layer disposed along a top portion of the copper bulk layer, wherein the first metal nitride layer comprises a first metal and the second metal nitride layer comprises a second metal, and a third metal nitride layer disposed above the second metal nitride layer, wherein the third metal nitride layer comprises a third metal, wherein the third metal, the second metal, and the first metal are different; a metal oxide layer disposed above the third metal nitride layer, wherein the metal oxide layer includes the third metal; and A second interconnect is disposed in the dielectric layer and extends through the metal oxide layer and the third metal nitride layer to the first interconnect.

10. The interconnect structure according to claim 9, wherein: The first metal is tantalum, the second metal is cobalt, and the third metal is aluminum.

11. The interconnect structure of claim 9, wherein: The first metal nitride layer has a first nitrogen concentration, the second metal nitride layer has a second nitrogen concentration, and the third metal nitride layer has a third nitrogen concentration; and The first nitrogen concentration, the second nitrogen concentration, and the third nitrogen concentration are different.

12. The interconnect structure according to claim 11, wherein: The third nitrogen concentration is greater than the first nitrogen concentration and the second nitrogen concentration.

13. The interconnect structure according to claim 12, wherein: The first nitrogen concentration is greater than the second nitrogen concentration.

14. The interconnect structure according to claim 9, wherein: The second metal nitride layer of the first interconnect is located between the copper body layer of the first interconnect and the second interconnect.

15. The interconnect structure according to claim 9, wherein: The first interconnect also has a metal layer disposed between the first metal nitride layer and the dielectric layer, wherein the metal layer includes the second metal.

16. The interconnect structure of claim 9, wherein: The density of the third metal nitride layer is 2.70 g / cm 3 ±10% to 2.80g / cm 3 ±10%; and The dielectric constant of the third metal nitride layer is 7.2±10% to 7.4±10%.

17. A method of manufacturing an interconnect structure, comprising: forming a copper interconnect in an interlayer dielectric (ILD) layer; depositing a capping layer and a metal nitride contact etch stop layer (CESL) on the capping layer over the copper interconnect and the interlayer dielectric layer, wherein an interface region between the metal nitride contact etch stop layer and the copper interconnect has a first surface nitrogen concentration; performing a nitrogen plasma treatment to modify an interface region between the metal nitride contact etch stop layer and the copper interconnect, wherein the nitrogen plasma treatment increases the first surface nitrogen concentration to a second surface nitrogen concentration that minimizes accumulation of copper vacancies in the interface region, The interface region includes a first interface between the metal nitride contact etch stop layer and the capping layer and a second interface between the capping layer and the copper interconnect. wherein the nitrogen plasma treatment also further drives nitrogen into the capping layer, and wherein, in a thickness direction from the metal nitride contact etch stop layer to the copper interconnect, a combined nitrogen concentration profile of the nitrogen-treated metal nitride contact etch stop layer and the capping layer increases from a top surface of the nitrogen-treated metal nitride contact etch stop layer to a peak region near the first interface, and then decreases from the peak region to a bottom surface of the capping layer at the second interface.

18. The method according to claim 17, wherein: Performing the nitrogen plasma treatment includes exposing the metal nitride contact etch stop layer to a nitrogen-containing plasma having a nitrogen concentration of 70±10% to 90±10%.

19. The method according to claim 17, wherein: Performing the nitrogen plasma treatment includes exposing the metal nitride contact etch stop layer to a nitrogen-containing plasma for 20 seconds ±10% to 30 seconds ±10%.

20. The method according to claim 17, wherein: After performing the nitrogen plasma treatment, the method further comprises: forming a non-metal oxide based contact etch stop layer over the metal nitride contact etch stop layer; forming a metal oxide contact etch stop layer over the non-metal oxide based contact etch stop layer, wherein the metal oxide contact etch stop layer and the metal nitride contact etch stop layer comprise the same metal; forming a second interlayer dielectric layer over the metal oxide contact etch stop layer; and A metal interconnect is formed in the second interlayer dielectric layer, wherein the metal interconnect extends through the second interlayer dielectric layer, the metal oxide contact etch stop layer, the oxide-based contact etch stop layer, and the metal nitride contact etch stop layer to the copper interconnect.

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