Brazing pad metallization systems and related methods

Abstract

The invention relates to a copper pad metallization system and a related method. A particular implementation of a method of forming an interconnect may include forming a grain layer (10) over a plurality of pads (6); patterning the photoresist layer (12) having a plurality of openings (14) exposing the plurality of pads (6); forming a plurality of copper interconnectors (18) by electroplating each of the plurality of copper interconnectors (18) into each of the plurality of openings (14); removing the photoresist layer (12); etching the grain layer (10); forming one or more layers (24) on the plurality of copper interconnectors (18); and patterning the polyimide layer (26) over the plurality of copper interconnectors (18) to form at least one opening (28) over at least one of the plurality of copper interconnectors (18).

Description

BACKGROUND 1. TECHNICAL FIELD

[0001] Aspects of the present document relate generally to methods for forming electrical interconnectors. More particular implementations relate to electrical interconnectors including copper pads. 2. BACKGROUND

[0003] Semiconductor packages have been designed that allow electrical signals to be routed from a semiconductor die to components of the package for interfacing with a circuit board or motherboard to which the semiconductor package is attached. Semiconductor packages have also been developed that help protect the semiconductor die from humidity, thermal conditions, or impacts and vibrations during operation and use. SUMMARY

[0004] An implementation of a method of forming an interconnector can include forming a seed layer over a plurality of pads; patterning a photoresist layer having a plurality of openings exposing the plurality of pads; forming a plurality of copper interconnectors by electroplating each copper interconnector of the plurality of copper interconnectors into each opening of the plurality of openings; removing the photoresist layer; etching the seed layer; forming one or more layers on the plurality of copper interconnectors; and patterning a polyimide layer over the plurality of copper interconnectors to form at least one opening over at least one copper interconnector of the plurality of copper interconnectors.

[0005] An implementation of a method of forming an interconnector can include one, all, or any of:

[0006] Forming one or more layers on at least one copper interconnector can further include electroless plating.

[0007] The one or more layers can include one of nickel, gold, palladium, or any combination thereof.

[0008] Forming one or more layers on at least one copper interconnector can further include sputtering.

[0009] The one or more layers include one of: titanium, nickel, and gold; titanium, nickel, and palladium; or any combination thereof.

[0010] The seed layer can include titanium and tungsten or copper.

[0011] The method can include backgrinding a second side of the semiconductor substrate opposite the first side including the plurality of pads to thin the semiconductor substrate.

[0012] An implementation of a method of forming interconnectors can include forming a seed layer over a plurality of pads; patterning a photoresist layer having a plurality of openings exposing the plurality of pads; forming a plurality of copper interconnectors by electroplating each of the plurality of copper interconnectors into each of the plurality of openings; applying an organic coating over each of the plurality of copper interconnectors; removing the photoresist layer; etching the seed layer; and patterning a polyimide layer over the plurality of copper interconnectors to form at least one opening over at least one of the plurality of copper interconnectors.

[0013] An implementation of a method of forming interconnectors can include one, all, or any of:

[0014] The method can include wire bonding to at least one of the copper interconnectors through the organic coating.

[0015] The method can include removing the organic coating after patterning the polyimide layer and wire bonding to at least one of the copper interconnectors through the at least one opening.

[0016] Removing the organic coating can further include cleaning or etching.

[0017] The method can include reducing formation of copper oxide by applying the organic coating over each of the copper interconnectors.

[0018] The polyimide layer can directly contact the organic coating.

[0019] The at least one opening in the polyimide layer over at least one of the copper interconnectors can expose only copper of the at least one copper interconnector.

[0020] The at least one opening in the polyimide layer over at least one of the copper interconnectors can expose only the organic coating over the at least one copper interconnector.

[0021] An implementation of a method of forming interconnectors can include forming a seed layer over a plurality of pads; patterning a photoresist layer having a plurality of openings exposing the plurality of pads; forming a plurality of copper interconnectors by electroplating each of the plurality of copper interconnectors into each of the plurality of openings; applying an aluminum layer over each of the plurality of copper interconnectors; removing the photoresist layer; etching the seed layer; and patterning a polyimide layer over the plurality of copper interconnectors to form at least one opening over at least one of the plurality of copper interconnectors.

[0022] An implementation of a method of forming interconnectors can include one, all, or any of:

[0023] Applying the aluminum layer can further include atomic layer deposition of the aluminum layer over each of the plurality of copper interconnectors prior to removing the photoresist layer.

[0024] Applying the aluminum layer can also include atomic layer depositing the aluminum layer on each of the plurality of copper interconnects after removing the photoresist layer.

[0025] The method can include wire bonding to at least one of the copper interconnects through the aluminum layer.

[0026] The method can include reducing the formation of copper oxide by applying the aluminum layer over each of the copper interconnects.

[0027] The above and other aspects, features, and advantages will become more apparent from the specific embodiments and drawings, which are described in detail below. BRIEF DESCRIPTION OF DRAWINGS

[0028] The specific embodiments will be described below with reference to the accompanying drawings, in which like reference numerals refer to like elements in the several figures, and:

[0029] Figure 1 is a side cross-sectional view of an implementation of a semiconductor substrate having a pad formed thereon;

[0030] Figure 2 is a side cross-sectional view of an implementation of a semiconductor substrate after depositing a seed layer; Figure 1 is a side cross-sectional view of an implementation of a semiconductor substrate after depositing a seed layer;

[0031] Figure 3 is a side cross-sectional view of an implementation of a semiconductor substrate after forming a photoresist pattern thereon; Figure 2 is a side cross-sectional view of an implementation of a semiconductor substrate after forming a photoresist pattern thereon;

[0032] Figure 4 is a side cross-sectional view of an implementation of a semiconductor substrate after electroplating a copper pad thereon; Figure 3 is a side cross-sectional view of an implementation of a semiconductor substrate after electroplating a copper pad thereon;

[0033] Figure 5 is a side cross-sectional view of an implementation of a semiconductor substrate after forming one or more layers over exposed surfaces of the copper pad and removing the photoresist; Figure 4 is a side cross-sectional view of an implementation of a semiconductor substrate after forming one or more layers over exposed surfaces of the copper pad and removing the photoresist;

[0034] Figure 6 is a side cross-sectional view of an implementation of a semiconductor substrate after etching / removing the seed layer; Figure 5 is a side cross-sectional view of an implementation of a semiconductor substrate after etching / removing the seed layer;

[0035] Figure 7 is a side cross-sectional view of an implementation of a semiconductor substrate after forming a patterned polyimide layer over the copper pad; Figure 6 is a side cross-sectional view of an implementation of a semiconductor substrate after forming a patterned polyimide layer over the copper pad;

[0036] Figure 8 is a side cross-sectional view of an implementation of a semiconductor substrate after forming an additional layer over exposed portions of the copper pad; Figure 7 is a side cross-sectional view of an implementation of a semiconductor substrate after forming an additional layer over exposed portions of the copper pad;

[0037] Figure 9 is a side cross-sectional view of another implementation of a semiconductor substrate having pads formed thereon;

[0038] Figure 10 is a side cross-sectional view of an implementation of a semiconductor substrate having a seed layer formed thereon Figure 9

[0039] Figure 11 is a side cross-sectional view of an implementation of a semiconductor substrate after forming a photoresist pattern thereon Figure 10

[0040] Figure 12 is a side cross-sectional view of an implementation of a semiconductor substrate after plating copper pads thereon Figure 11

[0041] Figure 13 is a side cross-sectional view of an implementation of a semiconductor substrate after removing photoresist and applying a layer to a top surface of the copper pads Figure 12

[0042] Figure 14 is a side cross-sectional view of an implementation of a semiconductor substrate after removing a seed layer Figure 13

[0043] Figure 15 is a side cross-sectional view of an implementation of a semiconductor substrate after forming a patterned polyimide layer over the copper pads and etching / removing the layer over the top surface of the copper pads Figure 14

[0044] Figure 16 is a side cross-sectional view of an implementation of a semiconductor substrate after forming a patterned polyimide layer over the copper pads Figure 13

[0045] Figure 17 is a side cross-sectional view of an implementation of a semiconductor substrate after removing a photoresist layer and a seed layer Figure 12

[0046] Figure 18 is a side cross-sectional view of an implementation of a semiconductor substrate after forming a patterned polyimide layer over the copper pads; and Figure 17

[0047] Figure 19 is a side cross-sectional view of an implementation of a semiconductor substrate after forming a metal layer over exposed portions of the copper pads. Figure 18 DETAILED DESCRIPTION

[0048] ​​​​​​​​​​The present disclosure, its aspects and particular implementations are not limited to the specific components, assembly procedures or method elements disclosed herein. Many additional components, assembly procedures and / or method elements known in the art for brazing pad metallization systems consistent with the intended operation and methods will be apparent to those of ordinary skill in the art and can be used with the particular implementations of the present disclosure. Thus, for example, although the present disclosure discloses particular implementations, such implementations and implementation components can include any shape, size, style, type, model, version, measure, concentration, material, quantity, method element, step, and / or the like known in the art for such brazing pad metallization systems and implementation components and methods consistent with the intended operation and methods.

[0049] In various semiconductor devices, logic circuitry and power circuitry can be combined. For example, in the case of a semiconductor device used to operate an automatic window opener in a car, the logic portion of the device senses a control signal indicating that a window is to be raised or lowered, and then activates the power portion (metal oxide field effect transistor [MOSFET]) to transfer power to a motor for a specified period of time to allow the window to be physically raised or lowered. The voltage and power used by the logic portion of the device is typically much smaller compared to the voltage and power required to operate the motor, so if the electrical interconnects used for the logic portion are used for the power portion of the device, the electrical interconnects can be damaged due to overheating and / or excessive current loading, even during the relatively short period of time during which high voltage / amperage is experienced during operation. In such systems, electrical interconnects adapted for higher power operation, such as thick copper interconnects, e.g., pads / bumps / pillars having a height greater than 10 microns, can be used to help the interconnects avoid damage during high voltage transient loading periods. Similar structures in the form of metal wires having a height greater than 10 microns are also used, and the principles disclosed herein can also be applied to metal wires. Since wire bonding is typically used to connect the source and drain pads of a MOSFET, for example, the ability of wire bondable materials utilizing thick copper interconnects to produce reliable wire bonds is a design consideration when such combined logic and power circuitry combinations are combined in a semiconductor device.

[0050] In some process implementations, thick copper pads with a layer of gold and / or nickel on their upper surfaces are used. Since the sidewalls of the thick copper pads remain exposed in this process, there is an increased likelihood of particle contamination causing shorts between the pads since there is nothing to fill the gap between adjacent pads. In other process implementations, to help reduce the likelihood of particle contamination causing failure of the thick copper pads, a layer of polyimide is used to fill the space between the pads and cover the upper surface of the thick copper pillars in applications such as (by way of non-limiting example) the automotive and other vehicle industries. An opening is formed in the polyimide layer to expose an upper portion of the thick copper pillar, and a wire bond is formed in the opening. However, to enable the polyimide to adhere to the gold on the upper surface of the thick copper pad, a palladium film is required as a top layer over the upper surface. The polyimide can also adhere to a layer of aluminum formed at the top layer over the upper surface of the thick copper pad, but not to the gold of the thick copper pad itself.

[0051] Various methods for forming thick copper interconnect systems are disclosed in this document, which utilize various layers of materials, with a polyimide material adhered to these layers of materials over the top surface of the thick copper pads / bumps / pillars. These methods are merely exemplary, and the combination of the methods and materials disclosed herein can be used in various system and method implementations. While in this document the term “pad” is used primarily to describe the methods and structures herein, it is to be understood that the same principles can be applied to other metallization structures, including bond pads, metal lines, or other large area metallization, such as dummy structures used to ensure local and wafer level uniformity.

[0052] One of the challenges with forming wire bonds with pure copper pads is that the copper oxide present on the bonding surface of the pad interferes with the formation of intermetallic and alloy compounds that form a good mechanical and electrical connection between the wire and the copper pad. Thus, the ability to minimize and reduce copper oxide formation during processing steps helps to form good wire bonds. Various method implementations disclosed herein show various methods of reducing copper oxide formation on the bonding / top surface of the copper pads disclosed herein.

[0053] Reference is made to Figure 1 , which shows a side cross-sectional view of a semiconductor device 2 that includes a semiconductor substrate portion 4 on which a plurality of pads 6 are formed. The pads 6 represent the outer layer of a stack of materials formed on / in the semiconductor substrate portion 4, which is not shown for easier illustration. The pads 6 are formed on the semiconductor substrate portion 4 by a process that includes forming a layer of copper on the semiconductor substrate portion 4, and then forming a layer of gold on the copper layer. The gold layer is then patterned to form the pads 6. The pads 6 are then subjected to a process that includes forming a layer of polyimide over the pads 6, and then forming an opening in the polyimide layer to expose an upper portion of the pads 6. A wire bond is then formed in the opening. Figure 1or other figures are shown, but are understood to be present to form active devices included in the semiconductor device 2. The material stack facilitates formation of structures such as, by way of non-limiting example, transistors, diodes, interconnects, traces, vias, insulating layers, and any other components of an active semiconductor device. Around each pad 6 is a layer of passivation material 8, which by way of non-limiting example can be silicon nitride, polyimide, or another electrically insulating material. By way of non-limiting example, the particular material of the semiconductor substrate can be silicon, silicon carbide, silicon on insulator, ruby, sapphire, gallium arsenide, gallium nitride, or any other semiconductor material type. By way of non-limiting example, particular types of semiconductor devices that can be embodied using the methods disclosed herein can include transistors, MOSFETs, insulated gate bipolar transistors (IGBTs), diodes, power devices, high electron mobility transistors (HEMTs), rectifiers, or any other power semiconductor device or other active semiconductor device type. While only two pads are shown in Figure 2 FIG. 1, it will be understood that this is merely for ease of illustration, as the disclosed methods can be employed at the die level or wafer level portion of the manufacturing process, and more than just two pads can be employed in various implementations.

[0054] Referring to Figure 2 , a side cross-sectional view of the semiconductor device 2 of Figure 1 is shown after formation of a seed layer 10 for electroplating thereon. The use of the seed layer 10 allows for an electrical connection of the seed layer material to be formed into each of the pads 6 during an electroplating operation. In various implementations, the seed layer 10 can be formed by sputtering. By way of non-limiting example, the seed layer 10 can include titanium and tungsten films, copper films, any combination thereof, or another metal film type that allows for electroplating of pure copper to the seed layer.

[0055] After formation of the seed layer 10, referring to Figure 3 , a photoresist layer 12 is applied and then patterned. By way of non-limiting example, the application process of the photoresist 12 can include spin coating, dispensing, stencil printing, doctor blading, or any other method for forming a uniform layer of material over the seed layer 10. The patterning process used can be specific to the particular type of photoresist employed. For example, in the case of a positive photoresist, the photoresist area over the pads 6 is exposed through a mask with an electromagnetic radiation source to cause a corresponding reaction in the photoresist material that allows a developing solution to wash away the exposed areas. In the case of a negative photoresist, the photoresist area outside of the pads is exposed to electromagnetic radiation, causing a corresponding reaction in the photoresist material that prevents the developing solution from washing away the exposed areas. As Figure 3As shown, the openings 14 in the photoresist 12 are larger than the size of the pads to allow the passivation material and any other under bump material to help support the bumps to be formed and to help prevent problems such as bump cracking later during operations. However, in other implementations, the size of the openings 14 can be the same or substantially the same as the size of the pads. The height / thickness 16 of the photoresist 12 is set to be higher or substantially the same as the height of the copper pads to be electroplated to help form the sidewalls and flat upper / bonding surface of each copper pad.

[0056] Referring to Figure 4 , the semiconductor device 2 is shown after the electroplating process is completed, which forms the copper pads / bumps / pillars 18 within each of the openings 14 of the photoresist 12 that are mechanically and electrically connected to each corresponding pad 6. In this implementation, a pure copper pad has been formed, which means that substantially all of the material of the pad is formed of only copper. However, in other implementations, a copper alloy can be electroplated, depending on the electrical or mechanical properties desired for the pad.

[0057] Referring to Figure 5 , the semiconductor device is shown after one or more layers of material 24 are formed on the top side / bonding surface 22 of each copper bump 18 and after the photoresist is stripped / removed. In various method implementations, the one or more layers can be formed using electroless plating. In instances where electroless plating is used to form the one or more layers, the electroless plating can be performed while the photoresist 12 is still present around the copper pads 18 after the electroplating of the copper pads, as shown in Figure 4 . However, in other implementations, the electroless plating can occur after the photoresist has been removed and after the seed layer 10 is removed, as in the structure shown in Figure 6 . While for ease of illustration, the one or more layers 24 are shown in Figure 5 as only being present on the top of the copper pads 18, where the electroless plating occurs after the photoresist and seed layer are removed, it should be understood that the material of the one or more layers can be deposited on the entire exposed surface of each copper pad 18. Thus, if it is desired to form the one or more layers 24 only on the bonding surface 22 of the copper pads 18, the electroless plating is performed while the photoresist 12 is still in place, as shown in Figure 4 .

[0058] While the previous discussion discloses the use of electroless plating to form the one or more layers of material 24, in other method implementations, sputtering can be used to form the one or more layers of material 24. In such implementations, the sputtering is performed after the electroplating of the copper pads 18 while the photoresist 12 is still in place around the pads, as shown in Figure 14The photoresist 12 is then stripped / removed as previously described, leaving one or more layers of material 24 on the bonding surface 22 of each copper pad 18, as shown in Figure 5

[0059] The material used in the one or more layers of material 24 depends on the particular formation method. In the case of electroless plating, in some implementations the material of the one or more layers can be nickel, gold, or palladium as a single layer. In other implementations, the material of the one or more layers can be nickel, gold, or palladium in two or more separate layers, each layer formed by electroless plating. In yet other implementations, the material of the one or more layers can be any combination of nickel, gold, and / or palladium formed using electroless plating as a single layer or multiple layers. In the case of sputtering, as non-limiting examples, the material of the one or more layers can be titanium, nickel, and gold, or titanium, nickel, and palladium formed in a single layer or as separate layers.

[0060] The process of removing the photoresist can be performed using various methods, including solvent stripping, washing, ashing, etching, or any other method for removing polymeric material, as non-limiting examples. As shown, the plated copper pads 18 are then exposed and raised to a desired height / thickness 20 above the surface of the seed layer 10. Since the seed layer 10 electrically shorts all of the copper pads 18 and all of the pads 6 together, it is necessary to remove it to again electrically isolate all of the pads 6 from one another.

[0061] Referring to Figure 6 , a semiconductor device 2 is shown after removal of the seed layer material 10 from around the copper pads 18, leaving the seed layer 10 present only as an under bump material for each copper pad. In various method implementations, the removal of the seed layer 10 can be performed using etching. Figure 5 Also shown is that, after removal of the seed layer 10, the one or more layers of material 24 remain formed on the top surface / bonding surface 22 of each copper pad 18. In various implementations, the one or more layers of material 24 can be formed of a material that is not removed / etched by the process used to remove / etch the seed layer. Figure 6

[0062] Referring to Figure 7 ​​, showing the semiconductor device 2 after the polyimide layer 26 is applied over the copper pads 18 and the openings 28 are patterned over the top surface / landing surface 22. Note that not every copper pad 18 can have a top surface 22 with one or more material layers 24 exposed through an opening in the polyimide layer 26. This can be because not all of the pads 6 are actually used for electrical interconnects and can be dummy pads used to maintain a certain amount of metal density at the pad layer to help improve processing uniformity or to help provide mechanical support / strength to the semiconductor device. The particular patterning method and process used to form the openings 28 in the polyimide 26 depends on the material of the polyimide and whether it is photopatterned using a positive exposure process or a negative exposure process, such as those previously described in this document. Because the material types used in the one or more material layers 24 are those previously described in this document, the polyimide 26 will adhere to the one or more layers 24 to form the openings 28 and allow wire bonding into the openings 28. Figure 8 shows the semiconductor device 2 after wire bonds 30 are wire bonded to the one or more materials 24 and to the copper pads 18.

[0063] Prior to the wire bonding process, the semiconductor device 2 can be thinned the semiconductor substrate portion by a backgrinding, lapping, dicing, polishing, or any other thinning process by way of non-limiting example. Due to the use of the polyimide 26, the mechanical strength of the remaining portion of the semiconductor substrate portion can be improved to support a thinner die than can otherwise be produced in the absence of the polyimide 26 in the material stack. Various method variations can be constructed using the principles disclosed in this document.

[0064] Referring to Figure 9 , a second semiconductor device 32 is shown in a side cross-sectional view that is structurally similar to the semiconductor device 2 of Figure 1 . The semiconductor device 32 includes a pad 34 surrounded by a passivation material 36. In various method implementations, the material of the semiconductor substrate portion 38 of the semiconductor device 32 can be any material disclosed in this document. In various method implementations, the material of the passivation material 36 can also be any material disclosed in this document. Further, the semiconductor device 32 can be any semiconductor device type disclosed in this document.

[0065] Referring to Figure 10 , the semiconductor device 32 is shown in a side cross-sectional view after a seed layer 40 is formed over the pad 34. The material of the seed layer 40 can be any material disclosed in this document for a seed layer used to electroplate copper. Figure 11A semiconductor device 32 is shown after a patterned photoresist layer 42 is formed over the seed layer 40 with openings 44 over the pads 34. The material of the photoresist 42 can be any of the materials disclosed in this document, and can be patterned using any of the patterning method implementations disclosed herein in various method implementations. The height / thickness 46 of the photoresist 42 over the seed layer 40 is again set at a level to enable / support the formation of copper pads at a desired thickness during electroplating.

[0066] Referring to Figure 12 A semiconductor device 32 is shown in a side cross-sectional view after the copper pads 48 are electroplated. The electroplating process used to form the copper pads 48 and the material of the copper pads 48 can be any of the processes and materials disclosed in this document. Figure 12 A semiconductor device 32 is also shown after one or more layers 50 are formed over the top surface / landing surface 52 of each copper pad 48. In various method implementations, the one or more layers 50 can include different materials formed and treated using corresponding methods. In a particular implementation, the one or more layers 50 are an organic coating that, when applied, prevents or substantially prevents oxygen from reacting with the newly plated copper of the copper pads 48, thereby reducing the formation of copper oxide on the landing surface 52. The organic coating is applied shortly after the electroplating of the copper pads is completed, thereby helping to seal the landing surface 52 of the copper pads 48 from further reaction with oxygen. In addition, the organic coating is a material to which a subsequently applied polyimide material will adhere to. In addition, the organic material in this implementation is one that can be passed through the material forming the wire bonds during the wire bonding process, and does not involve a cleaning or removal step.

[0067] In another implementation, the one or more layers 50 are an organic material that is thicker or more tightly bonded to the copper layer than the previously disclosed organic material of the previous method implementation. This organic material has the same ability to prevent further formation of copper oxide on the landing surface 52 of the copper pads 48, but requires removal / cleaning from the landing surface 52 using a cleaning step that will be discussed below prior to the actual wire bonding. In various implementations, the organic material that can be employed in either method implementation can be an organic solderability preservative sold by RBP Chemical Technology, Inc. of Milwaukee, Wisconsin; MacDermid Alpha Electronics Solutions of Waterbury, Connecticut; or Shikoku Chemicals Corporation of Takamatsu, Kagawa, Japan.

[0068] In another implementation, the one or more layers 50 are layers of aluminum deposited on the bonding surface 52 that immediately react with oxygen to form aluminum oxide (alumina). In particular implementations, the aluminum oxide layers are deposited using atomic layer deposition, and the thickness of the aluminum oxide layers can be between 1 and 5 atoms. However, in other implementations, other materials besides aluminum can be used in the one or more layers 50, such as, by way of non-limiting example, titanium nitride, tantalum nitride, any combination thereof, or other materials capable of being deposited using ALD. Such layers are thick enough to prevent oxygen diffusion to the copper pads 48 and formation of copper oxide, but thin enough to be passed through by the wire bonds during the wire bonding process. In various method implementations that employ atomic layer deposition, the aluminum is deposited while the photoresist 42 is present in the atomic layer deposition chamber, resulting in the structure shown. However, in other implementations, the aluminum can be deposited after the photoresist 42 has been lifted off the seed layer 40 but before the seed layer 40 is etched. This can occur to avoid problems with outgassing or contamination of the process caused by the presence of thick photoresist after the plating process has been completed. The aluminum adds an additional benefit in that the subsequently applied polyimide will adhere to the aluminum layer. Figure 12 The structure shown results. However, in other implementations, the aluminum can be deposited after the photoresist 42 has been lifted off the seed layer 40 but before the seed layer 40 is etched. This can occur to avoid problems with outgassing or contamination of the process caused by the presence of thick photoresist after the plating process has been completed. The aluminum adds an additional benefit in that the subsequently applied polyimide will adhere to the aluminum layer.

[0069] In other method implementations, a layer of aluminum between about 1 micrometer and about 4 micrometers is sputtered to form the one or more layers 50. In some implementations, the layer of aluminum can be about 2 micrometers thick. When the layer of aluminum is applied shortly after the copper plating, the layer of aluminum can help reduce copper oxide formation, and also aid in the adhesion of the polyimide subsequently formed over the copper pads.

[0070] Referring to Figure 13 , the semiconductor device 32 is shown after the photoresist has been removed in a side cross-sectional view. In various method implementations, any of the methods disclosed in this document can be used to remove the photoresist. In Figure 13 , the one or more layers 50 of the copper pad 48 can be the previously mentioned organic material or a layer of aluminum deposited using the previously discussed atomic layer deposition. Figure 14 The semiconductor device 32 is shown after the exposed portions of the seed layer 40 that are not part of the copper pad 48 have been removed. The removal of the seed layer 40 can be performed using any of the methods disclosed herein. In various methods, the particular removal method can also take into account the resistance of the material of the one or more layers 50 present to the particular removal method. In some embodiments where there is a layer of aluminum applied after the photoresist is removed, causing the aluminum to be deposited on the seed layer 40, a removal method can be employed that is capable of removing the aluminum initially, either alone or in combination with the material of the seed layer 40.

[0071] Referring to Figure 15 , the semiconductor substrate 32 is shown after a layer of polyimide 54 is applied over the copper pad 48 and the layer is patterned to form an opening 56.Figure 15 This is a side sectional view after the material of one or more layers 50 exposed through opening 56 has been removed. In this embodiment of the method, the material of one or more layers 50 is an organic material that needs to be removed / cleaned from the bonding surface 52 of the copper pad 48 prior to wire bonding. In this embodiment of the method, because the organic material cannot be penetrated through the bonding, it needs to be removed after the polyimide layer 54 is formed, while still providing adhesion of the polyimide to the bonding surface 52 of the copper pad 48.

[0072] Figure 16 An alternative structure resulting from an alternative method implemented using this method is shown, wherein an aluminum layer or organic coating is formed over one or more layers 50 formed above the bonding surface 52. For example... Figure 15 As shown, a polyimide layer 54 has been formed over the copper pads 48 and patterned using any of the methods disclosed herein to form openings 56. However, in this particular embodiment of the method, the exposed material of one or more layers 50 is not removed, and wire bonding is performed by bonding through an organic coating or an aluminum layer formed by atomic layer deposition. In this way, the bonding is not affected by copper oxide while the pure copper pads are still bonded, and the polyimide layer 54 is still able to adhere to the bonding surface 52 of each copper pad in the copper pads 48.

[0073] refer to Figure 17 This shows that in such Figure 12 The copper pad 58 is shown after the photoresist has been removed and after the seed layer 60 has been etched. However, in this particular embodiment of the method, no layer is applied over the top / bonding surface 62 of the copper pad after the seed layer 60 is formed and before the seed layer is etched, thus leaving the top / bonding surface 62 as copper. Figure 18 This illustrates the process after forming the polyimide layer 64 and forming the opening 66 to expose the top / bonding surface 62. Figure 17 The copper pad 58. In some implementations, the polyimide layer 64 is sufficiently adhered / bonded to the top / joining surface 62 of the copper pad 58 such that no additional layer is applied to the top / joining surface 62. In such implementations, bonding is then performed directly on the top / joining surface 62.

[0074] In other specific implementations, such as Figure 19As shown, after forming the opening 66 in the polyimide 64, one or more layers 68 are formed over the top / bonding surface 62 of the copper pad 58. In some implementations, electroless plating can be used to form a layer of nickel, a layer of palladium, a layer of gold, or any combination thereof to form the one or more layers 68. In other implementations, sputtering can be used to apply titanium and aluminum (as separate layers or a single layer) to form the one or more layers 68. In other implementations, sputtering can be used to apply titanium tungsten and aluminum (as separate layers or a single layer) to form the one or more layers 68. In yet other implementations, atomic layer deposition can be employed to form one or more layers 68 of any of the materials disclosed herein for atomic layer deposition. As Figure 19 As shown, where sputtering is used to form the one or more layers 68, the material of the one or more layers 68 can rise up around the edges of the polyimide layer 64 of the opening 66.

[0075] In various method implementations, various possible combinations of electroless plating / sputtering / atomic layer deposition can be employed to form various layers on the top / bonding layer 62 of the copper pad 58.

[0076] Where the above description refers to specific implementations of copper pad metallization systems and implementing assemblies, subassemblies, methods, and sub-methods, it should be readily apparent that numerous modifications can be made without departing from the spirit thereof, and that these implementations, implementing assemblies, subassemblies, methods, and sub-methods can be applied to other copper pad metallization systems.

Claims

1. A method of forming interconnectors, the method comprising: forming a seed layer (10) over a plurality of pads (6); patterning a photoresist layer (12) having a plurality of openings (14) exposing the plurality of pads (6); forming a plurality of copper interconnectors (18) by electroplating each of the plurality of copper interconnectors (18) into each of the plurality of openings (14); removing the photoresist layer (12); etching the seed layer (10); forming one or more layers (24) on the plurality of copper interconnectors (18); and patterning a polyimide layer (26) over the plurality of copper interconnectors (18) to form at least one opening (28) over at least one of the plurality of copper interconnectors (18).

2. The method of claim 1, wherein forming the one or more layers (24) on the at least one copper interconnector further comprises electroless plating.

3. The method of claim 2, wherein the one or more layers (24) comprise one of: nickel, gold, palladium, or any combination thereof.

4. The method of claim 1, wherein forming the one or more layers (24) on the at least one copper interconnector further comprises sputtering.

5. The method of claim 4, wherein the one or more layers (24) comprise one of: titanium, nickel, and gold; titanium, nickel, and palladium; or any combination thereof.

6. The method of claim 1, wherein the seed layer (10) comprises titanium and tungsten or copper.

7. The method of claim 1, further comprising back grinding a second side of a semiconductor substrate (4) opposite a first side comprising the plurality of pads (6) to thin the semiconductor substrate (4).

8. A method of forming interconnectors, the method comprising: forming a seed layer (40) over a plurality of pads (34); patterning a photoresist layer (42) having a plurality of openings (44) exposing the plurality of pads (34); forming a plurality of copper interconnectors (48) by electroplating each of the plurality of copper interconnectors (48) into each of the plurality of openings (44); applying an organic coating over each of the plurality of copper interconnectors (48); removing the photoresist layer (42); etching the seed layer (40); and patterning a polyimide layer (54) over the plurality of copper interconnectors (48) to form at least one opening (56) over at least one of the plurality of copper interconnectors (48).

9. The method of claim 8, further comprising wire bonding to the at least one copper interconnector through the organic coating.

10. The method of claim 8, further comprising: removing the organic coating after patterning the polyimide layer (54); and wire bonding to the at least one copper interconnector through the at least one opening (56).

11. The method of claim 10, wherein removing the organic coating further comprises cleaning or etching.

12. The method of claim 8, further comprising reducing the formation of copper oxide by applying the organic coating over each copper interconnect.

13. The method of claim 8, wherein the polyimide layer (54) directly contacts the organic coating.

14. The method of claim 10, wherein the at least one opening (56) in the polyimide layer (54) over the at least one copper interconnect exposes only copper of the at least one copper interconnect.

15. The method of claim 9, wherein the at least one opening (56) in the polyimide layer (54) over the at least one copper interconnect exposes only the organic coating over the at least one copper interconnect.

16. A method of forming interconnects, the method comprising: forming a seed layer (40) over a plurality of pads (34); patterning a photoresist layer (42) having a plurality of openings (44) exposing the plurality of pads (34); forming a plurality of copper interconnects (48) by electroplating each of the plurality of copper interconnects (48) into each of the plurality of openings (44); applying an aluminum layer over each of the plurality of copper interconnects (48); removing the photoresist layer (42); etching the seed layer (40); and patterning a polyimide layer (54) over the plurality of copper interconnects (48) to form at least one opening (56) over at least one of the plurality of copper interconnects (48).

17. The method of claim 16, wherein applying an aluminum layer further comprises atomic layer depositing the aluminum layer on each of the plurality of copper interconnects (48) prior to removing the photoresist layer (42).

18. The method of claim 16, wherein applying an aluminum layer further comprises atomic layer depositing the aluminum layer on each of the plurality of copper interconnects (48) after removing the photoresist layer (42).

19. The method of claim 16, further comprising wire bonding to the at least one copper interconnect through the aluminum layer.

20. The method of claim 16, further comprising reducing the formation of copper oxide by applying the aluminum layer over each copper interconnect.

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