Method for forming semiconductor device and semiconductor device

By forming a high-k gate dielectric layer in the semiconductor device and doping lanthanum into the annealing process, the problem of multiple depletion effects in metal oxide semiconductor devices is solved, tuning the threshold voltage is achieved, and the performance of the device is improved. Programmability.

CN113284950BActive Publication Date: 2024-12-24TAIWAN SEMICONDUCTOR MANUFACTURING CO LTD
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Patent Information

Application Number
CN202110046200.0
Authority / Receiving Office
CN · China
Patent Type
Patents(China)
Current Assignee / Owner
Priority Date
2020-07-27
Filing Date
2021-01-14
Publication Date
2024-12-24
Estimated Expiration
2041-01-14

AI Technical Summary

Technical Problem

There is a multiple depletion effect in metal oxide semiconductor (MOS) devices, which leads to an increase in the thickness of the effective gate dielectric, making it difficult to generate an inverse layer on the semiconductor surface, and the formation of metal gates is complex, making it difficult to meet the different requirements of NMOS and PMOS devices. .

Method used

By forming high-k gate dielectric layers located on different semiconductor regions in the semiconductor device, and in the annealing process, the lanthanum in the lanthanum-containing layer is incorporated into these dielectrics, the threshold voltage is tuned, and the threshold voltage tuning of different series of threshold voltages is achieved. .

Benefits of technology

It effectively solves the multi-depletion effect, improves the performance of the gate dielectric, realizes selective tuning of the threshold voltage, meets the requirements of different semiconductor devices, and improves the programmability of the device.

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Abstract

A method for forming a semiconductor device includes: forming a first gate dielectric, a second gate dielectric, and a third gate dielectric respectively located above a first semiconductor region, a second semiconductor region, and a third semiconductor region. The method also includes: depositing a first lanthanum-containing layer covering the first gate dielectric; and depositing a second lanthanum-containing layer covering the second gate dielectric. The second lanthanum-containing layer is thinner than the first lanthanum-containing layer. Then an annealing process is performed to drive the lanthanum in the first lanthanum-containing layer and the second lanthanum-containing layer into the first gate dielectric and the second gate dielectric, respectively. During the annealing process, there is no lanthanum-containing layer on the third gate dielectric. According to other embodiments of the present application, a semiconductor device is also provided.
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