Integrated circuit for storing data and medium for storing digital representation of the integrated circuit

Abstract

A structure of an integrated circuit for storing data is disclosed. The integrated circuit includes a memory cell array of bit cells configured in a static random access memory (SRAM) architecture. The memory cell array is coupled to word lines arranged in rows, which control operations such as read operations and write operations. In order to enhance the read sensing margin of the SRAM configuration, the read port of the bit cell may include a word line that drives two transistors (e.g., a PMOS transistor and an NMOS transistor) to reduce data-related current leakage from the read bit line. An additional weak transistor keeper configuration may be used in the integrated circuit to compensate for current leakage from the read bit line. For example, a weak NMOS keeper including a sense amplifier, an inverter, and an NMOS connected to a supply voltage VDD provides a path between the read bit line and VDD through the weak NMOS keeper.

Description

[0001] CROSS-REFERENCE TO RELATED APPLICATIONS

[0002] This application claims priority to Indian application serial number 201911000569 filed on January 5, 2019, the entire contents of which are incorporated by reference. Technical Field

[0003] The present disclosure relates generally to the field of memory cells, and more particularly to static random access memories (SRAMs). Background Art

[0004] System-on-chip (SOC) designs are widely used in consumer electronics due to their lower power consumption and smaller form factor. These advantages have promoted the application of SOC designs in wearable devices, Internet of Things (IoT) products, and medical devices. SOC systems are designed to improve energy efficiency to maximize system life. Operation at the minimum energy point can be achieved by scaling the dynamic voltage to a lower supply voltage. In current SOCs, SRAM occupies a large circuit area and consumes a lot of power and energy. For example, traditional six-transistor (6T) SRAM cannot operate optimally at ultra-low voltages due to degradation of design parameters such as static noise margin (SNM), poor read and write margins, and exponentially increasing sensitivity to process voltage temperature (PVT) fluctuations.

[0005] Although eight-transistor (8T) SRAM cells with independent read ports for decoupled read and write operations have been designed to improve operation in ultra-low voltage applications and increase cell stability, these 8T SRAM cell designs may be affected by data-dependent read bit line (RBL) leakage through their read ports. RBL leakage reduces the read sensing margin of 8T SRAM cells by minimizing the voltage and time window (e.g., due to the small switching current ratio at ultra-low voltage). Decoupled SRAM cells are also designed to improve their RBL sensing margin. For example, a 10-transistor (10T) SRAM cell has been designed to inject leakage current from an unselected cell to the RBL, regardless of the stored data, to improve the sensing margin. However, due to the stacking of three N-type metal oxide semiconductors (NMOS) in the read '0' discharge path, this particular 10T SRAM design suffers from read '0' delay degradation. BRIEF DESCRIPTION OF THE DRAWINGS

[0006] The disclosed embodiments have other advantages and features, which will become more apparent from the detailed description, the appended claims and the accompanying drawings (or figures). A brief description of the drawings is as follows.

[0007] Figure 1Depicted is a circuit diagram illustrating an 8T SRAM cell in accordance with at least one embodiment.

[0008] Figure 2 Depicted is a circuit diagram illustrating a 10T SRAM cell in accordance with at least one embodiment.

[0009] Figure 3 The principle of RBL sensing for 8T SRAM cells through two read operation embodiments according to at least one embodiment is shown.

[0010] Figure 4 The principle of RBL sensing for a 10T SRAM cell through two read operation embodiments according to at least one embodiment is shown.

[0011] Figure 5 is a graph showing the ratio of 8T SRAM and 10T SRAM RBL leakage current as a function of supply voltage according to at least one embodiment.

[0012] Figure 6 is a graph illustrating RBL sensing margins of 8T SRAM and 10T SRAM cell configurations based at least on temperature according to at least one embodiment.

[0013] Figure 7 is a graph illustrating RBL sensing margins of 8T SRAM cells and 10T SRAM cells based at least on the number of cells per RBL according to at least one embodiment.

[0014] Figure 8 is a graph illustrating RBL sensing margin variation over time for an 8T SRAM cell and a 10T SRAM cell according to at least one embodiment.

[0015] Fig. 9 Depicted is a circuit diagram illustrating a weak P-type metal oxide semiconductor (PMOS) keeper for a 10T SRAM cell array in accordance with at least one embodiment.

[0016] Fig.10 A circuit diagram illustrating a weak NMOS keeper for a 10T SRAM cell array in accordance with at least one embodiment is depicted.

[0017] Fig.11 is a graph illustrating an RBL voltage based on a supply voltage VDD according to at least one embodiment.

[0018] Fig.12 is a graph illustrating read latency based on VDD according to at least one embodiment.

[0019] Fig.13Depicted is a flow chart of various operations in the design and fabrication of integrated circuits in accordance with at least one embodiment.

[0020] FIG. 14A to FIG. 14C Depicted is a block diagram of a computer system suitable for embodiments of the present technology as well as circuit designs and circuit embodiments of the technology in accordance with at least one embodiment. DETAILED DESCRIPTION

[0021] The drawings and the following description relate to the preferred embodiments by way of illustration only.It should be noted that from the following discussion, alternative embodiments of the structures and methods disclosed herein should be readily identified as viable alternatives that can be employed without departing from the principles of the claimed invention.

[0022] Reference is now made in detail to several embodiments, examples of which are shown in the accompanying drawings. It should be noted that similar or identical reference numerals may be used in the drawings whenever feasible and may indicate similar or identical functions. The accompanying drawings depict embodiments of the disclosed systems (or methods) for illustrative purposes only. It should be readily appreciated by those skilled in the art from the following description that alternative embodiments of the structures and methods illustrated herein may be employed without departing from the principles described herein.

[0023] Circuit Configuration Overview

[0024] One embodiment of the disclosed system, method, and computer readable storage medium includes data-independent current leakage to improve read sensing margin in SRAM cells and compensation for current leakage through weak NMOS keepers that reduces the minimum supply voltage required to operate the SRAM cells. A "cell" or "bit cell" as referred to herein refers to a portion of an integrated circuit in which a single bit is stored.

[0025] Figure 1A circuit diagram illustrating an 8T SRAM cell 100 is depicted. The 8T SRAM cell 100 includes a write port 102 and a read port 104. The write port 102 contains data storage portions of values ​​Q and QB (i.e., a "Q bar"), where QB is the inverse of Q. The read port 104 is decoupled (e.g., the RBL 124 of the read port 104 is separated from the write bit line (WBL) of the write port 202) to reduce the likelihood that a read operation interferes with current traveling into a data storage node, thereby improving static noise margin. The read port 104 includes transistors 111 and 112. Transistor 111 is coupled to a read word line (RWL), transistor 112, and RBL 124, such that when RWL='0' (i.e., a logic value on RWL is zero), the read port operates in a standby state, and when RWL='1', the read port 104 operates in a read state. In the standby state, transistor 111 is in the 'OFF' state, and data QB is not driven onto RBL 124. In the read state, transistor 111 is in the 'ON' state, and data QB is driven onto RBL 124. Transistor 112 is coupled to transistor 111, a data storage node (e.g., a data storage node associated with data value QB) via path 122, and a common ground, such that when QB='0', transistor 112 is turned off, and when QB='1', transistor 112 is turned on. In some embodiments, transistors 111 and 112 are NMOS transistors

[0026] Prior to a read operation, RBL is pre-charged to a logic value of '1'. During a read operation, transistor 111 is turned on and the value of QB is driven onto RBL 124. The operation of reading Q='0' is referred to herein as "RBL reads '0'". For RBL reads '0', QB, which is the inverse of Q, is '1', thereby turning on transistor 112. In the case where both transistors 111 and 112 are turned on, the charge on RBL is discharged to a common ground. A logic value '0' may be determined based on the discharge. The operation of reading Q='1' is referred to herein as "RBL reads '1'". For RBL reads '1', QB is '0', thereby turning off transistor 112. In the case where transistor 111 is turned on and transistor 112 is turned off, in some embodiments, the charge on RBL 124 is not discharged to a common ground, and a logic value '1' is determined based on the charge held on RBL 124.

[0027] Figure 2A circuit diagram illustrating a 10T SRAM cell 200 is depicted. The 10T SRAM cell 200 includes a write port 202 and a read port 204. The write port 202 contains data storage portions of values ​​Q and QB (i.e., a "Q bar"), where QB is the inverse of Q. The read port 204, similar to the read port 104 of the 8T SRAM cell 100, is decoupled (e.g., the RBL 224 of the read port 204 is separated from the write bit line (WBL) of the write port 202) to reduce the likelihood that a read operation interferes with current traveling into a data storage node, thereby improving static noise margin. The read port 204 is a 4-transistor (4T) read port including transistors 211 to 214. Compared to the configuration of the 8T SRAM cell 100, the 10T SRAM cell 200 includes additional transistors 213 and 214 in its configuration. Transistor 211 is coupled to RWL, transistor 212, and RBL 224. Transistor 212 is coupled to transistor 211, transistor 213, and a common ground. Transistor 213 is coupled to a read word line bar (RWLB), a data storage node (e.g., a data storage node associated with data value QB) through path 222, transistor 212, and transistor 214. Transistor 214 is coupled to RWLB, transistor 212, transistor 213, and a common ground. In some embodiments, transistors 211, 212, and 214 are NMOS transistors and transistor 213 is a PMOS transistor. The configuration of transistor 211 is designed to enable standby and read operations such that when RWL='0', read port 204 operates in a standby condition, and when RWL='1', read port 204 operates in a read condition. When RWL='0', read word line bar (RWLB)='1' because its value is the inverse of the value of RWL. Thus, in the standby condition, transistor 211 is in the 'OFF' state, transistor 213 is in the 'OFF' state, transistor 214 is in the 'ON' state, and data QBT is not driven onto RBL 224. In the read condition, transistor 211 is in the 'ON' state and data QBT is driven onto RBL 224 (e.g., QBT is driven to the common ground because transistor 214 is in the 'ON' state).

[0028] In some embodiments, the configuration of transistors 213 and 214 (eg, Figure 4) allows data-independent leakage current in the read port 204 by using a configuration of driving transistor 212 using QBT instead of QB. Due to the configuration similarity between transistors 111 and 112 in the 8T SRAM cell 100 and transistors 211 and 212 in the 10T SRAM cell 200, the read port 204 is capable of RBL discharge similar to the 8T SRAM cell 100. However, in order to drive transistors 212 and 213, an additional RWLB signal is routed for data-independent RBL discharge, and the maximum leakage of the read port 204 is reduced compared to the maximum leakage of the read port 104 during standby operation.

[0029] Performance Analysis of Circuit Configurations

[0030] Figure 3 The RBL sensing principle of an 8T SRAM cell is illustrated through two read operation embodiments. Read operation embodiments 300a and 300b illustrate data-dependent current leakage scenarios for an 8T SRAM cell array (e.g., current leakage depends on the data stored in unselected cells). Read operation embodiment 300a illustrates a value of '0' (e.g., Q='0' and QB='1') read onto the RBL, represented as 'RBL0', to correspond to the read value. Read operation embodiment 300b illustrates a value of '1' (e.g., Q='1' and QB='0') read onto the RBL, represented as 'RBL1', to correspond to the read value. Two-transistor (2T) read ports 301a, 302a, 301b, and 302b are coupled (although Figure 3 1 and 112). Read ports 301a and 302a correspond to SRAM cells including corresponding write ports of corresponding data storage nodes (e.g., data storage nodes for Q and QB). Read ports 301a and 302a are respectively the same read ports as 301b and 302b, but different signals are applied at the gates of the transistors depending on the data stored in the cells of the array of different read operation embodiments. Thus, the configuration described using read ports 301a and 302a applies to the same figure numbers of read ports 301b and 302b. Read port 301a includes transistors 311a and 312a with a configuration similar to that of transistors 111 and 112. Read port 302a includes transistors 315a and 316a with a configuration also similar to that of transistors 111 and 112. As shown Figure 3 As depicted, read ports 301a and 301b correspond to selected cells, while read ports 302a and 302b correspond to unselected cells (eg, the RBL is reading values ​​from the selected cell but not the unselected cells).

[0031] During the read operation embodiment 300a, the selected cell is storing the value of QB = '1', while the unselected cells are storing the value of QB = '0'. RBL0 is precharged to a logic value of '1' and is reading QB = '1' (i.e., Q = '0'). Transistors 311a and 312a are in the "ON" state, and RBL0 passes current I cell_8T Although the unselected cells are holding the value of QB = '0' and RWL is '0' to enable the standby operation of the unselected cells, the minimum drain current I leak_min_8T Discharge from RBL0 through transistors 315a and 316a. Minimum leakage notation is used to reflect the minimum leakage from the read port that occurs when RWL is '0' and QB is '0', thereby 'turning off' the corresponding transistor (e.g., transistors 315a and 316a). Thus, during the read operation embodiment 300a, the total current discharged from RBL0 is I cell_8T +I leak_min_8T The read operation embodiment 300a may reflect a conditional worst-case read '0' operation (ie, data-dependent current leakage when QB='0' at unselected cells).

[0032] During the read operation embodiment 300b, the selected cell is holding a value of QB='0' and the unselected cell is holding a value of QB='1'. RBL1 is precharged to a logic value of '1' and is reading QB='0' (i.e., Q='1'). Transistor 311b is in the 'ON' state, transistor 312b is in the 'OFF' state, and RBL1 is pulled up by the value of RWL='1' so that a logic value of '1' can be maintained on RBL1. Although transistor 315b is in the 'OFF' state, there is a leakage current through transistor 315b and through the 'ON' transistor 316b. This leakage current I leak_max_8T is the maximum leakage current through the unselected cells. Thus, during the read operation embodiment 300b, the total current discharged from RBL1 is I leak_max_8T In some embodiments, I leak_max_8T Depends on the number of unselected cells connected to RBL. The read operation embodiment 300b may reflect a conditional worst read '1' operation (ie, data dependent current leakage when QB='1' at unselected cells).

[0033] In some embodiments, data-dependent current leakage limits the maximum number of bit cells per RBL and results in a small RBL sensing margin. Graph 320 depicts the RBL sensing margin of an 8T SRAM cell array over time. The voltage difference between the charges on RBL0 and RBL1 is represented on the y-axis, while time is represented on the x-axis. In some embodiments, the RBL sensing margin is based on the current difference RBL0-RBL1 or (Icell_8T +I leak_min_8T )-(I leak_max_8T ) is determined. In the graph 320, the voltage of RBL0 over time is depicted as a dashed line, while the voltage of RBL1 over time is depicted as a solid line. The vertical dotted line represents the time when RWL switches from '0' to '1'. For a 10T SRAM cell array, Figure 4 As described in the description of , since the additional RWLB signal drives the additional two transistors, the RBL sensing margin is increased compared to the margin of the 8T SRAM cell array.

[0034] Figure 4 The RBL sensing principle of a 10T SRAM cell is illustrated through two read operation embodiments. Read operation embodiments 400a and 400b illustrate data-independent current leakage scenarios for a 10T SRAM cell array (e.g., current leakage is independent of data held in unselected cells). Read operation embodiment 400a illustrates a value of '0' (e.g., Q='0' and QB='1') read onto the RBL, represented as 'RBL0', to correspond to the read value. Read operation embodiment 400b illustrates a value of '1' (e.g., Q='1' and QB='0') read onto the RBL, represented as 'RBL1', to correspond to the read value. 2T read ports 401a, 402a, 401b, and 402b are coupled (although Figure 4 10T SRAM memory cell configuration). The 10T SRAM memory cell configuration includes an additional PMOS transistor and an NMOS transistor (e.g., transistors 213 and 214) to correspond to the SRAM cell of the corresponding 'QBT' node. Read ports 401a and 402a are the same read ports as 401b and 402b, respectively, but different signals are applied at the gates of the transistors depending on the data stored in the cells of the array for different read operation embodiments. Thus, the configuration described using read ports 401a and 402a applies to the same figure numbers of read ports 401b and 402b. Read port 401a includes transistors 411a and 412a with a configuration similar to that of transistors 111 and 112. Read port 402a includes transistors 415a and 416 with a configuration also similar to that of transistors 111 and 112. Since (although not depicted in Figure 4 ) RWLB and two additional transistors are added, so the transistor 416 in the unselected cell is driven by QBT='0' during standby operation. Because the transistor 416 is always in the "OFF" state during standby operation, there is no data-dependent current leakage. For example, the current leakage in different unselected cells is the same regardless of what data value each unselected cell holds. Figure 4As depicted, read ports 401a and 401b correspond to selected cells, while read ports 402a and 402b correspond to unselected cells (eg, the RBL is reading values ​​from the selected cell but not the unselected cells).

[0035] During the read operation embodiment 400a, the selected cell is storing the value of QB = '1', while the unselected cells are storing the value of QB = '0'. RBL0 is precharged to a logic value of '1' and is reading QB = '1' (i.e., Q = '0'). Transistors 411a and 412a are in the "ON" state, and RBL0 passes current I cell_10T Although the unselected cells are holding the value of QB = '0' and RWL is '0' to enable the standby operation of the unselected cells, the minimum drain current I leak_10T The total current discharged from RBL0 is I cell_10T +I leak_10T .

[0036] During the read operation embodiment 400b, the selected cell is holding a value of QB='0' and the unselected cell is holding a value of QB='1'. RBL1 is precharged to a logic value of '1' and is reading QB='0' (i.e., Q='1'). Transistor 411b is in the 'ON' state, transistor 412b is in the 'OFF' state, and RBL1 is pulled up by the value of RWL='1' so that a logic value of '1' can be maintained on RBL1. Although transistor 415b is in the 'OFF' state, there is a leakage current I through transistor 415b and through the 'ON' transistor 416. leak_10T Thus, during the read operation embodiment 400b, the total current discharged from RBL1 is I leak_10T In some embodiments, I leak_10T Depends on the number of unselected cells connected to the RBL.

[0037] Graph 420 depicts the RBL sensing margin of a 10T SRAM cell array over time. Similar to graph 320, the y-axis of graph 420 represents the voltage difference between the charges on RBL0 and RBL1, while the x-axis represents time. In some embodiments, the RBL sensing margin is based on the current difference RBL0-RBL1 or In some embodiments, and The RBL sensing margin of the 10T SRAM cell array is larger than that of the 8T SRAM cell array. Because there is no data-dependent current leakage in the 10T SRAM cell array, the maximum number of bit cells per RBL may be less constrained.

[0038] Performance Analysis of Circuit Configurations

[0039] Now, refer to Figures 5 to 8 , illustrates a graph comparing the performance of an 8T SRAM cell array configuration and a 10T cell array configuration.

[0040] Figure 5 is a graph illustrating the ratio of leakage current of 8T SRAM and 10T SRAM as a function of supply voltage. Figure 5 The data can be obtained using simulation scenarios with read '1' operation, process corners of fast NMOS and fast PMOS (FF), temperatures of 80°C and 150°C, QB='1' for the unselected read port of 8T SRAM, and QBT='0' for the unselected read port of 10T SRAM. The simulation can be run on software such as Synopsys HSPICE Simulator to obtain the RBL leakage of the 8T SRAM cell and the 10T SRAM cell shown, which are operated at different operating voltages from 0.2V to 1V with a step of 0.1V. The leakage ratio at 80°C is shown in data set 510, while the leakage ratio at 150°C is shown in data set 520. The current leakage ratio of data set 510 is higher than the leakage ratio of 520. For each incremental supply voltage, the RBL leakage current of the 10T SRAM cell is improved by about 15% compared to the RBL leakage current of the 8T SRAM cell.

[0041] Figure 6 is a graph illustrating RBL sensing margins for at least an 8T SRAM cell configuration and a 10T SRAM cell configuration based on temperature. A simulation setup with 256 cells per RBL and a supply voltage VDD of 0.35V can be used to obtain Figure 6The simulation results are shown in the curve graph of . Data set 510 corresponds to the RBL sensing performance of the 8T SRAM cell configuration, while data set 520 corresponds to the RBL sensing performance of the 10T SRAM cell configuration. Three process corners are compared in conjunction with the 8T SRAM configuration and the 10T SRAM configuration: FF, typical NMOS typical PMOS (TT), and slow NMOS slow PMOS (SS). In some embodiments, the 10T SRAM cell array achieves an improvement in the RBL sensing margin at certain process corners and temperatures. For example, at the process corner fast NMOS fast PMOS (FF) and a temperature of 150°C, which may be the worst scenario for RBL leakage, the RBL detection margin of the 10T SRAM cell array can be improved by approximately 100mV compared to the 8T SRAM cell array.

[0042] Figure 7 is a graph illustrating the RBL sensing margin of an 8T SRAM cell and a 10T SRAM cell based at least on the number of cells per RBL. The RBL sensing margin is shown as a percentage of the supply voltage VDD. The RBL sensing margin can be obtained using a simulation setup with 0.35V VDD and FF process corner. Figure 7 The simulation results are shown. The RBL sensing margin at 150°C in the 10T SRAM under the data set 720 is about 30% higher than the RBL sensing margin at 150°C in the 8T SRAM under the data set 710. The RBL sensing margin at 80°C in the 10T SRAM under the data set 722 is about 15% higher than the RBL sensing margin at 80°C in the 8T SRAM under the data set 720. Furthermore, the 10T SRAM supports up to 1024 cells per RBL at 80°C and 150°C, while the 8T SRAM only supports 1024 cells per RBL at 80°C.

[0043] Number of cells per RBL 8T；150℃ 10T；150℃ 8T；80℃ 10T；80℃ 128 60.86 78.57 93.43 98 256 36.86 63.71 82.29 90.86 512 11.43 46.86 67.14 82.86 1024 9.71 30 46.57 71.14

[0044] Table 1: RBL sensing margin per number of cells in RBL

[0045] Figure 8 8T SRAM cell and 10T SRAM cell RBL sensing margin over time. The RBL sensing time window can be critical for single-ended sense amplifier sensing. For data set 810, an 8T SRAM with 256 cells per RBL is depicted, the sensing time window is approximately 50 picoseconds with an RBL sensing voltage of 19mV. In some embodiments, both the 50ps sensing time window and the 19mV RBL sensing voltage are negligible. In contrast, Figure 8Improved sensing time window and RBL sensing voltage for 10T SRAM are shown. For data set 820, a 10T SRAM with 256 cells per RBL is depicted, the sensing time window is approximately 500ps, and the RBL sensing voltage is 155mV. Similar improvements are shown by data sets 822 and 824 for 10T SRAM configurations, where the number of cells per RBL is increased.

[0046] Additional circuit configuration

[0047] In some embodiments, RBL single-ended sensing employs large signal sensing through a sense inverter and a weak transistor keeper (eg, a weak PMOS keeper). Fig. 9 and Fig.10 Circuit diagrams for large signal sensing using weak PMOS keepers and weak NMOS keepers are depicted respectively. The weak PMOS keepers can be used to compensate for current leakage through unselected cells of an SRAM cell array. Although Fig. 9 and Fig.10 The weak PMOS keeper configuration and the NMOS keeper configuration of a 10T SRAM cell array are depicted, but the weak PMOS keeper configuration and the NMOS keeper configuration may also be applied to other SRAM configurations (eg, an 8T SRAM cell array).

[0048] Fig. 9A circuit diagram 900 illustrating a weak PMOS keeper 920 for a 10T SRAM cell array is depicted. The cells (e.g., cells 901 and 902) of the 10T SRAM cell array are coupled to a sense inverter 930 and a weak PMOS keeper 920. Although not depicted, more cells can be coupled (e.g., 256 cells are coupled). The configuration of the read ports of cells 901 and 902 is similar to that of the read port 204 (i.e., the QBT drives the transistor of the read port). RBL 910 generates a path that couples the cell to the input of the sense inverter 930 and the PMOS source of the weak PMOS keeper 920. The weak PMOS keeper 920 includes four PMOS transistors. Three of the four PMOS transistors are driven by the VSS voltage at their gates, and when VSS is low, the supply VDD is driven through each of the three PMOS. The fourth PMOS transistor is coupled to the sense inverter, RBL, and three VSS driven PMOSs so that when the RBL 910 is reading QBT='1', the fourth PMOS selectively compensates for leakage current. For example, when the RBL 910 is reading a logic value of '1', the output of the sense inverter is '0', which acts as the value of 'Q' and acts as a driver for a weak PMOS keeper to compensate for leakage current by enabling a path from the RBL 910 through the 'ON' PMOS transistor to the supply voltage VDD. In some embodiments, the configuration depicted in Figure 900 presents a design choice of a tradeoff between a larger RBL sensing margin and a read '0' timing (e.g., minimizing the time delay to read '0' or discharge the RBL to '0'). At the process corner of slow NMOS fast PMOS (SF), the read '0' timing may be worse, thereby limiting the minimum VDD or lowest operating voltage. As the minimum VDD increases, the speed of discharging the RBL to read 0 may increase.

[0049] Fig.10A circuit diagram 1000 illustrating a weak NMOS keeper 1020 for a 10T SRAM cell array is depicted. The cells (e.g., cells 1001 and 1002) of the 10T SRAM cell array are coupled to a sense inverter 1030 and a weak NMOS keeper 1020. Although not depicted, more cells may be coupled. The configuration of the read ports of cells 1001 and 1002 is similar to that of read port 204 (i.e., the QBT drives the transistor of the read port). RBL 1010 creates a path that couples the cell to the input of the sense inverter 1030 and the source of the NMOS of the weak NMOS keeper 1020. The NMOS is also coupled to VDD and driven by the output of the inverter. The value of the inverter output RBL connected to the output of the sense inverter 1030 is input. When RBL 1010 is reading QBT='1', weak NMOS keeper 1020 compensates for leakage current, and when RBL 1010 is reading QBT='0', no leakage current is compensated (e.g., NMOS is "OFF" and RBL has no path to VDD). In some embodiments, using a weak NMOS keeper instead of a weak PMOS keeper improves the minimum VDD (e.g., allowing a lower VDD sufficient to operate the SRAM) and read '0' timing at certain process corners.

[0050] Performance Analysis of Additional Circuit Configurations

[0051] Now, refer to Fig.11 and Fig.12 , illustrates a graph comparing the performance of a weak PMOS keeper configuration and a weak NMOS keeper configuration for a 10T SRAM cell array.

[0052] Fig.11 The results depicted in can be obtained by simulation setup of 256 cells per RBL and by sweeping VDD from 0.35V to 0.6V for all process corners (i.e., FF, fast NMOS slow PMOS (FS), SF, SS, and TT) at both temperatures -40°C and 150°C. In some embodiments, the simulation setup includes a 10T SRAM with a low voltage threshold (LVT), a sense inverter (e.g., a minimum size inverter) with LVT, a weak PMOS keeper with LVT and size NFIN=2 (i.e., two FINs of a transistor), and a weak NMOS keeper with an ultra-low voltage threshold (ULVT) where NFIN=2 and NFIN=3.

[0053] Fig.11 is a graph illustrating RBL voltages for various weak PMOS keeper configurations and weak NMOS keeper configurations based on supply voltage VDD. Fig.11Embodiments of worst-case process corner simulation results (e.g., worst of FF, SF, FS, SS, and TT) for reading a '1' at 150°C, reading a '0' at -40°C, and sense inverter trip points at 150°C and -40°C are depicted. For a weak PMOS keeper, line 1101 is the worst read '1' at 150°C. In some embodiments, a read '0' failure occurs when the RBL voltage is above the sense inverter trip point, and a read '1' failure occurs when the RBL voltage is below the sense inverter trip point. At VDD=0.38V, line 1101 is below the worst sense inverter trip point at 150°C (i.e., line 1103), indicating that the worst read '1' failure occurs at 150°C. For a weak PMOS keeper, line 1102 is the worst read '0' at -40°C. At VDD = 0.49V, line 1102 is above the worst sense inverter trip point at -40°C trip point (i.e., line 1104), indicating that the worst read '0' failure occurs at -40°C. Therefore, for the weak PMOS keeper, the lowest 0.5V VDD is limited by the worst read '0' at -40°C (i.e., at least 0.5V is required to avoid both read '0' and '1' failures).

[0054] Lines 1105 to 1107 correspond to weak NMOS keeper simulation data. For the RBL voltage of a weak NMOS keeper with NFIN=3 at 150°C (as depicted by line 1105), the minimum VDD for the worst read '1' is 0.41V (i.e., the voltage before line 1105 is lower than the line 1103 crossing). Therefore, for a weak NMOS keeper with NFIN=3, the minimum VDD of 0.41V is limited by the worst read '1' operation at 150°C. For the RBL voltage of a weak NMOS keeper with NFIN=2 at 150°C as depicted by line 1106, there is a minimum VDD for the worst read '1' of 0.45V. Therefore, for an NMOS keeper with NFIN=2, the minimum VDD of 0.45V is limited by the worst read '1' operation at 150°C. For the RBL voltage of the weak NMOS keeper with NFIN=3 at -40°C as depicted by line 1107, the minimum VDD is not limited by the worst read '0'. In some embodiments, the minimum VDD of the weak PMOS keeper (e.g., limited to 0.5V to properly perform the read '0' and '1' functions) is greater than the minimum VDD of the weak NMOS keeper (e.g., limited to 0.45V to properly perform the read '0' and '1' functions). Fig.11 The weak NMOS keeper configuration shown can achieve better than Fig.10 A 50mV improvement for the weak PMOS keeper configuration is shown.

[0055] Fig.121203 is a graph illustrating the read delay based on VDD for a weak PMOS keeper configuration and a weak NMOS keeper configuration as described herein. For three 10T SRAM configurations, simulation results of read '0' delay at -40°C are depicted as a function of VDD: a weak PMOS keeper with a minimum VDD of 0.5V (e.g., line 1201), a weak NMOS keeper with NFIN=3 and a minimum VDD of 0.41V (e.g., line 1202), and a weak NMOS keeper with NFIN=2 and a minimum VDD of 0.45V (e.g., line 1203). In some embodiments, the read '0' delay is determined as the time it takes for Q to rise to 80% based on the time it takes for RWL to rise to 50% of the maximum voltage charge. Compared to the weak NMOS keepers depicted by lines 1202 and 1203, the read '0' delay shown increases faster as the minimum VDD applied to the weak PMOS keeper depicted by line 1201 decreases. Thus, the weak NMOS keeper can improve the read '0' delay at -40°C.

[0056] Electronic Design Automation Systems and Workflows

[0057] Fig.13 Various processes 1300 for transforming and verifying design data and instructions representing an integrated circuit are illustrated when designing, verifying, and manufacturing an article such as an integrated circuit using software tools with a computer and possibly special hardware aids. The term 'EDA' represents the term 'electronic design automation'. These processes begin at 1310, where a product idea is created using information supplied by a designer; at 1312, the information is transformed during the process of creating an article (referred to herein as a design or device), which uses an EDA software tool, also referred to herein as EDA software, as a design tool or using a verification tool. At 1334, when the design is complete, the design can be taped off, which is typically sending the artwork (e.g., geometric pattern) of the integrated circuit to a manufacturing plant to manufacture a mask set, which is then used to manufacture the integrated circuit. After taping off, at 1336, a semiconductor die is manufactured; and, at 1338, a packaging and assembly process is performed, so that at 1340, an integrated circuit is completed, which can also be represented herein as a circuit, device, component, chip, or SoC (system on chip).

[0058] Articles of manufacture (e.g., circuits or systems) are used in business at a variety of levels of abstraction, which may range from low-level transistor layouts to high-level description languages. Most designers begin designing circuits and systems at a higher level of abstraction using a hardware description language ('HDL') such as VHDL, Verilog, SystemVerilog, SystemC, MyHDL, or OpenVera. High-level HDLs are easier for developers to understand, especially for large systems, and can describe highly complex concepts that are difficult to grasp using lower levels of abstraction. High-level HDL descriptions can be converted to logic-level register transfer level ('RTL') descriptions, gate-level descriptions, layout-level descriptions, or mask-level descriptions. Each lower level of abstraction introduces more detail into the design description. Lower levels of abstraction can be automatically generated by a computer, derived from a design library, or created by another design automation program. An example of a specification language at a lower level of abstraction that is used to describe simulation-based circuits in detail is SPICE.

[0059] The design process using EDA software tool 1312 includes processes 1314 to 1332, which are described below. This design flow description is for illustrative purposes only and is not intended to limit the present disclosure. For example, actual integrated circuit design may require the designer to perform design operations in a different order than described herein.

[0060] During system design 1314, designers describe the functionality to be manufactured. Designers may also perform what-if planning to refine functionality and check costs, etc. Hardware-software architecture partitioning may be performed at this stage.

[0061] During logic design and functional verification 1316, modules in the circuit are specified in one or more hardware description languages ​​or HDLs, and the functional accuracy of the design in the HDL is checked, that is, to match the requirements of the specification of the circuit or system designed to ensure that the design produces the correct output. For example, the functional accuracy of the module corresponding to the SRAM memory array in the circuit can be checked to verify the proper read '0' operation and read '1' operation using data-independent leakage. In one embodiment, the functional accuracy of the transistor keeper module (e.g., a weak NMOS keeper configuration) is checked to verify the proper compensation for RBL current leakage. Exemplary HDL languages ​​are Verilog, VHDL, and SystemC. Functional verification is typically accomplished using software-based simulators and other tools such as test bench generators, static HDL checking tools, and formal verification tools. In some cases, special hardware called 'emulators' or 'prototyping systems' is used to accelerate functional verification.

[0062] During synthesis and design for test 1318, the HDL code is transformed into a netlist. The netlist can be optimized for the target technology. Additionally, tests can be designed and implemented to check the finished integrated circuit.

[0063] During netlist verification 1320 , the netlist is checked to see if it meets timing constraints and corresponds to the HDL code.

[0064] During design planning 1322, an overall floor plan of the integrated circuit is constructed and analyzed for timing and top-level routing.

[0065] During layout implementation 1324, physical placement (positioning of circuit elements such as transistors or capacitors) and routing (connection of circuit elements by multiple conductors) occurs, and library cells may be selected to perform a particular logic function.

[0066] During analysis and extraction 1326, circuit functionality is verified at the layout level, which permits refinement of the layout design.

[0067] During physical verification 1328, the layout design is checked to ensure the correctness of manufacturing constraints, such as DRC constraints, electrical constraints, lithography constraints, and that the circuit system functionality matches the HDL design specifications.

[0068] During resolution enhancement 1330, geometric manipulation of the layout is performed to improve the manufacturability of the design.

[0069] During tape-out, data is created for use in producing lithography masks (after applying lithography enhancements, if appropriate).

[0070] During mask data preparation 1332, tape-out data is used to produce photolithography masks that are used to produce finished integrated circuits.

[0071] For all of the integrated circuit design tools mentioned above, similar tools from other EDA vendors such as Cadence, Siemens, other corporate entities, or various non-commercial tools from universities, or open source repositories may be used as alternatives.

[0072] The various embodiments of the present disclosure may be used during one or more of the above stages. Specifically, some embodiments of the present disclosure may be used for EDA software 1312 .

[0073] The storage subsystem is preferably used to store some or all of the EDA tools described herein and programs and data structures for developing units of the library and for using the physical and logical designs of the library. These programs and data structures are usually executed by one or more processors in a manner known to those of ordinary skill in the art.

[0074] General computer system applications

[0075] Fig.14A , Fig. 14B and Fig. 14C is a simplified block diagram of a computer system suitable for use with embodiments of the technology, as well as circuit designs and circuit embodiments of the technology.

[0076] exist Fig.14A , the computer system 1410 typically includes at least one computer or processor 1414, which communicates with several peripheral devices via a bus subsystem 1412. Typically, the computer may include or the processor may be any of the following: a microprocessor, a graphics processing unit, or a digital signal processor and its electronic processing equivalents (such as an application specific integrated circuit ('ASIC') or a field programmable gate array ('FPGA')). The terms 'processor' and 'computer' are also defined below. These peripheral devices may include a storage subsystem 1424, which includes a memory subsystem 1426 and a file storage subsystem 1428, a user interface input device 1422, a user interface output device 1420, and a network interface subsystem 1416. The input devices and output devices allow a user to interact with the computer system 1410.

[0077] The computer system may be a server computer, a client computer, a workstation, a mainframe, a personal computer (PC), a tablet PC, a set-top box (STB), a personal digital assistant (PDA), a mobile phone, a smartphone, a network appliance, a rack-mounted 'blade', a kiosk, a television, a game station, a network router, switch or bridge, or any data processing machine capable of executing instructions (sequentially or otherwise) specifying actions to be taken by the machine.

[0078] Computer systems typically include an operating system, such as Microsoft's Windows, Sun Microsystems' Solaris, Apple Computer's MacOS, Linux, or Unix. Computer systems typically also may include a basic input / output system (BIOS) and processor firmware. The processor uses the operating system, BIOS, and firmware to control subsystems and interfaces connected to the processor.

[0079] The innovations, embodiments and / or examples of the claimed inventions are not limited to conventional computer applications nor to programmable devices that run them. For example, the claimed innovations, embodiments and / or examples may include optical computers, quantum computers, analog computers, etc. The computer system may be a multi-processor or multi-core system and may use or be implemented in a distributed or remote system. The term 'processor' herein is used in the broadest sense to include a single processor and an array of multi-core processors or multi-processor arrays, including graphics processing units, digital signal processors, digital processors, and combinations of these devices. Further, although only a single computer system or a single machine may be described, the use of such terms in the singular shall also refer to any computer system or collection of machines that individually or jointly execute instructions to perform one or more of the instruction sets discussed herein. Due to the ever-changing nature of computers and networks, Fig.14A The description of the computer system 1410 depicted in FIG. 1 is intended only as an example for purposes of illustrating the preferred embodiment. Many other configurations of the computer system 1410 are possible with more Fig.14A More or fewer components of the computer system depicted in FIG.

[0080] The network interface subsystem 1416 provides an interface to an external network, including an interface to a communication network 1418; and is coupled to corresponding interface devices in other computer systems or machines via the communication network 1418. The communication network 1418 may include many interconnected computer systems, machines, and communication links. These communication links may be wired links, optical links, wireless links, or any other device for conveying information. The communication network 1418 may be any suitable computer network, for example, a wide area network such as the Internet and / or a local area network such as Ethernet. The communication network may be a wired communication network and / or a wireless communication network, and the communication network may use encryption methods and decryption methods, such as those that may be used in a virtual private network. The communication network uses one or more communication interfaces, which may receive data from other systems and transmit data to other systems. Embodiments of the communication interface typically include an Ethernet card, a modem (e.g., telephone, satellite, cable, or ISDN), a (asynchronous) digital subscriber line (DSL) unit, a FireWire interface, a USB interface, etc. One or more communication protocols may be used, such as HTTP, TCP / IP, RTP / RTSP, IPX, and / or UDP.

[0081] User interface input device 1422 can include alphanumeric keyboard, keypad, pointing device such as mouse, trackball, touch pad, stylus or graphic input board, scanner, touch screen incorporated into display, audio input device such as voice recognition system or microphone, eye gaze recognition, brain wave pattern recognition, and other types of input devices. Such equipment can be connected to computer system by wired or wireless mode. Generally speaking, use term "input device' is intended to include all possible types of equipment and mode that information is input into computer system 1410 or communication network 1418. User interface input device usually allows user to select objects, icons, texts, etc. that appear on some types of user interface output devices (e.g., display subsystem).

[0082] The user interface output device 1420 may include a display subsystem, a printer, a fax machine, or a non-visual display such as an audio output device. The display subsystem may include a cathode ray tube (CRT), a flat panel device such as a liquid crystal display (LCD), a projection device, or some other device such as a virtual reality system for creating a visible image. The display subsystem may also provide a non-visual display such as via an audio output or a tactile output (e.g., vibration) device. In general, the use of the term 'output device' is intended to include all possible types of devices and methods for outputting information from the computer system 1410 to a user or another machine or computer system.

[0083] The memory subsystem 1426 typically includes several memories including a main random access memory ('RAM') 1430 (or other volatile storage device) for storing instructions and data during program execution and a read-only memory ('ROM') 1432 in which fixed instructions are stored. The file storage subsystem 1428 provides persistent storage for program and data files and may include a hard drive, a floppy disk drive and associated removable media, a CD-ROM drive, an optical drive, flash memory, or a removable media cartridge. Databases and modules that implement the functionality of certain embodiments may be stored by the file storage subsystem 1428.

[0084] The bus subsystem 1412 provides a device for allowing the various components and subsystems of the computer system 1410 to communicate with each other as expected. Although the bus subsystem 1412 is schematically shown as a single bus, alternative embodiments of the bus subsystem may use multiple buses. For example, a RAM-based main memory may communicate directly with a file storage system using a direct memory access ('DMA') system.

[0085] Fig. 14BA memory 1440 such as a non-transitory computer-readable data and information storage medium associated with the file storage subsystem 1428 and / or with the network interface subsystem 1416 is depicted and may include data structures that specify the circuit design. The memory 1440 may be a hard disk, floppy disk, CD-ROM, optical media, removable media cartridge, or other medium that stores computer-readable data in volatile or non-volatile form. Software read into the computer from such a memory may be converted at selected moments in time from a tangible form to data transmitted through a medium (such as a network, connector, wire, or trace as electrical impulses, or a medium such as space or the atmosphere as electromagnetic radiation, where wavelengths in the electromagnetic spectrum are longer than infrared light).

[0086] Fig. 14C An integrated circuit 1490 created using the described techniques is shown, the integrated circuit 1490 including one or more cells selected, for example, from a cell library.

[0087] Other configuration considerations

[0088] Example benefits and advantages of the disclosed configuration include data-independent RBL current leakage (e.g., during standby operation) of a 10T SRAM cell array. Because the leakage is data-independent, the design of a 10T SRAM cell array may not be limited by the number of bit cells per bit line. Bit line sensing margins may also be increased due to the reduction of RBL leakage in the read port of the cell. Figures 5 to 8 are simulation results showing these advantages (eg, increased sensing time window for 10T SRAM configurations).

[0089] The weak transistor keepers described herein also have benefits and advantages. The read sensing margin may be limited by the switch current ratio at low voltages, which in turn limits the minimum supply voltage VDD MIN. To improve the read sensing margin, a weak PMOS keeper may be used to compensate for bit line leakage in large signal sensing. In some embodiments, the size of the weak PMOS keeper is affected by the desired trade-off between the read sensing margin and read '0' timing, and the read '0' penalty at the SF process corner. In some embodiments, a weak NMOS keeper improves the read sensing margin and read '0' timing of a weak PMOS keeper for large signal sensing. As Fig.10 As shown, a weak NMOS keeper as described herein can increase VDD MIN by 50 mV for NFIN=2 and by 90 mV for NFIN=3. Fig.11 Other improvements are shown in , where the read '0' delay is shown to be improved by approximately 163% for VDD=0.6V, 140% for VDD=0.54V, and 115% for VDD=0.5V.

[0090] Throughout the specification, multiple instances may implement components, operations or structures described as single instances. Although the individual operations of one or more methods are illustrated and described as individual operations, one or more operations in the individual operations may be performed simultaneously, and it is not necessary to perform these operations in the illustrated order. The structures and functions presented as individual components in the example configuration may be implemented as combined structures or components. Similarly, the structures and functions presented as individual components may be implemented as individual components. These and other variations, modifications, additions and improvements fall within the scope of the subject matter herein.

[0091] Certain embodiments are described herein as including logic or a number of components, modules, or mechanisms. Modules may constitute software modules (e.g., code embodied on a machine-readable medium or embodied in a transmission signal) or hardware modules. A hardware module is a tangible unit capable of performing a specific operation and may be configured or arranged in a specific manner. In example embodiments, one or more computer systems (e.g., stand-alone client or server computer systems) or one or more hardware modules (e.g., a processor or group of processors) of a computer system may be configured by software (e.g., an application or application portion) as a hardware module that operates to perform certain operations as described herein.

[0092] In various embodiments, hardware modules may be implemented mechanically or electronically. For example, a hardware module may include dedicated circuitry or logic that is permanently configured to perform certain operations (e.g., as a dedicated processor, such as a field programmable gate array (FPGA) or an application specific integrated circuit (ASIC)). A hardware module may also include programmable logic or circuitry (e.g., such as that contained within a general-purpose processor or other programmable processor) that is temporarily configured by software to perform certain operations. It should be appreciated that the decision to implement a hardware module mechanically, in a dedicated and permanently configured circuitry, or in a temporarily configured circuitry (e.g., configured by software) may be driven by cost and time considerations.

[0093] Therefore, the term "hardware module" should be understood to cover tangible entities, i.e., entities that are physically constructed, permanently configured (e.g., hardwired) or temporarily configured (e.g., programmed) to operate in a particular manner or perform certain operations described herein. As used herein, a "hardware-implemented module" refers to a hardware module. Considering an embodiment in which a hardware module is temporarily configured (e.g., programmed), each of the hardware modules does not need to be configured or instantiated at any one moment in time. For example, in the case where the hardware module includes a general-purpose processor configured using software, the general-purpose processor can be configured as different hardware modules at different times. The software can accordingly configure the processor to, for example, constitute a specific hardware module at one moment in time and constitute different hardware modules at different moments in time.

[0094] Hardware modules can provide information to other hardware modules and receive information from other hardware modules. Thus, the described hardware modules can be considered to be communicatively coupled. In the case where multiple such hardware modules exist simultaneously, communication can be achieved by signal transmission (e.g., by appropriate circuits and buses) connecting the hardware modules. In an embodiment where multiple hardware modules are configured or instantiated at different times, communication between these hardware modules can be achieved, for example, by storing and retrieving information in a memory structure accessible to multiple hardware modules. For example, a hardware module can perform an operation and store the output of the operation in a memory device to which it is communicatively coupled. Another hardware module can then access the memory device later to retrieve and process the stored output. The hardware module can also initiate communication with an input device or an output device, and can operate on a resource (e.g., a collection of information).

[0095] The various operations of the example methods described herein may be performed at least in part by one or more processors that are temporarily configured (e.g., by software) or permanently configured to perform the relevant operations. Whether temporarily or permanently configured, such processors may constitute processor-implemented modules that operate to perform one or more operations or functions. In some example embodiments, the modules referred to herein may include processor-implemented modules.

[0096] Likewise, the methods described herein may be implemented at least in part by a processor. For example, at least some of the operations in the method may be performed by one or more processors or a hardware module implemented by the processor. The performance of some operations in the operation may be distributed among one or more processors, not only residing in a single machine, but also deployed on several machines. In some example embodiments, one or more processors may be located in a single location (e.g., in a home environment, in an office environment, or as a server cluster), while in other embodiments, the processor may be distributed among several locations.

[0097] The one or more processors may also operate to support execution of related operations in a "cloud computing" environment or as "software as a service" (SaaS). For example, at least some of the operations may be performed by a computer group (as an example of a machine including a processor), which may be accessed via a network (e.g., the Internet) and via one or more appropriate interfaces (e.g., an application program interface (API)).

[0098] The execution of certain operations in the operation may be distributed among one or more processors, not only residing in a single machine, but also deployed on several machines. In some example embodiments, one or more processors or processor-implemented modules may be located in a single geographic location (e.g., within a home environment, within an office environment, or within a server farm). In other example embodiments, one or more processors or processor-implemented modules may be distributed over several geographic locations.

[0099] Some parts of this specification are presented in terms of algorithms or symbolic representations of operations on data stored as bits or binary digital signals in a machine memory (e.g., computer memory). These algorithms or symbolic representations are examples of techniques used by those of ordinary skill in the field of data processing to convey the essence of their work to other technicians in the field. As used herein, an "algorithm" is a self-consistent sequence of operations or similar processes that produce a desired result. In this context, algorithms and operations involve physical manipulation of physical quantities. Typically, but not necessarily, these quantities can take the form of electrical, magnetic, or optical signals that can be stored, accessed, transmitted, combined, compared, or otherwise manipulated by a machine. Sometimes, mainly for common reasons, it is convenient to use words such as "data", "content", "bit", "value", "element", "symbol", "character", "item", "number", "digit", etc. to refer to such signals. However, these words are just convenient labels and are to be associated with appropriate physical quantities.

[0100] Unless specifically stated otherwise, discussions herein using terms such as "process," "compute," "calculate," "determine," "present," "display," and the like may refer to the actions or processes of a machine (e.g., a computer) that operates on or transforms data identified as physical (e.g., electronic, magnetic, or optical) quantities within one or more memories (e.g., volatile memory, non-volatile memory, or a combination thereof), registers, or other machine components that receive, store, transmit, or display information.

[0101] As used herein, any reference to "one embodiment" or "an embodiment" means that a particular element, feature, structure, or characteristic described in conjunction with the embodiment is included in at least one embodiment. The phrase "in one embodiment" appearing in various places in the specification does not necessarily refer to the same embodiment.

[0102] Some embodiments may be described using the expressions "coupled" and "connected" along with their derivatives. It should be understood that these terms are not intended to be synonymous with each other. For example, the term "connected" may be used to describe some embodiments to indicate that two or more elements are in direct physical or electrical contact with each other. In another example, some embodiments may be described using the term "coupled" to indicate that two or more elements are in direct physical or electrical contact with each other. However, the term "coupled" may also mean that two or more elements are not in direct contact with each other, but still cooperate or interact with each other. The embodiments are not limited to this context.

[0103] As used herein, the terms "comprises," "comprising," "includes," "including," "has," "having," or any other variation thereof, are intended to cover non-exclusive inclusion. For example, a process, method, article, or apparatus that includes a list of elements is not necessarily limited to only those elements, but may include other elements not expressly listed or inherent to such process, method, article, or apparatus. Further, unless expressly stated otherwise, "or" refers to an inclusive or and not an exclusive or. For example, a condition A or B satisfies any of the following: A is true (or exists) and B is false (or does not exist), A is false (or does not exist) and B is true (or exists), and both A and B are true (or exist).

[0104] In addition, "a" or "an" is used to describe the elements and components of the embodiments herein. This is done only for convenience and to give a general sense of the invention. The description should be read to include one or at least one, and unless otherwise clearly indicated, the singular also includes the plural.

[0105] After reading this disclosure, those skilled in the art should appreciate additional alternative structural designs and functional designs for systems and processes for performing SRAM cell array operations (e.g., read operations) using data-independent current leakage and compensating current leakage (e.g., using weak NMOS keepers) through the principles disclosed herein. Therefore, although specific embodiments and applications have been illustrated and described, it should be understood that the disclosed embodiments are not limited to the precise constructions and components disclosed herein. Various modifications, changes and variations that are obvious to those skilled in the art may be made to the arrangement, operation and details of the methods and apparatus disclosed herein without departing from the spirit and scope defined in the appended claims.

Claims

1. An integrated circuit for storing data, comprising: A memory cell array including a bit cell having a static random access memory architecture, wherein the bit cell includes i) a write port and ii) a read port having a plurality of transistors; as well as a plurality of word lines and bit lines arranged in rows and columns in the memory cell array such that the plurality of word lines and bit lines are coupled to the memory cell array, wherein a first transistor of the plurality of transistors is coupled to at least i) a first word line of the plurality of word lines, ii) a first bit line of the plurality of bit lines, and iii) a second transistor of the plurality of transistors, wherein a control electrode of the first transistor is coupled to the first word line, a first electrode of the first transistor is coupled to the first bit line, and a second electrode of the first transistor is coupled to a first electrode of the second transistor, wherein the second transistor is further coupled to at least a third transistor among the plurality of transistors and a fourth transistor among the plurality of transistors, wherein a control electrode of the second transistor is coupled to a first electrode of the third transistor and a first electrode of the fourth transistor, and a second electrode of the second transistor is grounded, wherein the third transistor is further coupled to at least the write port and a second word line of the plurality of word lines, wherein a second electrode of the third transistor is coupled to the write port, and a control electrode of the third transistor is coupled to the second word line, and The fourth transistor is further coupled to at least the second word line, wherein a control electrode of the fourth transistor is coupled to the second word line, and a second electrode of the fourth transistor is grounded.

2. The integrated circuit of claim 1, wherein a leakage current during a read '0' operation through at least one selected cell of the memory cell array is substantially similar to a leakage current during a read '1' operation through the at least one selected cell.

3. The integrated circuit of claim 1, wherein the logic value carried on the second word line is the inverse of the logic value carried on the first word line.

4. The integrated circuit of claim 1, wherein during standby operation, a logic value of '0' drives the second transistor.

5. The integrated circuit according to claim 1, wherein the first bit line is also coupled to a weak NMOS keeper, the weak NMOS keeper comprising an inverter and an NMOS transistor, The output of the inverter can be used for memory read operations, and The NMOS transistor is also coupled to a supply voltage source.

6. The integrated circuit according to claim 5, wherein the NMOS transistor and three additional NMOS transistors are connected in series, and For a read '1' operation, the minimum supply voltage (VDD MIN) is approximately 0.45V.

7. The integrated circuit according to claim 5, wherein the NMOS transistor and five additional NMOS transistors are connected in series, and For a read '1' operation, VDD MIN is approximately 0.41V.

8. The integrated circuit of claim 1, wherein a sensing time window of the first bit line is at least 0.5 nanoseconds (ns).

9. The integrated circuit of claim 1, wherein a sensing voltage of the first bit line is in a range of 25% to 80% of a supply voltage when operating at 150°C.

10. A non-transitory computer-readable storage medium storing a digital representation of an integrated circuit for storing data, the integrated circuit comprising: A memory cell array including a bit cell having a static random access memory architecture, wherein the bit cell includes i) a write port and ii) a read port having a plurality of transistors; as well as a plurality of word lines and bit lines arranged in rows and columns in the memory cell array such that the plurality of word lines and bit lines are coupled to the memory cell array, wherein a first transistor of the plurality of transistors is coupled to at least i) a first word line of the plurality of word lines, ii) a first bit line of the plurality of bit lines, and iii) a second transistor of the plurality of transistors, wherein a control electrode of the first transistor is coupled to the first word line, a first electrode of the first transistor is coupled to the first bit line, and a second electrode of the first transistor is coupled to a first electrode of the second transistor, wherein the second transistor is further coupled to at least a third transistor among the plurality of transistors and a fourth transistor among the plurality of transistors, wherein a control electrode of the second transistor is coupled to a first electrode of the third transistor and a first electrode of the fourth transistor, and a second electrode of the second transistor is grounded, wherein the third transistor is further coupled to at least the write port and a second word line of the plurality of word lines, wherein a second electrode of the third transistor is coupled to the write port, and a control electrode of the third transistor is coupled to the second word line, and The fourth transistor is further coupled to at least the second word line, wherein a control electrode of the fourth transistor is coupled to the second word line, and a second electrode of the fourth transistor is grounded.

11. The non-transitory computer readable storage medium of claim 10, wherein a leakage current during a read '0' operation through at least one selected cell of the memory cell array is substantially similar to a leakage current during a read '1' operation through the at least one selected cell. 12 . The non-transitory computer readable storage medium of claim 10 , wherein the logic value carried on the second word line is the inverse of the logic value carried on the first word line. 13 . The non-transitory computer readable storage medium of claim 10 , wherein during a standby operation, a logic value of '0' drives the second transistor.

14. The non-transitory computer readable storage medium according to claim 10, wherein the first bit line is also coupled to a weak NMOS keeper, the weak NMOS keeper comprising an inverter and an NMOS transistor, The output of the inverter can be used for memory read operations, and The NMOS transistor is also coupled to a supply voltage source.

15. The non-transitory computer readable storage medium of claim 14, wherein the NMOS transistor and three additional NMOS transistors are connected in series, and For a read '1' operation, VDD MIN is 0.45V. 16 . The non-transitory computer readable storage medium of claim 10 , wherein a sensing time window of the first bit line is at least 0.5 ns. 17 . The non-transitory computer readable storage medium of claim 10 , wherein a sensing voltage of the first bit line is in a range of 25% to 80% of a supply voltage when operating at 150° C.

18. An integrated circuit for storing data, comprising: a memory cell array including bit cells having a static random access memory architecture, wherein the bit cells include a write port and a read port; as well as a plurality of word lines and bit lines arranged in rows and columns in the memory cell array such that the plurality of word lines and bit lines are coupled to the memory cell array, wherein a bit line of the plurality of bit lines is coupled to at least a sensing inverter and a weak NMOS keeper, the weak NMOS keeper comprising an inverter and an NMOS transistor, and The output of the sense inverter may be used for a memory read operation.

19. The integrated circuit of claim 18, wherein the memory cell array is an 8T SRAM cell array.

20. The integrated circuit of claim 18, wherein the memory cell array is a 10T SRAM cell array.

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