A floating point number processing method, device and storage medium

Abstract

The embodiment of the present application provides a floating-point number processing method, device and storage medium. In the embodiment of the present application, in response to a floating-point number processing instruction, at least two floating-point numbers to be processed can be obtained; the at least two floating-point numbers are used as signed fixed-point numbers, and a given point number processing component is provided; the at least two floating-point numbers are processed by the fixed-point number processing component to obtain a first processing result; according to the respective sign attributes of the at least two floating-point numbers and the first processing result, a second processing result is output as a response to the floating-point number processing instruction. Accordingly, in the embodiment of the present application, the floating-point number processing task can be converted into a fixed-point number processing task without the perception of the upper-level application, that is, the floating-point number processing task can be performed by the fixed-point number processing component, which can effectively improve the processor's processing performance for floating-point numbers, thereby improving the overall performance of the processor.

Description

Technical Field

[0001] The present application relates to the field of data processing technology, and in particular to a floating point number processing method, device and storage medium. Background Art

[0002] Comparison instructions (comparison operations) are relatively basic functions in the processor and are used in almost every application. Especially in applications involving a large number of sorting and / or query tasks, the performance of comparison instructions is a key indicator affecting the overall performance of the processor.

[0003] At present, many processors usually mainly provide comparison instruction functions for fixed-point numbers, while the performance of comparison instructions for floating-point numbers is relatively weak or even non-existent, which seriously affects the performance of the comparison instructions of the processor. Summary of the invention

[0004] Multiple aspects of the present application provide a floating point number processing method, device and storage medium to optimize the processing performance of floating point numbers.

[0005] The present application provides a floating point number processing method, including:

[0006] In response to a floating point number processing instruction, obtaining at least two floating point numbers to be processed;

[0007] Taking the at least two floating point numbers as signed fixed point numbers, and providing a given point number processing component;

[0008] Processing the at least two floating-point numbers using the fixed-point number processing component to obtain a first processing result;

[0009] According to the sign attributes of the at least two floating-point numbers and the first processing result, a second processing result is output as a response to the floating-point number processing instruction.

[0010] The embodiment of the present application also provides a processor, including a compiling component and a fixed-point number processing component, wherein the compiling component is communicatively connected with the fixed-point number processing component;

[0011] The compiling component is used to obtain at least two floating-point numbers to be processed in response to a floating-point number processing instruction; provide the at least two floating-point numbers as signed fixed-point numbers to a given point number processing component; obtain a first processing result returned by the fixed-point number processing component; and output a second processing result as a response to the floating-point number processing instruction according to the sign attributes of the at least two floating-point numbers and the first processing result.

[0012] The fixed-point number processing component is used to process the at least two floating-point numbers to obtain the first processing result, and return the first processing result to the compilation component.

[0013] The embodiment of the present application also provides a processor, including a compiling component, a floating-point number processing component and a fixed-point number processing component, wherein the compiling component is communicatively connected with the floating-point number processing component and the fixed-point number processing component;

[0014] The compiling component is used for obtaining at least two floating-point numbers to be processed in response to a floating-point processing instruction if the performance of the floating-point processing component is lower than a preset standard; providing the at least two floating-point numbers as signed fixed-point numbers to a given point processing component; obtaining a first processing result returned by the fixed-point processing component; and outputting a second processing result as a response to the floating-point processing instruction according to the sign attributes of the at least two floating-point numbers and the first processing result.

[0015] The fixed-point number processing component is used to process the at least two floating-point numbers to obtain the first processing result, and return the first processing result to the compilation component.

[0016] An embodiment of the present application also provides a computer-readable storage medium storing computer instructions. When the computer instructions are executed by one or more processors, the one or more processors are caused to execute the aforementioned floating-point number processing method.

[0017] In an embodiment of the present application, in response to a floating-point number processing instruction, at least two floating-point numbers to be processed can be obtained; the at least two floating-point numbers are used as signed fixed-point numbers, and a given point number processing component is provided; the at least two floating-point numbers are processed by the fixed-point number processing component to obtain a first processing result; and a second processing result is output as a response to the floating-point number processing instruction according to the respective sign attributes of the at least two floating-point numbers and the first processing result. Accordingly, in an embodiment of the present application, the floating-point number processing task can be converted into a fixed-point number processing task without the perception of the upper-layer application, that is, the floating-point number processing task can be performed by the fixed-point number processing component, which can effectively improve the processor's processing performance for floating-point numbers, thereby improving the overall performance of the processor. BRIEF DESCRIPTION OF THE DRAWINGS

[0018] The drawings described herein are used to provide a further understanding of the present application and constitute a part of the present application. The illustrative embodiments of the present application and their descriptions are used to explain the present application and do not constitute an improper limitation on the present application. In the drawings:

[0019] Figure 1a A schematic diagram of the structure of a processor provided for an exemplary embodiment of the present application;

[0020] Figure 1b A schematic diagram of the structure of another processor provided for an exemplary embodiment of the present application;

[0021] Figure 2 A logical schematic diagram of a floating point number processing solution provided for an exemplary embodiment of the present application;

[0022] Figure 3 A data format of a floating point number provided for an exemplary embodiment of the present application;

[0023] Figure 4 A schematic diagram of the storage form of a floating-point number with a non-negative property provided by an exemplary embodiment of the present application when used as a signed fixed-point number;

[0024] Figure 5 A schematic diagram of the storage form of a floating-point number with a negative attribute as a signed fixed-point number provided by an exemplary embodiment of the present application;

[0025] Figure 6 A flowchart of a floating-point number processing method provided in one embodiment of the present application. DETAILED DESCRIPTION

[0026] In order to make the purpose, technical solution and advantages of the present application clearer, the technical solution of the present application will be clearly and completely described below in combination with the specific embodiments of the present application and the corresponding drawings. Obviously, the described embodiments are only part of the embodiments of the present application, not all of the embodiments. Based on the embodiments in the present application, all other embodiments obtained by ordinary technicians in this field without making creative work are within the scope of protection of the present application.

[0027] In response to technical problems such as the inability of existing processors to support floating-point processing functions or insufficient floating-point processing performance, in some embodiments of the present application: in response to a floating-point processing instruction, at least two floating-point numbers to be processed can be obtained; the at least two floating-point numbers are used as signed fixed-point numbers, and a given point processing component is provided; the at least two floating-point numbers are processed using the fixed-point processing component to obtain a first processing result; and a second processing result is output as a response to the floating-point processing instruction based on the respective sign attributes of the at least two floating-point numbers and the first processing result. Accordingly, in the embodiments of the present application, the floating-point processing task can be converted into a fixed-point processing task without the perception of the upper-level application, that is, the fixed-point processing component can be used to perform the floating-point processing task, which can effectively improve the processor's processing performance for floating-point numbers, thereby improving the overall performance of the processor.

[0028] The technical solutions provided by various embodiments of the present application are described in detail below in conjunction with the accompanying drawings.

[0029] Figure 1a A schematic diagram of the structure of a processor provided by an exemplary embodiment of the present application. Figure 1a As shown, the processor may include: a compiling component 10 and a fixed-point number processing component 20, and the compiling component 10 and the fixed-point number processing component 20 are communicatively connected.

[0030] The processor may be an embedded low-power, low-cost CPU, such as Arm cortex M core, etc. Of course, it may also be a single instruction multiple data stream SIMD processor, such as an embedded GPU, etc. These are only exemplary, and in this embodiment, the type of processor is not limited.

[0031] During the research process, the applicant found that most processors usually mainly provide fixed-point number processing functions, while the floating-point number processing function is usually relatively weak or even non-existent, resulting in insufficient floating-point number processing performance, affecting the overall performance of the processor.

[0032] In this regard, the applicant proposes that the compilation component 10 in the processor can be improved: in the stage of compiling the upper-level application, the floating-point number processing task is converted into a fixed-point number processing task. Among them, in this embodiment, the compilation component 10 may refer to a component in the processor for running a compiler. A compiler is a program that converts a programming language program with a higher degree of abstraction (also called a source program) into a programming language program with a lower degree of abstraction (also called a target program). In actual applications, the upper-level application will first be compiled by the compilation component 10 and then run under the processor.

[0033] For compiling component 10, in the compiling process, floating-point number processing instructions can be monitored, and at least two floating-point numbers to be processed under the floating-point number processing instructions can be obtained. Wherein, the floating-point number processing instruction can be a floating-point number comparison instruction, etc. Of course, it can also be other processing instructions derived based on the comparison instruction, and the present embodiment does not limit the floating-point number processing instruction. For different floating-point number processing instructions, the quantity of the floating-point numbers to be processed involved may not be exactly the same. Because in most cases, a single floating-point number processing instruction is processed for two floating-point numbers, for example, the size of two floating-point numbers is compared, two floating-point numbers are sorted, etc., therefore, in the following text, the technical scheme will be described as an example with the processing procedure of two floating-point numbers.

[0034] Figure 3 A floating point data format is provided for an exemplary embodiment of the present application. Figure 3 , a floating point number can contain a sign bit, an exponent field, and a mantissa field. Among them, the sign bit is used to represent the sign attribute of the floating point number. For a floating point number with a non-negative attribute, the value on the sign bit is 1, and for a floating point number with a negative attribute, the value on the sign bit is 0. In addition, Figure 3 The figure shows a single-precision floating point number float32, which can be described by a 32-bit binary number, in which the first 23 bits are used as the mantissa field, the middle 8 bits are used as the exponent field, and the highest bit is used as the sign bit. Of course, in this embodiment, the type of floating point number is not limited, except Figure 3 The floating point number in this embodiment may also be a half-precision floating point number float16 or a double-precision floating point number double, etc. For different types of floating point numbers, the number of bits of the binary number used to describe the floating point number may not be exactly the same.

[0035] Based on this, the compiling component 10 may treat the at least two floating-point numbers under the floating-point processing instruction as signed fixed-point numbers, and provide the given point processing component 20 .

[0036] Here, treating a floating point number as a signed fixed point number may refer to treating a binary number used to describe a floating point number as a fixed point number. It is worth noting that no data conversion is required here, because in the processor, both fixed point numbers and floating point numbers can be represented by binary numbers, so the binary number used to describe a floating point number can be directly treated as a fixed point number. For example, for the aforementioned float32, the 32-bit binary number used to describe float32 can be treated as a signed fixed point number.

[0037] The fixed-point number processing component 20 can process at least two floating-point numbers under the floating-point number processing instruction. It should be understood that the fixed-point number processing component 20 processes the floating-point number provided by the compilation component 10 as a signed fixed-point number, and the fixed-point number processing component 20 does not perceive that it is processing a floating-point number. The fixed-point number processing component 20 can output a first processing result to the compilation component 10 after processing at least two floating-point numbers under the floating-point number processing instruction.

[0038] After receiving the first processing result returned by the fixed-point number processing component 20, the compiling component 10 may output a second processing result as a response to the floating-point number processing instruction according to the sign attributes of the at least two floating-point numbers and the first processing result.

[0039] In this embodiment, in some scenarios, the sign attributes of at least two floating-point numbers under the fixed-point number processing instruction are known, for example, the fixed-point number processing instruction carries the sign attribute identifier of each floating-point number. In this scenario, the second processing result can be directly output according to the sign attributes of the at least two floating-point numbers and the first processing result. The sign attribute is used to describe the positive or negative of the floating-point number.

[0040] In this scenario, if at least one of the at least two floating-point numbers has a non-negative attribute, the first processing result is output as the second processing result; if both of the at least two floating-point numbers have a negative attribute, the result opposite to the first processing result is output as the second processing result. Wherein, in the case of comparing floating-point numbers, the opposite result of the first processing result is specifically: GT (greater than)=>LT (less than), GE (greater than or equal to)=>LE (less than or equal to), LT (less than)=>GT (greater than), LE (less than or equal to)=>GE (greater than or equal to), EQ (equal)=>EQ (equal).

[0041] Taking two floating point numbers as an example, three cases are described below, and it is verified that the second processing result can be output according to the sign attributes of at least two floating point numbers and the first processing result.

[0042] The first case: Both floating-point numbers have the non-negative property.

[0043] Floating-point numbers with the non-negative attribute can include zero, reduced numbers, unreduced numbers, positive infinity +INF, and non-numeric index NAN, etc. Figure 4 A schematic diagram of the storage format of a floating-point number with a non-negative property as a signed fixed-point number provided by an exemplary embodiment of the present application, Figure 4 32-bit binary numbers for describing zero, reduced number, non-reduced number, positive infinity +INF and non-numeric value NAN are shown in FIG.

[0044] The applicant discovered during the research process that for floating-point numbers with non-negative attributes (positive attributes or 0), they are usually processed in the order of sign bit, exponent field, and mantissa field, which is consistent with the order of fields in the binary number used to describe the floating-point numbers with non-negative attributes. For example, when two floating-point numbers need to be compared, they can be compared in the order of sign bit, exponent field, and mantissa field. For the special floating-point number NaN, usually when NaN and other floating-point numbers are processed together, any output result is correct. Accordingly, this embodiment proposes that the binary number corresponding to the floating-point number with non-negative attributes can be directly regarded as a fixed-point number for processing.

[0045] It is worth noting that when a floating point number is processed as a signed fixed point number, the compiling component 10 can store the floating point number as a complement code, and provide the complement code of the floating point number to the given point number processing component 20. The highest bit of the binary number of the floating point number used to describe the non-negative attribute is non-1, so the binary number will be used as a non-negative fixed point number. The complement code of the non-negative fixed point number is the same as the original code, and accordingly, for the fixed point number processing component 20, for a floating point number with a non-negative attribute, it will be processed according to the complement code of the binary number of the floating point number used to describe the non-negative attribute.

[0046] Thus, for a floating point number with a non-negative attribute, the first processing result output by the fixed point number processing component 20 will be consistent with the result obtained according to the conventional processing logic of the floating point number. Figure 4 ,Will Figure 4 After comparing the floating point numbers (32-bit binary numbers) as signed fixed-point numbers, the first processing result will be zero < largest unreduced number < smallest reduced number < largest reduced number < positive infinity, which conforms to the traditional floating point comparison rule of zero < positive unreduced floating point number < positive reduced floating point number < +INF. This verifies the correctness of the aforementioned "if at least one of the at least two floating point numbers has a non-negative attribute, the first processing result can be output as the second processing result".

[0047] In this case, there is also a special distribution feature, that is, two floating-point numbers are zero at the same time. Under the traditional processing rules of floating-point numbers, a floating-point number 0 with a negative attribute and a floating-point number 0 with a positive attribute are equal, but under the fixed-point number processing rules, the situation of +0>-0 may occur. From the comparison result alone, it may be inconsistent with the result obtained by the traditional processing logic of floating-point numbers, but in the processing scenarios such as comparison, sorting, addition and subtraction, it does not affect the final result. Therefore, in this embodiment, the situation where the floating-point numbers are zero at the same time can be ignored, and if special processing is required for this situation, this special situation can be discovered in time by adding screening conditions, and the required processing rules can be configured, which does not affect the implementation of the overall solution of this embodiment.

[0048] The second case: one floating point number has the negative attribute and the other floating point number has the non-negative attribute.

[0049] In this case, it is usually possible to directly process floating point numbers based on the sign attribute. For example, when two floating point numbers need to be compared, the floating point number with the non-negative attribute is usually larger than the floating point number with the negative attribute.

[0050] As mentioned above, when a floating-point number is used as a signed fixed-point number, the binary number used to describe the floating-point number will be stored in the form of a two's complement. Unlike floating-point numbers with non-negative properties, when storing a floating-point number with a negative property as a two's complement, it is necessary to invert all bits except the highest bit (i.e., the sign bit) (0 becomes 1, 1 becomes 0) and then add 1 to obtain the two's complement corresponding to the floating-point number with a negative property. Figure 5 A schematic diagram of the storage format of a floating-point number with a negative attribute as a signed fixed-point number provided by an exemplary embodiment of the present application. Figure 5 The other 31 bits except the sign bit are the result of inverting the original code.

[0051] On this basis, the fixed-point number processing component 20 can process the binary number used to describe the floating-point number as a signed fixed-point number. For example, when two floating-point numbers need to be compared, the first processing result output by the fixed-point number processing component 20 must be that the floating-point number with a non-negative attribute is greater than the floating-point number with a negative attribute (according to the fixed-point number processing rules, the fixed-point number processing component 20 will compare based on the sign of the fixed-point number, that is, the negative fixed-point number is usually smaller than the non-negative fixed-point number), which is consistent with the result obtained according to the traditional processing logic of the floating-point number. That is to say, the correctness of the aforementioned "if at least one of the at least two floating-point numbers has a non-negative attribute, the first processing result can be output as the second processing result" is verified.

[0052] The third case: Both floating-point numbers have negative attributes at the same time.

[0053] refer to Figure 5 , Figure 5 Several exemplary storage forms of floating-point numbers with negative attributes as signed fixed-point numbers are shown in FIG. During the research process, the applicant found that after storing floating-point numbers with negative attributes in the form of two's complement, the larger the last 31 bits in the two's complement, the smaller the floating-point number represented by the two's complement. In this way, the first processing result output by the fixed-point number processing component 20 will be opposite to the result obtained according to the traditional processing logic of the floating-point number. That is, the correctness of the aforementioned "if at least two floating-point numbers have negative attributes, the result opposite to the first processing result will be output as the second processing result" is verified.

[0054] In summary, in this embodiment, the compiling component 10 can store the at least two floating-point numbers under the floating-point number processing instruction as complements, and provide the complements corresponding to the at least two floating-point numbers to the fixed-point number processing component 20. The fixed-point number processing component 20 can process the complements corresponding to the at least two floating-point numbers to obtain a first processing result. Moreover, it can be determined whether to transform the first processing result to obtain a second processing result according to the distribution of the sign attributes of the at least two floating-point numbers.

[0055] In other scenarios, the sign attributes of at least two floating-point numbers in the fixed-point number processing instruction are unknown. In such scenarios, it is not possible to directly output the second processing result based on the sign attributes of the at least two floating-point numbers and the first processing result.

[0056] In this scenario, an attribute description parameter can be determined based on the sign bits of at least two floating-point numbers, and the attribute description parameter is used to describe the distribution characteristics of the positive and negative attributes of the at least two floating-point numbers; and the second processing result is output based on the attribute description parameter and the first processing result.

[0057] The distribution characteristics of the positive and negative attributes of at least two floating point numbers may include both negative attributes, both non-negative attributes, a mixture of negative and non-negative attributes, etc. The attribute description parameters corresponding to different distribution characteristics may not be completely the same.

[0058] Optionally, the compilation component 10 performs an AND operation on the sign bits of at least two floating-point numbers to obtain an attribute description parameter. Among them, the compilation component 10 can shift the binary number used to describe the floating-point number to obtain the highest bit of the binary number, that is, the sign bit of the floating-point number. The attribute description parameter can be obtained by performing an AND operation on the sign bits of at least two floating-point numbers. In practical applications, if the signs of at least two floating-point numbers are both 1, that is, at least two floating-point numbers have negative attributes, the attribute description parameter will be 1, and in other cases, the attribute description parameter will be 0. Therefore, the attribute description parameter can correspond to the concept of classifying the distribution of the symbol attribute in the aforementioned scenario where the symbol attributes of at least two floating-point numbers are known.

[0059] On this basis, the compilation component 10 can perform an XOR operation on the attribute description parameter and the first processing result to obtain an evaluation index for the first processing result; if the evaluation index is true, the first processing result is output as the second processing result; if the evaluation index is false, the result opposite to the first processing result is output as the second processing result.

[0060] It is worth noting that although the concept of attribute description parameters is proposed in this embodiment, in actual applications, it can be determined by means of logical expressions whether to directly use the first processing result output by the fixed-point number processing component 20 as the second processing result. For the compilation component 10, there is no need to provide the attribute description parameters separately, but they are hidden in the logical expression.

[0061] For example, when the sign attributes of at least two floating-point numbers under the floating-point number processing instruction are unknown, the compilation component 10 may determine the second processing result according to the following exemplary logic:

[0062] int A = *(int*)&a; --- Treat the floating point number a as a signed fixed point number

[0063] int B = *(int*)&b; --- treat the floating point number b as a signed fixed point number

[0064] bool f=(A>B)^((A&B&0x80000000)>>31

[0065] Wherein, bool f represents a Boolean variable, and a Boolean variable can be used in a logical expression, and the result of the logical expression operation is true or false. In the above example, the logical expression is (A>B)^((A&B&0x80000000)>>31, wherein ((A&B&0x80000000)>>31 corresponds to the attribute description parameter in this embodiment, and (A>B) corresponds to the first processing result in this embodiment. It should be understood that the first processing result is the actual output of the fixed-point number processing component 20, and is not limited to (A>B) in the above example.

[0066] Accordingly, in this embodiment, even when the sign attribute of the floating-point number is unknown, the second processing result can be accurately determined.

[0067] In this embodiment, in response to a floating-point number processing instruction, at least two floating-point numbers to be processed can be obtained; the at least two floating-point numbers are used as signed fixed-point numbers and provided to a given point number processing component 20; the at least two floating-point numbers are processed using the fixed-point number processing component 20 to obtain a first processing result; and according to the respective sign attributes of the at least two floating-point numbers and the first processing result, a second processing result is output as a response to the floating-point number processing instruction. Accordingly, in an embodiment of the present application, the floating-point number processing task can be converted into a fixed-point number processing task without the perception of the upper-layer application, that is, the floating-point number processing task can be performed using the fixed-point number processing component 20, which can effectively improve the processor's processing performance for floating-point numbers, thereby improving the overall performance of the processor.

[0068] Figure 1b A schematic diagram of the structure of another processor provided by an exemplary embodiment of the present application. Figure 1b , the processor and Figure 1a The differences between the processors shown are, Figure 1b The processor also includes a floating point processing component 30. Figure 2 A logical diagram of a floating point number processing solution provided for an exemplary embodiment of the present application. Figure 2 In the above or below embodiments, the compilation component 10 may perform hardware detection on the processor.

[0069] For the compiling component 10, if it is determined that the processor Figure 1a As shown, there is no floating point number processing component, and the compilation component 10 can execute the processing logic in the aforementioned embodiment.

[0070] If the processor is determined to be Figure 1b If there is a floating point number processing component 30, the performance of the floating point number processing component 30 can be further tested:

[0071] In one case, if it is determined that the performance of the floating point processing component 30 in the processor is lower than a preset standard, the compiling component 10 may execute the processing logic in the aforementioned embodiment.

[0072] In another case, if it is determined that the performance of the floating-point processing component 30 in the processor is higher than or equal to the aforementioned preset standard, the compilation component 10 can use the fixed-point processing component 20 to process the floating-point numbers that have not been processed when the load ratio between the floating-point processing component 30 and the fixed-point processing component 20 is higher than the preset load balance index, until the load ratio satisfies the load balance index or all the floating-point numbers that have not been processed are processed.

[0073] Wherein, when the performance of the floating-point processing component 30 in the processor is higher than or equal to the aforementioned preset standard, the compiling component 10 can count the number of floating-point processing instructions and fixed-point processing instructions initiated by the upper-layer application in a unit time, and use the ratio of the number of the two processing instructions as the load ratio between the floating-point processing component 30 and the fixed-point processing component 20. Obviously, the more the number of floating-point processing instructions is and the fewer the number of fixed-point processing instructions is, the higher the load ratio will be.

[0074] In this embodiment, the preset load balancing index may be 1:1. Of course, this embodiment is not limited thereto, and the load balancing index may also be other ratios, such as a:1.

[0075] In this embodiment, the compiling component 10 can pre-build a task set, which can be used to accommodate at least one floating-point number processing task, and a single floating-point number processing task can contain at least two floating-point numbers that have not been processed. In practical applications, the floating-point number processing instruction in the above embodiment will generate a corresponding floating-point number processing task. And the floating-point number processing tasks may be concurrent or high-incidence.

[0076] Based on this, in this embodiment, the compilation component 10 can configure the floating-point numbers that have not yet been processed into a task set; select a floating-point processing task from the task set as a task to be processed; use the fixed-point number processing component 20 to process the task to be processed; based on the remaining floating-point number processing tasks in the task set, update the load ratio; if the updated load ratio does not meet the load balance index, continue to use the fixed-point number processing component 20 to process the next floating-point number processing task in the task set, and update the load ratio again.

[0077] refer to Figure 2, the compiling component 10 can find the floating-point processing tasks whose sign attributes of the floating-point numbers are known from the floating-point processing tasks initiated by the upper-layer application, and add them to the task set. Afterwards, a floating-point processing task can be taken out from the task set (in actual application, it can be taken out randomly), and the floating-point number under the floating-point processing task is used as a fixed-point number with a sign, and provided to the given point processing component 20 for processing. The fixed-point processing component 20 can output the first processing result to the compiling component 10 according to the fixed-point processing rule. The compiling component 10 can output the second processing result according to the sign attribute of the floating-point number under the floating-point processing task and the first processing result. The specific process can refer to the above-mentioned embodiment, which will not be repeated here. At this point, a floating-point processing task will be reduced in the task set, and the compiling component 10 can update the load ratio accordingly. For example, the floating-point processing task can be reduced by 1, and the load ratio can be recalculated. Of course, the number of fixed-point processing tasks may change synchronously. When updating the load ratio, the compiling component 10 needs to consider the change of the fixed-point processing task.

[0078] Then, the compiling component 10 can determine again whether the load ratio is higher than the load balancing index. If so, it continues to take out a floating point processing task from the task set, and again uses the fixed point processing component 20 to process the floating point processing task, and updates the load ratio.

[0079] This cycle is repeated until the load ratio reaches the load balance index, or the task set is empty, then the cycle is stopped, that is, the fixed-point processing component 20 is stopped from being used to process the floating-point processing tasks.

[0080] In practical applications, floating point number processing tasks including floating point numbers with unknown sign attributes can be handled by the floating point number processing component 30. Usually, the number of such floating point number processing tasks is small, so it will not cause excessive impact on the load of the floating point number processing component 30.

[0081] In addition, it is worth noting that, in this embodiment, the compiling component 10 may also use the load ratio and load balance index between the fixed-point number processing component 20 and the floating-point number processing component 30. In this case, the more the number of floating-point number processing instructions is and the fewer the number of fixed-point number processing instructions is, the lower the load ratio will be. Accordingly, the judgment condition for determining whether to use the fixed-point number processing component 20 to process the floating-point number will also become that the load ratio is lower than the load balance index. Other details will not be described in detail here.

[0082] In summary, in this embodiment, different processing schemes can be adopted based on the hardware perception of the processor for different perception results. For the case where the floating-point number processing performance in the processor is relatively weak or non-existent, the fixed-point number processing component 20 can be directly used to process the floating-point numbers. With the help of the high performance of the fixed-point number processing component 20, the processing performance of the processor for floating-point number processing can be effectively improved; and for the case where the floating-point number processing component 30 and the fixed-point number processing component 20 need to be load balanced, the load of the floating-point number processing component 30 can be alleviated by using the fixed-point number processing component 20 to process some floating-point numbers, thereby optimizing the load balancing effect between the floating-point number processing component 30 and the fixed-point number processing component 20 and improving the overall performance of the processor.

[0083] Of course, in some possible design solutions, if it is known whether the processor includes a floating-point processing component, it is only necessary to configure the compilation component 10 with an adaptive processing logic, without configuring the compilation component 10 with a hardware detection logic.

[0084] Figure 6 The flowchart of a floating point number processing method provided by an embodiment of the present application is shown below. The floating point number processing method provided by this embodiment can be executed by a floating point number processing device, which can be implemented as software or a combination of software and hardware, and the floating point number processing device can be integrated in the compilation component of the processor. Figure 6 As shown, the method includes:

[0085] Step 600, in response to a floating point number processing instruction, obtaining at least two floating point numbers to be processed;

[0086] Step 601: taking at least two floating point numbers as signed fixed point numbers and providing a given point number processing component;

[0087] Step 602: Process at least two floating-point numbers using a fixed-point number processing component to obtain a first processing result;

[0088] Step 603: Output a second processing result as a response to the floating-point number processing instruction according to the sign attributes of the at least two floating-point numbers and the first processing result.

[0089] In an optional embodiment, the step of outputting a second processing result according to the sign attributes of the at least two floating-point numbers and the first processing result comprises:

[0090] If at least one of the at least two floating-point numbers has a non-negative attribute, the first processing result is output as the second processing result;

[0091] If at least two floating-point numbers both have a negative attribute, a result opposite to the first processing result is output as the second processing result.

[0092] In an optional embodiment, the method further comprises:

[0093] If the sign attributes of the at least two floating-point numbers are unknown, then based on the sign bits of the at least two floating-point numbers, an attribute description parameter is determined, the attribute description parameter being used to describe a distribution feature of the sign attributes of the at least two floating-point numbers;

[0094] Output a second processing result according to the attribute description parameter and the first processing result.

[0095] In an optional embodiment, the step of determining an attribute description parameter based on the sign bits of at least two floating point numbers includes:

[0096] An AND operation is performed on the sign bits of at least two floating-point numbers to obtain an attribute description parameter.

[0097] In an optional embodiment, the step of outputting the second processing result according to the attribute description parameter and the first processing result includes:

[0098] Performing an XOR operation on the attribute description parameter and the first processing result to obtain an evaluation index for the first processing result;

[0099] If the evaluation index is true, the first processing result is output as the second processing result;

[0100] If the evaluation index is false, a result opposite to the first processing result is output as the second processing result.

[0101] In an optional embodiment, the step of treating at least two floating point numbers as signed fixed point numbers and providing a given point number processing component comprises:

[0102] The at least two floating point numbers are stored as complement codes respectively, and the complement codes corresponding to the at least two floating point numbers are provided to a given point number processing component.

[0103] In an optional embodiment, the step of processing at least two floating-point numbers using a fixed-point number processing component to obtain a first processing result includes:

[0104] The fixed-point number processing component is used to process the complements corresponding to at least two floating-point numbers to obtain a first processing result.

[0105] In an optional embodiment, before responding to the floating point number processing instruction, the method further includes:

[0106] Perform hardware detection on the processor;

[0107] If it is determined that there is no floating point processing component in the processor or the performance of the floating point processing component is lower than a preset standard, an operation in response to the floating point processing instruction is executed.

[0108] In an optional embodiment, the method further comprises:

[0109] If it is determined that the performance of the floating-point processing component in the processor is higher than or equal to a preset standard, then when the load ratio between the floating-point processing component and the fixed-point processing component is higher than the load balance index, the fixed-point processing component is used to process the floating-point numbers that have not been processed until the load ratio meets the load balance index or all the floating-point numbers that have not been processed are processed.

[0110] In an optional embodiment, the step of processing the unprocessed floating point numbers using the fixed point number processing component includes:

[0111] Allocate the floating point numbers that have not been processed into a task set, the task set includes at least one floating point number processing task, and a single floating point number processing task includes at least two floating point numbers that have not been processed;

[0112] Select a floating point number processing task from the task set as the task to be processed;

[0113] Use fixed-point number processing components to process pending tasks;

[0114] Based on the remaining floating-point processing tasks in the task set, the load ratio value is updated;

[0115] If the updated load ratio value does not satisfy the load balance index, the fixed-point number processing component is continuously used to process the next floating-point number processing task in the task set, and the load ratio value is updated again.

[0116] In an optional embodiment, the method further comprises:

[0117] A floating-point number whose sign attribute is known and has not been processed is determined to be a floating-point number that has not been processed.

[0118] In an optional embodiment, the step of processing at least two floating point numbers using a fixed point number processing component includes:

[0119] A fixed-point number processing component is used to compare at least two floating-point numbers.

[0120] The execution subject of each step of the method provided in the above embodiment may be the same device, or the method may be executed by different devices. For example, the execution subject of steps 601 to 603 may be device A; for another example, the execution subject of steps 601 and 602 may be device A, and the execution subject of step 603 may be device B; and so on.

[0121] In addition, in some of the processes described in the above embodiments and the accompanying drawings, multiple operations that appear in a specific order are included, but it should be clearly understood that these operations may not be executed in the order in which they appear in this article or executed in parallel, and the sequence numbers of the operations, such as 601, 602, etc., are only used to distinguish between different operations, and the sequence numbers themselves do not represent any execution order. In addition, these processes may include more or fewer operations, and these operations may be executed in sequence or in parallel. It should be noted that the descriptions of "first", "second", etc. in this article are used to distinguish different messages, devices, modules, etc., do not represent the order of precedence, and do not limit the "first" and "second" to be different types.

[0122] It is worth noting that the technical details in the above-mentioned embodiments of the floating-point number processing method can be referred to the relevant description in the aforementioned processor embodiment. In order to save space, they will not be repeated here, but this should not cause a loss in the protection scope of this application.

[0123] Accordingly, an embodiment of the present application further provides a computer-readable storage medium storing a computer program, which, when executed, can implement each step that can be executed by a processor in the above method embodiment.

[0124] Those skilled in the art will appreciate that the embodiments of the present application may be provided as methods, systems, or computer program products. Therefore, the present application may adopt the form of a complete hardware embodiment, a complete software embodiment, or an embodiment in combination with software and hardware. Moreover, the present application may adopt the form of a computer program product implemented in one or more computer-usable storage media (including but not limited to disk storage, CD-ROM, optical storage, etc.) that include computer-usable program code.

[0125] The present application is described with reference to the flowchart and / or block diagram of the method, device (system) and computer program product according to the embodiment of the present application. It should be understood that each process and / or box in the flowchart and / or block diagram, and the combination of the process and / or box in the flowchart and / or block diagram can be realized by computer program instructions. These computer program instructions can be provided to a processor of a general-purpose computer, a special-purpose computer, an embedded processor or other programmable data processing device to produce a machine, so that the instructions executed by the processor of the computer or other programmable data processing device produce a device for realizing the function specified in one process or multiple processes in the flowchart and / or one box or multiple boxes in the block diagram.

[0126] These computer program instructions may also be stored in a computer-readable memory that can direct a computer or other programmable data processing device to work in a specific manner, so that the instructions stored in the computer-readable memory produce a manufactured product including an instruction device that implements the functions specified in one or more processes in the flowchart and / or one or more boxes in the block diagram.

[0127] These computer program instructions may also be loaded onto a computer or other programmable data processing device so that a series of operational steps are executed on the computer or other programmable device to produce a computer-implemented process, whereby the instructions executed on the computer or other programmable device provide steps for implementing the functions specified in one or more processes in the flowchart and / or one or more boxes in the block diagram.

[0128] In a typical configuration, a computing device includes one or more processors (CPU), input / output interfaces, network interfaces, and memory.

[0129] The memory may include non-permanent storage in a computer-readable medium, random access memory (RAM) and / or non-volatile memory in the form of read-only memory (ROM) or flash RAM. The memory is an example of a computer-readable medium.

[0130] Computer readable media include permanent and non-permanent, removable and non-removable media that can be implemented by any method or technology to store information. Information can be computer readable instructions, data structures, program modules or other data. Examples of computer storage media include, but are not limited to, phase change memory (PRAM), static random access memory (SRAM), dynamic random access memory (DRAM), other types of random access memory (RAM), read-only memory (ROM), electrically erasable programmable read-only memory (EEPROM), flash memory or other memory technology, compact disk read-only memory (CD-ROM), digital versatile disk (DVD) or other optical storage, magnetic cassettes, magnetic tape magnetic disk storage or other magnetic storage devices or any other non-transmission media that can be used to store information that can be accessed by a computing device. As defined herein, computer readable media does not include temporary computer readable media (transitory media), such as modulated data signals and carrier waves.

[0131] It should also be noted that the terms "include", "comprises" or any other variations thereof are intended to cover non-exclusive inclusion, so that a process, method, commodity or device including a series of elements includes not only those elements, but also other elements not explicitly listed, or also includes elements inherent to such process, method, commodity or device. In the absence of more restrictions, the elements defined by the sentence "comprises a ..." do not exclude the existence of other identical elements in the process, method, commodity or device including the elements.

[0132] The above is only the embodiment of the present application and is not intended to limit the present application. For those skilled in the art, the present application may have various changes and variations. Any modification, equivalent replacement, improvement, etc. made within the spirit and principle of the present application should be included in the protection scope of the present application.

Claims

1. A floating point number processing method, characterized in that: include: In response to a floating point number processing instruction, obtaining at least two floating point numbers to be processed; storing the at least two floating point numbers as complements respectively, and providing the complements corresponding to the at least two floating point numbers to a given point number processing component; Using the fixed-point number processing component to compare the at least two floating-point numbers to obtain a first processing result; If at least one of the at least two floating-point numbers has a non-negative attribute, outputting the first processing result as a response to the floating-point number processing instruction; If the at least two floating-point numbers both have a negative attribute, a result opposite to the first processing result is output as a second processing result as a response to the floating-point number processing instruction.

2. The method according to claim 1, characterized in that Also includes: If the sign attributes of the at least two floating-point numbers are unknown, determining an attribute description parameter based on the sign bits of the at least two floating-point numbers, wherein the attribute description parameter is used to describe a distribution feature of the sign attributes of the at least two floating-point numbers; The second processing result is output according to the attribute description parameter and the first processing result.

3. The method according to claim 1, characterized in that The step of determining an attribute description parameter based on the sign bits of the at least two floating point numbers comprises: An AND operation is performed on the sign bits of the at least two floating-point numbers to obtain the attribute description parameter.

4. The method according to claim 2, characterized in that: Outputting the second processing result according to the attribute description parameter and the first processing result includes: Performing an XOR operation on the attribute description parameter and the first processing result to obtain an evaluation index for the first processing result; If the evaluation index is true, the first processing result is output as the second processing result; If the evaluation index is false, a result opposite to the first processing result is output as the second processing result.

5. The method according to claim 1, characterized in that Before responding to the floating point number processing instruction, the method further includes: Perform hardware detection on the processor; If it is determined that there is no floating point processing component in the processor or the performance of the floating point processing component is lower than a preset standard, the operation in response to the floating point processing instruction is executed.

6. The method according to claim 5, characterized in that Also includes: If it is determined that the performance of the floating-point number processing component in the processor is higher than or equal to the preset standard, then when the load ratio between the floating-point number processing component and the fixed-point number processing component is higher than a preset load balance index, the fixed-point number processing component is used to process the floating-point numbers that have not been processed until the load ratio meets the load balance index or all the floating-point numbers that have not been processed are processed.

7. The method according to claim 6, characterized in that The method of using the fixed-point number processing component to process the floating-point number that has not been processed includes: Allocating the unprocessed floating-point numbers into a task set, wherein the task set includes at least one floating-point number processing task, and a single floating-point number processing task includes at least two unprocessed floating-point numbers; Selecting a floating point number processing task from the task set as a task to be processed; Processing the pending task using the fixed-point number processing component; Based on the remaining floating point number processing tasks in the task set, updating the load ratio value; If the updated load ratio does not satisfy the load balance index, the fixed-point number processing component is continuously used to process the next floating-point number processing task in the task set, and the load ratio is updated again.

8. The method according to claim 7, characterized in that Also includes: A floating point number whose sign attribute is known and has not been processed is determined as the floating point number that has not been processed.

9. A processor, characterized in that: It includes a compiling component and a fixed-point number processing component, wherein the compiling component is communicatively connected with the fixed-point number processing component; The compiling component is used to obtain at least two floating point numbers to be processed in response to the floating point number processing instruction; storing the at least two floating point numbers as complements respectively, and providing the complements corresponding to the at least two floating point numbers to a given point number processing component; Obtaining a first processing result returned by the fixed-point number processing component; If at least one of the at least two floating-point numbers has a non-negative attribute, outputting the first processing result as a response to the floating-point number processing instruction; If both of the at least two floating-point numbers have a negative attribute, outputting a result opposite to the first processing result as a second processing result as a response to the floating-point number processing instruction; The fixed-point number processing component is used to compare the at least two floating-point numbers to obtain the first processing result, and return the first processing result to the compilation component.

10. A processor, characterized in that: It includes a compiling component, a floating-point number processing component and a fixed-point number processing component, wherein the compiling component is in communication with the floating-point number processing component and the fixed-point number processing component; The compiling component is configured to obtain at least two floating point numbers to be processed in response to a floating point processing instruction if the performance of the floating point processing component is lower than a preset standard; storing the at least two floating point numbers as complements respectively, and providing the complements corresponding to the at least two floating point numbers to a given point number processing component; Obtaining a first processing result returned by the fixed-point number processing component; If at least one of the at least two floating-point numbers has a non-negative attribute, outputting the first processing result as a response to the floating-point number processing instruction; If both of the at least two floating-point numbers have a negative attribute, outputting a result opposite to the first processing result as a second processing result as a response to the floating-point number processing instruction; The fixed-point number processing component is used to compare the complements corresponding to the at least two floating-point numbers to obtain the first processing result, and return the first processing result to the compilation component.

11. The processor according to claim 10, characterized in that The compilation component is also used to: If it is determined that the performance of the floating-point number processing component in the processor is higher than or equal to the preset standard, then when the load ratio between the floating-point number processing component and the fixed-point number processing component is higher than a preset load balance index, the fixed-point number processing component is used to process the floating-point numbers that have not been processed until the load ratio meets the load balance index or all the floating-point numbers that have not been processed are processed.

12. A computer-readable storage medium storing computer instructions, characterized in that: When the computer instructions are executed by one or more processors, the one or more processors are caused to execute the floating-point number processing method according to any one of claims 1 to 8.

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