Vertical memory device

Abstract

A vertical memory device is provided that includes first horizontal gate electrodes disposed on a substrate and spaced apart from one another in a first direction that is substantially perpendicular to an upper surface of the substrate. Each of the first horizontal gate electrodes extends in a second direction that is substantially parallel to the upper surface of the substrate. A vertical channel extends through the first horizontal gate electrodes in the first direction. A charge storage structure is disposed between each of the first horizontal gate electrodes and the vertical channel. A first vertical gate electrode extends through the first horizontal gate electrodes in the first direction. The first vertical gate electrode is electrically insulated from the first horizontal gate electrodes. A first horizontal channel is disposed at a portion of each of the first horizontal gate electrodes adjacent to the first vertical gate electrode.

Description

[0001] This application claims priority to Korean Patent Application No. 10-2020-0021414, filed on February 21, 2020, with the Korean Intellectual Property Office, the entire disclosure of which is incorporated herein by reference. Technical Field

[0002] The present invention relates to a vertical memory device, and more specifically, to a vertical NAND flash memory device. Background Technology

[0003] In VNAND flash memory devices with a cell-on-periphery (COP) architecture, upper circuit patterns (such as upper contact plugs or upper wirings) are formed on the pads of the word lines to apply electrical signals to the pads on the substrate. The word lines can be connected to the upper circuit patterns via vias extending through the word lines. Electrical signals can be transmitted from pass transistors on the substrate via lower circuit patterns to the through-vias. As the number of stacked word lines increases, the number of pass transistors, lower circuit patterns, upper circuit patterns, and through-vias for applying electrical signals to the word lines also increases. Therefore, the substrate area increases, which leads to a degradation in the integration density of the VNAND flash memory device. Summary of the Invention

[0004] An exemplary embodiment of the present invention provides a vertical memory device with improved electrical characteristics.

[0005] According to an exemplary embodiment of the present invention, a vertical memory device includes first horizontal gate electrodes disposed on a substrate and spaced apart from each other in a first direction substantially perpendicular to an upper surface of the substrate. Each of the first horizontal gate electrodes extends in a second direction substantially parallel to the upper surface of the substrate. A vertical channel extends through the first horizontal gate electrodes in the first direction. A charge storage structure is disposed between each of the first horizontal gate electrodes and the vertical channel. The first vertical gate electrode extends through the first horizontal gate electrode in the first direction. The first vertical gate electrode is electrically insulated from the first horizontal gate electrode. The first horizontal channel is disposed at the portion of each of the first horizontal gate electrodes adjacent to the first vertical gate electrode.

[0006] According to an exemplary embodiment of the present invention, a vertical memory device includes horizontal gate electrodes disposed on a substrate and spaced apart from each other in a first direction substantially perpendicular to an upper surface of the substrate. Each of the horizontal gate electrodes extends in a second direction substantially parallel to the upper surface of the substrate. Each of the horizontal gate electrodes includes a first portion comprising metal and a second portion comprising polysilicon doped with impurities. A vertical channel extends through the first portion of each of the horizontal gate electrodes in the first direction. A charge storage structure is disposed between each of the horizontal gate electrodes and the vertical channel. The vertical gate electrodes extend through the second portion of each of the horizontal gate electrodes in the first direction. A gate insulating pattern is disposed on the sidewalls of the vertical gate electrodes. The horizontal channel is disposed at the second portion of each of the horizontal gate electrodes.

[0007] According to an exemplary embodiment of the present invention, horizontal gate electrodes are disposed on a substrate and spaced apart from each other in a first direction substantially perpendicular to the upper surface of the substrate. Each of the horizontal gate electrodes extends in a second direction substantially parallel to the upper surface of the substrate. A vertical channel extends through the horizontal gate electrodes in the first direction. A tunnel insulating pattern, a floating gate, and a gate insulating structure are sequentially stacked between each of the horizontal gate electrodes and the vertical channel. The vertical gate electrode extends through the horizontal gate electrode in the first direction. The vertical gate electrode is electrically insulated from the horizontal gate electrode. The horizontal channel is disposed at the portion of each of the horizontal gate electrodes adjacent to the vertical gate electrode.

[0008] According to an exemplary embodiment of the present invention, a vertical memory device includes word lines disposed on a substrate and spaced apart from each other in a first direction substantially perpendicular to an upper surface of the substrate. Each of the word lines extends in a second direction substantially parallel to the upper surface of the substrate. A select line is disposed on the word lines and extends in the second direction. A vertical channel extends through the select line and the word lines in the first direction. A charge storage structure is disposed on the sidewall of the vertical channel. A first switching transistor is configured to control an electrical signal applied to the word lines. The first switching transistor includes a first vertical gate electrode extending through the word lines in the first direction. The first vertical gate electrode is electrically insulated from the word lines. A first horizontal channel is disposed at a portion of each word line adjacent to the first vertical gate electrode. A second switching transistor is configured to control an electrical signal applied to the select line. The second switching transistor includes a second vertical gate electrode extending through the select line in the first direction. The second vertical gate electrode is spaced apart from the first vertical gate electrode in the second direction and electrically insulated from the select line. A second horizontal channel is disposed at a portion of the select line adjacent to the second vertical gate electrode.

[0009] According to an exemplary embodiment of the present invention, a vertical memory device includes vertical channels disposed on a substrate. Each of the vertical channels extends in a first direction substantially perpendicular to an upper surface of the substrate. Charge storage structures are respectively disposed on sidewalls of the vertical channels. Word lines are disposed on the substrate and spaced apart from each other in the first direction. Each of the word lines extends in a second direction to surround the charge storage structure, the second direction being substantially parallel to the upper surface of the substrate. First switching transistors are configured to control electrical signals applied to the word lines. Each of the first switching transistors includes a first vertical gate electrode extending through the word line in the first direction. The first vertical gate electrode is electrically insulated from the word line. A first horizontal channel is disposed at a portion of each word line adjacent to the first vertical gate electrode. First transmission transistors are respectively electrically connected to the word lines and configured to apply electrical signals to the word lines. Second transmission transistors are electrically connected to at least one of the first switching transistors. A plurality of vertical channels, a plurality of charge storage structures corresponding to the plurality of vertical channels, and a plurality of word lines surrounding the plurality of vertical channels define a memory block, the memory block being configured to perform an erase operation of the vertical memory device. A memory block is one of a plurality of memory blocks arranged in a third direction, which is substantially parallel to the upper surface of the substrate and substantially perpendicular to the second direction. Word lines included in each of the plurality of memory blocks at the same level are shared to define a shared memory block comprising one word line at each level. One of the first transfer transistors is electrically connected to a corresponding word line at the corresponding level in the shared memory block. One of the second transfer transistors is electrically connected to a corresponding memory block among the plurality of memory blocks in the shared memory block.

[0010] According to an exemplary embodiment, a vertical memory device includes a substrate comprising a first region and a second region. A first transfer transistor is disposed on the second region of the substrate. A second transfer transistor and a third transfer transistor are disposed on the first region of the substrate. A first lower circuit pattern, a second lower circuit pattern, and a third lower circuit pattern are disposed on the substrate. The first to third lower circuit patterns are electrically connected to the first to third transfer transistors, respectively. A common source plate (CSP) is disposed on the first to third lower circuit patterns. A first horizontal gate electrode, a second horizontal gate electrode, and a third horizontal gate electrode are disposed on the CSP. The first to third horizontal gate electrodes are spaced apart from each other in a first direction, which is substantially perpendicular to the upper surface of the substrate. Each of the first to third horizontal gate electrodes extends in a second direction, which is substantially parallel to the upper surface of the substrate. Vertical channels all extend in the first direction through the first to third horizontal gate electrodes disposed on the first region of the substrate. Charge storage structures are disposed on the sidewalls of the vertical channels. A first switching transistor is disposed on the first region of the substrate. The first switching transistor is configured to control an electrical signal applied to a second horizontal gate electrode. Each of the first switching transistors includes a first vertical gate electrode extending in a first direction through a first horizontal gate electrode to a third horizontal gate electrode. The first vertical gate electrode is electrically insulated from the first horizontal gate electrode to the third horizontal gate electrode. A first horizontal channel is disposed at the portion of each of the second horizontal gate electrodes adjacent to the first vertical gate electrode. A second switching transistor is disposed on a first region of the substrate. The second switching transistor is configured to control an electrical signal applied to a third horizontal gate electrode. Each of the second switching transistors includes a second vertical gate electrode extending in a first direction through a first horizontal gate electrode to a third horizontal gate electrode. The second vertical gate electrode is spaced apart from the first vertical gate electrode in a second direction. The second vertical gate electrode is electrically insulated from the first horizontal gate electrode to the third horizontal gate electrode. A second horizontal channel is disposed at the portion of each of the third horizontal gate electrodes adjacent to the second vertical gate electrode. A first contact plug, a second contact plug, and a third contact plug are disposed on the first horizontal gate electrode, the second horizontal gate electrode, and the third horizontal gate electrode, respectively, on a second region of the substrate. A first through-via, a second through-via, and a third through-via extend through the first horizontal gate electrode to the third horizontal gate electrode and are electrically insulated from the first horizontal gate electrode to the third horizontal gate electrode. The first through-hole to the third through-hole are respectively formed at positions corresponding to the first contact plug to the third contact plug, and are electrically connected to the first contact plug to the third contact plug on the second region of the substrate. The first through-hole to the third through-hole are respectively electrically connected to the corresponding first transmission transistor. The first switching transistor is respectively electrically connected to the corresponding second transmission transistor. The second switching transistor is respectively electrically connected to the corresponding third transmission transistor.

[0011] In a vertical memory device according to an exemplary embodiment of the present invention, the pad region of the pad forming the word line can be reduced, and the layout freedom of the upper circuit pattern on the pad region can be increased. Attached Figure Description

[0012] Figures 1 to 23 These are plan views and cross-sectional views illustrating a method for manufacturing a vertical memory device according to an exemplary embodiment of the present invention.

[0013] Figure 24 This is a plan view illustrating a vertical memory device according to a comparative embodiment, which may correspond to Figure 18 .

[0014] Figure 25 and Figure 26 This is a plan view illustrating an exemplary embodiment of a vertical memory device according to the present invention, which may correspond to Figure 15 .

[0015] Figures 27 to 29 These are plan views and cross-sectional views illustrating an exemplary embodiment of a vertical memory device according to the present invention.

[0016] Figure 30 It is a vertical memory device according to an exemplary embodiment of the present invention.

[0017] Figure 31 , Figure 32A , Figure 32B , Figure 33A and Figure 33B These are plan views and cross-sectional views illustrating an exemplary embodiment of a vertical memory device according to the present invention.

[0018] Figure 34 , Figure 35A , Figure 35B , Figure 36A , Figure 36B and Figure 37 These are plan views and cross-sectional views illustrating an exemplary embodiment of a vertical memory device according to the present invention.

[0019] Figure 38A and Figure 38B This is a cross-sectional view illustrating an exemplary embodiment of a vertical memory device according to the present invention.

[0020] Figures 39 to 49 These are plan views and cross-sectional views illustrating a method for manufacturing a vertical memory device according to an exemplary embodiment of the present invention.

[0021] Figure 50 This is a plan view illustrating an exemplary embodiment of a vertical memory device according to a concept conceived in the present invention.

[0022] Figure 51 This is a perspective view showing an exemplary embodiment of a molded part according to the concept of the present invention.

[0023] Figures 52 to 54 These are plan views and cross-sectional views illustrating an exemplary embodiment of a vertical memory device according to the present invention.

[0024] Figure 55 This is a plan view illustrating a vertical memory device according to a comparative embodiment, which may correspond to Figure 52 .

[0025] Figure 56 and Figure 57 This is a plan view illustrating an exemplary embodiment of a vertical memory device according to a concept conceived in the present invention. Detailed Implementation

[0026] A vertical memory device and a method of manufacturing the same, according to exemplary embodiments of the present invention, will be described more fully below with reference to the accompanying drawings. It will be understood that although the terms “first,” “second,” and / or “third” may be used herein to describe various elements, components, regions, layers, and / or portions, these elements, components, regions, layers, and / or portions should not be limited by these terms. These terms are used only to distinguish one element, component, region, layer, or portion from another element, component, region, layer, or portion.

[0027] In the following detailed description of exemplary embodiments, a direction substantially perpendicular to the upper surface of the substrate can be defined as a first direction D1, and two directions substantially parallel to the upper surface of the substrate and intersecting each other can be defined as a second direction D2 and a third direction D3, respectively. In exemplary embodiments, the second direction D2 and the third direction D3 may be substantially perpendicular to each other. However, exemplary embodiments of the inventive concept are not limited thereto.

[0028] Figures 1 to 23 These are plan views and cross-sectional views illustrating a method for manufacturing a vertical memory device according to an exemplary embodiment of the present invention. Figure 1 , Figure 2 , Figure 6 , Figure 8 , Figure 13 , Figure 15 , Figure 18 and Figure 20 It's a floor plan. Figures 3 to 5 , Figure 7A , Figure 7B , Figures 9 to 12 , Figure 14 , Figures 16A to 17 , Figure 19 as well as Figures 21A to 23 It is a sectional view.

[0029] Figures 3 to 5 , Figure 7A , Figure 14 , Figure 16A , Figure 16B , Figure 19 , Figure 21A and Figure 21B These are sectional views taken along line A-A' of the corresponding plan view. Figures 9 to 12 and Figure 22 These are sectional views taken along line B-B' of the corresponding plan view. Figure 17 and Figure 23 These are sectional views taken along line C-C' of the corresponding plan view. Figures 2 to 23 yes Figure 1 The graph of region X, Figure 7B yes Figure 7A An enlarged cross-sectional view of region Y.

[0030] Reference Figure 1 In an exemplary embodiment, the substrate 100 may include a first region I and a second region II that at least partially surrounds the first region I.

[0031] In an exemplary embodiment, substrate 100 may include a group IV semiconductor material (such as at least one material selected from silicon, germanium, silicon-germanium, etc.) or a group III-V compound (such as at least one compound selected from GaP, GaAs, GaSb, etc.). In an exemplary embodiment, substrate 100 may be a silicon-on-insulator (SOI) substrate or a germanium-on-insulator (GOI) substrate. In an exemplary embodiment, substrate 100 may include p-type impurities (such as boron, etc.).

[0032] In an exemplary embodiment, the first region I and the second region II can be a cell array region and a pad region (or extension region) that can be formed together as a cell region, respectively. The pad region can be disposed at each of the opposing lateral sides of the cell array region (e.g., in the second direction D2). For example, memory cells, each including a gate electrode, a channel, and a charge storage structure, can be formed on the first region I of the substrate 100, and pads for transmitting electrical signals to upper contact plugs of the memory cells and contact upper contact plugs of the gate electrodes can be formed on the second region II of the substrate 100. In an exemplary embodiment, a third region can also be formed in the substrate 100 to surround the second region II of the substrate 100, and an upper circuit pattern for applying electrical signals to the memory cells via the upper contact plugs can be formed on the third region of the substrate 100.

[0033] In the following text, region X, which includes a portion of the first region I and the second region II of the substrate 100, will be described.

[0034] Reference Figure 2and Figure 3 In an exemplary embodiment, a lower circuit pattern may be formed on a substrate 100, and a first insulating interlayer 150 and a second insulating interlayer 170 may be sequentially formed on the substrate 100 to cover the lower circuit pattern.

[0035] The substrate 100 may include a field region and an active region 101, wherein an isolation pattern 110 is formed on the field region and no isolation pattern is formed on the active region 101. In an exemplary embodiment, the isolation pattern 110 may be formed by a shallow trench isolation (STI) process or the like, and may include an oxide (such as silicon oxide). However, exemplary embodiments of the present invention are not limited thereto.

[0036] In an exemplary embodiment, the vertical memory device may have a peripheral upper cell (COP) structure. For example, a lower circuit pattern may be formed on a substrate 100, and memory cells, upper contact plugs, and the upper circuit pattern may be formed on top of the lower circuit pattern.

[0037] The lower circuit pattern may include transistors, lower contact plugs, lower wiring, lower vias, etc.

[0038] Alternatively, the vertical memory device may not have a COP structure, and in this exemplary embodiment, a peripheral circuit pattern replacing the lower circuit pattern may be formed on a third region of the substrate 100. For example, transistors, lower contact plugs, lower wiring, lower vias, etc., covered by a first insulating layer 150 and a second insulating layer 170 on the substrate 100 may be formed on the third region of the substrate 100 to be electrically connected to the upper circuit pattern.

[0039] Reference Figure 2 and Figure 3 as well as Figure 8 , Figure 9 , Figure 15 and Figure 17 In some exemplary embodiments, a first transistor may be formed on a second region II of the substrate 100, and a second and third transistor may be formed on a first region I of the substrate 100. The second transistor may be formed on a portion of the first region I adjacent to the second region II of the substrate 100. In exemplary embodiments, each of the first and second transistors may function as a transmission transistor.

[0040] For example, the first transistor may include a first lower gate structure 142 and a first impurity region 102 and a second impurity region 103, respectively serving as source and drain, located above the adjacent active region 101. Figure 17 The second transistor shown may include a second lower gate structure 144 and a third impurity region 104 and a fourth impurity region 105, respectively serving as source and drain, located above the adjacent active region 101. Figure 9 The third transistor shown may include a third lower gate structure 146 and a fifth impurity region 106 and a sixth impurity region 107, which serve as source and drain respectively, located above the adjacent active region 101.

[0041] The first lower gate structure 142 may include a first lower gate insulating pattern 122 and a first lower gate electrode 132 sequentially stacked on the substrate 100. The second lower gate structure 144 may include a second lower gate insulating pattern 124 and a second lower gate electrode 134 sequentially stacked on the substrate 100. The third lower gate structure 146 may include a third lower gate insulating pattern 126 and a third lower gate electrode 136 sequentially stacked on the substrate 100.

[0042] A first insulating interlayer 150 can be formed on the substrate 100 to cover the first transistor, the second transistor, and the third transistor. A first lower contact plug 162, a second lower contact plug 163, a fourth lower contact plug 165, a fifth lower contact plug 166, a seventh lower contact plug 168, and an eighth lower contact plug 169 can be formed extending through the first insulating interlayer 150 to contact the first impurity region 102, the second impurity region 103, the third impurity region 104, the fourth impurity region 105, the fifth impurity region 106, and the sixth impurity region 107, respectively. A third lower contact plug 164 and a sixth lower contact plug 167 can also be formed extending through the first insulating interlayer 150 to contact the first lower gate electrode 132 and the second lower gate electrode 134, respectively. Additionally, in an exemplary embodiment, a ninth lower contact plug can also be formed extending through the first insulating interlayer 150 to contact the third lower gate electrode 136.

[0043] First lower wiring 182, second lower wiring 183, fourth lower wiring 185, fifth lower wiring 186, seventh lower wiring 188, and eighth lower wiring 189 can be formed on the first insulating layer 150 to contact the first lower contact plug 162, second lower contact plug 163, fourth lower contact plug 165, fifth lower contact plug 166, seventh lower contact plug 168, and eighth lower contact plug 169, respectively. Third lower wiring 184 and sixth lower wiring 187 can be formed on the first insulating layer 150 to contact the third lower contact plug 164 and sixth lower contact plug 167, respectively. For example, the first lower wiring 182 to the eighth lower wiring 189 can be formed on the upper surface of the first insulating layer 150.

[0044] The first lower via 192, the ninth lower wiring 202, the fourth lower via 212, and the twelfth lower wiring 222 can be (e.g., in the first direction D1) sequentially stacked on the first lower wiring 182. The second lower via 194, the tenth lower wiring 204, the fifth lower via 214, and the thirteenth lower wiring 224 can be (e.g., in the first direction D1) sequentially stacked on the fourth lower wiring 185, and the third lower via 196, the eleventh lower wiring 206, the sixth lower via 216, and the fourteenth lower wiring 226 can be (e.g., in the first direction D1) sequentially stacked on the seventh lower wiring 188.

[0045] The second insulating interlayer 170 may be formed on the first insulating interlayer 150 to cover the first lower wiring 182, the second lower wiring 183, the third lower wiring 184, the fourth lower wiring 185, the fifth lower wiring 186, the sixth lower wiring 187, the seventh lower wiring 188, the eighth lower wiring 189, the ninth lower wiring 202, the tenth lower wiring 204, the eleventh lower wiring 206, the twelfth lower wiring 222, the thirteenth lower wiring 224 and the fourteenth lower wiring 226, as well as the first lower via 192, the second lower via 194, the third lower via 196, the fourth lower via 212, the fifth lower via 214 and the sixth lower via 216.

[0046] In an exemplary embodiment, the first lower gate structure 142 of the first transistor can be connected to the driving circuit via the third lower contact plug 164 and the third lower wiring 184, and the second impurity region 103 of the first transistor can be connected to the driving circuit via the second lower contact plug 163 and the second lower wiring 183. For example, the first transistor can transmit electrical signals from the driving circuit to the first lower contact plug 162, the first lower wiring 182, the first lower via 192, the ninth lower wiring 202, the fourth lower via 212, and the twelfth lower wiring 222.

[0047] Additionally, the fourth impurity region 105 of the second transistor can be connected to the driving circuit via the fifth lower contact plug 166 and the fifth lower wiring 186, and the second lower gate structure 144 of the second transistor can be connected to the driving circuit via the sixth lower contact plug 167 and the sixth lower wiring 187. For example, the second transistor can transmit electrical signals from the driving circuit to the fourth lower contact plug 165, the fourth lower wiring 185, the second lower via 194, the tenth lower wiring 204, the fifth lower via 214, and the thirteenth lower wiring 224.

[0048] In an exemplary embodiment, each element of the underlying circuit pattern can be formed by patterning and / or damascene processes.

[0049] Reference Figure 4An exemplary embodiment may include the sequential formation (e.g., stacked in the first direction D1) of a common source plate (CSP) 240, a sacrificial layer structure 290, and a support layer 300 on the second insulating interlayer 170.

[0050] In an exemplary embodiment, CSP 240 may include polycrystalline silicon doped with n-type impurities. Alternatively, CSP 240 may include sequentially stacked metal silicide layers and polycrystalline silicon layers doped with n-type impurities. The metal silicide layers may include, for example, tungsten silicide. However, exemplary embodiments of the inventive concept are not limited thereto.

[0051] The sacrificial layer structure 290 may include a first sacrificial layer 260, a second sacrificial layer 270, and a third sacrificial layer 280 sequentially stacked (e.g., in the first direction D1). In an exemplary embodiment, the first sacrificial layer 260 and the third sacrificial layer 280 may include oxides (such as silicon oxide, etc.), and the second sacrificial layer 270 may include nitrides (such as silicon nitride, etc.). However, exemplary embodiments of the inventive concept are not limited thereto.

[0052] In an exemplary embodiment, the support layer 300 may include a material having etch selectivity relative to the first sacrificial layer 260, the second sacrificial layer 270, and the third sacrificial layer 280. For example, the support layer 300 may include polysilicon doped with n-type impurities. However, exemplary embodiments of the inventive concept are not limited thereto. A portion of the support layer 300 may extend through the sacrificial layer structure 290 to contact the upper surface of the CSP 240, and said portion may be formed into a support pattern.

[0053] The first insulating layer 310 and the first gate electrode layer 320 can be alternately and repeatedly stacked on the support layer 300 in the first direction D1. Therefore, a molded layer comprising a plurality of first insulating layers 310 and a plurality of first gate electrode layers 320 alternately and repeatedly stacked in the first direction D1 can be formed. In an exemplary embodiment, the first insulating layer 310 may include an oxide (such as silicon oxide), and the first gate electrode layer 320 may include polysilicon doped with n-type impurities, etc. However, exemplary embodiments of the present invention are not limited thereto.

[0054] Reference Figure 4 and Figure 6 In an exemplary embodiment, a first separation pattern 330 may be formed through the lowermost gate electrode layer 320 of the first gate electrode layer 320. The first separation pattern 330 may be formed on a second region II of the substrate 100 and may include an oxide (such as silicon oxide). However, exemplary embodiments of the inventive concept are not limited thereto. In an exemplary embodiment, a plurality of first separation patterns 330 may be spaced apart from each other on a third direction D3.

[0055] Reference Figure 5 In an exemplary embodiment, a photoresist pattern can be formed on the uppermost first insulating layer 310 of the first insulating layer 310, partially covering the uppermost first insulating layer 310. The photoresist pattern can be used as an etching mask to etch the uppermost first insulating layer 310 and the uppermost first gate electrode layer 320 below the uppermost first insulating layer 310 of the first gate electrode layer 320. Therefore, a portion of the first insulating layer 310 directly below the uppermost first gate electrode layer 320 can be exposed.

[0056] After performing a trimming process to reduce the area of ​​the photoresist pattern by a given ratio, an etching process can be performed so that the reduced photoresist pattern can be used as an etching mask to etch the uppermost first insulating layer 310 of the first insulating layer 310, the uppermost first gate electrode layer 320 of the first gate electrode layer 320, an exposed first insulating layer 310 of the first insulating layer 310, and a first gate electrode layer 320 below the exposed first insulating layer 310 of the first gate electrode layer 320. By repeatedly performing the trimming and etching processes, a molded part comprising multiple stepped layers can be formed, which may comprise sequentially stacked first gate electrode layers 320 and first insulating layers 310 and have a stepped shape. The length of the stepped layer (e.g., in the second direction D2) may decrease as the distance from the substrate 100 in the first direction D1 increases.

[0057] In the following, each of the "step layers" can be considered to include not only the exposed portion but also the portion covered by the step layer above it, and thus can refer to the entire portion of the first gate electrode layer 320 and the entire portion of the first insulating layer 310 at each level (e.g., distance from the upper surface of the substrate 100 in the first direction D1). The exposed portion of a step layer not covered by the step layer above it can be referred to as a "step". In an exemplary embodiment, the steps can be arranged in the second direction D2. In an exemplary embodiment, the first plurality of steps in the molding can have a substantially constant length difference between adjacent steps in the second direction D2. The second plurality of steps in the molding can have a length difference between adjacent steps in the second direction D2 that is greater than the length difference in the first plurality of steps. In an exemplary embodiment, the first plurality of steps can include most of the steps in the molding. In the following, the steps in the first plurality of steps can be referred to as first steps, and the steps in the second plurality of steps can be referred to as second steps. Figure 5Two second steps are shown. The steps are indicated by dashed lines in each plan view.

[0058] The molded part can be formed on the support layer 300 on the first region I and the second region II of the substrate 100. For example... Figure 5 In the exemplary embodiment shown, the upper surface of the lateral end of the support layer 300 may not be covered by the molding and may be exposed. Each of the steps in the molding may be formed on the second region II of the substrate 100.

[0059] Reference Figure 6 , Figure 7A and Figure 7B In an exemplary embodiment, a third insulating interlayer 340 may be formed on the CSP 240 to cover the exposed edge upper surfaces of the molded part and the support layer 300. In an exemplary embodiment, the upper portion of the third insulating interlayer 340 may be planarized until the upper surface of the uppermost of the first insulating layers 310 is exposed. Therefore, the sidewalls of the molded part may be covered by the third insulating interlayer 340. A fourth insulating interlayer 350 may be formed on the molded part and the third insulating interlayer 340. For example, as... Figure 7A In the exemplary embodiment, the lower surface of the fourth insulating interlayer 350 can directly contact the upper surface of the third insulating interlayer 340.

[0060] The channel holes may be formed through the fourth insulating interlayer 350, the molding, the support layer 300, and the sacrificial layer structure 290, and may extend in the first direction D1 to expose a portion of the upper surface of the CSP 240 on the first region I of the substrate 100. In an exemplary embodiment, a plurality of channel holes may be formed to be spaced apart from each other in each of the second direction D2 and the third direction D3.

[0061] A charge storage structure layer and a channel layer can be sequentially formed on the sidewalls of the channel aperture, the exposed upper surface of the CSP 240, and the fourth insulating interlayer 350, and a fill layer can be formed on the channel layer to fill the channel aperture. The fill layer, channel layer, and charge storage structure layer can be planarized until the upper surface of the fourth insulating interlayer 350 is exposed to form a charge storage structure 400, a first channel 410, and a fill pattern 420 sequentially stacked in each channel aperture. Each of the charge storage structure 400, the first channel 410, and the fill pattern 420 can extend in a first direction D1. The first channel can be referred to as a vertical channel.

[0062] like Figure 7BIn an exemplary embodiment, the charge storage structure 400 may include a tunnel insulating pattern 390, a charge storage pattern 380, and a first blocking pattern 370, which are sequentially stacked from the outer lateral sidewalls of the first channel 410 in a horizontal direction substantially parallel to the upper surface of the substrate 100, and sequentially stacked in a vertical direction on the lower surface of the first channel 410. In an exemplary embodiment, the tunnel insulating pattern 390 and the first blocking pattern 370 may include oxides (such as silicon oxide), the charge storage pattern 380 may include nitrides (such as silicon nitride), and the filling pattern 420 may include oxides (such as silicon oxide). However, exemplary embodiments of the inventive concept are not limited thereto.

[0063] The top portion of the charge storage structure 400, the first channel 410, and the filling pattern 420 sequentially stacked in each of the channel vias can be removed to form a first trench, and a cover pattern 430 can be formed to fill the first trench. In an exemplary embodiment, the cover pattern 430 may include polysilicon doped with n-type impurities, etc. However, exemplary embodiments of the inventive concept are not limited thereto.

[0064] In an exemplary embodiment, the plurality of first channels 410 may be spaced apart from each other in each of the second direction D2 and the third direction D3, thus defining a channel array. Figure 6 In an exemplary embodiment, the channel array may include a first channel column 410a and a second channel column 410b. The first channel column 410a includes a first channel 410 arranged in a second direction D2, and the second channel column 410b includes a first channel 410 arranged in the second direction D2 and spaced apart from the first channel column 410a in a third direction D3. In an exemplary embodiment, the first channel 410 included in the first channel column 410a may be positioned relative to the first channel 410 included in the second channel column 410b in a direction forming an acute angle with either the second direction D2 or the third direction D3.

[0065] The first channel column 410a and the second channel column 410b can be arranged alternately and repeatedly in the third direction D3. In an exemplary embodiment, five first channel columns 410a and four second channel columns 410b can be alternately arranged in the third direction D3, which can form a channel group.

[0066] In the following text, the four channel columns arranged in the channel group may be referred to as the first channel column 410a, the second channel column 410b, the third channel column 410c, and the fourth channel column 410d, respectively. The channel column located in the central part of the channel group may be referred to as the fifth channel column 410e, and the other four channel columns may be referred to as the first channel column 410a, the second channel column 410b, the third channel column 410c, and the fourth channel column 410d, respectively.

[0067] Two channel groups disposed on the third-direction D3 can form a channel block. Memory cells, each including the first channel 410, charge storage structure 400, and gate electrode (shown later), can also correspondingly define memory groups and memory blocks. In a vertical memory device, erase operations can be performed on a block-by-block basis; that is, each memory block can be configured to perform an erase operation on the vertical memory device. Figure 6 Two memory blocks are shown set on a third-party D3, and each of the memory blocks may include two memory groups set on the third-party D3.

[0068] Some of the first insulating layer 310 and the first gate electrode layer 320, as well as the fourth insulating interlayer 350, can be partially etched to form a first opening extending in the second direction D2, and a second partition pattern 440 can be formed in the first opening.

[0069] In an exemplary embodiment, the second dividing pattern 440 may extend through the upper portion of some of the first channels 410. For example, as Figure 6 In the exemplary embodiment shown, the second partition pattern 440 may extend through the fifth channel column 410e in each channel group. Additionally, the second partition pattern 440 may extend through the fourth insulating interlayer 350, the first gate electrode layers 320 at the two levels above, and the first insulating layers 310 at the two levels above, and partially through the first insulating layer 310 at the third highest level. The second partition pattern 440 may extend along the second direction D2 in the first region I and the second region II of the substrate 100, and may extend through the stepped layers at the two levels above in the molding. Therefore, the first gate electrode layers 320 at the corresponding two levels above can be separated in the third direction D3 by the second partition pattern 440.

[0070] Reference Figure 8 and Figure 9 In an exemplary embodiment, a fifth insulating layer 450 may be formed on the fourth insulating layer 350, the cover pattern 430, and the second separating pattern 440. A second opening 460 and a third opening 465 may be formed through the third insulating layer 340, the fourth insulating layer 350, and the fifth insulating layer 450, as well as the molding.

[0071] In an exemplary embodiment, each of the second opening 460 and the third opening 465 may extend along a second direction D2 on a first region I and a second region II of the base 100. The second opening 460 may extend to opposite ends of the molded part having a stepped shape in the second direction D2. However, in an exemplary embodiment, the third opening 465 may be partially discontinuous on the second region II of the base 100. Therefore, the molded part may be completely separated by the second opening 460 in a third direction D3. However, as Figure 8 In the exemplary embodiment, the molded parts may not be completely separated by the third opening 465 in the third direction D3, and the molded parts on opposite sides of the third opening 465 in the third direction D3 may be connected to each other by the first connecting portion 990. In the exemplary embodiment, the first connecting portion 990 may extend downward from the third highest level in the first direction D1 and may overlap with the first separating pattern 330 in the first direction D1.

[0072] An etching process can be performed until the second opening 460 and the third opening 465 expose the upper surface of the support layer 300, and the second opening 460 and the third opening 465 can further extend through the upper part of the support layer 300. As the second opening 460 and the third opening 465 are formed, the sidewalls of the first insulating layer 310 and the first gate electrode layer 320 of the molded part can be exposed, and the first insulating layer 310 and the first gate electrode layer 320 can be separated into a first insulating pattern 315 and a gate electrode, respectively.

[0073] The first insulating pattern 315 and the gate electrode at opposite sides of the third opening 465 may not be completely separated, but may be partially connected to each other via a first connecting portion 990. For example, the first connecting portion 990 of the molding may include a connecting pattern for the first insulating pattern 315 and a connecting pattern for the gate electrode, and the first insulating patterns 315 at opposite sides of the third opening 465 (e.g., on the third direction D3) may be connected to each other, and the gate electrodes at opposite sides of the third opening 465 may be connected to each other. The molding may have a flat upper surface on the first region I of the substrate 100, and may have a stepped shape on each of the opposite ends of the second region II of the substrate 100 and the first region I of the substrate 100 in the second direction D2. The molding may extend in the second direction D2.

[0074] In an exemplary embodiment, each of the gate electrodes may extend in a second direction D2, and a plurality of gate electrodes stacked in a first direction D1 may form a gate electrode structure. The gate electrode structure may have a stepped shape including a stepped layer of gate electrodes. The step of each stepped layer that is not stacked by the step layer above it (such as the end of each stepped layer in the second direction D2) may be referred to as a pad.

[0075] In an exemplary embodiment, multiple gate electrode structures may be formed on the third direction D3, and these multiple gate electrode structures may be spaced apart from each other on the third direction D3 by the second opening 460 and the third opening 465. However, in an exemplary embodiment, the gate electrode structures on opposite sides of the third opening 465 may not be completely separated from each other, but may be partially connected to each other by the connection pattern of the gate electrodes in the first connection portion 990 of the molding part. A pair of adjacent gate electrode structures separated by the second opening 460 on the third direction D3 may be referred to as a single gate electrode structure.

[0076] The gate electrode structure may include a first gate electrode 752, a second gate electrode 754, and a third gate electrode 756 sequentially stacked in a first direction D1. In an exemplary embodiment, the first gate electrode 752 may be formed at the lowest horizontal level to serve as a ground select line (GSL), the third gate electrode 756 may be formed at the highest horizontal level and a second horizontal level from above to serve as a string select line (SSL), and the second gate electrode 754 may be formed at multiple horizontal levels between the first gate electrode 752 and the third gate electrode 756 to serve as a word line. However, gate electrodes that can perform erase operations by utilizing the gate-induced drain leakage (GIDL) phenomenon may also be disposed below the first gate electrode 752 and / or above the third gate electrode 756.

[0077] However, the exemplary embodiments of the present invention are not limited thereto, and in other exemplary embodiments, the number of stacks of each of the first gate electrode 752, the second gate electrode 754 and the third gate electrode 756 may vary.

[0078] In an exemplary embodiment, each of the second opening 460 and the third opening 465 may extend along a second direction D2 between memory groups on a first region I of the substrate 100. A plurality of second openings 460 may be arranged on a third direction D3, and a plurality of third openings 465 may be arranged on a third direction D3. For example, in an exemplary embodiment, the second openings 460 may be formed at each of the opposing lateral sides of a shared memory block on a third direction D3, the shared memory block comprising a plurality of memory blocks sharing word lines with each other. The third openings 465 may be formed between memory blocks within the shared memory block and between memory groups within each of the memory blocks.

[0079] Figure 8 Two memory blocks are shown, each including two memory groups that share word lines to form a shared memory block. Therefore, second openings 460 are formed on opposite sides of the shared memory blocks (e.g., lateral sides on the third direction D3). Additionally, three third openings 465 are formed between the four memory groups in the shared memory block. However, exemplary embodiments of the inventive concept are not limited thereto, and the number of memory groups included in each memory block and the number of memory blocks included in each shared memory block can vary. For example, in another exemplary embodiment, a shared memory block may include four or eight memory blocks.

[0080] exist Figure 8 In the exemplary embodiment of the shared memory block shown, word lines at each level can be connected to each other via a connection pattern of gate electrodes in the first connection portion 990 of the molding for sharing. Eight SSLs formed by the third gate electrode 756 can be spaced apart from each other via a second separator pattern 440 and a third opening 465, and four GSLs formed by the first gate electrode 752 can be spaced apart from each other via a first separator pattern 330 and a third opening 465. For example, each memory block in the shared memory block can include two word lines formed by the second gate electrode 754 at each level, which can be connected to each other via the first connection portion 990 to serve as one word line. Furthermore, two word lines at each level in each memory block included in the shared memory block can also be connected to each other via the first connection portion 990 to serve as one word line. Therefore, the shared memory block can include four word lines at each level to serve as one word line.

[0081] Spacer layers can be formed on the sidewalls of the second opening 460 and the third opening 465 and on the upper surface of the fifth insulating interlayer 450. A portion of the spacer layer on the bottom of the second opening 460 and the third opening 465 can be removed by an anisotropic etching process to form spacer 470, and a portion of the support layer 300 can be partially exposed.

[0082] The exposed portion of the support layer 300 and the portion of the sacrificial layer structure 290 below the exposed portion of the support layer 300 can be removed to expand each of the second opening 460 and the third opening 465 downward (e.g., in the first direction D1). Therefore, each of the second opening 460 and the third opening 465 can expose the upper surface of the CSP 240 and can also extend through the upper portion of the CSP 240.

[0083] In an exemplary embodiment, spacer 470 may comprise undoped polysilicon. When the sacrificial layer structure 290 is partially removed, the sidewalls of the second opening 460 and the third opening 465 may be covered by spacer 470, so the first insulating pattern 315 of the molded part and the gate electrodes 752, 754 and 756 may not be removed.

[0084] Reference Figure 10 In an exemplary embodiment, the sacrificial layer structure 290 can be removed through the second opening 460 and the third opening 465. For example, the sacrificial layer structure 290 can be removed by a wet etching process, thereby forming the first gap 295. However, exemplary embodiments of the inventive concept are not limited thereto.

[0085] In exemplary embodiments, hydrofluoric acid (HF) and / or phosphoric acid (H3PO4) may be used to perform the wet etching process. However, exemplary embodiments of the present invention are not limited thereto.

[0086] With the formation of the first gap 295, the lower surface of the support layer 300 and the upper surface of the CSP 240 can be exposed. Additionally, a portion of the sidewalls of the charge storage structure 400 can be exposed by the first gap 295, and this exposed sidewall of the charge storage structure 400 can be further removed during a wet etching process to expose the outer sidewalls of the first channel 410. Therefore, the charge storage structure 400 can include an upper portion and a lower portion separated from each other by the first gap 295, the upper portion extending through the molding to cover a large portion of the outer sidewalls of the first channel 410, and the lower portion covering the bottom surface of the first channel 410 on the CSP 240.

[0087] Reference Figure 11 In an exemplary embodiment, spacer 470 can be removed, and a channel connection layer can be formed on the sidewalls of the second opening 460 and the third opening 465, as well as in the first gap 295. A portion of the channel connection layer in the second opening 460 and the third opening 465 can be removed by an etch-back process to form a channel connection pattern 480 in the first gap 295.

[0088] As the channel connection pattern 480 is formed, the first channels 410 (such as the first channels 410 included in each channel group) between adjacent (e.g., adjacent on the third direction D3) second and third openings 460 and 465 can be connected to each other.

[0089] In an exemplary embodiment, the channel connection pattern 480 may include undoped polysilicon or polysilicon doped with n-type impurities, etc. However, exemplary embodiments of the present invention are not limited thereto.

[0090] like Figure 11In an exemplary embodiment, an air gap 485 may be formed in the channel connection pattern 480.

[0091] Reference Figure 12 In an exemplary embodiment, a third dividing pattern 490 and a fourth dividing pattern 495 may be formed in the second opening 460 and the third opening 465, respectively (see reference). Figure 13 ).

[0092] In an exemplary embodiment, the third partition pattern 490 and the fourth partition pattern 495 may include oxides (such as silicon oxide). However, exemplary embodiments of the present invention are not limited thereto.

[0093] Reference Figure 13 and Figure 14 In an exemplary embodiment, a sixth insulating layer 500 may be formed on the fifth insulating interlayer 450 and the third and fourth partition patterns 490 and 495, and a first upper contact plug 510, a second upper contact plug 520 and a third upper contact plug 530 may be formed on the second region II of the substrate 100.

[0094] Each of the first upper contact plug 510, the second upper contact plug 520, and the third upper contact plug 530 can extend in the first direction D1 through the third insulating interlayer 340, the fourth insulating interlayer 350, the fifth insulating interlayer 450, the sixth insulating interlayer 500, and the first insulating pattern 315, and can contact the pads of the third gate electrode 756, the second gate electrode 754, and the first gate electrode 752, respectively. Figure 13 A shared memory block comprising two memory blocks including a shared word line is shown, thus showing a second upper contact plug 520 at each level, eight first upper contact plugs 510 at each level, and four third upper contact plugs 530 at each level to correspond to a second gate electrode 754 at each level, eight third gate electrodes 756 at each level, and four first gate electrodes 752 at each level, respectively.

[0095] However, exemplary embodiments of the present invention are not limited thereto, and the first upper contact plug 510, the second upper contact plug 520 and the third upper contact plug 530 may not be limited to the positions shown in the drawings, but may be freely arranged on the pads of the third gate electrode 756, the second gate electrode 754 and the first gate electrode 752, respectively.

[0096] like Figure 15 and Figure 16AAs shown in the exemplary embodiment, each of the following can be formed by forming a hole through the upper part of the third insulating interlayer 340, the fourth insulating interlayer 350, the fifth insulating interlayer 450, the sixth insulating interlayer 500, the seventh insulating interlayer 540, the molding, the support layer 300, the channel connection pattern 480, the CSP 240, and the second insulating interlayer 170, and filling the hole with a conductive material: a first through-hole 562, a second through-hole 564, a third through-hole 566, and a first vertical gate electrode 580. Figure 16A In the exemplary embodiment, each of the first through-via 562, the second through-via 564, and the third through-via 566 can contact the twelfth lower wiring 222, and the first vertical gate electrode 580 can contact the thirteenth lower wiring 224. Compared to the first vertical gate electrode 580 extending in the first direction D1, each of the first gate electrode 752, the second gate electrode 754, and the third gate electrode 756 extending in the second direction D2 (e.g., the horizontal direction) can be referred to as a horizontal gate electrode.

[0097] A second insulating pattern 552, a third insulating pattern 554, and a fourth insulating pattern 556 can be formed on the sidewalls of the first through-hole 562, the second through-hole 564, and the third through-hole 566, respectively, and a fifth insulating pattern 570 can be formed on the sidewall of the first vertical gate electrode 580. Therefore, the first through-hole 562, the second through-hole 564, the third through-hole 566, and the first vertical gate electrode 580 can be electrically insulated from the corresponding gate electrodes 752, 754, and 756, the support layer 300, the channel connection pattern 480, and the CSP 240 of the molded part.

[0098] In an exemplary embodiment, the first through-hole 562, the second through-hole 564, the third through-hole 566, and the first vertical gate electrode 580 may include metal, metal nitride, metal silicide, etc., and the second insulating pattern 552, the third insulating pattern 554, the fourth insulating pattern 556, and the fifth insulating pattern 570 may include oxides (e.g., silicon oxide, etc.). However, exemplary embodiments of the present invention are not limited thereto.

[0099] In an exemplary embodiment, the first through-hole 562, the second through-hole 564, and the third through-hole 566 may extend through a second step of the molded part, which may be disposed at positions corresponding to the first upper contact plug 510, the second upper contact plug 520, and the third upper contact plug 530 respectively in the second direction D2. The third through-hole 566 may extend through the portion of the support layer 300 not covered by the molded part.

[0100] A common source contact plug can also be formed on the portion of the support layer 300 that is not covered by the molded part.

[0101] In an exemplary embodiment, a first vertical gate electrode 580 may be formed on a portion of a first region I of the substrate 100 adjacent to a second region II of the substrate 100, and a plurality of first vertical gate electrodes 580 may be arranged in each of the second direction D2 and the third direction D3. In an exemplary embodiment, the first vertical gate electrodes 580 may be formed at each of the opposing lateral sides of the second partition pattern 440 in the third direction D3 in each memory group. Figure 15 In an exemplary embodiment, seven first vertical gate electrodes 580 are shown at each of the relative lateral sides of the second partition pattern 440 in each memory bank in the third direction D3. However, the exemplary embodiments of the inventive concept are not limited thereto, and in other exemplary embodiments, the number of the first vertical gate electrodes 580 and their positioning at each of the relative lateral sides of the second partition pattern 440 may vary.

[0102] In an exemplary embodiment, in a plan view (e.g., in a plane defined by a second direction D2 and a third direction D3), each first vertical gate electrode 580 may have a circular, elliptical, or regular polygonal shape. However, exemplary embodiments of the inventive concept are not limited thereto.

[0103] In an exemplary embodiment, a first vertical gate electrode 580, a fifth insulating pattern 570 covering the sidewalls of the first vertical gate electrode 580, and portions of the second gate electrode 754 at multiple horizontal levels surrounding the fifth insulating pattern 570 can form a first switching transistor 600. This portion of the second gate electrode 754 can serve as a channel for the first switching transistor 600 and is therefore referred to as a second channel. For example, the first switching transistor 600 may include a first vertical gate electrode 580, a fifth insulating pattern 570 surrounding the first vertical gate electrode 580 and serving as a gate insulating pattern for the first vertical gate electrode 580, and a second channel 590 surrounding the gate insulating pattern and serving as a channel. Compared to a first channel 410 extending in a first direction D1, the second channel 590 may be referred to as a horizontal channel, and each of the second channel 590, third channel 595, fourth channel 597, and fifth channel 790, which will be described later, may also be referred to as a horizontal channel. The second gate electrode 754 and the resulting horizontal channel may comprise polysilicon doped with impurities.

[0104] In an exemplary embodiment, a second transistor serving as a transfer transistor may be formed under each memory block on a first region I of substrate 100. The transfer transistor may be electrically connected to a plurality of first vertical gate electrodes 580 in each memory block via a thirteenth lower wiring 224. Thus, as many second transistors as there are memory blocks in each shared memory block may be disposed under the shared memory blocks, and each second transistor may selectively apply an electrical signal to a corresponding memory block; the second transistor may be referred to as a memory block select transistor. In the figures, two memory block select transistors are shown under one shared memory block. However, exemplary embodiments of the inventive concept are not limited thereto.

[0105] The electrical signal applied to the second horizontal gate electrode 754, which serves as a word line, can be controlled by the first switching transistor 600 of the corresponding memory block, which includes the first vertical gate electrode 580. The electrical signal is applied to the first switching transistor 600 via the memory block selection transistor.

[0106] Reference Figure 16B In an exemplary embodiment, a filling insulating pattern 243 may also be formed in the portion of the CSP 240 through which the first through-hole 562, the second through-hole 564, the third through-hole 566 and the first vertical gate electrode 580 extend.

[0107] For reference Figure 4 As shown in the exemplary embodiment, a CSP 240 can be formed on the second insulating interlayer 170, and holes can be formed in the regions through which the first through-hole 562, the second through-hole 564, the third through-hole 566, and the first vertical gate electrode 580 extend. An insulating filling pattern 243 can fill the holes. In the exemplary embodiment, the insulating filling pattern 243 may include oxides (such as silicon oxide) or nitrides (such as silicon nitride). However, the exemplary embodiments of the inventive concept are not limited thereto.

[0108] Since the filling insulating pattern 243 has been formed previously, when forming holes for the first through-hole 562, the second through-hole 564, the third through-hole 566 and the first vertical gate electrode 580, an etching process for removing a portion of the CSP240 can be easily performed.

[0109] Reference Figure 18 and Figure 19 In an exemplary embodiment, an eighth insulating layer 610 may be formed on the seventh insulating layer 540, the first through-hole 562, the second through-hole 564, the third through-hole 566 and the first vertical gate electrode 580, and a fourth upper contact plug 622, a fifth upper contact plug 624, a sixth upper contact plug, a seventh upper contact plug 630 and an eighth upper contact plug 640 may be formed.

[0110] The fourth upper contact plug 622, the fifth upper contact plug 624, and the sixth upper contact plug can extend through the seventh insulating layer 540 and the eighth insulating layer 610 to contact the first upper contact plug 510, the second upper contact plug 520, and the third upper contact plug 530, respectively. The seventh upper contact plug 630 can extend through the eighth insulating layer 610 to contact one of the corresponding ones of the first through hole 562, the second through hole 564, and the third through hole 566. The eighth upper contact plug 640 can extend through the fifth insulating layer 450, the sixth insulating layer 500, the seventh insulating layer 540, and the eighth insulating layer 610 to contact the covering pattern 430.

[0111] A ninth insulating layer 650 can be formed on the eighth insulating layer 610, the fourth upper contact plug 622, the fifth upper contact plug 624, the sixth upper contact plug, the seventh upper contact plug 630, and the eighth upper contact plug 640, and a first upper wiring 662, a second upper wiring 664, a third upper wiring 666, a fourth upper wiring 670, and a fifth upper wiring 675 can be formed through the ninth insulating layer 650. For example, as Figure 19 In the exemplary embodiment shown, the first upper wiring 662, the second upper wiring 664, the third upper wiring 666, the fourth upper wiring 670 and the fifth upper wiring 675 can extend through the entire thickness of the ninth insulating interlayer 650 in the first direction D1.

[0112] The first upper wiring 662 can contact the fourth upper contact plug 622 and the seventh upper contact plug 630 on the first through hole 562; the second upper wiring 664 can contact the fifth upper contact plug 624 and the seventh upper contact plug 630 on the second through hole 564; and the third upper wiring 666 can contact the sixth upper contact plug and the seventh upper contact plug 630 on the third through hole 566.

[0113] Two adjacent eighth upper contact plugs 640 on the third direction D3 can form a pair and can be electrically connected to each other via a corresponding one of the fourth upper wiring 670 and the fifth upper wiring 675. The fourth upper wiring 670 and the fifth upper wiring 675 can be arranged in a zigzag pattern along the third direction D3.

[0114] Reference Figure 20 , Figure 21A , Figure 22 and Figure 23 In an exemplary embodiment, a tenth insulating layer 680 may be formed on the ninth insulating layer 650, the first upper wiring 662, the second upper wiring 664, the third upper wiring 666, the fourth upper wiring 670, and the fifth upper wiring 675, and a first upper via 690 and a second upper via may be formed through it.

[0115] like Figure 22 In the exemplary embodiment, the first upper via 690 can contact the fourth upper wiring 670, and the second upper via can contact the fifth upper wiring 675.

[0116] An eleventh insulating layer 700 may be formed on the tenth insulating layer 680, the first upper via 690, and the second upper via. A sixth upper wiring 710 extending through the eleventh insulating layer 700 to contact the first upper via 690 and a seventh upper wiring 715 extending through the eleventh insulating layer 700 to contact the second upper via may also be formed. For example, the sixth upper wiring 710 and the seventh upper wiring 715 may extend through the entire thickness of the eleventh insulating layer 700 in the first direction D1.

[0117] In an exemplary embodiment, each of the sixth upper wiring 710 and the seventh upper wiring 715 may extend on the third-party direction D3 and may be connected to a plurality of first upper vias 690 and a plurality of second upper vias, respectively. In an exemplary embodiment, the sixth upper wiring 710 and the seventh upper wiring 715 may be used as bit lines of a vertical memory device.

[0118] Vertical memory devices can be manufactured using the above-described process.

[0119] Reference Figure 21B An exemplary embodiment, as shown in reference Figure 16B As shown, a filling insulating pattern 243 can also be formed in the portion of CSP 240 through which the first through-hole 562, the second through-hole 564, the third through-hole 566 and the first vertical gate electrode 580 extend.

[0120] Vertical memory devices can have the following structural characteristics.

[0121] The vertical memory device may include a first transistor disposed on a second region II of substrate 100, a second transistor disposed on a first region I of substrate 100, a lower circuit pattern electrically connected to the first and second transistors on substrate 100, a CSP 240 disposed on the lower circuit pattern, and a first horizontal gate electrode 752, a second horizontal gate electrode 754, and a third horizontal gate electrode 756 spaced apart from each other in a first direction D1 and disposed on the CSP 240. Each of the first horizontal gate electrode 752, the second horizontal gate electrode 754, and the third horizontal gate electrode 756 may extend along a second direction D2 in the first region I and the second region II of substrate 100. A first channel 410 extends through the first horizontal gate electrode 752, the second horizontal gate electrode 754, and the third horizontal gate electrode 756 in the first direction D1 in the first region I of substrate 100. Charge storage structures 400 are respectively disposed on the sidewalls of the first channel 410. The first vertical gate electrode 580 extends in a first direction D1 through the first horizontal gate electrode 752, the second horizontal gate electrode 754, and the third horizontal gate electrode 756, but is electrically insulated from the first horizontal gate electrode 752, the second horizontal gate electrode 754, and the third horizontal gate electrode 756, and is electrically insulated from the first horizontal channel (i.e., the second channel 590) at the portion of each second horizontal gate electrode 754 adjacent to the first vertical gate electrode 580. The vertical memory device may further include a first switching transistor 600 for controlling an electrical signal applied to the second horizontal gate electrode 754 on a first region I of the substrate 100, a first upper contact plug 510, a second upper contact plug 520, and a third upper contact plug 530 respectively electrically connected to the first horizontal gate electrode 752, the second horizontal gate electrode 754, and the third horizontal gate electrode 756 on a second region I of the substrate 100, and on the second region I of the substrate 100. The first through-hole 562, second through-hole 564, and third through-hole 566 on the first upper contact plug 510, the second upper contact plug 520, and the third upper contact plug 530, respectively, are electrically connected to the first through-hole 562, the second through-hole 564, and the third through-hole 566. These through-holes can extend (e.g., in the first direction D1) through the first horizontal gate electrode 752, the second horizontal gate electrode 754, and the third horizontal gate electrode 756, but can be electrically insulated from them. The first through-hole 562, the second through-hole 564, and the third through-hole 566 can be electrically connected to the corresponding first transistor, and the first switching transistor 600 can be electrically connected to the corresponding second transistor.

[0122] As shown above, in a vertical memory device, word lines included in multiple memory blocks can be shared to form a shared memory block. Therefore, the number of upper circuit patterns for applying electrical signals to the shared word lines on the second region II of the substrate 100 (e.g., the second upper contact plug 520, the fifth upper contact plug 624, the seventh upper contact plug 630, the second upper wiring 664, and the second through via 564), the number of first transistors electrically connected to the upper circuit patterns below the upper circuit patterns, and the number of lower circuit patterns electrically connected to the first transistors can be reduced. Therefore, the area of ​​the second region II of the substrate 100 can be reduced, and the layout freedom of the upper circuit patterns on the second region II of the substrate 100 can be increased.

[0123] A first switching transistor 600 electrically connected to each word line and a second transistor electrically connected to the first switching transistor 600 serve as transmission transistors. Therefore, the word lines of each memory block included in a shared memory block can be operated independently. For example, a memory block select transistor can also be formed. The first switching transistor 600 can be formed on a portion of a first region I of substrate 100 adjacent to a second region II of substrate 100, without increasing the area of ​​the second region II of substrate 100. Additionally, the first switching transistor 600 may include a first vertical gate electrode 580, a fifth insulating pattern 570 surrounding the first vertical gate electrode 580, and a second channel 590 surrounding the fifth insulating pattern 570. Therefore, the area of ​​the vertical memory device has a relatively small increase.

[0124] For example, the second channel 590 of the first switching transistor 600 can use a portion of the second gate electrode 754, thus avoiding additional processes for forming the second channel 590. However, in an exemplary embodiment where a portion of the second gate electrode 754 is used as the second channel 590, the second channel 590 can be formed to have a lower impurity concentration than other portions of the second gate electrode 754, if necessary. In an exemplary embodiment where the remaining portions of the second gate electrode 754 (i.e., other portions) have a higher impurity concentration than the second channel 590, the other portions can have relatively low resistance.

[0125] For reference Figure 4 As shown in the exemplary embodiment, when the first insulating layer 310 and the first gate electrode layer 320 are alternately and repeatedly stacked on the support layer 300, the impurity concentration in the region where the second channel 590 will be formed and the impurity concentration in the region where other portions of the second gate electrode 754 will be formed can be controlled, thereby achieving different impurity concentrations.

[0126] In an exemplary embodiment, a first transistor for transmitting electrical signals applied by each driving circuit to a word line via a lower circuit pattern and an upper circuit pattern, and / or a second transistor for transmitting electrical signals applied by each driving circuit to a first switching transistor 600 via a lower circuit pattern, may not be formed. In this exemplary embodiment, electrical signals may be directly transmitted from each driving circuit to a word line or a first switching transistor 600 via a lower circuit pattern and / or an upper circuit pattern.

[0127] In an exemplary embodiment, the vertical memory device may not have a COP structure. In this exemplary embodiment, the peripheral circuit pattern, which replaces the lower circuit pattern, may be formed on a third region of the substrate 100. For example, the first to third transistors, as well as the lower contact plugs, lower vias, and lower wirings electrically connected to the first to third transistors, may not be formed under the CSP 240, but may be formed on the third region of the substrate 100 to be electrically connected to the upper circuit pattern. However, even in this exemplary embodiment, the number of the first and second transistors and the circuit patterns electrically connected to the first and second transistors can be reduced to increase the integration density of the vertical memory device.

[0128] In the following text, reference will be made to Figure 24 The comparative embodiments shown in the figure specifically illustrate the decrease in area due to the reduction in the number of first transistors and the increase in area due to the addition of second transistors.

[0129] Figure 24 This is a plan view illustrating a vertical memory device according to a comparative embodiment, which may correspond to Figure 18 .

[0130] Reference Figure 24 In a vertical memory device according to a comparative embodiment, each memory block includes a word line in each horizontal direction, and two memory blocks that do not share a word line are disposed on a third direction D3. For example, a third separator pattern 490 instead of a fourth separator pattern 495 may be formed between memory blocks that are completely spaced apart from each other and do not share a word line. The vertical memory device does not include a first switching transistor 600 and a second transistor connected to the first switching transistor 600.

[0131] exist Figure 24 In the vertical memory device of the comparative embodiment, two word lines are formed at each level in the two memory blocks, so two upper circuit patterns can be formed to connect to the two memory blocks respectively, and two first transistors used as transmission transistors can be formed under the two memory blocks. Therefore, if each memory block includes word lines at 100 levels, then 200 first transistors are formed on the second region II of the substrate 100 in the two memory blocks.

[0132] Reference Figure 18 In a vertical memory device according to an exemplary embodiment of the present invention, two word lines are formed at each level in two memory blocks. However, these two word lines can be connected to each other and shared by the two memory blocks, which can form a shared memory block. Therefore, only one word line can be formed at each level. Thus, only one upper circuit pattern can be formed to connect to the two memory blocks, and only one first transistor can be formed under the two memory blocks. As a result, if each memory block includes word lines at 100 levels respectively, then 100 first transistors are formed on the second region II of the substrate 100 in the shared memory block.

[0133] In addition, Figure 18 In the exemplary embodiment shown, a second transistor, serving as a transfer transistor for independently operating word lines in an on-off manner in each memory block, can be formed in each memory block. Therefore, two second transistors can be formed on a first region I of the substrate 100.

[0134] In a vertical memory device according to an exemplary embodiment of the present invention, 102 transistors are required to independently operate the word lines in each memory block, which is significantly fewer than the 200 transistors required to independently operate the word lines in each memory block in a vertical memory device according to a comparative embodiment. Furthermore, if the shared memory block comprises more than two memory blocks, the number of transistors required in the shared memory block can be greatly reduced.

[0135] Figure 25 and Figure 26 This is a plan view illustrating an exemplary embodiment of a vertical memory device according to the present invention, which may correspond to Figure 15 .

[0136] Reference Figure 25 In an exemplary embodiment, the first vertical gate electrode 580 of the first switching transistor 600 may have a stripe extending in the second direction D2 in a plan view (e.g., in a plane defined by the second direction D2 and the third direction D3), and the plurality of first vertical gate electrodes 580 may be spaced apart from each other in the third direction D3.

[0137] Optionally, refer to Figure 26In an exemplary embodiment, the first vertical gate electrode 580 of the first switching transistor 600 may have a stripe extending in the third direction D3 in a plan view (e.g., in a plane defined by a second direction D2 and a third direction D3), and a plurality of first vertical gate electrodes 580 may be spaced apart from each other in the second direction D2. In an exemplary embodiment, the first vertical gate electrodes 580 may be arranged in a zigzag pattern along the second direction D2, wherein the lateral ends of adjacent first vertical gate electrodes 580 in the third direction D3 are offset from each other.

[0138] However, exemplary embodiments of the present invention are not limited thereto; the first vertical gate electrode 580 may be used in... Figure 15 , Figure 25 and Figure 26 The exemplary embodiments shown in the examples are arranged in combination of two or more of the arrangements.

[0139] Figures 27 to 29 These are plan views and cross-sectional views illustrating an exemplary embodiment of a vertical memory device according to the present invention. Figure 27 It's a floor plan. Figure 28 It is along Figure 27 The sectional view taken by line A-A'. Figure 29 It is along Figure 27 A sectional view taken by line D-D'.

[0140] Reference Figures 27 to 29 In an exemplary embodiment, a shared memory block that shares word lines included in two memory blocks can also share SSL at each level of the two memory blocks.

[0141] Therefore, with Figure 20 Compared to the exemplary embodiment, which completely separates the second separation pattern 440 in each of the third gate electrodes 756 at the two levels above, which are respectively used as SSL, on the third-party D3, Figure 27 The second separation pattern 440 of the exemplary embodiment may extend only along the second direction D2 in the first region I of the substrate 100, so that each of the third gate electrodes 756 at the two horizontal positions above may not be separated on the third direction D3.

[0142] In an exemplary embodiment, the second separating pattern 440 may extend outward from the central portion of the first region I of the substrate 100 along the second direction D2, and the end of the second separating pattern 440 in the second direction D2 may be coplanar with the end of the first region I of the substrate 100 in the second direction D2 (such as the first end of the first switching transistor 600 in the second direction D2, away from the central portion of the first region I of the substrate 100). Alternatively, the end of the second separating pattern 440 in the second direction D2 may be aligned with the second end of the first switching transistor 600 in the second direction D2, near the central portion of the first region I of the substrate 100. However, exemplary embodiments of the present invention are not limited thereto, and the end of the second separating pattern 440 may be located at any position between the first end and the second end. Furthermore, in an exemplary embodiment, the second separating pattern 440 may not be formed.

[0143] The first connecting portion 990 of the molded part in the shared memory block can extend upward in the first direction D1 to the boundary region between the uppermost step and the second highest step, and the first dividing pattern 330 can overlap with the first connecting portion 990 in the first direction D1.

[0144] Therefore, in Figure 27 In the shared memory block shown in the exemplary embodiment, not only word lines at each level but also SSLs at each level can be shared without being separated. Therefore, a first upper contact plug 510, a fourth upper contact plug 622, a first upper wiring 662, a first through-hole 562, and a first transistor can be formed on the second region II of the substrate 100. Therefore, when combined with... Figure 20 When compared to the eight SSLs at each level shown in the exemplary embodiment and the upper circuit pattern electrically connected to the eight SSLs, the area of ​​the second region II of the substrate 100 can be significantly reduced.

[0145] A second switching transistor 605 may also be formed close to the first switching transistor 600 on the first region I of the substrate 100. The second switching transistor 605 may be adjacent to the first switching transistor 600 in the second direction D2. The second switching transistor 605 may include a second vertical gate electrode 585, a sixth insulating pattern 575 surrounding the second vertical gate electrode 585, and a third channel 595 surrounding the sixth insulating pattern 575. Just as the second channel 590 of the first switching transistor 600 is part of the second gate electrode 754, the third channel 595 of the second switching transistor 605 may also be part of the third gate electrode 756. In an exemplary embodiment, the third channel 595 may have an impurity concentration different from that of other portions of the third gate electrode 756. For example, in an exemplary embodiment, the third channel 595 may have a lower impurity concentration than other portions of the third gate electrode 756. In an exemplary embodiment, the second switching transistor 605 may (e.g., in the second direction D2) be disposed between the first switching transistor 600 and the first channel 410.

[0146] In an exemplary embodiment, a fourth transistor, which serves as a transmission transistor, may be formed below the second switching transistor 605 to be electrically connected to the second switching transistor 605.

[0147] like Figure 28 In an exemplary embodiment, the fourth transistor may include a fourth lower gate structure 148 at the upper portion of the active region 101 and a seventh impurity region 108 and an eighth impurity region 109 serving as the source and drain, respectively. The fourth lower gate structure 148 may include a fourth gate insulating pattern 128 and a fourth lower gate electrode 138 sequentially stacked on the substrate 100 (e.g., in the first direction D1).

[0148] A tenth lower contact plug 802 and an eleventh lower contact plug 804, extending through the first insulating interlayer 150 in the first direction D1 to contact the seventh impurity region 108 and the eighth impurity region 109, respectively, and a twelfth lower contact plug 806, contacting the fourth lower gate electrode 138, can be formed. Additionally, a fifteenth lower wiring 812, a sixteenth lower wiring 814, and a seventeenth lower wiring 816 can be formed on the tenth lower contact plug 802, the eleventh lower contact plug 804, and the twelfth lower contact plug 806, respectively.

[0149] The seventh lower via 822, the eighteenth lower wiring 832, the eighth lower via 842, and the nineteenth lower wiring 852 can be (e.g., in the first direction D1) sequentially stacked on the fifteenth lower wiring 812. The fourth lower gate structure 148 of the fourth transistor can be electrically connected to the drive circuit via the twelfth lower contact plug 806 and the seventeenth lower wiring 816, and the eighth impurity region 109 of the fourth transistor can be electrically connected to the drive circuit via the eleventh lower contact plug 804 and the sixteenth lower wiring 814.

[0150] Since the shared memory block shares an SSL at each level, eight fourth transistors can be connected to the shared SSL to apply electrical signals, allowing the eight parts of the shared SSL to operate independently. Therefore, the fourth transistors can be called SSL selection transistors. However, the shared SSL can be formed at two levels, so the two first transistors and eight fourth transistors can form a total of ten transistors, which is less than sixteen transistors. Sixteen transistors are... Figure 20 The exemplary embodiment shows the number of transistors when the shared memory block does not share SSL.

[0151] Figure 30 It is a vertical memory device according to an exemplary embodiment of the present invention.

[0152] Reference Figure 30 An exemplary embodiment, with Figure 29 The layout of the exemplary embodiments is different (in Figure 29 In the layout of the exemplary embodiment, the first channel 410, the second switching transistor 605, and the first switching transistor 600 are arranged in this order from the center portion of the first region I of the substrate 100 toward the end of the first region I of the substrate 100 in the second direction D2. Figure 30 An exemplary embodiment of the layout has a first channel 410, a first switching transistor 600, and a second switching transistor 605 arranged in a second direction D2 from the center portion of a first region I of the substrate 100 in the order of a first channel 410, a first switching transistor 600, and a second switching transistor 605.

[0153] The second transistor and the fourth transistor can be formed under the first switching transistor 600 and the second switching transistor 605, respectively.

[0154] Figure 31 , Figure 32A , Figure 32B , Figure 33A and Figure 33B These are plan views and cross-sectional views illustrating an exemplary embodiment of a vertical memory device according to the present invention. Figure 31 It's a floor plan. Figure 32A and Figure 32B It is along Figure 31 The sectional view taken by line A-A'. Figure 33A and Figure 33B They are along Figure 31 A sectional view taken from lines D-D' and C-C'.

[0155] Reference Figure 31 , Figure 32A and Figure 33A In an exemplary embodiment, a shared memory block that shares word lines included in two memory blocks can also share GSLs therein.

[0156] Therefore, with Figure 20 Compared to the exemplary embodiment, the first separation pattern 330 may not be formed. The four GSLs in the shared memory block may be connected to each other via the connection pattern of the gate electrodes in the first connection portion 990 of the molding.

[0157] For example, such as Figure 31 In the exemplary embodiment shown, the shared memory block may include a first gate electrode 752 serving as a GSL, and an upper circuit pattern, a lower circuit pattern, and a first transistor may be connected to the GSL. Additionally, each of the fourth transistors in the shared memory block may be electrically connected to a third switching transistor to selectively apply an electrical signal to the four sections of the GSL. Therefore, the four sections of the GSL can operate independently and can thus be referred to as GSL select transistors. For example, the fourth transistors may serve as both an SSL select transistor and a GSL select transistor. However, for example, four fourth transistors may be formed in each memory block, and the two sections of the GSL may operate independently in each memory block. Therefore, in the exemplary embodiment, two fourth transistors may form a pair, and the two pairs of fourth transistors may apply an electrical signal to the third switching transistor.

[0158] like Figure 32A In the exemplary embodiment shown, the third switching transistor may include a second vertical gate electrode 585, a sixth insulating pattern 575 surrounding the second vertical gate electrode 585, and a fourth channel 597 surrounding the sixth insulating pattern 575. The fourth channel 597 may have an impurity concentration different from that of other portions of the first gate electrode 752. For example, in the exemplary embodiment, the impurity concentration of the fourth channel 597 may be lower than that of other portions of the first gate electrode 752.

[0159] In another exemplary embodiment, reference is made to Figure 31 , Figure 32B and Figure 33BThe second transistor, instead of the fourth transistor, can be used as both a block select transistor and a GSL select transistor. The third switching transistor may include a first vertical gate electrode 580, a fifth insulating pattern 570 surrounding the first vertical gate electrode 580, and a fourth channel 597 surrounding the fifth insulating pattern 570.

[0160] As shown above, the two parts of GSL can operate independently within each memory block. Therefore, with Figures 1 to 23 Compared to the exemplary embodiment, two second transistors can be formed in each memory block to apply an electrical signal to a third switching transistor. The two second transistors in each memory block can form a pair and can apply an electrical signal to a first switching transistor 600.

[0161] Figure 34 , Figure 35A , Figure 35B , Figure 36A , Figure 36B and Figure 37 These are plan views and cross-sectional views illustrating an exemplary embodiment of a vertical memory device according to the present invention. Figure 34 Is with Figure 15 The corresponding floor plan, Figure 35A , Figure 35B , Figure 36A , Figure 36B and Figure 37 It is along Figure 34 A sectional view taken from line E-E'.

[0162] Reference Figure 34 and Figure 35A In an exemplary embodiment, each of the first vertical gate electrodes 580 may have sloping sidewalls, and the width of each of the first vertical gate electrodes 580 (e.g., the length in the third direction D3) may gradually decrease from its top toward its bottom.

[0163] Therefore, the distance between adjacent first vertical gate electrodes 580 can increase from their tops toward their bottoms. For example, as Figure 35A In the exemplary embodiment shown, the first width W1 of the first portion of the second channel 590 at the uppermost horizontal level of the second gate electrode 754 between adjacent first vertical gate electrodes 580 can be smaller than the second width W2 of the second portion of the second channel 590 at the lowermost horizontal level of the second gate electrode 754 between adjacent first vertical gate electrodes 580. Therefore, when the current is along the horizontal direction (e.g., along...), Figure 34When the line F-F' direction shown in the exemplary embodiment flows in the second channel 590, the resistance of the portion of the second channel 590 at the uppermost horizontal level of the second gate electrode 754 may be greater than the resistance of the portion of the second channel 590 at the lowermost horizontal level of the second gate electrode 754.

[0164] Therefore, in order to reduce the resistance difference between the upper and lower levels of the second channel 590 to maintain the constant electrical characteristics of the second channel 590, the impurity concentration of the second channel 590 at each level, including the polysilicon doped with n-type impurities, can be adjusted. For example, as per [reference to...] Figure 4 As shown in the exemplary embodiment, when the first insulating layer 310 and the first gate electrode layer 320 are alternately and repeatedly stacked on the support layer 300, the first gate electrode layer 320 can be deposited such that the impurity concentration of the first gate electrode layer 320 increases from the lowest level to the highest level. Therefore, even though the second channel 590 at the upper level has a relatively small area and a reduced width between adjacent first vertical gate electrodes 580, the second channel 590 at the upper level can have a relatively high impurity concentration to have a resistance similar to that of the second channel 590 at the lower level.

[0165] Reference Figure 35B In an exemplary embodiment, each of the first vertical gate electrodes 580 may include a lower portion, a central portion, and an upper portion that are sequentially stacked (e.g., in a first direction D1). The width of the central portion (e.g., its length in a third direction D3) may be greater than the width of the upper portion. The width of the upper portion may be greater than the width of the lower portion.

[0166] In an exemplary embodiment, the impurity concentration of one second gate electrode 754 at the center level can be greater than the impurity concentration of one second gate electrode 754 at the upper level. The impurity concentration of the second gate electrode 754 at the upper level can be greater than the impurity concentration of one second gate electrode 754 at the lower level. Therefore, even if one second channel 590 at the center level (as part of one second gate electrode 754 at the center level) in the second channel 590 has a relatively small area, it can still have a relatively high impurity concentration to have a resistance similar to that of either the second channel 590 at the upper level or the second channel 590 at the lower level.

[0167] like Figure 35A and Figure 35BIn the exemplary embodiment shown, the width of the first vertical gate electrode 580 (e.g., the length in the third direction D3) may vary along the first direction D1, and the impurity concentration of the second gate electrode 754 (e.g., the second channel 590) that is at the same level as the first portion of the first vertical gate electrode 580 with a relatively large width may be greater than the impurity concentration of the second gate electrode 754 (e.g., the second channel 590) that is at the same level as the second portion of the first vertical gate electrode 580 with a relatively small width.

[0168] Reference Figure 36A In an exemplary embodiment, the first vertical gate electrode 580 may have a first protrusion 580a protruding from the sidewall of the first vertical gate electrode 580 facing the first gate electrode 752, the second gate electrode 754, and the third gate electrode 756 in a horizontal direction (e.g., in the third direction D3). Therefore, the sidewall of the first vertical gate electrode 580 may have a non-flat surface, wherein the first protrusion 580a protrudes toward the first gate electrode 752, the second gate electrode 754, and the third gate electrode 756, but the first vertical gate electrode 580 does not protrude toward the first insulating pattern 315.

[0169] Such as about Figures 15 to 17 As shown in the exemplary embodiment, after forming the hole for the first vertical gate electrode 580, a wet etching process may be performed, for example, to remove the portions of the first gate electrode 752, the second gate electrode 754, and the third gate electrode 756 exposed by the hole. The portions of the support layer 300, channel interconnect pattern 480, and CSP240 that may include doped polysilicon exposed by the hole may also be removed.

[0170] The fifth insulating pattern 570 can be formed on the sidewall of the hole, and the first vertical gate electrode 580 can be formed to fill the rest of the hole, so that the first protrusion 580a protrudes towards the second channel 590 in the horizontal direction.

[0171] Since each of the first vertical gate electrodes 580 includes a first protrusion 580a, the control of the first vertical gate electrode 580 over the portion of the second channel 590 between the first vertical gate electrodes 580 can be improved, and the on-off characteristics of the first switching transistor 600 can be improved.

[0172] Optionally, refer to Figure 36BIn an exemplary embodiment, each of the first vertical gate electrodes 580 may include a second protrusion 580b that protrudes toward the first insulating pattern 315 from a sidewall of the first vertical gate electrode 580 facing the first insulating pattern 315 in a horizontal direction (e.g., in the third direction D3). Therefore, the sidewall of the first vertical gate electrode 580 may have an uneven surface, wherein the second protrusion 580b protrudes toward the first insulating pattern 315, but the first vertical gate electrode 580 does not protrude toward the first gate electrode 752, the second gate electrode 754, and the third gate electrode 756.

[0173] The second protrusion 580b can be formed by forming a hole for the first vertical gate electrode 580, for example, by performing a wet etching process to partially remove the portion of the first insulating pattern 315 exposed by the hole, and can also remove the portions of the fourth insulating interlayer 350, the fifth insulating interlayer 450, the sixth insulating interlayer 500 and the seventh insulating interlayer 540 exposed by the hole.

[0174] Reference Figure 37 In an exemplary embodiment, the portion of the second channel 590 adjacent to each of the first vertical gate electrodes 580 (e.g., on the third direction D3) may have a low-doped portion 590a having a relatively low doping concentration. Therefore, the portion of the second channel 590 adjacent to each of the first vertical gate electrodes 580 may have a lower doping concentration than the portion of the second channel 590 distant from each of the first vertical gate electrodes 580.

[0175] Such as about Figures 15 to 17 As shown in the exemplary embodiment, after forming the hole for the first vertical gate electrode 580, impurities having a conductivity type opposite to that of the impurities doped into the first gate electrode 752, the second gate electrode 754, and the third gate electrode 756 (e.g., p-type impurities) can be doped into portions of the first gate electrode 752, the second gate electrode 754, and the third gate electrode 756 adjacent to the hole. Therefore, a low-impurity-doped portion 590a having an impurity doping concentration lower than that of the n-type impurities in each of the first gate electrode 752, the second gate electrode 754, and the third gate electrode 756 can be formed (e.g., on the third direction D3) in the portion of the second channel 590 near the first vertical gate electrode 580.

[0176] As a result, the width of the depletion region of the second channel 590 near the first vertical gate electrode 580 can be increased, and the on-off characteristics of the first switching transistor 600 can be improved.

[0177] Figure 38A and Figure 38BThis is a cross-sectional view illustrating an exemplary embodiment of a vertical memory device according to the present invention. Figure 38B yes Figure 38A An enlarged cross-sectional view of region Z.

[0178] Reference Figure 38A and Figure 38B In an exemplary embodiment, the charge storage structure and the channel in the channel hole can have the same characteristics as... Figure 7A and Figure 7B The exemplary embodiments of the structure and / or shape are different from the structure and / or shape.

[0179] For example, the gate insulating structure 375, the floating gate 385, and the tunnel insulating pattern 390 can be sequentially stacked in a horizontal direction on the sidewalls of the channel via between each of the vertical channel and the horizontal gate electrode. Each of the gate insulating structure 375, the floating gate 385, and the tunnel insulating pattern 390 can have a cylindrical shape. In addition, a first channel 410 having a cup-shaped shape can be formed on the inner sidewall of the tunnel insulating pattern 390, and the internal space formed by the inner wall of the first channel 410 can be filled with a filler pattern 420.

[0180] In an exemplary embodiment, the gate insulating structure 375 may include a first nitride layer 372, a first oxide layer 374, a second nitride layer 376, and a second oxide layer 378 sequentially stacked from the sidewalls of the channel via. However, the exemplary embodiments of the present invention are not limited thereto, and the gate insulating structure 375 may include any number of oxide and nitride layers stacked alternately. The floating gate 385 may include doped polysilicon, etc. The first channel 410 may directly contact the upper surface of the CSP 240 for electrical connection thereto. Therefore, the channel connection pattern 480 and the support layer 300 may not be formed on the CSP 240.

[0181] Insulating spacers can also be formed between CSP 240 and the first gate electrode 752.

[0182] Figures 39 to 49 These are plan views and cross-sectional views illustrating a method for manufacturing a vertical memory device according to an exemplary embodiment of the present invention. Figure 40 , Figure 41 , Figure 44 , Figure 45 and Figure 48 It's a floor plan. Figure 39 , Figure 42 , Figure 43 , Figure 46 , Figure 47 and Figure 49 It is a sectional view. Figure 39 , Figure 42 , Figure 46 and Figure 49These are sectional views taken along line A-A' of the corresponding plan view. Figure 43 and Figure 47 These are sectional views taken along line B-B' of the corresponding plan view.

[0183] This method may include with Figures 1 to 23 The exemplary embodiments thereof are substantially the same or similar in process, therefore, for ease of explanation, repeated descriptions thereof are omitted here.

[0184] Reference Figure 39 An exemplary embodiment can perform with Figures 1 to 4 The process is similar to that shown in the diagram. However, a fourth sacrificial layer 760, replacing the first gate electrode layer 320, can be formed on the support layer 300. The fourth sacrificial layer 760 can be stacked alternately and repeatedly with the first insulating layer 310 in the first direction D1. In an exemplary embodiment, the fourth sacrificial layer 760 may include a material that has etch selectivity relative to the first insulating layer 310. For example, the fourth sacrificial layer 760 may be a nitride such as silicon nitride.

[0185] Reference Figure 40 An exemplary embodiment can perform with Figures 5 to 11 The process is similar to that of the exemplary embodiment. However, each of the second opening 460 and the third opening 465 may be partially discontinuous on the portion of the first region I of the substrate 100 adjacent to the second region II of the substrate 100, and the second connecting portion 995 may be formed in the molding.

[0186] Therefore, each of the first insulating layer 310 and the fourth sacrificial layer 760 may not be completely separated from each of the second opening 460 and the third opening 465 on the third direction D3. Additionally, the portion of the sacrificial layer structure 290 below the second connecting portion 995 of the molded part may not be removed and may be retained.

[0187] Reference Figures 41 to 43 In an exemplary embodiment, portions of the fourth sacrificial layer 760 exposed by the second opening 460 and the third opening 465 may be removed to form a second gap between the first insulating layers 310 at various levels, and a portion of the outer wall of the charge storage structure 400 (e.g., the outer wall of the first blocking pattern 370) may be exposed by the second gap.

[0188] In an exemplary embodiment, the fourth sacrificial layer 760 can be removed by a wet etching process using phosphoric acid (H3PO4) or sulfuric acid (H2SO4). However, exemplary embodiments of the present invention are not limited thereto.

[0189] During the wet etching process, the portion of the fourth sacrificial layer 760 adjacent to the second connection portion 995 of the molded part (such as an insulating structure) may not be removed and may be retained.

[0190] A second barrier layer 770 may be formed on the exposed outer wall of the charge storage structure 400, the inner wall of the second gap, the surface of the first insulating layer 310, the upper surface of the CSP 240, and the upper surface of the fifth insulating interlayer 450. A second gate electrode layer may be formed on the second barrier layer 770.

[0191] In an exemplary embodiment, the second barrier layer 770 may include a metal oxide (such as aluminum oxide). The second gate electrode layer may include a gate barrier layer and a gate conductive layer sequentially stacked. In an exemplary embodiment, the gate barrier layer may include a metal nitride, and the gate conductive layer may include a metal.

[0192] The second gate electrode layer can be partially removed to form a gate electrode in each of the second gaps. In an exemplary embodiment, the second gate electrode layer can be partially removed by a wet etching process. However, exemplary embodiments of the inventive concept are not limited thereto.

[0193] In an exemplary embodiment, the gate electrode may extend in the second direction D2, and multiple gate electrodes may be stacked in the first direction D1 to be spaced apart from each other, forming a gate electrode structure comprising multiple gate electrodes (e.g., horizontal gate electrodes) sequentially stacked in the first direction D1. However, the gate electrode may be partially cut off by the second connecting portion 995 of the molding part.

[0194] The gate electrode structure may include a first gate electrode 782, a second gate electrode 784, and a third gate electrode 786 sequentially stacked in a first direction D1. In an exemplary embodiment, the first gate electrode 782 may be formed at the lowest horizontal level to provide a word line (GSL), the third gate electrode 786 may be formed at the highest horizontal level and a second horizontal level from above to provide an SSL, and the second gate electrode 784 may be formed at multiple horizontal levels between the first gate electrode 782 and the third gate electrode 786 to provide word lines.

[0195] Reference Figure 44 In an exemplary embodiment, a third separating layer may be formed on the second barrier layer 770 to fill the second opening 460 and the third opening 465, and the third separating layer and the second barrier layer 770 may be planarized until the upper surface of the fifth insulating interlayer 450 is exposed, such that the third separating pattern 490 and the fourth separating pattern 495 may be formed in the second opening 460 and the third opening 465, respectively, and the second barrier layer 770 may be transformed into the second barrier pattern 775 (see reference). Figure 46 ).

[0196] An etching mask that does not cover the area overlapping with the second connection portion 995 of the molded part can be used to etch the fourth insulating interlayer 350, the fifth insulating interlayer 450, the molded part, the support layer 300, and the channel connection pattern 480 to form the fourth opening 492 and the fifth opening 497. The portions of the fourth sacrificial layer 760 exposed by the fourth opening 492 and the fifth opening 497 can be removed to form a third gap between the first insulating layers 310 at various levels. A fifth channel 790 can be formed to fill the third gap.

[0197] During the etching process, the portion of the second blocking pattern 775 exposed by the third gap can also be removed to expose the sidewalls of the first gate electrode 782, the second gate electrode 784, and the third gate electrode 786. Therefore, the fifth channel 790 filling the third gap can contact the sidewalls of each of the first gate electrode 782, the second gate electrode 784, and the third gate electrode 786.

[0198] In an exemplary embodiment, during the etching process, the fourth sacrificial layer 760 between the fourth opening 492 and the fifth opening 497 may be partially retained or completely removed.

[0199] In an exemplary embodiment, the fifth channel 790 may include polysilicon doped with n-type impurities. However, exemplary embodiments of the present invention are not limited thereto.

[0200] Reference Figures 45 to 47 In an exemplary embodiment, a fifth dividing pattern 493 and a sixth dividing pattern 498 may be formed to fill the fourth opening 492 and the fifth opening 497, respectively.

[0201] In an exemplary embodiment, the fifth partition pattern 493 and the sixth partition pattern 498 may include oxides (such as silicon oxide). Thus, apart from the region forming the first connecting portion 990 of the molded part, the third partition pattern 490 and the fifth partition pattern 493 may be connected to each other to extend in the second direction D2, and the fourth partition pattern 495 and the sixth partition pattern 498 may be connected to each other to extend in the second direction D2.

[0202] Reference Figure 48 and Figure 49 An exemplary embodiment can perform with Figures 13 to 23 The processes shown in the exemplary embodiments are substantially the same or similar to those used to manufacture the vertical memory device.

[0203] and Figures 1 to 23 The processes of the exemplary embodiments differ, in reference to Figures 39 to 49In the exemplary embodiment of the vertical memory device, the first gate electrode 782, the second gate electrode 784, and the third gate electrode 786 may comprise metal, and the fifth channel 790 connected to the first gate electrode 782, the second gate electrode 784, and the third gate electrode 786 on the portion of the first region I of the substrate 100 adjacent to the second region II of the substrate 100 may comprise polysilicon doped with n-type impurities. Therefore, not only each of the first gate electrode 782, the second gate electrode 784, and the third gate electrode 786, but also the fifth channel 790 connected to each of the first gate electrode 782, the second gate electrode 784, and the third gate electrode 786 can be used as a horizontal gate electrode. The first gate electrode 782, the second gate electrode 784, and the third gate electrode 786, and the adjacent fifth channel 790, may be referred to as a first portion and a second portion of the horizontal gate electrode, respectively. The first portion and the second portion may be in direct contact with each other, and a blocking pattern is not disposed between the first portion and the second portion. In an exemplary embodiment, the third vertical gate electrode 780, the seventh insulating pattern 776 covering the sidewall of the third vertical gate electrode 780, and the fifth channel 790 may form the fourth switching transistor 602.

[0204] In an exemplary embodiment, in a plan view (e.g., in a plane defined by a second direction D2 and a third direction D3), each of the opposing lateral ends of the fifth channel 790 in the second direction D2 may have a curved line along the third direction D3. Each of the opposing lateral ends of the fifth channel 790 may be recessed at a region adjacent to each of the fifth partition pattern 493 and the sixth partition pattern 498, and may be protruding at a region adjacent to each of the second partition pattern 440. Therefore, the width (e.g., the length in the second direction D2) of the portion of the fifth channel 790 adjacent to each of the fifth partition pattern 493 and the sixth partition pattern 498 may be smaller than the width (e.g., the length in the second direction D2) of the portion of the fifth channel 790 adjacent to the second partition pattern 440. A fourth sacrificial layer 760 may be retained in a region adjacent to the protruding portion of the fifth channel 790. For example, a fourth sacrificial layer 760 comprising silicon nitride, etc., may be partially retained between the first and second portions of the horizontal gate electrode. Therefore, the nitride layer can be disposed between the first and second portions of the horizontal gate electrode.

[0205] Figure 50 This is a plan view illustrating an exemplary embodiment of a vertical memory device according to a concept of the present invention. This vertical memory device can be used with... Figures 39 to 49 The exemplary embodiments of the vertical memory device are similar, so repeated descriptions are omitted here for ease of explanation.

[0206] Reference Figure 50In an exemplary embodiment, in a plan view (e.g., in a plane defined by a second direction D2 and a third direction D3), each of the opposing lateral ends of the fifth channel 790 in the second direction D2 may protrude at a region adjacent to each of the fifth partition pattern 493 and the sixth partition pattern 498, and may be recessed at a region adjacent to each of the second partition pattern 440. Therefore, the width (e.g., the length in the second direction D2) of the portion of the fifth channel 790 adjacent to each of the fifth partition pattern 493 and the sixth partition pattern 498 may be greater than the width in the second direction D2 of the portion of the fifth channel 790 adjacent to the second partition pattern 440. The fourth sacrificial layer 760 may be retained in the region adjacent to the recessed portion of the fifth channel 790.

[0207] In an exemplary embodiment, the vertical memory device may be implemented by the following steps: forming a fourth opening 492 and a fifth opening 497; removing portions of the fourth sacrificial layer 760 exposed by the fourth opening 492 and the fifth opening 497 to form a fifth channel 790; forming a second opening 460 and a third opening 465; and removing portions of the fourth sacrificial layer 760 exposed by the second opening 460 and the third opening 465 to form a first gate electrode 782, a second gate electrode 784, and a third gate electrode 786.

[0208] Figure 51 This is a perspective view showing an exemplary embodiment of a molded part according to the concept of the present invention. Figures 52 to 54 These are plan views and cross-sectional views illustrating an exemplary embodiment of a vertical memory device according to the present invention. Figure 52 It's a floor plan. Figure 53 It is along Figure 52 The sectional view taken by line A-A'. Figure 54 It is along Figure 52 A sectional view taken by line C-C'. Figure 51 yes Figure 1 A diagram of region W.

[0209] For ease of explanation, Figure 51 The first insulating layer 310 is not shown; only the gate electrode pattern formed by patterning the first gate electrode layer 320 is shown. Figure 52 In the diagram, the boundary of the step set in the second direction D2 is shown with a dashed line, while the boundary of the step set in the third direction D3 is shown with alternating long and short dashed lines.

[0210] Reference Figure 51In an exemplary embodiment, the first gate electrode pattern 322, the second gate electrode pattern 324, the third gate electrode pattern 326, the fourth gate electrode pattern 328, and the fifth gate electrode pattern 329 can be formed on the second region II of the substrate 100. The first gate electrode pattern 322, the second gate electrode pattern 324, the third gate electrode pattern 326, the fourth gate electrode pattern 328, and the fifth gate electrode pattern 329 can be formed together with the first gate electrode layer 320 retained on the first region I of the substrate 100 to form a molded part.

[0211] The first gate electrode pattern 322 can be formed on the horizontal surface of the molded part and can be stacked in a stepped shape, wherein the length of the stepped layer in the second direction D2 can gradually increase from the top of the uppermost horizontal surface to the bottommost horizontal surface. Figure 51 In an exemplary embodiment, four first gate electrode patterns 322 are formed at the horizontal position above. However, exemplary embodiments of the inventive concept are not limited thereto.

[0212] The second gate electrode pattern 324 can be formed at the horizontal level below the molded part, and can be stacked in a stepped shape, wherein the length of the stepped layer in each of the second direction D2 and the third direction D3 can gradually increase from the top of the uppermost horizontal level towards the lowermost horizontal level. Figure 51 In an exemplary embodiment, four second gate electrode patterns 324 are formed at the following horizontal position. However, exemplary embodiments of the inventive concept are not limited thereto.

[0213] The third gate electrode pattern 326 may be formed (e.g., in the first direction D1) at multiple horizontal levels (below the first gate electrode pattern 322 and above the second gate electrode pattern 324). A predetermined number of third gate electrode patterns 326 having the same length in the second direction D2 and stacked in the first direction D1 can form a third gate electrode pattern group. The third gate electrode pattern groups may be stacked in a stepped shape, wherein the length of the step layer in the second direction D2 gradually increases from the top of the uppermost level to the bottommost level. In an exemplary embodiment, the length of the ends of the third gate electrode pattern groups not covered by the uppermost third gate electrode pattern groups (such as the steps of each third gate electrode pattern group) in the second direction D2 may be constant. However, the steps of some third gate electrode pattern groups may have a longer length in the second direction D2 than the steps of other third gate electrode pattern groups.

[0214] The fourth gate electrode pattern 328 can be formed at multiple horizontal positions on the uppermost third gate electrode pattern 326, spaced apart from the first gate electrode pattern 322 in the second direction D2. The fourth gate electrode patterns 328 can be stacked in a stepped shape, wherein the length of each step layer in each of the second and third directions D2 and D3 gradually increases from the top of the uppermost horizontal position towards the bottommost horizontal position. The step layers of the fourth gate electrode pattern 328 can extend towards the step layers of the first gate electrode pattern 322 in the second direction D2. Therefore, compared to the other step layers of the fourth gate electrode pattern 328, the lower step of the fourth gate electrode pattern 328 can be spaced apart from the first gate electrode pattern 322 by the shortest distance.

[0215] The fifth gate electrode pattern 329 can be formed at the uppermost level of the third gate electrode pattern 326 in each third gate electrode pattern group, and can be stacked in a stepped shape, wherein the length of the step layer in the third direction D3 can gradually increase from the top of the uppermost level toward the bottommost level.

[0216] In a plan view (e.g., in a plane defined by a first direction D1 and a second direction D2), the relative lateral ends of each of the fifth gate electrode patterns 329 in the third direction D3 may be aligned in the second direction D2 with the relative lateral ends of each of the second gate electrode patterns 324 and the fourth gate electrode patterns 328 in the third direction D3.

[0217] Reference Figures 52 to 54 In an exemplary embodiment, the gate electrode structure of a vertical memory device may have Figure 51 The stepped shape is shown in the exemplary embodiment.

[0218] For example, the third gate electrode 756 may be formed at the two upper horizontal positions within the first gate electrode pattern 322, and the second gate electrode 754 may be formed at the other lower horizontal positions of the first gate electrode pattern 322, and at the upper three horizontal positions of the third gate electrode pattern 326, the fifth gate electrode pattern 329, and the second gate electrode pattern 324. The first gate electrode 752 may be formed at the lowest horizontal position within the second gate electrode pattern 324. However, exemplary embodiments of the present invention are not limited thereto.

[0219] The third dividing pattern 490 can be formed in Figure 51In the exemplary embodiment, each of the opposite lateral ends of region W in the third direction D3 extends in the second direction D2. The fourth dividing pattern 495 may extend in the second direction D2 through the central portion of the fourth gate electrode pattern 328 in the third direction D3. Additionally, the fourth dividing pattern 495 may extend in the second direction D2 through each of the opposite lateral ends of the steps at the second highest level of each of the second gate electrode patterns 324, the fourth gate electrode pattern 328, and the fifth gate electrode pattern 329 in the third direction D3. However, the fourth dividing pattern 495 may be cut off at the region forming the first connecting portion 990 of the molded part.

[0220] Figure 52 An exemplary embodiment illustrates two memory blocks disposed on a third direction D3 sharing word lines at each level via a first connection portion 990 of a molded member to form a shared memory block. However, pads for the word lines other than the two upper word lines in each memory block are disposed on the third direction D3 from the boundary between the two memory blocks to form a stepped shape comprising four steps. The stepped shape of each memory block is symmetrical with respect to the boundary between them.

[0221] Therefore, the four word line pads disposed on the third direction D3 in each of the two memory blocks can be shared by a shared memory block comprising the two memory blocks, which may include the four word line pads, and correspondingly, four on-circuit patterns and four first transistors can be formed. A first switching transistor 600 and two second transistors can be formed on a first region I of the substrate 100, and the two portions of the shared word line at each level can operate independently.

[0222] Each of the second transistors can be electrically connected to all the first switching transistors 600 in each memory block to serve as a memory block select transistor. As a result, eight word lines can be operated independently via word line pads set on the third-direction D3 in the shared memory block.

[0223] In the following, by comparing embodiments, the decrease in area due to the reduction in the number of first transistors and the increase in area due to the addition of second transistors will be specifically explained.

[0224] Figure 55 This is a plan view illustrating a vertical memory device according to a comparative embodiment, which may correspond to Figure 52 .

[0225] Reference Figure 55 In the vertical memory device according to the comparative embodiment, a third partition pattern 490 may be formed between memory blocks, and word lines of the memory blocks may not be shared.

[0226] Therefore, eight upper circuit patterns can be formed corresponding to eight word pads disposed on the third-direction D3, and eight first transistors can be electrically connected to the eight upper circuit patterns. However, second transistors may not be formed.

[0227] If each memory block includes 100 word line pads in addition to the two levels above, 100 upper circuit patterns can be formed, and 100 first transistors, each serving as a transmission transistor, can be formed below the 100 upper circuit patterns. Therefore, in the two memory blocks, 200 first transistors can be formed on the second region II of the substrate 100.

[0228] In reference Figures 52 to 54 In the exemplary embodiment of the vertical memory device, 100 first transistors can be formed on a second region II of substrate 100 in two memory blocks, and two second transistors can be formed on a first region I of substrate 100. Therefore, the total number of transistors required in the two memory blocks is 102. Thus, the vertical memory device according to the exemplary embodiment can provide the same functionality as the vertical memory device according to the comparative embodiment, but with a significantly fewer number of transistors and improved integration.

[0229] In addition, Figures 52 to 54 The length of each step in the third direction D3 shown in the exemplary embodiment can be in Figure 55 The comparative embodiment shows each step having twice the length in the third direction D3. Therefore, Figures 52 to 54 The vertical memory device shown in the exemplary embodiments provides increased layout freedom for the upper circuit pattern.

[0230] Figure 56 and Figure 57 This is a plan view illustrating an exemplary embodiment of a vertical memory device according to a concept conceived in the present invention.

[0231] These vertical memory devices can be used to reference... Figures 27 to 30 An exemplary embodiment shows a second switching transistor 605 added to a reference. Figures 52 to 54 The exemplary embodiments shown illustrate the implementation of a vertical memory device.

[0232] As described above, although the inventive concept has been described with reference to exemplary embodiments, it will be readily understood by those skilled in the art that many modifications may be made in the exemplary embodiments without substantially departing from the novel teachings and advantages of the inventive concept.

Claims

1. A vertical memory device, the vertical memory device comprising: First horizontal gate electrodes are disposed on the substrate and spaced apart from each other in a first direction that is substantially perpendicular to the upper surface of the substrate, wherein each of the first horizontal gate electrodes extends in a second direction that is substantially parallel to the upper surface of the substrate. A vertical channel extends through the first horizontal gate electrode in a first direction; A charge storage structure is disposed between each of the first horizontal gate electrodes and the vertical channel; A first vertical gate electrode extends through a first horizontal gate electrode in a first direction, and the first vertical gate electrode is electrically insulated from the first horizontal gate electrode. A first horizontal channel is disposed at the portion of each of the first horizontal gate electrodes adjacent to the first vertical gate electrode; and The common source plate is mounted on the substrate. The first horizontal gate electrode is disposed on the common source plate, and the first vertical gate electrode extends through the common source plate in the first direction and is electrically insulated from the common source plate.

2. The vertical memory device according to claim 1, wherein, The first horizontal gate electrode and the first horizontal channel comprise polycrystalline silicon doped with impurities.

3. The vertical memory device according to claim 2, wherein: The width of the first vertical gate electrode varies along a first direction and includes a first portion with a relatively large width and a second portion with a relatively small width. The impurity doping concentration of the first horizontal gate electrode, which is at the same level as the first portion of the first vertical gate electrode, is greater than that of the first horizontal gate electrode, which is at the same level as the second portion of the first vertical gate electrode.

4. The vertical memory device according to claim 3, wherein: The width of the first vertical gate electrode decreases from its top towards its bottom; and The impurity doping concentration of the first horizontal gate electrode decreases from the uppermost level to the lowermost level.

5. The vertical memory device according to claim 2, wherein, The portion of each of the first horizontal gate electrodes that forms the first horizontal channel has a lower impurity doping concentration than the remaining portion of the first horizontal gate electrode that does not form the first horizontal channel.

6. The vertical memory device according to claim 2, wherein, The portion of the first horizontal channel near the first vertical gate electrode has a lower impurity doping concentration than the portion of the first horizontal channel farther from the first vertical gate electrode.

7. The vertical memory device according to claim 1, wherein: The first vertical gate electrode has a protrusion on the sidewall facing the first horizontal channel; and The protrusion extends from the sidewall toward the first horizontal channel in a horizontal direction that is substantially parallel to the upper surface of the base.

8. The vertical memory device according to claim 1, wherein, The vertical memory device includes a plurality of first vertical gate electrodes spaced apart from each other in a horizontal direction substantially parallel to the upper surface of the substrate.

9. The vertical memory device according to claim 8, wherein: In a plan view defined by a second direction and a third direction, each of the plurality of first vertical gate electrodes has a strip extending in a third direction, which is substantially parallel to the upper surface of the substrate and substantially perpendicular to the second direction. The first vertical gate electrode is arranged in a Z-shaped pattern along the second direction.

10. The vertical memory device according to any one of claims 1 to 9, wherein the vertical memory device further comprises: A gate insulating pattern is disposed between the first vertical gate electrode and the first horizontal channel, and the gate insulating pattern covers the sidewall of the first vertical gate electrode. The first vertical gate electrode, the gate insulating pattern, and the first horizontal channel form a switching transistor, which is configured to control an electrical signal applied to the first horizontal gate electrode.

11. The vertical memory device according to claim 1, wherein: The base includes a first region and a second region that at least partially surrounds the first region; A first horizontal gate electrode is formed on a first region and a second region of the substrate; The first horizontal gate electrode has pads formed at its lateral ends in the second direction, wherein the pads of the first horizontal gate electrode are stacked in a stepped shape on the second region of the substrate. Vertical channels are provided in the first region of the substrate; and The first vertical gate electrode and the first horizontal channel are disposed on the portion of the first region adjacent to the second region of the substrate in the second direction.

12. The vertical memory device of claim 11, further comprising: The first contact plugs are respectively disposed on the pads of the first horizontal gate electrode, and the first contact plugs are electrically connected to each pad of the first horizontal gate electrode. Through-holes extend through the first horizontal gate electrode in a first direction and are electrically insulated from the first horizontal gate electrode, wherein through-holes are formed on the second region of the substrate at positions corresponding to the first contact plugs; as well as A first transmission transistor is disposed on a second region of the substrate, and the first transmission transistor is electrically connected to a through-hole.

13. The vertical memory device according to claim 12, in, A vertical channel is disposed on the common source plate, and a through-hole extends through the common source plate in the first direction and is electrically insulated from the common source plate. The first transmission transistor is located below the through-hole.

14. The vertical memory device of claim 13, further comprising: The second transmission transistor is disposed on a first region of the substrate below the first vertical gate electrode, and the second transmission transistor is electrically connected to the first vertical gate electrode.

15. The vertical memory device according to claim 14, wherein: The vertical memory device includes a channel array comprising a plurality of vertical channels arranged in a second direction and a third direction, the third direction being substantially parallel to the upper surface of the substrate and substantially perpendicular to the second direction. The channel array includes a plurality of channel blocks arranged in a third direction, each of the plurality of channel blocks including a vertical channel among the plurality of vertical channels; and A plurality of memory blocks are defined to correspond to the plurality of channel blocks, each of the plurality of memory blocks including: a vertical channel included in the corresponding channel block of the plurality of vertical channels; a plurality of charge storage structures located on the sidewalls of the vertical channel included in the corresponding channel block of the plurality of vertical channels; and a first horizontal gate electrode surrounding the vertical channel included in the corresponding channel block of the plurality of vertical channels. Each of the plurality of memory blocks is configured to perform an erase operation on the vertical memory device, and Each of the plurality of memory blocks includes a second transfer transistor.

16. A vertical memory device, the vertical memory device comprising: Horizontal gate electrodes are disposed on a substrate and spaced apart from each other in a first direction that is substantially perpendicular to the upper surface of the substrate. Each of the horizontal gate electrodes extends in a second direction that is substantially parallel to the upper surface of the substrate. Each of the horizontal gate electrodes includes a first portion comprising metal and a second portion comprising polycrystalline silicon doped with impurities. A vertical channel extends in a first direction through the first portion of each horizontal gate electrode; A charge storage structure is disposed between each of the horizontal gate electrodes and the vertical channel; A vertical gate electrode extends in a first direction through the second portion of each horizontal gate electrode; A gate insulating pattern is disposed on the sidewall of the vertical gate electrode; A horizontal channel is provided at the second portion of each of the horizontal gate electrodes; and The common source plate is mounted on the substrate. The horizontal gate electrode is disposed on the common source plate, and the vertical gate electrode extends through the common source plate in the first direction and is electrically insulated from the common source plate.

17. The vertical memory device according to claim 16, wherein, In a plan view defined by a second direction and a third direction, each of the second portions of each of the horizontal gate electrodes has a curved line along the third direction at its opposite lateral ends in the second direction, the third direction being substantially parallel to the upper surface of the substrate and substantially perpendicular to the second direction.

18. The vertical memory device of claim 16, further comprising: A blocking pattern covers the lower and upper surfaces of each of the horizontal gate electrodes, as well as a portion of the sidewalls. In this configuration, the first and second portions of each of the horizontal gate electrodes are in contact with each other, and the blocking pattern is not disposed between the first and second portions.

19. The vertical memory device according to claim 16, wherein: The vertical memory device includes a plurality of vertical channels arranged in a second direction and a third direction, the third direction being substantially parallel to the upper surface of the substrate and substantially perpendicular to the second direction. The vertical memory device further includes: The channel connection pattern is set on the common source electrode plate. The horizontal gate electrode is disposed on the channel connection pattern. The plurality of vertical channels extend through the channel connection pattern to the common source plate in a first direction and are connected to each other through the channel connection pattern. The vertical gate electrode extends through the channel connection pattern in the first direction and is electrically insulated from the channel connection pattern.

20. A vertical memory device, the vertical memory device comprising: Horizontal gate electrodes are disposed on a substrate and spaced apart from each other in a first direction that is substantially perpendicular to the upper surface of the substrate, wherein each of the horizontal gate electrodes extends in a second direction that is substantially parallel to the upper surface of the substrate. A vertical channel extends through the horizontal gate electrode in the first direction; Tunnel insulating patterns, floating gates, and gate insulating structures are sequentially stacked between each of the horizontal gate electrodes and the vertical channel; A vertical gate electrode extends through a horizontal gate electrode in a first direction, and the vertical gate electrode is electrically insulated from the horizontal gate electrode. A horizontal channel is provided at the portion of each of the horizontal gate electrodes adjacent to the vertical gate electrode, and The common source plate is mounted on the substrate. The horizontal gate electrode is disposed on the common source plate, and the vertical gate electrode extends through the common source plate in the first direction and is electrically insulated from the common source plate.

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