Gallium nitride semiconductor structure and preparation method thereof

Abstract

The present invention provides a gallium nitride semiconductor structure and a preparation method thereof, comprising a gallium nitride layer, a trench shielding structure, a first metal layer and a second metal layer. The present invention forms a gallium nitride layer on a composite pattern substrate, and can further reduce the dislocation density during the growth process and can concentrate the dislocations in a specific area to form a defect closure area, while the gallium nitride material formed in other growth areas has almost no dislocation defects, and then forms a trench and an insulating barrier layer on the defect closure area, wherein the insulating barrier layer can block the electrode metal and impurity metal elements from diffusing into the dislocations, thereby failing to form a leakage channel, and the gallium nitride layer below the ohmic contact area or the Schottky contact area has no dislocations, thereby improving the reliability and stability of the device. The present invention can obtain high-quality gallium nitride crystals, and can produce a gallium nitride device structure that can withstand large currents and voltages through the trench shielding structure, thereby improving the device performance.

Description

Technical Field

[0001] The present invention relates to the field of semiconductor technology, and in particular to a gallium nitride semiconductor structure and a preparation method thereof. Background Art

[0002] Gallium nitride belongs to the third generation of semiconductor materials with high bandgap width. Compared with the first generation of Si and the second generation of GaAs, it has superior physical properties, such as wider bandgap width, higher breakdown electric field, higher thermal conductivity, higher electron saturation rate and higher radiation resistance. It has a high operating temperature and can be used as an excellent material for microwave power transistors. Gallium nitride crystals are generally hexagonal wurtzite structures, and the atomic volume is about half of GaAs. The main reason why gallium nitride is favored is its wide bandgap characteristics, which makes gallium nitride devices faster and have higher breakdown voltages than silicon or other IIIV devices.

[0003] In terms of device types, GaN is mainly used in light-emitting diodes, field-effect transistors, diodes, solar cells, etc. Among them, FET involves various types of devices such as IGFET, HEMT, MOSFET, bipolar transistor, JFET, MISFET, IGBT, etc.

[0004] In recent years, GaN heteroepitaxial technology has developed rapidly, and metal organic chemical vapor deposition (MOCVD), hydride vapor phase epitaxy (HVPE), and molecular beam epitaxy (MBE) have become the mainstream growth technologies for preparing GaN materials. Epitaxial substrates generally use sapphire (single crystal Al2O3), silicon carbide (SiC), gallium arsenide (GaAs), silicon, etc. In order to improve the quality of the epitaxial layer, buffer layer technology, lateral epitaxial growth technology, suspended epitaxial technology, etc. have been developed.

[0005] The limitations of heteroepitaxial technology itself restrict the improvement of GaN-based material quality and device performance. Due to the different degrees of lattice mismatch and thermal mismatch between the heterogeneous substrate and GaN, high-density dislocations (~10 8-9 / cm 2 ), dislocations will reduce carrier mobility, lifetime and thermal conductivity. There are many ways to prepare GaN materials. The best method at present is HVPE (hydride vapor phase epitaxy), but the dislocation density still reaches ~10 5 / cm 2 When the metal electrode forms an ohmic contact with the gallium nitride material, the electrode metal and impurity metal elements will diffuse into the dislocation, forming leakage current, reducing the output power of the device, and seriously affecting the stability and reliability of the device.

[0006] In order to improve the reliability and stability of devices, everyone is looking for breakthroughs in device technology.

[0007] Therefore, it is necessary to provide a novel gallium nitride semiconductor structure and a preparation method thereof to improve device performance. Summary of the invention

[0008] In view of the above-mentioned shortcomings of the prior art, an object of the present invention is to provide a gallium nitride semiconductor structure and a preparation method thereof, so as to solve the gallium nitride crystal quality problem in the prior art and the problem of gallium nitride device breakdown caused by leakage channels easily formed due to crystal dislocations.

[0009] The present invention forms a gallium nitride layer on a composite pattern substrate by using a lateral epitaxial technology. During the growth process, the dislocation density can be further reduced and the dislocations can be concentrated in a specific area to form a defect closure area, while the gallium nitride material formed in other growth areas has almost no dislocation defects. Then, a groove is opened above the defect closure area by an overlay technique, and an insulating barrier layer is formed. Then, an electrode is made on the surface. The insulating barrier layer blocks the electrode metal and impurity metal elements from diffusing into the dislocations, and a leakage channel cannot be formed. There is no dislocation below the ohmic contact area or the Schottky contact area, thereby improving the reliability and stability of the device.

[0010] To achieve the above objectives and other related objectives, the present invention provides a gallium nitride semiconductor structure, the gallium nitride semiconductor structure comprising:

[0011] A gallium nitride layer, wherein the gallium nitride layer has a defect closure region;

[0012] A trench shielding structure, the trench shielding structure is located in the gallium nitride layer, and comprises a trench and an insulating barrier layer covering the bottom and sidewalls of the trench, and the vertical projection of the insulating barrier layer covers the corresponding defect closure area;

[0013] A first metal layer, the first metal layer is in contact with the gallium nitride layer;

[0014] The second metal layer is in contact with the insulating barrier layer and the gallium nitride layer, and the first metal layer and the second metal layer are located on two opposite sides of the gallium nitride layer.

[0015] Optionally, the insulating barrier layer includes one or a combination of a SiO2 layer, a Si3N4 layer, and an Al2O3 layer; and the thickness of the insulating barrier layer is 0.1 μm to 3 μm.

[0016] Optionally, the depth of the groove is 0.2 μm to 5 μm, and the width of the groove is 0.5 μm to 10 μm.

[0017] The present invention also provides a method for preparing a gallium nitride semiconductor structure, comprising the following steps:

[0018] providing a composite pattern substrate;

[0019] forming a gallium nitride layer on the composite pattern substrate, wherein a defective closing region is formed in the gallium nitride layer;

[0020] Providing a temporary support substrate, and bonding the temporary support substrate to the gallium nitride layer;

[0021] removing the composite pattern substrate to expose the gallium nitride layer and forming a first metal layer, wherein the first metal layer is in contact with the gallium nitride layer;

[0022] The temporary support substrate is removed to expose the gallium nitride layer, a trench is formed in the gallium nitride layer, and an insulating barrier layer is formed in the trench to cover the bottom and sidewalls of the trench to form a trench shielding structure, and the vertical projection of the insulating barrier layer covers the corresponding defect closure area;

[0023] A second metal layer is formed, the second metal layer being in contact with the insulating barrier layer and the gallium nitride layer.

[0024] Optionally, the insulating barrier layer includes one or a combination of a SiO2 layer, a Si3N4 layer, and an Al2O3 layer; and the thickness of the insulating barrier layer is 0.1 μm to 3 μm.

[0025] Optionally, the depth of the groove is 0.2 μm to 5 μm, and the width of the groove is 0.5 μm to 10 μm.

[0026] Optionally, the composite pattern substrate includes a registration mark, and the groove is formed in the gallium nitride layer through an overlay process.

[0027] Optionally, after removing the composite pattern substrate to expose the gallium nitride layer and before forming the first metal layer, a planarization step is further included.

[0028] Optionally, the composite pattern substrate includes a growth substrate, a dielectric layer protrusion and a buffer layer.

[0029] Optionally, the step of forming the defect closing region in the gallium nitride layer includes:

[0030] forming a conical gallium nitride layer protrusion on the composite pattern substrate, wherein the top of the conical gallium nitride layer protrusion is away from the composite pattern substrate;

[0031] A gallium nitride capping layer is formed on the conical gallium nitride layer protrusion, wherein the doping concentration of the conical gallium nitride layer protrusion is greater than that of the gallium nitride capping layer, so as to form a defect closing region in the gallium nitride layer.

[0032] As described above, the gallium nitride semiconductor structure and the preparation method thereof of the present invention have the following beneficial effects:

[0033] A conical GaN layer protrusion is formed on a composite pattern substrate to obtain a conical GaN layer protrusion with high doping, high carrier concentration and high crystal quality, and then a GaN capping layer is formed on the conical GaN layer protrusion. Since the conical GaN layer protrusion has a conical morphology, a defective closing area can be formed to concentrate defects.

[0034] Furthermore, since the conical GaN layer protrusion has a conical morphology, the carriers can be gathered to the top of the conical GaN layer protrusion like a funnel to transmit the carriers, so that the current is guided and the carriers can be prevented from passing through the defect closure area with more defects in the edge area;

[0035] Through the alignment marks in the composite pattern substrate, a trench shielding structure can be formed in the gallium nitride layer, and the vertical projection of the insulating barrier layer completely covers the corresponding defect closure area. Therefore, the trench shielding structure can prevent the electric field from breaking through the device at the dislocation, and a gallium nitride device structure that can withstand large current and high voltage can be produced, thereby improving device performance.

[0036] In summary, the gallium nitride semiconductor structure and preparation method of the present invention include a gallium nitride layer, a trench shielding structure, a first metal layer and a second metal layer. The present invention forms a gallium nitride layer on a composite pattern substrate, and the dislocation density can be further reduced during the growth process and the dislocations can be concentrated in a specific area to form a defect closure area, while the gallium nitride material formed in other growth areas has almost no dislocation defects, and then a groove and an insulating barrier layer are formed on the defect closure area, wherein the insulating barrier layer can block the electrode metal and impurity metal elements from diffusing into the dislocations, thereby failing to form a leakage channel, and the gallium nitride layer below the ohmic contact area or the Schottky contact area has no dislocations, thereby improving the reliability and stability of the device. The present invention can obtain high-quality gallium nitride crystals. After XRD testing, the FWHM in the 002 direction and the 102 direction are both less than 50 sec, and a gallium nitride device structure that can withstand large currents and voltages can be produced, thereby improving device performance. BRIEF DESCRIPTION OF THE DRAWINGS

[0037] Figure 1 It is a schematic diagram of the process flow of preparing a gallium nitride semiconductor structure in an embodiment.

[0038] Figure 2 to Figure 13Shown are schematic structural diagrams of various steps in preparing a gallium nitride semiconductor structure in an embodiment.

[0039] Figure 2a It is a schematic structural diagram of a composite pattern substrate with registration marks in an embodiment.

[0040] Fig.14 The figure shows a scanning electron microscope image after forming a conical GaN layer protrusion in the embodiment.

[0041] Fig.15 Shown is a scanning electron microscope image after the gallium nitride layer is formed in the embodiment.

[0042] Component number description

[0043] 101 Composite Graphic Substrate

[0044] 1011 Growth substrate

[0045] 1012 Dielectric layer protrusion

[0046] 1013 Buffer layer

[0047] 102 Conical GaN layer protrusion

[0048] 103 GaN capping layer

[0049] 104 Temporary support substrate

[0050] 105 Hollow

[0051] 106 First Metal Layer

[0052] 107 Metal substrate

[0053] 108 Groove

[0054] 109 Insulation barrier

[0055] 110 Second metal layer

[0056] A Defect closure area

[0057] Q Registration mark DETAILED DESCRIPTION

[0058] The following describes the embodiments of the present invention through specific examples, and those skilled in the art can easily understand other advantages and effects of the present invention from the contents disclosed in this specification. The present invention can also be implemented or applied through other different specific embodiments, and the details in this specification can also be modified or changed in various ways based on different viewpoints and applications without departing from the spirit of the present invention.

[0059] For example, when describing the embodiments of the present invention in detail, for the sake of convenience, the cross-sectional diagrams showing the device structure will not be partially enlarged according to the general scale, and the schematic diagrams are only examples, which should not limit the scope of protection of the present invention. In addition, in actual production, the three-dimensional dimensions of length, width and depth should be included.

[0060] For ease of description, spatial relational terms such as "under", "below", "below", "below", "above", "on", etc. may be used herein to describe the relationship of one element or feature shown in the drawings to other elements or features. It will be understood that these spatial relational terms are intended to include other directions of the device in use or operation in addition to the directions depicted in the drawings. In addition, when a layer is referred to as being "between" two layers, it can be the only layer between the two layers, or there can be one or more intervening layers. As used herein, "between..." means including the end point values.

[0061] In the context of the present application, a structure in which a first feature is described as being "above" a second feature may include embodiments in which the first and second features are formed in direct contact, and may also include embodiments in which additional features are formed between the first and second features, such that the first and second features may not be in direct contact.

[0062] It should be noted that the illustrations provided in this embodiment are only used to illustrate the basic concept of the present invention in a schematic manner, and therefore the illustrations only show components related to the present invention rather than being drawn according to the number, shape and size of components in actual implementation. In actual implementation, the type, quantity and proportion of each component may be changed arbitrarily, and the component layout may also be more complicated.

[0063] The fewer dislocations in the GaN epitaxial layer, the higher the device performance and stability will be. However, in the prior art, when growing the GaN outer layer, some dislocations will inevitably occur due to the growth substrate. The present invention eliminates the harmfulness of dislocations through dislocation centralization technology, and reduces the potential crowding at the contact point of the crystal dislocation electrode through the trench structure shielding technology, further suppresses the reverse leakage current, reduces leakage, prevents the device from being broken down by voltage, and improves the device's withstand voltage and other performance.

[0064] See also Figure 1 This embodiment provides a method for preparing a gallium nitride semiconductor structure, but the preparation of the gallium nitride semiconductor structure is not limited thereto and is only taken as an example. Figure 2 to Figure 15 , which may include the following steps:

[0065] First, a composite pattern substrate 101 is provided, wherein the composite pattern substrate 101 may include a growth substrate 1011 , a dielectric layer protrusion 1012 , and a buffer layer 1013 , but is not limited thereto.

[0066] Next, a gallium nitride layer is formed on the composite pattern substrate 101, wherein the gallium nitride layer has a defective closing region A. In this embodiment, the gallium nitride layer may include a conical gallium nitride layer protrusion 102 and a gallium nitride capping layer 103, but is not limited thereto. The specific preparation may include: firstly forming the gallium nitride layer protrusion 102 on the composite pattern substrate 101, wherein the cone top of the conical gallium nitride layer protrusion 102 is away from the composite pattern substrate 101; and forming the gallium nitride capping layer 103 on the conical gallium nitride layer protrusion 102, wherein the doping concentration of the conical gallium nitride layer protrusion 102 is greater than that of the gallium nitride capping layer 103, and the conical gallium nitride layer protrusion 102 and the gallium nitride capping layer 103 form a defective closing region A.

[0067] Next, a temporary support substrate 104 is provided, and the temporary support substrate 104 is bonded onto the gallium nitride cap layer 103 .

[0068] Next, a first chemical etching process is used to remove the dielectric layer protrusion 1012 to form a cavity 105 .

[0069] Next, a second chemical etching process is used to remove the buffer layer 1013 and a portion of the conical GaN layer protrusions 102 to peel off the growth substrate 1011 .

[0070] Next, a planarization process may be performed to expose the conical bottom of the GaN layer protrusion 102 .

[0071] Next, a first metal layer 106 is formed on the exposed surface of the conical GaN layer protrusion 102 .

[0072] Next, the temporary supporting substrate 104 is removed.

[0073] Next, a trench 108 is formed in the gallium nitride capping layer 103 through an overlay process.

[0074] Next, an insulating barrier layer 109 is formed in the trench 108 to cover the bottom and sidewalls of the trench 108 to form a trench shielding structure, and the vertical projection of the insulating barrier layer 109 in the trench shielding structure completely covers the corresponding defect closing area A.

[0075] Next, a second metal layer 110 is formed in the trench 108 .

[0076] In this embodiment, a conical GaN layer protrusion is formed on a composite pattern substrate to obtain a conical GaN layer protrusion with high doping, high carrier concentration and high crystal quality, and then a GaN capping layer is formed on the conical GaN layer protrusion. Since the conical GaN layer protrusion has a conical morphology, a defect closing region can be formed in the GaN layer to concentrate the defects. Furthermore, since the conical GaN layer protrusion has a conical morphology, the carriers can be gathered to the top of the conical GaN layer protrusion like a funnel to transmit the carriers, so that the current is guided and the carriers can be prevented from passing through the defect closing region with more defects in the edge region. A trench shielding structure is provided, and the projection of the insulating barrier layer in the vertical direction completely covers the corresponding defect closure area, so that the trench shielding structure can prevent the electric field from breaking through the device at the dislocation, and a gallium nitride device structure capable of withstanding large current and large voltage can be manufactured, thereby improving the device performance; thus, the method for preparing the gallium nitride semiconductor structure of this embodiment can obtain high-quality gallium nitride crystals, and after XRD testing, the FWHM in the 002 direction and the 102 direction are both less than 50 sec; the trench shielding structure can prevent the electric field from breaking through the device at the dislocation, and a gallium nitride device structure capable of withstanding large current and large voltage can be manufactured, thereby improving the device performance.

[0077] The specific preparation steps are as follows:

[0078] See also Figure 2 First, the composite pattern substrate 101 is provided. The composite pattern substrate 101 includes a growth substrate 1011, a dielectric layer protrusion 1012 and a buffer layer 1013.

[0079] Specifically, in this embodiment, the dielectric layer protrusion 1012 is located between the growth substrate 1011 and the buffer layer 1013, but it is not limited thereto. In another embodiment, the buffer layer 1013 may also be located below the dielectric layer protrusion 1012, and there is no excessive restriction here. Among them, the growth substrate 1011 may include one or a combination of a sapphire substrate, a Si substrate, a SiC substrate, a ZnO substrate, and a gallium nitride substrate, which can be selected according to needs, and there is no excessive restriction here. In this embodiment, a sapphire substrate is preferably used, but it is not limited thereto.

[0080] As an example, the material of the dielectric layer protrusion 1012 may include SiO2 layer, SiON x Layer or SiN x A combination of one or more layers.

[0081] As an example, the dielectric layer protrusions 1012 are arranged in a spaced arrangement or in contact with each other; when the dielectric layer protrusions 1012 are arranged in a spaced arrangement, they may be in a square, rectangular, elliptical, trapezoidal, or a combination thereof.

[0082] As an example, the buffer layer 1013 includes an AlN layer, an Al x Ga 1-x A combination of one or more of an N layer or a ZnO layer.

[0083] Specifically, in this embodiment, the dielectric layer protrusions 1012 are made of SiO2 layer; the dielectric layer protrusions 1012 are arranged at intervals, and the shape of the dielectric layer protrusions 1012 is rectangular, with a width range of 1μm to 20μm, such as 1μm, 5μm, 10μm, 20μm, etc.; the spacing is 1μm to 20μm, such as 1μm, 5μm, 10μm, 20μm, etc.; the height is 0.1μm to 5μm, such as 0.1μm, 1μm, 2.5μm, 5μm, etc. The buffer layer 1013 is made of AlN layer. However, the selection of the material and shape of the dielectric layer protrusions 1012 and the buffer layer 1013 is not limited to this, and no excessive restriction is made here.

[0084] As an example, Figure 2a The composite pattern substrate 101 includes a registration mark Q, and during the overlay process, the registration mark Q is used for alignment. The registration mark may be a square or other shape, and the side length may be 10 μm to 1000 μm, such as 10 μm, 100 μm, 1000 μm, etc., but is not limited thereto.

[0085] Next, see Figure 3 , using MOCVD method, but not limited to this, the conical gallium nitride layer protrusion 102 is formed on the composite pattern substrate 101, and the cone top of the conical gallium nitride layer protrusion 102 is far away from the composite pattern substrate 101.

[0086] As an example, the conical GaN layer protrusions 102 are arranged at intervals or in contact with each other.

[0087] Specifically, in this embodiment, the conical GaN layer protrusions 102 are arranged in a mutually spaced manner, but are not limited thereto. In another embodiment, by controlling MOCVD process parameters, the conical GaN layer protrusions 102 that are in contact with each other may also be formed. No excessive limitation is made here.

[0088] Among them, since the conical GaN layer protrusion 102 has a conical morphology, when the GaN cover layer 103 is subsequently formed, a dislocation aggregation area, that is, a defect closure area A, will be formed in the GaN cover layer 103. Figure 4 , Fig.14 and Fig.15 shown.

[0089] Next, see Figure 4, using MOCVD method, but not limited to this, a gallium nitride capping layer 103 is formed on the conical gallium nitride layer protrusion 102, the doping concentration of the conical gallium nitride layer protrusion 102 is greater than that of the gallium nitride capping layer 103, and the conical gallium nitride layer protrusion 102 and the gallium nitride capping layer 103 form the defect closure area A.

[0090] Specifically, the growth of the gallium nitride capping layer 103 also adopts the MOCVD method to epitaxially grow from the surface of the conical gallium nitride layer protrusion 102 to the outside to form the gallium nitride capping layer 103 with a conical morphology, and by controlling the process parameters of the MOCVD method, the following can be finally obtained: Figure 5 The gallium nitride capping layer 103 shown has a flat surface, and when the gallium nitride capping layer 103 is epitaxially grown, the gallium nitride capping layer 103 will also form a defect aggregation area between adjacent gallium nitride capping layers 103, that is, the defect closing area A extends into the gallium nitride capping layer 103, and as the defect closing area A extends along the conical gallium nitride layer protrusion 102 toward the gallium nitride capping layer 103, the density of defects will gradually weaken until it disappears, so that the defects such as dislocations in the growth process of the conical gallium nitride layer protrusion 102 and the gallium nitride capping layer 103 can be concentrated through the defect closing area A, thereby reducing the defect probability in other areas.

[0091] like Figure 6 First, the temporary support substrate 104 is formed on the surface of the gallium nitride cover layer 103 to provide support and facilitate subsequent process operations. The material of the temporary support substrate 104 is not overly restricted here and can be selected according to needs.

[0092] Next, see Figure 7 , a first etching solution is used to remove the dielectric layer protrusion 1012 to form the cavity 105, wherein the first etching solution includes an HF solution or a BOE solution that reacts with the dielectric layer protrusion 1012, and the type, action time, temperature, etc. of the first etching solution can be selected as needed and are not excessively restricted here.

[0093] Next, see Figure 8 Based on the cavity 105 , a second etching solution is used to remove the buffer layer 1013 to peel off the growth substrate 1011 .

[0094] As an example, the second corrosion solution is a KOH solution, a NaOH solution, or a mixed solution of H2SO4 and H3PO4.

[0095] Specifically, the buffer layer 1013 can be removed by the second etching solution to peel off the growth substrate 1011 , and because the second etching solution can react with the gallium nitride material, the second etching solution can remove a portion of the gallium nitride capping layer 103 .

[0096] Next, a planarization process is performed to expose the conical bottom of the GaN layer protrusion 102 and obtain a flat surface.

[0097] Next, see Fig. 9 , a first metal layer 106 may be formed first, and then a metal substrate 107 may be formed through the first metal layer 106 .

[0098] Next, see Fig.10 , using the first metal layer 106 and the metal substrate 107 as support, remove the temporary support substrate 104.

[0099] Next, see Fig.11 A groove photolithography pattern is made by overlay lithography technology, and a groove 108 is formed in the gallium nitride capping layer 103 by ICP etching, wherein the groove 108 is located above the defect closing region A.

[0100] As an example, the depth of the groove 108 is 0.2 μm to 5 μm, such as 0.2 μm, 1 μm, 2 μm, 5 μm, etc., and the width of the groove 108 is 0.5 μm to 10 μm, such as 0.5 μm, 1 μm, 2 μm, 5 μm, 10 μm, etc.

[0101] Next, see Fig.12 , an insulating barrier layer 109 is formed to constitute a trench shielding structure, and the vertical projection of the trench shielding structure completely covers the corresponding defect closing area A.

[0102] Next, see Fig.13 , a second metal layer 110 is formed in the trench 108 , and the second metal layer 110 is in contact with the insulating barrier layer 109 and the gallium nitride capping layer 103 .

[0103] The materials and preparation sequence of the first metal layer 106 and the second metal layer 110 mentioned above can be adjusted according to specific preparation requirements and are not excessively limited herein.

[0104] The present embodiment further provides a gallium nitride semiconductor structure, comprising a gallium nitride layer, a trench shielding structure, a first metal layer and a second metal layer, wherein the gallium nitride layer has a defect closure region, the trench shielding structure is located in the gallium nitride layer, comprises a trench and an insulating barrier layer covering the bottom and sidewalls of the trench, and a vertical projection of the insulating barrier layer covers the corresponding defect closure region, the first metal layer is in contact with the gallium nitride layer, the second metal layer is in contact with the insulating barrier layer and the gallium nitride layer, and the first metal layer and the second metal layer are located on opposite sides of the gallium nitride layer.

[0105] As an example, the gallium nitride layer may include a gallium nitride layer protrusion and a gallium nitride capping layer covering the gallium nitride layer protrusion, but is not limited thereto.

[0106] See also Fig.13 In this embodiment, the gallium nitride semiconductor structure includes a conical gallium nitride layer protrusion 102, a gallium nitride capping layer 103, a trench shielding structure, a first metal layer 106 and a second metal layer 110. The gallium nitride capping layer 103 covers the conical gallium nitride layer protrusion 102, the doping concentration of the conical gallium nitride layer protrusion 102 is greater than that of the gallium nitride capping layer 103, and the gallium nitride capping layer 103 has a defect closure area A; the trench shielding structure includes a trench 108 located in the gallium nitride capping layer 103 and an insulating barrier layer 109 covering the bottom and sidewall of the trench 108, and the vertical projection of the insulating barrier layer completely covers the corresponding defect closure area A; the first metal layer 106 is in contact with the conical gallium nitride layer protrusion 102; and the second metal layer 110 is in contact with the insulating barrier layer 109 and the gallium nitride capping layer 103.

[0107] As an example, the insulating barrier layer 109 includes one or a combination of a SiO2 layer, a Si3N4 layer, and an Al2O3 layer; the thickness of the insulating barrier layer 109 is 0.1 μm to 3 μm, such as 0.1 μm, 1 μm, 2 μm, and 3 μm.

[0108] As an example, the depth of the groove 108 is 0.2 μm to 5 μm, such as 0.2 μm, 1 μm, 2 μm, 5 μm, etc., and the width of the groove 108 is 0.5 μm to 10 μm, such as 0.5 μm, 1 μm, 2 μm, 5 μm, 10 μm, etc.

[0109] As an example, the conical GaN layer protrusions 102 are arranged at intervals or in contact with each other.

[0110] The gallium nitride semiconductor structure in this embodiment has been tested by XRD, and the FWHM of the gallium nitride crystal in the 002 direction and the 102 direction are both less than 50 sec; the trench shielding structure can prevent the electric field from breaking through the device at the dislocation, and a gallium nitride device structure capable of withstanding large current and high voltage can be manufactured, thereby improving device performance.

[0111] In summary, the gallium nitride semiconductor structure and the preparation method thereof of the present invention form a conical gallium nitride layer protrusion on a composite pattern substrate to obtain a conical gallium nitride layer protrusion with high doping, high carrier concentration and high crystal quality, and then form a gallium nitride capping layer on the conical gallium nitride layer protrusion. Since the conical gallium nitride layer protrusion has a conical morphology, the conical gallium nitride layer protrusion and the gallium nitride capping layer can form a defective closing area, so that the defects are concentrated; further, since the conical gallium nitride layer protrusion has a conical morphology, it can be like a funnel. The carriers are gathered to the convex top of the conical gallium nitride layer to transmit the carriers, so that the current is guided and the carriers are prevented from passing through the defect closure area with more defects in the edge area; through the alignment mark in the composite pattern substrate, a groove shielding structure can be formed in the gallium nitride layer, and the vertical projection of the insulating barrier layer completely covers the corresponding defect closure area, so that the groove shielding structure can prevent the electric field from breaking through the device at the dislocation, and a gallium nitride device structure that can withstand large current and high voltage can be produced, thereby improving the device performance.

[0112] The gallium nitride semiconductor structure of the present invention and its preparation method include a gallium nitride layer, a groove shielding structure, a first metal layer and a second metal layer. The present invention forms a gallium nitride layer on a composite pattern substrate, and can further reduce the dislocation density during the growth process and can concentrate the dislocations in a specific area to form a defect closure area, while the gallium nitride material formed in other growth areas has almost no dislocation defects, and then forms a groove and an insulating barrier layer on the defect closure area, wherein the insulating barrier layer can block the electrode metal and impurity metal elements from diffusing into the dislocation, thereby failing to form a leakage channel, and the gallium nitride layer below the ohmic contact area or the Schottky contact area has no dislocation, thereby improving the reliability and stability of the device. The present invention can obtain high-quality gallium nitride crystals. After XRD testing, the FWHM in the 002 direction and the 102 direction are both less than 50 sec, and a gallium nitride device structure capable of withstanding large currents and voltages can be manufactured, thereby improving device performance.

[0113] The above embodiments are merely illustrative of the principles and effects of the present invention, and are not intended to limit the present invention. Anyone familiar with the art may modify or alter the above embodiments without departing from the spirit and scope of the present invention. Therefore, all equivalent modifications or alterations made by a person of ordinary skill in the art without departing from the spirit and technical concept disclosed by the present invention shall still be covered by the claims of the present invention.

Claims

1. A gallium nitride semiconductor structure, characterized in that: The gallium nitride semiconductor structure comprises: A gallium nitride layer, wherein the bottom of the gallium nitride layer has a defect closing region and a conical gallium nitride layer protrusion, and the defect closing region is located between adjacent conical gallium nitride layer protrusions; A trench shielding structure, the trench shielding structure is located on the top of the gallium nitride layer, and comprises a trench and an insulating barrier layer covering the bottom and sidewalls of the trench, and the vertical projection of the insulating barrier layer covers the corresponding defect closure area; A first metal layer, the first metal layer is in contact with the gallium nitride layer; The second metal layer fills the trench and contacts the insulating barrier layer and the gallium nitride layer, and the first metal layer and the second metal layer are located on two opposite sides of the gallium nitride layer.

2. The gallium nitride semiconductor structure according to claim 1, characterized in that: The insulating barrier layer includes one or a combination of a SiO2 layer, a Si3N4 layer, and an Al2O3 layer; the thickness of the insulating barrier layer is 0.1 μm to 3 μm.

3. The gallium nitride semiconductor structure according to claim 1, characterized in that: The depth of the groove is 0.2 μm to 5 μm, and the width of the groove is 0.5 μm to 10 μm.

4. A method for preparing a gallium nitride semiconductor structure, characterized in that: The following steps are involved: providing a composite pattern substrate; A gallium nitride layer is formed on the composite pattern substrate, and a defective closing region is formed in the gallium nitride layer; wherein the step of forming the defective closing region in the gallium nitride layer comprises: forming a conical gallium nitride layer protrusion on the composite pattern substrate, wherein the top of the conical gallium nitride layer protrusion is away from the composite pattern substrate; forming a gallium nitride capping layer on the conical gallium nitride layer protrusions, wherein the doping concentration of the conical gallium nitride layer protrusions is greater than that of the gallium nitride capping layer, so as to form a defect closing region in the gallium nitride layer, wherein the defect closing region is located between adjacent conical gallium nitride layer protrusions; Providing a temporary support substrate, and bonding the temporary support substrate to the gallium nitride layer; removing the composite pattern substrate to expose the gallium nitride layer and forming a first metal layer, wherein the first metal layer is in contact with the gallium nitride layer; The temporary support substrate is removed to expose the gallium nitride layer, a trench is formed in the gallium nitride layer, and an insulating barrier layer is formed in the trench to cover the bottom and sidewalls of the trench to form a trench shielding structure, and the vertical projection of the insulating barrier layer covers the corresponding defect closure area; A second metal layer is formed, the second metal layer filling the trench and contacting the insulating barrier layer and the gallium nitride layer.

5. The method for preparing a gallium nitride semiconductor structure according to claim 4, characterized in that: The insulating barrier layer includes one or a combination of a SiO2 layer, a Si3N4 layer, and an Al2O3 layer; the thickness of the insulating barrier layer is 0.1 μm to 3 μm.

6. The method for preparing a gallium nitride semiconductor structure according to claim 4, characterized in that: The depth of the groove is 0.2 μm to 5 μm, and the width of the groove is 0.5 μm to 10 μm.

7. The method for preparing a gallium nitride semiconductor structure according to claim 4, characterized in that: The composite pattern substrate includes a plate alignment mark, and the groove is formed in the gallium nitride layer through an overlay process.

8. The method for preparing a gallium nitride semiconductor structure according to claim 4, characterized in that: After removing the composite pattern substrate to expose the gallium nitride layer and before forming the first metal layer, a planarization step is also included.

9. The method for preparing a gallium nitride semiconductor structure according to claim 4, characterized in that: The composite pattern substrate comprises a growth substrate, a dielectric layer protrusion and a buffer layer.

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