A power switch device structure and manufacturing method thereof

Abstract

The present invention provides a power switch device structure and a manufacturing method thereof, wherein the power switch device structure includes a drain layer, a substrate, a first conductive type epitaxial layer, an interlayer dielectric layer, a source layer and a gate layer, wherein the epitaxial layer contains a gate trench and a voltage-resistant trench; the first control gate layer and the second control gate layer in the gate trench are electrically connected to the gate layer, the shielding gate layer, the second conductive type body region and the first conductive type source region are electrically connected to the source layer, and the first conductive layer, the second conductive layer, the third conductive layer in the voltage-resistant trench, the second conductive type body region on the left side of the voltage-resistant trench and the second conductive type body region on the right side of the voltage-resistant structure are electrically connected to the source layer. The trench gate structure in the power switch device structure of the present invention can reduce the gate-drain capacitance Cgd, and the voltage-resistant structure can increase the drain-source capacitance Cds and enhance the voltage-resistant capability of the device, thereby effectively improving the drain voltage oscillation resistance and voltage-resistant capability of the power switch device.

Description

Technical Field

[0001] The invention belongs to the field of semiconductor devices and relates to a power switch device structure and a manufacturing method thereof. Background Art

[0002] In power applications, metal oxide semiconductor field effect transistors (MOSFETs) have been widely used as switch tubes. The existing common technology is a trench structure, which has a high breakdown voltage while reducing the on-resistance, but has the problem of large dynamic loss caused by excessive gate-drain capacitance; the split gate trench (Spilt Gate Trench, referred to as SGT) metal oxide semiconductor field effect transistor device separates the trench gate of the ordinary trench metal oxide semiconductor field effect transistor into two gates through dielectric isolation, connects one of the gates to the source potential through a left-right structure or an upper-lower structure, reduces the gate-drain overlap area to reduce the Miller capacitance Cgd, improve the device switching speed, and reduce the dynamic loss of the device. Therefore, the split gate trench metal oxide semiconductor field effect transistor device has been widely used in medium and low voltage applications. However, most of the current split gate trench metal oxide semiconductor field effect transistor devices are prone to failure in high-speed switching applications due to the limitations of the ability to resist drain voltage oscillation and the withstand voltage, thereby affecting the normal operation of electrical appliances.

[0003] Therefore, in the field of semiconductor design and manufacturing, there is an urgent need to develop a power switching device with strong ability to resist drain voltage fluctuations and high voltage resistance. Summary of the invention

[0004] In view of the above-mentioned shortcomings of the prior art, an object of the present invention is to provide a power switch device structure and a manufacturing method thereof, so as to solve the problems of weak drain voltage oscillation resistance and poor high voltage resistance of the power switch device in the prior art.

[0005] In order to achieve the above-mentioned object and other related objects, the present invention provides a power switch device structure, wherein the power switch device comprises:

[0006] A stacked structure, comprising a drain layer, a substrate, a first conductivity type epitaxial layer, an interlayer dielectric layer, a source layer and a gate layer stacked in sequence in a vertical direction;

[0007] A trench gate structure, comprising a gate trench and a field plate located in the gate trench, a first control gate layer, a second control gate layer, a shield gate layer, a first gate dielectric layer and a second gate dielectric layer, wherein the gate trench opens from the top surface of the epitaxial layer and extends toward the bottom surface of the epitaxial layer, but does not penetrate the bottom surface of the epitaxial layer; the field plate is located at the bottom of the gate trench; the first control gate layer, the second control gate layer and the shield gate layer are all located above the field plate, and the shield gate layer is located between the first control gate layer and the second control gate layer in the horizontal direction, the bottom surfaces of the first control gate layer and the second control gate layer are both higher than the bottom surface of the shield gate, the first control gate layer and the second control gate layer are electrically connected to the gate layer through a first contact hole and a second contact hole respectively, and the shield gate layer is electrically connected to the source layer through a third contact hole; the first gate dielectric layer surrounds the side and bottom of the first control gate layer, and the second gate dielectric layer surrounds the side and bottom of the second control gate layer;

[0008] A second conductive type body region, located on the top of the epitaxial layer and distributed on the left and right sides of the trench gate structure, and the bottom surface of the body region is not lower than the bottom surfaces of the first control gate layer and the second control gate layer;

[0009] A first conductive type source region is located on the top of the body region and is electrically connected to the source layer through a fourth contact hole, and a bottom surface of the source region is not lower than the bottom surface.

[0010] Optionally, a material of the first control gate layer includes polysilicon, a material of the second control gate layer includes polysilicon, and a material of the shield gate layer includes polysilicon.

[0011] Optionally, the fourth contact hole penetrates the source region in a vertical direction and extends downward into the body region.

[0012] Optionally, the power switch device structure also includes a voltage-resistant structure, which includes a voltage-resistant groove and an insulating layer, a first conductive layer, a second conductive layer, a third conductive layer, a first isolation layer and a second isolation layer located in the voltage-resistant groove, and the body region is also distributed on both sides of the voltage-resistant groove, wherein the portion of the body region distributed on both sides of the voltage-resistant groove serves as a component of the voltage-resistant structure, the voltage-resistant groove opens from the top surface of the epitaxial layer and extends toward the bottom surface of the epitaxial layer, but does not penetrate the bottom surface of the epitaxial layer, and the voltage-resistant groove is spaced a preset distance from the gate groove in the horizontal direction; the insulating layer is located the bottom of the voltage-resistant groove; the first conductive layer, the second conductive layer and the third conductive layer are all located above the insulating layer, and the third conductive layer is located between the first conductive layer and the second conductive layer in the horizontal direction, and the bottom surfaces of the first conductive layer and the second conductive layer are higher than the bottom surface of the third conductive layer; the first conductive layer, the second conductive layer and the third conductive layer are electrically connected to the source layer through the fifth contact hole, the sixth contact hole and the seventh contact hole, respectively; the first isolation layer surrounds the side and bottom of the first conductive layer, and the second isolation layer surrounds the side and bottom of the second conductive layer.

[0013] Optionally, the body region is also distributed on both sides of the voltage-resistant structure, and the part of the body region distributed on both sides of the voltage-resistant structure is not provided with the source region, the bottom surface of the body region is not lower than the bottom surface of the first conductive layer and the second conductive layer, and the part of the body region distributed on both sides of the voltage-resistant structure is electrically connected to the source layer through the eighth contact hole and the ninth contact hole respectively.

[0014] Optionally, a material of the first conductive layer includes polysilicon, a material of the second conductive layer includes polysilicon, and a material of the third conductive layer includes polysilicon.

[0015] Optionally, the first conductivity type is N-type, and the second conductivity type is P-type.

[0016] The present invention also provides a method for manufacturing a power switch device structure, comprising the following steps: providing a substrate, and forming a first conductive type epitaxial layer on the substrate;

[0017] A trench gate structure is formed, wherein the trench gate structure includes a gate trench and a field plate located in the gate trench, a first control gate layer, a second control gate layer, a shield gate layer, a first gate dielectric layer and a second gate dielectric layer, wherein the gate trench opens from the top surface of the epitaxial layer and extends toward the bottom surface of the epitaxial layer, but does not penetrate the bottom surface of the epitaxial layer; the field plate is located at the bottom of the gate trench; the first control gate layer, the second control gate layer and the shield gate layer are all located above the field plate, and the shield gate layer is located between the first control gate layer and the second control gate layer in the horizontal direction, the bottom surfaces of the first control gate layer and the second control gate layer are both higher than the bottom surface of the shield gate, the first gate dielectric layer surrounds the side and bottom of the first control gate layer, and the second gate dielectric layer surrounds the side and bottom of the second control gate layer;

[0018] Forming a second conductive type body region on the top of the epitaxial layer, wherein the bottom surface of the body region is not lower than the bottom surfaces of the first control gate layer and the second control gate layer, and the body region is distributed on the left and right sides of the gate trench;

[0019] forming a first conductivity type source region on top of the body region;

[0020] An interlayer dielectric layer, a source layer and a gate layer are sequentially formed on the epitaxial layer, and a first contact hole, a second contact hole, a third contact hole and a fourth contact hole are formed vertically penetrating the interlayer dielectric layer, the interlayer dielectric layer covers the upper surface of the epitaxial layer and the trench gate structure, the first control gate layer and the second control gate layer are electrically connected to the gate layer through the first contact hole and the second contact hole respectively, the shielding gate layer is electrically connected to the source layer through the third contact hole; the source region is electrically connected to the source layer through the fourth contact hole.

[0021] Optionally, forming the trench gate structure includes:

[0022] forming the gate trench in the epitaxial layer;

[0023] forming a field plate material layer, wherein the field plate material layer covers the upper surface of the epitaxial layer and the inner wall of the gate trench but does not completely fill the gate trench;

[0024] forming a first conductive material layer, wherein the first conductive material layer covers the field plate material layer and fills the gate trench;

[0025] removing the portion of the first conductive material layer outside the gate trench, so that the remaining portion of the first conductive material layer is flush with the upper surface of the epitaxial layer, and the portion of the first conductive material layer inside the field plate material layer serves as the shielding gate layer;

[0026] Etching the field plate material layer to obtain the field plate, and forming a first control gate trench and a second control gate trench in the gate trench, wherein the first control gate trench and the second control gate trench are respectively located on both sides of the shielding gate layer, and the bottom surfaces of the first control gate trench and the second control gate trench are both higher than the bottom surface of the shielding gate layer;

[0027] forming a gate dielectric layer, wherein the gate dielectric layer covers an inner wall of the first control gate trench and an inner wall of the second control gate trench, but does not completely fill the first control gate trench and the second control gate trench;

[0028] A second conductive material layer is formed on the surface of the gate dielectric layer, and portions of the gate dielectric layer and the second conductive material layer located outside the gate trench are removed; a portion of the gate dielectric layer located on an inner wall of the first control gate trench serves as the first gate dielectric layer, a portion of the gate dielectric layer located on an inner wall of the second control gate trench serves as the second gate dielectric layer, a portion of the second conductive material layer located in the first control gate trench serves as the first control gate layer, and a portion of the second conductive material layer located in the second control gate trench serves as the second control gate layer.

[0029] Optionally, the first conductive material layer is made of polysilicon, and the second conductive material layer is made of polysilicon.

[0030] Optionally, forming the body region and the source region includes:

[0031] Doping first type impurities into the top of the epitaxial layer on the left and right sides of the gate trench to obtain the second conductive type body region;

[0032] Second type impurities are doped into the top of the body region at one side of the gate trench to obtain the first conductive type source region.

[0033] Optionally, forming the first contact hole, the second contact hole, the third contact hole and the fourth contact hole includes: forming the first contact hole, the second contact hole, the third contact hole and the fourth contact hole in the interlayer dielectric layer, and filling the first contact hole, the second contact hole, the third contact hole and the fourth contact hole with conductive material.

[0034] Optionally, the fourth contact hole penetrates the source region in a vertical direction and extends downward into the body region.

[0035] Optionally, a method for forming the field plate includes a thermal oxidation method, and a method for forming the first gate dielectric layer and the second gate dielectric layer includes a dry oxygen growth method.

[0036] Optionally, a method of forming the shield gate layer, the first control gate layer and the second control gate layer comprises chemical vapor deposition.

[0037] Optionally, the method for manufacturing the power switching device structure also includes the step of forming a voltage-resistant structure, wherein the voltage-resistant structure includes a voltage-resistant groove and an insulating layer, a first conductive layer, a second conductive layer, a third conductive layer, a first isolation layer and a second isolation layer located in the voltage-resistant groove, and the body region is also distributed on both sides of the voltage-resistant groove, wherein the portion of the body region distributed on both sides of the voltage-resistant groove serves as a component of the voltage-resistant structure, the voltage-resistant groove opens from the top surface of the epitaxial layer and extends toward the bottom surface of the epitaxial layer, but does not penetrate the bottom surface of the epitaxial layer, and the voltage-resistant groove is horizontally spaced a preset distance from the gate groove; the insulating layer is located at the bottom of the voltage-resistant groove; the first conductive layer, the second conductive layer and the The third conductive layer is located above the insulating layer, and the third conductive layer is located between the first conductive layer and the second conductive layer in the horizontal direction, and the bottom surfaces of the first conductive layer and the second conductive layer are higher than the bottom surface of the third conductive layer; the method for manufacturing the power switching device structure also includes the steps of forming a fifth contact hole, a sixth contact hole and a seventh contact hole penetrating the interlayer dielectric layer in the vertical direction, and the first conductive layer, the second conductive layer and the third conductive layer are electrically connected to the source layer through the fifth contact hole, the sixth contact hole and the seventh contact hole respectively; the first isolation layer surrounds the side and bottom of the first conductive layer, and the second isolation layer surrounds the side and bottom of the second conductive layer.

[0038] Optionally, the voltage-resistant structure and the gate trench are manufactured simultaneously.

[0039] Optionally, the body region is also distributed on both sides of the voltage-resistant structure, and the portion of the body region distributed on both sides of the voltage-resistant structure is not provided with the source region; the method for manufacturing the power switching device structure also includes the step of forming an eighth contact hole and a ninth contact hole penetrating the interlayer dielectric layer in a vertical direction, and the portion of the body region distributed on both sides of the voltage-resistant structure is electrically connected to the source layer through the eighth contact hole and the ninth contact hole, respectively.

[0040] Optionally, a material of the first conductive layer includes polysilicon, a material of the second conductive layer includes polysilicon, and a material of the third conductive layer includes polysilicon.

[0041] Optionally, the first conductivity type is N-type, and the second conductivity type is P-type.

[0042] As described above, a power switching device structure and a manufacturing method thereof of the present invention improves the structure of the gate trench of the device, thereby increasing the drain-source overlap area of ​​the device while ensuring a lower gate-drain capacitance Cgd, thereby increasing the drain-source capacitance Cds, so that the device has a stronger ability to resist drain voltage oscillations and is less likely to fail in fast switching applications; in addition, a voltage-resistant structure can be further increased, and the second conductive type body regions on the left and right sides of the voltage-resistant trench are directly electrically connected to the source layer, so that when the device is in a voltage-resistant state, the second conductive type body region and the first conductive type epitaxial layer are reverse-biased and depleted, thereby reducing the electric field peak at the bottom of the trench and improving the voltage-resistant capability of the device; furthermore, the gate trench and the voltage-resistant trench have the same process steps, and only differ in the potential contact connection, thereby improving the device performance without increasing the process difficulty. BRIEF DESCRIPTION OF THE DRAWINGS

[0043] Figure 1 It shows a cross-sectional structure schematic diagram of the power switch device of the present invention.

[0044] Figure 2 Shown is a process flow chart of a method for manufacturing a power switch device of the present invention.

[0045] Figure 3 It is a schematic diagram showing the method for manufacturing a power switch device of the present invention for forming a gate trench and a voltage-resistant trench.

[0046] Figure 4 It is a schematic diagram showing the method for manufacturing a power switch device of the present invention to form an oxide film layer.

[0047] Figure 5 It is a schematic diagram showing the formation of a first conductive material layer in the method for manufacturing a power switching device of the present invention.

[0048] Figure 6 It is a schematic diagram showing the method for manufacturing a power switch device of the present invention for forming a shielding grid layer and a third conductive layer.

[0049] Figure 7 It is a schematic diagram showing the method for manufacturing a power switch device of the present invention for forming a first control gate trench, a second control gate trench, a first voltage-resistant trench and a second voltage-resistant trench.

[0050] Figure 8 It is a schematic diagram showing the formation of a gate dielectric layer in the method for manufacturing a power switch device of the present invention.

[0051] Fig. 9 It is a schematic diagram showing the formation of a second conductive material layer in the method for manufacturing a power switch device of the present invention.

[0052] Fig.10It is a schematic diagram showing the method for manufacturing a power switch device of the present invention, wherein the gate dielectric layer and the second conductive material outside the gate trench and the voltage-resistant trench are removed.

[0053] Fig.11 It is a schematic diagram showing the method for manufacturing a power switch device of the present invention for forming a second conductivity type body region and a first conductivity type source region.

[0054] Fig.12 It is a schematic diagram showing the method for manufacturing a power switch device of the present invention for forming an interlayer dielectric layer, a source layer, a gate layer, a drain layer and a contact hole.

[0055] Component number description

[0056] 1 Drain layer

[0057] 2 Substrate

[0058] 3 Epitaxial layer

[0059] 30 Trench gate structure

[0060] 301 Field Board

[0061] 302 First gate dielectric layer

[0062] 303 Second gate dielectric layer

[0063] 304 First Oxide Layer

[0064] 305 Nitride layer

[0065] 306 Second oxide layer

[0066] 307 Hard mask layer

[0067] 308 Field plate material layer

[0068] 31 Gate trench

[0069] 311 First control gate layer

[0070] 312 Second control gate layer

[0071] 313 Shielding layer

[0072] 314 first control gate trench

[0073] 315 Second control gate trench

[0074] 316 first conductive material layer

[0075] 317 second conductive material layer

[0076] 32 Pressure-resistant structure

[0077] 321 Insulation layer

[0078] 322 First Isolation Layer

[0079] 323 Second isolation layer

[0080] 324 gate dielectric layer

[0081] 33 Pressure-resistant groove

[0082] 331 First conductive layer

[0083] 332 second conductive layer

[0084] 333 Third conductive layer

[0085] 334 First pressure-resistant groove

[0086] 335 Second pressure-resistant groove

[0087] 34 Second conductivity type body region

[0088] 35. First conductivity type source region

[0089] 4 Interlayer dielectric layer

[0090] 41 First contact hole

[0091] 42 Second contact hole

[0092] 43 Third contact hole

[0093] 44 Fourth contact hole

[0094] 45 Fifth contact hole

[0095] 46 Sixth contact hole

[0096] 47 Seventh contact hole

[0097] 48 Eighth contact hole

[0098] 49 Ninth contact hole

[0099] 5 Source layer

[0100] 6. Gate layer DETAILED DESCRIPTION

[0101] The following describes the embodiments of the present invention through specific examples, and those skilled in the art can easily understand other advantages and effects of the present invention from the contents disclosed in this specification. The present invention can also be implemented or applied through other different specific embodiments, and the details in this specification can also be modified or changed in various ways based on different viewpoints and applications without departing from the spirit of the present invention.

[0102] See also Figures 1 to 12 It should be noted that the illustrations provided in this embodiment are only used to illustrate the basic concept of the present invention in a schematic manner. Although the illustrations only show components related to the present invention rather than being drawn according to the number, shape and size of components in actual implementation, the form, quantity, positional relationship and proportion of each component in actual implementation can be changed at will under the premise of realizing the technical solution of this party, and the component layout form may also be more complicated.

[0103] Embodiment 1

[0104] This embodiment provides a power switch device structure. Figure 1 , which is a schematic diagram of the structure of the power switch device, includes a stacked structure, a trench gate structure 30, a second conductive type body region 34 and a first conductive type source region 35, wherein the stacked structure includes a drain layer 1, a substrate 2, a first conductive type epitaxial layer 3, an interlayer dielectric layer 4, a source layer 5 and a gate layer 6 stacked in sequence in a vertical direction; the trench gate structure 30 includes a gate trench and a field plate 301, a first control gate layer 311, a second control gate layer 312, a shielding gate layer 313, a first gate dielectric layer 302 and a second gate dielectric layer 303 located in the gate trench, wherein the gate trench opens from the top surface of the epitaxial layer 3 and extends toward the bottom surface of the epitaxial layer 3, but does not penetrate the bottom surface of the epitaxial layer 3; the field plate 301 is located at the bottom of the gate trench; the first control gate layer 311, the second control gate layer 312 and the shielding gate layer 313 are all located above the field plate 301, and the The shielding gate layer 313 is located between the first control gate layer 311 and the second control gate layer 312 in the horizontal direction, the bottom surfaces of the first control gate layer 311 and the second control gate layer 312 are both higher than the bottom surface of the shielding gate 313, the first control gate layer 311 and the second control gate layer 312 are electrically connected to the gate layer 6 through the first contact hole 41 and the second contact hole 42 respectively, and the shielding gate layer 313 is electrically connected to the source layer 5 through the third contact hole 43; the first gate dielectric layer 302 surrounds the side and bottom of the first control gate layer 311, and the second gate dielectric layer 303 surrounds the side and bottom of the second control gate layer 312; the second conductive type body region 34 is located at the top of the epitaxial layer 3 and distributed on the left and right sides of the trench gate structure 30; the first conductive type source region 35 is located at the top of the body region 34 and is electrically connected to the source layer 5 through the fourth contact hole 44.

[0105] As an example, the bottom surface of the body region 34 is not lower than the bottom surfaces of the first control gate layer 311 , the second control gate layer 312 , the first conductive layer 331 and the second conductive layer 332 , and the bottom surface of the source region 35 is not lower than the bottom surface of the body region 34 .

[0106] As an example, the material of the first control gate layer 311 includes polysilicon or other suitable materials, the material of the second control gate layer 312 includes polysilicon or other suitable materials, and the material of the shield gate layer 313 includes polysilicon or other suitable materials.

[0107] Specifically, the structural design of the trench gate structure 30 can reduce the gate-drain overlap area of ​​the device, thereby reducing the parasitic overlap capacitance Cgd between the drain and the gate.

[0108] As an example, the power switching device structure may further include a voltage-resistant structure 32 arranged at intervals from the trench gate structure 30, the voltage-resistant structure 32 including a voltage-resistant groove and an insulating layer 321, a first conductive layer 331, a second conductive layer 332, a third conductive layer 333, a first isolation layer 322 and a second isolation layer 323 located in the voltage-resistant groove, the body region 34 is also distributed on both sides of the voltage-resistant groove, wherein the portion of the body region 34 distributed on both sides of the voltage-resistant groove serves as a component of the voltage-resistant structure 32, the voltage-resistant groove opens from the top surface of the epitaxial layer 3 and extends toward the bottom surface of the epitaxial layer 3, but does not penetrate the bottom surface of the epitaxial layer 3, and the voltage-resistant groove is horizontally spaced a preset distance from the gate groove; the insulating layer 321 is located at the The bottom of the voltage-resistant groove; the first conductive layer 331, the second conductive layer 332 and the third conductive layer 333 are all located above the insulating layer 321, and the third conductive layer 333 is located between the first conductive layer 331 and the second conductive layer 332 in the horizontal direction, the bottom surfaces of the first conductive layer 331 and the second conductive layer 332 are higher than the bottom surface of the third conductive layer 333, and the first conductive layer 331, the second conductive layer 332 and the third conductive layer 333 are electrically connected to the source layer 5 through the fifth contact hole 45, the seventh contact hole 47 and the sixth contact hole 46 respectively; the first isolation layer 322 surrounds the side and bottom of the first conductive layer 331, and the second isolation layer 323 surrounds the side and bottom of the second conductive layer 332.

[0109] As an example, the body region 34 distributed on both sides of the voltage-resistant trench is not provided with the source region 35 , and the body region 34 distributed on both sides of the voltage-resistant trench is electrically connected to the source layer 5 through the eighth contact hole 48 and the ninth contact hole 49 respectively.

[0110] As an example, the material of the first conductive layer 331 includes polysilicon or other suitable materials, the material of the second conductive layer 332 includes polysilicon or other suitable materials, and the material of the third conductive layer 333 includes polysilicon or other suitable materials.

[0111] Specifically, the first conductive layer 331, the second conductive layer 332 and the third conductive layer 333 in the voltage-resistant groove are all connected to the source potential, which can increase the drain-source overlap area, thereby increasing the drain-source capacitance Cds, which is beneficial to improving the device's ability to resist drain voltage oscillation. In addition, there is no source doping region in the second conductive type body region on both sides of the voltage-resistant structure, which can form a PN junction with the first conductive type epitaxial layer, thereby further improving the device's voltage resistance.

[0112] As an example, the first conductivity type is N type, and the second conductivity type is P type.

[0113] The power switch device structure of this embodiment combines the trench gate structure 30 and the voltage-resistant structure 32 together by changing the potential connection mode and body region structure in the trench, thereby ensuring a lower gate-drain capacitance Cgd and increasing the drain-source capacitance Cds of the device, thereby enhancing the device's ability to resist drain voltage oscillations and withstand voltage, which is beneficial to avoiding device failure in high-speed switching applications.

[0114] Embodiment 2

[0115] This embodiment provides a method for manufacturing a power switch device structure. Figure 2 , shown as a process flow chart of the method, comprising the following steps:

[0116] S1: providing a substrate, and forming a first conductivity type epitaxial layer on the substrate;

[0117] S2: forming a trench gate structure, the trench gate structure comprising a gate trench and a field plate located in the gate trench, a first control gate layer, a second control gate layer, a shielding gate layer, a first gate dielectric layer and a second gate dielectric layer, wherein the gate trench opens from the top surface of the epitaxial layer and extends toward the bottom surface of the epitaxial layer, but does not penetrate the bottom surface of the epitaxial layer; the field plate is located at the bottom of the gate trench; the first control gate layer, the second control gate layer and the shielding gate layer are all located above the field plate, and the shielding gate layer is located between the first control gate layer and the second control gate layer in the horizontal direction, the bottom surfaces of the first control gate layer and the second control gate layer are both higher than the bottom surface of the shielding gate, the first gate dielectric layer surrounds the side and bottom of the first control gate layer, and the second gate dielectric layer surrounds the side and bottom of the second control gate layer;

[0118] S3: forming a second conductive type body region on the top of the epitaxial layer, wherein the body region is distributed on the left and right sides of the gate trench;

[0119] S4: forming a first conductivity type source region on the top of the body region;

[0120] S5: An interlayer dielectric layer, a source layer and a gate layer are sequentially formed on the epitaxial layer, and a first contact hole, a second contact hole, a third contact hole and a fourth contact hole are formed vertically penetrating the interlayer dielectric layer, the interlayer dielectric layer covers the upper surface of the epitaxial layer and the trench gate structure, the first control gate layer and the second control gate layer are electrically connected to the gate layer through the first contact hole and the second contact hole respectively, the shielding gate layer is electrically connected to the source layer through the third contact hole; the source region is electrically connected to the source layer through the fourth contact hole.

[0121] As an example, see Figures 3 to 12 , which is a schematic diagram of the structure presented in each step of the method for manufacturing the power switch device structure described in this embodiment.

[0122] First see Figures 3 to 10 , performing the step S1 and the step S2: providing a substrate 2, forming a first conductive type epitaxial layer 3 on the substrate 2, and forming a trench gate structure 30, wherein the trench gate structure 30 includes a gate trench 31 and a field plate 301 located in the gate trench 31, a first control gate layer 311, a second control gate layer 312, a shielding gate layer 313, a first gate dielectric layer 302, and a second gate dielectric layer 303, wherein the gate trench 31 opens from the top surface of the epitaxial layer 3 and extends toward the bottom surface of the epitaxial layer 3, but does not penetrate the bottom surface of the epitaxial layer 3; the field plate 301 is located in the The bottom of the gate groove 31; the first control gate layer 311, the second control gate layer 312 and the shielding gate layer 313 are all located above the field plate 301, and the shielding gate layer 313 is located between the first control gate layer 311 and the second control gate layer 312 in the horizontal direction, the bottom surfaces of the first control gate layer 311 and the second control gate layer 312 are both higher than the bottom surface of the shielding gate layer 313, the first gate dielectric layer 302 surrounds the side and bottom of the first control gate layer 311, and the second gate dielectric layer 303 surrounds the side and bottom of the second control gate layer 312.

[0123] Specifically, the substrate 2 may be a silicon substrate, a germanium substrate or other suitable substrates. In this embodiment, the substrate 2 is preferably made of P-type silicon.

[0124] Specifically, the epitaxial layer 3 is formed on the substrate 2 by a vapor phase epitaxial growth method or other suitable epitaxial methods. The material of the epitaxial layer 3 includes N-type silicon or other suitable materials.

[0125] As an example, the conductivity types of the substrate 2 and the epitaxial layer 3 may also be N-type and P-type, respectively.

[0126] Specifically, forming the trench gate structure 30 includes the following steps:

[0127] like Figure 3 As shown, a hard mask layer 307 is formed on the upper surface of the epitaxial layer 3 by vapor deposition or a suitable method, and the hard mask layer 307 is patterned by photolithography, etching and other processes to obtain an opening in the hard mask layer 307, the bottom of the opening exposes the upper surface of the epitaxial layer 3, and then the epitaxial layer 3 is etched using the patterned hard mask layer 307 as a mask to form a gate trench 31.

[0128] In this embodiment, a voltage-resistant trench 33 is also formed simultaneously. The voltage-resistant trench 33 is spaced apart from the gate trench 31 by a preset distance in the horizontal direction.

[0129] As an example, the hard mask layer 307 includes a first oxide layer 304, a nitride layer 305 and a second oxide layer 306 stacked in sequence in a vertical direction, the first oxide layer 304 is made of silicon dioxide or other suitable materials, the nitride layer 305 is made of silicon nitride or other suitable materials, and the second oxide layer 306 is made of silicon dioxide or other suitable materials.

[0130] It should be noted that in other embodiments, the hard mask layer 307 may also adopt a single-layer structure or other suitable multi-layer material layer combination, which is not limited to this embodiment.

[0131] As an example, the gate trench 31 and the voltage-resistant trench 33 are formed by wet etching and / or dry etching, or other suitable processes.

[0132] like Figure 4 As shown, a field plate material layer 308 is grown on the upper surface of the epitaxial layer 3, the inner wall of the gate trench 31 and the inner wall of the voltage-resistant trench 33 by using a thermal growth field oxygen method or other suitable method, and the field plate material layer 308 does not completely fill the gate trench 31 and the voltage-resistant trench 33. The field plate material layer 308 can be made of silicon oxide or other suitable insulating materials.

[0133] like Figure 5 As shown, a first conductive material layer 316 is formed, and the first conductive material layer 316 covers the field plate material layer 308 and fills the gate trench 31 and the voltage-resistant trench 33 .

[0134] Specifically, the first conductive material layer 316 is formed on the upper surface of the field plate material layer 308 by chemical vapor deposition, physical vapor deposition or other suitable methods. The first conductive material layer 316 may be made of N-type polysilicon or other suitable materials.

[0135] like Figure 6As shown, wet etching and / or dry etching, or other suitable processes are used to remove the portion of the first conductive material layer 316 outside the gate trench 31 and the voltage-resistant trench 33 .

[0136] Specifically, in the gate trench 31 , the remaining first conductive material layer 316 serves as the shielding gate layer 313 . In the voltage-resistant trench 33 , the remaining first conductive material layer 316 serves as the third conductive layer 333 .

[0137] As an example, the upper surfaces of the shielding gate layer 313 and the third conductive layer 333 are on the same level as the upper surface of the epitaxial layer 3 .

[0138] like Figure 7 As shown, wet etching and / or dry etching, or other suitable processes are used to etch the field plate material layer 308 to obtain the field plate 301 and the insulating layer 321, and to form a first control gate trench 314 and a second control gate trench 315 in the gate trench 31, and to form a first voltage-resistant trench 334 and a second voltage-resistant trench 335 in the voltage-resistant trench 33.

[0139] Specifically, the first control gate groove 314 and the second control gate groove 315 are respectively located on both sides of the shielding gate layer 313, and the bottom surfaces of the first control gate groove 314 and the second control gate groove 315 are higher than the bottom surface of the shielding gate layer 313; the first voltage-resistant groove 334 and the second voltage-resistant groove 335 are respectively located on both sides of the third conductive layer 333, and the bottom surfaces of the first control voltage-resistant groove 334 and the second voltage-resistant groove 335 are higher than the bottom surface of the shielding gate layer 313.

[0140] like Figure 8 As shown, a gate dielectric layer 324 is formed, and the gate dielectric layer 324 covers the inner wall of the first control gate trench 314 and the inner wall of the second control gate trench 315, but does not fill the first control gate trench 314 and the second control gate trench 315; the gate dielectric layer 324 covers the inner wall of the first voltage-resistant trench 334 and the inner wall of the second voltage-resistant trench 335, but does not fill the first voltage-resistant trench 334 and the second voltage-resistant trench 335.

[0141] Specifically, the gate dielectric layer 324 may include silicon oxide or other suitable materials, and the method of forming the gate dielectric layer 324 includes a dry oxygen growth method or other suitable methods.

[0142] like Fig. 9 As shown, a second conductive material layer 317 is formed on the surface of the gate dielectric layer 324 by chemical vapor deposition, physical vapor deposition or other suitable methods.

[0143] As an example, the material of the second conductive material layer 317 includes N-type polysilicon or other suitable materials.

[0144] like Fig.10 As shown, chemical mechanical polishing or other appropriate methods are used to remove the gate dielectric layer 324 and the second conductive material layer 317 located outside the gate trench 31 and the voltage-resistant trench 33 .

[0145] Specifically, the remaining portion of the gate dielectric layer 324 located on the inner wall of the first control gate trench 314 serves as the first gate dielectric layer 302, the remaining portion of the gate dielectric layer 324 located on the inner wall of the second control gate trench 315 serves as the second gate dielectric layer 303, the remaining portion of the second conductive material layer 317 located in the first control gate trench 314 serves as the first control gate layer 311, and the portion of the second conductive material layer 317 located in the second control gate trench 315 serves as the second control gate layer 312.

[0146] Specifically, the remaining portion of the gate dielectric layer 324 located on the inner wall of the first voltage-resistant groove 334 serves as the first isolation layer 322, the remaining portion of the gate dielectric layer 324 located on the inner wall of the second voltage-resistant groove 335 serves as the second isolation layer 323, the remaining portion of the second conductive material layer 317 located in the first voltage-resistant groove 334 serves as the first conductive layer 331, and the remaining portion of the second conductive material layer 317 located in the second voltage-resistant groove 335 serves as the second conductive layer 332.

[0147] Please see again Fig.11 , perform step S3 and step S4: form a second conductive type body region 34 on the top of the epitaxial layer 3, the body region 34 is distributed on the left and right sides of the gate trench 31; and form a first conductive type source region 35 on the top of the body region 34.

[0148] In this embodiment, the body region 34 is also distributed on both sides of the voltage-resistant trench 33, and the portion of the body region 34 distributed on both sides of the voltage-resistant trench 33 is not provided with the source region 35. That is, for the gate trench 31 adjacent to the voltage-resistant trench 33, the source region 35 is formed only on one side of the gate trench 31.

[0149] Specifically, boron or other suitable impurities are implanted into the left and right sides of the gate trench 31 and the voltage-resistant trench 33 at the top of the epitaxial layer 3 , and the second conductive type body region 34 is formed after annealing.

[0150] Specifically, arsenic or other suitable impurities are implanted into the top of the body region 34 on the side of the gate trench 31 that is not adjacent to the voltage-resistant trench 33 , and the first conductive type source region 35 is formed after annealing.

[0151] Specifically, the bottom surface of the body region 34 is not lower than the bottom surfaces of the first control gate layer 311 , the second control gate layer 312 , the first conductive layer 331 and the second conductive layer 332 , and the bottom surface of the source region 35 is not lower than the bottom surface of the body region 34 .

[0152] Please see again Fig.12 , execute the step S5: sequentially form an interlayer dielectric layer 4, a source layer 5 and a gate layer 6 on the epitaxial layer 3, form a drain layer 1 at the bottom of the substrate 2, and form a first contact hole 41, a second contact hole 42, a third contact hole 43, a fourth contact hole 44, a fifth contact hole 45, a sixth contact hole 46, a seventh contact hole 47, an eighth contact hole 48 and a ninth contact hole 49 that penetrate the interlayer dielectric layer 4 in a vertical direction.

[0153] Specifically, the interlayer dielectric layer 4 covers the upper surface of the epitaxial layer 3, the trench gate structure 30 and the voltage-resistant structure 32, the first control gate layer 311 and the second control gate layer 312 are electrically connected to the gate layer 6 through the first contact hole 41 and the second contact hole 42 respectively, and the shielding gate layer 313 is electrically connected to the source layer 5 through the third contact hole 43; the source region 35 is electrically connected to the source layer 5 through the fourth contact hole 44, and the first conductive layer 331, the second conductive layer 332, the third conductive layer 333, the body region 34 on the left side of the voltage-resistant trench 33 and the body region 34 on the right side of the voltage-resistant trench 33 are electrically connected to the source layer 5 through the fifth contact hole 45, the seventh contact hole 47, the sixth contact hole 46, the eighth contact hole 48 and the ninth contact hole 49 respectively.

[0154] Specifically, the fourth contact hole 44 passes through the source region 35 and extends to the body region 34 .

[0155] As an example, a method of forming the interlayer dielectric layer 4 includes chemical vapor deposition or other suitable methods.

[0156] As an example, a method of forming the source layer 5 and the gate layer 6 includes sputtering or other suitable methods.

[0157] As an example, the material of the source electrode layer 5 and the drain electrode layer 1 includes any one of metals such as copper, aluminum, nickel, or other suitable metals and alloys.

[0158] As an example, the material of the gate layer 6 includes any one of metals and alloys such as tantalum, tungsten, nickel, tantalum nitride, titanium nitride, or other suitable metals or alloys.

[0159] The manufacturing method of the power switch device structure of this embodiment adopts basically the same process steps to form the trench gate structure 30 and the voltage-resistant structure 32, which differ only in the potential contact connection, and improves the device performance without increasing the process difficulty. Among them, the trench gate structure 30 can reduce the overlapping area of ​​the device gate and drain, thereby reducing the parasitic overlapping capacitance Cgd between the drain and the gate; the voltage-resistant structure 32 can increase the overlapping area of ​​the drain and source, thereby increasing the drain-source capacitance Cds. The combination of the two structures not only ensures a lower gate-drain capacitance Cgd, but also increases the drain-source capacitance Cds of the device, thereby enhancing the ability to resist drain voltage shock. In addition, the second conductive type body region 34 is formed on the top of the epitaxial layer 3 on the left and right sides of the voltage-resistant trench 33, which can form a PN junction with the first conductive type epitaxial layer 3, thereby improving the voltage-resistant capability of the high-performance power switch device.

[0160] In summary, a power switch device structure and a manufacturing method thereof of the present invention electrically connects the control gate layer in the gate trench to the gate of the device, and electrically connects the shielding gate layer to the source of the device, thereby reducing the gate-drain overlap area of ​​the device, thereby reducing the gate-drain capacitance Cgd. In addition, by electrically connecting the first conductive layer, the second conductive layer and the third conductive layer in the voltage-resistant trench adjacent thereto to the source of the device, the source-drain overlap area is increased, thereby increasing the source-drain capacitance Cds, thereby increasing the device's ability to resist drain voltage oscillation; in addition, the present invention forms a second conductive type body region on the top of the epitaxial layer on the left and right sides of the voltage-resistant trench, and electrically connects the second conductive type body region to the source of the device. Under the voltage-resistant condition, the second conductive type body region and the first conductive type epitaxial layer are reversely biased to form a depletion layer, reducing the electric field peak at the bottom of the trench, thereby improving the voltage-resistant capability of the device; and the trench gate structure and the voltage-resistant structure of the power switch device structure and the manufacturing method thereof of the present invention have the same process steps, and are only different in potential contact connection, which improves the device performance without increasing the process difficulty. Therefore, the present invention effectively overcomes various disadvantages of the prior art without increasing the difficulty of the process, and has a high industrial utilization value.

[0161] The above embodiments are merely illustrative of the principles and effects of the present invention, and are not intended to limit the present invention. Anyone familiar with the art may modify or alter the above embodiments without departing from the spirit and scope of the present invention. Therefore, all equivalent modifications or alterations made by a person of ordinary skill in the art without departing from the spirit and technical concept disclosed by the present invention shall still be covered by the claims of the present invention.

Claims

1. A power switch device structure, characterized in that: include: A stacked structure, comprising a drain layer, a substrate, a first conductivity type epitaxial layer, an interlayer dielectric layer, a source layer and a gate layer stacked in sequence in a vertical direction; A trench gate structure, comprising a gate trench and a field plate located in the gate trench, a first control gate layer, a second control gate layer, a shield gate layer, a first gate dielectric layer and a second gate dielectric layer, wherein the gate trench opens from the top surface of the epitaxial layer and extends toward the bottom surface of the epitaxial layer, but does not penetrate the bottom surface of the epitaxial layer; the field plate is located at the bottom of the gate trench; the first control gate layer, the second control gate layer and the shield gate layer are all located above the field plate, and the shield gate layer is located between the first control gate layer and the second control gate layer in the horizontal direction, the bottom surfaces of the first control gate layer and the second control gate layer are both higher than the bottom surface of the shield gate, the first control gate layer and the second control gate layer are electrically connected to the gate layer through a first contact hole and a second contact hole respectively, and the shield gate layer is electrically connected to the source layer through a third contact hole; the first gate dielectric layer surrounds the side and bottom of the first control gate layer, and the second gate dielectric layer surrounds the side and bottom of the second control gate layer; A second conductive type body region, located on the top of the epitaxial layer and distributed on the left and right sides of the trench gate structure, and the bottom surface of the body region is not lower than the bottom surfaces of the first control gate layer and the second control gate layer; A first conductive type source region is located on the top of the body region and is electrically connected to the source layer through a fourth contact hole, and the bottom surface of the source region is not lower than the bottom surface of the body region; the power switching device structure also includes a voltage-resistant structure, the voltage-resistant structure includes a voltage-resistant groove and an insulating layer, a first conductive layer, a second conductive layer, a third conductive layer, a first isolation layer and a second isolation layer located in the voltage-resistant groove, and the body region is also distributed on both sides of the voltage-resistant groove, wherein the parts of the body region distributed on both sides of the voltage-resistant groove serve as components of the voltage-resistant structure, the voltage-resistant groove opens from the top surface of the epitaxial layer and extends toward the bottom surface of the epitaxial layer, but does not penetrate the bottom surface of the epitaxial layer, and the voltage-resistant groove is The insulating layer is located at the bottom of the voltage-resistant groove; the first conductive layer, the second conductive layer and the third conductive layer are all located above the insulating layer, and the third conductive layer is located between the first conductive layer and the second conductive layer in the horizontal direction, and the bottom surfaces of the first conductive layer and the second conductive layer are higher than the bottom surface of the third conductive layer; the first conductive layer, the second conductive layer and the third conductive layer are electrically connected to the source layer through the fifth contact hole, the sixth contact hole and the seventh contact hole, respectively; the first isolation layer surrounds the side and bottom of the first conductive layer, and the second isolation layer surrounds the side and bottom of the second conductive layer.

2. The power switch device structure according to claim 1, characterized in that: The material of the first control gate layer includes polysilicon, the material of the second control gate layer includes polysilicon, and the material of the shield gate layer includes polysilicon.

3. The power switch device structure according to claim 1, characterized in that: The fourth contact hole penetrates the source region in a vertical direction and extends downward into the body region.

4. The power switch device structure according to claim 1, characterized in that: The portion of the body region distributed on both sides of the voltage-resistant groove is not provided with the source region, the bottom surface of the body region is not lower than the bottom surfaces of the first conductive layer and the second conductive layer, and the portion of the body region distributed on both sides of the voltage-resistant structure is electrically connected to the source layer through the eighth contact hole and the ninth contact hole respectively.

5. The power switch device structure according to claim 1, characterized in that: The material of the first conductive layer includes polysilicon, the material of the second conductive layer includes polysilicon, and the material of the third conductive layer includes polysilicon.

6. The power switch device structure according to claim 1, characterized in that: The first conductivity type is N type, and the second conductivity type is P type.

7. A method for manufacturing a power switch device structure, characterized in that: The following steps are involved: Providing a substrate, and forming a first conductivity type epitaxial layer on the substrate; A trench gate structure is formed, wherein the trench gate structure includes a gate trench and a field plate located in the gate trench, a first control gate layer, a second control gate layer, a shield gate layer, a first gate dielectric layer and a second gate dielectric layer, wherein the gate trench opens from the top surface of the epitaxial layer and extends toward the bottom surface of the epitaxial layer, but does not penetrate the bottom surface of the epitaxial layer; the field plate is located at the bottom of the gate trench; the first control gate layer, the second control gate layer and the shield gate layer are all located above the field plate, and the shield gate layer is located between the first control gate layer and the second control gate layer in the horizontal direction, the bottom surfaces of the first control gate layer and the second control gate layer are both higher than the bottom surface of the shield gate, the first gate dielectric layer surrounds the side and bottom of the first control gate layer, and the second gate dielectric layer surrounds the side and bottom of the second control gate layer; Forming a second conductive type body region on the top of the epitaxial layer, wherein the bottom surface of the body region is not lower than the bottom surfaces of the first control gate layer and the second control gate layer, and the body region is distributed on the left and right sides of the gate trench; forming a first conductivity type source region on top of the body region; An interlayer dielectric layer, a source layer and a gate layer are sequentially formed on the epitaxial layer, and a first contact hole, a second contact hole, a third contact hole and a fourth contact hole are formed in the vertical direction penetrating the interlayer dielectric layer, the interlayer dielectric layer covers the upper surface of the epitaxial layer and the trench gate structure, the first control gate layer and the second control gate layer are electrically connected to the gate layer through the first contact hole and the second contact hole respectively, the shielding gate layer is electrically connected to the source layer through the third contact hole; the source region is electrically connected to the source layer through the fourth contact hole, wherein the method for manufacturing the power switch device structure also includes the step of forming a voltage-resistant structure, the voltage-resistant structure includes a voltage-resistant trench and an insulating layer, a first conductive layer, a second conductive layer, a third conductive layer, a first isolation layer and a second isolation layer located in the voltage-resistant trench, the body region is also distributed on both sides of the voltage-resistant trench, wherein the portion of the body region distributed on both sides of the voltage-resistant trench is a component of the voltage-resistant structure, and the voltage-resistant trench is formed from the top surface of the epitaxial layer The gate electrode is provided with an opening and extends toward the bottom surface of the epitaxial layer, but does not penetrate the bottom surface of the epitaxial layer, and the voltage-resistant groove is spaced a preset distance from the gate groove in the horizontal direction; the insulating layer is located at the bottom of the voltage-resistant groove; the first conductive layer, the second conductive layer and the third conductive layer are all located above the insulating layer, and the third conductive layer is located between the first conductive layer and the second conductive layer in the horizontal direction, and the bottom surfaces of the first conductive layer and the second conductive layer are higher than the bottom surface of the third conductive layer; the method for manufacturing the power switching device structure also includes the step of forming a fifth contact hole, a sixth contact hole and a seventh contact hole penetrating the interlayer dielectric layer in the vertical direction, and the first conductive layer, the second conductive layer and the third conductive layer are electrically connected to the source layer through the fifth contact hole, the sixth contact hole and the seventh contact hole respectively; the first isolation layer surrounds the side and bottom of the first conductive layer, and the second isolation layer surrounds the side and bottom of the second conductive layer.

8. The method for manufacturing a power switch device structure according to claim 7, characterized in that: Forming the trench gate structure includes: forming the gate trench in the epitaxial layer; forming a field plate material layer, wherein the field plate material layer covers the upper surface of the epitaxial layer and the inner wall of the gate trench but does not completely fill the gate trench; forming a first conductive material layer, wherein the first conductive material layer covers the field plate material layer and fills the gate trench; removing the portion of the first conductive material layer outside the gate trench, so that the remaining portion of the first conductive material layer is flush with the upper surface of the epitaxial layer, and the portion of the first conductive material layer inside the field plate material layer serves as the shielding gate layer; Etching the field plate material layer to obtain the field plate, and forming a first control gate trench and a second control gate trench in the gate trench, wherein the first control gate trench and the second control gate trench are respectively located on both sides of the shielding gate layer, and the bottom surfaces of the first control gate trench and the second control gate trench are both higher than the bottom surface of the shielding gate layer; forming a gate dielectric layer, wherein the gate dielectric layer covers an inner wall of the first control gate trench and an inner wall of the second control gate trench, but does not completely fill the first control gate trench and the second control gate trench; A second conductive material layer is formed on the surface of the gate dielectric layer, and portions of the gate dielectric layer and the second conductive material layer located outside the gate trench are removed; a portion of the gate dielectric layer located on an inner wall of the first control gate trench serves as the first gate dielectric layer, a portion of the gate dielectric layer located on an inner wall of the second control gate trench serves as the second gate dielectric layer, a portion of the second conductive material layer located in the first control gate trench serves as the first control gate layer, and a portion of the second conductive material layer located in the second control gate trench serves as the second control gate layer.

9. The method for manufacturing a power switch device structure according to claim 8, characterized in that: The material of the first conductive material layer includes polysilicon, and the material of the second conductive material layer includes polysilicon.

10. The method for manufacturing a power switch device structure according to claim 7, characterized in that: Forming the body region and the source region includes: Doping first type impurities into the top of the epitaxial layer on the left and right sides of the gate trench to obtain the second conductive type body region; Second type impurities are doped into the top of the body region at one side of the gate trench to obtain the first conductive type source region.

11. The method for manufacturing a power switch device structure according to claim 8, characterized in that: Forming the first contact hole, the second contact hole, the third contact hole and the fourth contact hole includes: forming the first contact hole, the second contact hole, the third contact hole and the fourth contact hole in the interlayer dielectric layer, and filling the first contact hole, the second contact hole, the third contact hole and the fourth contact hole with conductive material.

12. The method for manufacturing a power switch device structure according to claim 7, characterized in that: The fourth contact hole penetrates the source region in a vertical direction and extends downward into the body region.

13. The method for manufacturing a power switch device structure according to claim 7, characterized in that: The method for forming the field plate includes a thermal oxidation method, and the method for forming the first gate dielectric layer and the second gate dielectric layer includes a dry oxygen growth method.

14. The method for manufacturing a power switch device structure according to claim 7, characterized in that: The method of forming the shield gate layer, the first control gate layer and the second control gate layer includes chemical vapor deposition.

15. The method for manufacturing a power switch device structure according to claim 7, characterized in that: The voltage-resistant structure and the gate trench are manufactured synchronously.

16. The method for manufacturing a power switch device structure according to claim 7, characterized in that: The portion of the body region distributed on both sides of the voltage-resistant structure is not provided with the source region; the method for manufacturing the power switching device structure also includes the step of forming an eighth contact hole and a ninth contact hole penetrating the interlayer dielectric layer in a vertical direction, and the portion of the body region distributed on both sides of the voltage-resistant structure is electrically connected to the source layer through the eighth contact hole and the ninth contact hole respectively.

17. The method for manufacturing a power switch device structure according to claim 7, characterized in that: The material of the first conductive layer includes polysilicon, the material of the second conductive layer includes polysilicon, and the material of the third conductive layer includes polysilicon.

18. The method for manufacturing a power switch device structure according to claim 7, characterized in that: The first conductivity type is N type, and the second conductivity type is P type.

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