Method, device and computer-readable medium for generating cyclic redundancy check code

Abstract

The present application provides a cyclic redundancy check code generation scheme, in which a first register and a second register are added for each bit of the target cyclic redundancy check code to be generated, wherein the first parameter of the first register is used to mark the bit of the data participating in the exclusive-OR logic operation, and the second parameter of the second register is used to mark the bit of the current cyclic redundancy check code participating in the exclusive-OR logic operation, thereby adjusting the bits participating in the operation by changing the parameters in the first register and the second register when the standard of the cyclic redundancy check code changes, so that it is suitable for the changed standard.

Description

Technical Field

[0001] The present application relates to the field of information technology, and in particular to a cyclic redundancy check code generation method, device and computer-readable medium. Background Art

[0002] Cyclic Redundancy Check (CRC) is a coding technology that generates a short fixed-bit check code based on a piece of data of indefinite length. It is mainly used to detect or verify errors that may occur in data after transmission or storage. The generated check code is calculated and attached to the data before transmission or storage, and the receiver checks to determine whether the data has changed.

[0003] In each processing cycle of generating a cyclic redundancy check code, the target cyclic redundancy check code (i.e., the cyclic redundancy check code obtained by processing in the current processing cycle) is calculated based on the current cyclic redundancy check code (i.e., the cyclic redundancy check code obtained by processing in the previous cycle). Taking the 8-bit cyclic redundancy check code generated by the polynomial x^8+x^6+x^3+1 as an example, assuming that 4 bits of input data are processed in each cycle, represented as din[3:0], the current cyclic redundancy check code is represented as c[7:0], and the target cyclic redundancy check code obtained by processing in the current cycle is represented as newcrc[7:0]. At this time, the value of each bit in newcrc[7:0] can be expressed by the following expression:

[0004]

[0005]

[0006]

[0007]

[0008]

[0009]

[0010]

[0011]

[0012] in, represents an exclusive-OR logic operation, newcrc[i], c[i], and din[i] represent the target cyclic redundancy check code, the current cyclic redundancy check code, and the i-th bit of the input data, respectively. In actual scenarios, different standard cyclic redundancy check codes use different generating polynomials. For example, the generating polynomial used by the 32-bit cyclic redundancy check code used in Ethernet is x^32+x^26+x^23+x^22+x^16+x^12+x^11+x^10+x^8+x^7+x^5+x^4+x^2+x^1+1, and the generating polynomial used by the 16-bit cyclic redundancy check code of the X25 standard is x^16+x^12+x^5+1.

[0013] In actual cyclic redundancy check code application scenarios, the circuit for calculating the cyclic redundancy check code is usually determined based on a pre-defined polynomial and bit width. Different generating polynomials will require different circuits to generate. Once the circuit is determined, it cannot be used to generate cyclic redundancy check codes of other standards. However, in some application scenarios, it is necessary to support many kinds of standard cyclic redundancy check codes. These different standard cyclic redundancy check codes will use different generating polynomials. Therefore, the existing method can only support one fixed standard cyclic redundancy check code, and cannot simultaneously support multiple cyclic redundancy check codes of different standards. Summary of the invention

[0014] An object of the present application is to provide a method, device and computer-readable medium for generating a cyclic redundancy check code, so as to solve the problem that multiple cyclic redundancy check codes of different standards cannot be supported simultaneously.

[0015] In an embodiment of the present application, a method for generating a cyclic redundancy check code is provided, the method comprising:

[0016] Obtain a first parameter of a first register and a second parameter of a second register corresponding to the i-th bit of a target cyclic redundancy check code to be generated, wherein the first parameter is used to mark the bit of data participating in an exclusive OR logic operation, and the second parameter is used to mark the bit of a current cyclic redundancy check code participating in an exclusive OR logic operation;

[0017] Determine a valid data bit and a valid check bit according to the first parameter and the second parameter, wherein the valid data bit is a bit of data participating in an exclusive OR logic operation, and the valid check bit is a bit of a current cyclic redundancy check code participating in the exclusive OR logic operation;

[0018] Determine the values ​​of the valid data bit and the valid check bit according to the input data and the current cyclic redundancy check code, and perform an exclusive OR logic operation on the values ​​of the valid data bit and the valid check bit to generate the value of the i-th bit of the target cyclic redundancy check code;

[0019] The target cyclic redundancy check code is determined according to values ​​of all bits of the target cyclic redundancy check code.

[0020] The present application also provides a data storage method, which includes:

[0021] Obtain a first parameter of a first register and a second parameter of a second register corresponding to the i-th bit of a target cyclic redundancy check code to be generated, wherein the first parameter is used to mark the bit of data participating in an exclusive OR logic operation, and the second parameter is used to mark the bit of a current cyclic redundancy check code participating in an exclusive OR logic operation;

[0022] Determine a valid data bit and a valid check bit according to the first parameter and the second parameter, wherein the valid data bit is a bit of data participating in an exclusive OR logic operation, and the valid check bit is a bit of a current cyclic redundancy check code participating in the exclusive OR logic operation;

[0023] Determine the values ​​of the valid data bit and the valid check bit according to the input data and the current cyclic redundancy check code, and perform an exclusive OR logic operation on the values ​​of the valid data bit and the valid check bit to generate the value of the i-th bit of the target cyclic redundancy check code;

[0024] Determining the target cyclic redundancy check code according to the values ​​of all bits of the target cyclic redundancy check code;

[0025] The data and the target cyclic redundancy check code are sent to a storage node, so that the storage node stores the data after completing verification of the data according to the target cyclic redundancy check code.

[0026] The present application provides a device for generating a cyclic redundancy check code, the device comprising:

[0027] A parameter determination module, used to obtain a first parameter of a first register and a second parameter of a second register corresponding to the i-th bit of a target cyclic redundancy check code to be generated, wherein the first parameter is used to mark the bit of the data participating in the XOR logic operation, and the second parameter is used to mark the bit of the current cyclic redundancy check code participating in the XOR logic operation;

[0028] A logic operation module, used to determine the valid data bits and valid check bits participating in the operation according to the first parameter and the second parameter, and determine the values ​​of the valid data bits and the valid check bits according to the input data and the current cyclic redundancy check code, and perform an exclusive OR logic operation on the values ​​of the valid data bits and the valid check bits to generate the value of the i-th bit of the target cyclic redundancy check code, wherein the valid data bits are the bits of the data participating in the exclusive OR logic operation, and the valid check bits are the bits of the current cyclic redundancy check code participating in the exclusive OR logic operation;

[0029] A generating module is used to determine the target cyclic redundancy check code according to the values ​​of all bits of the target cyclic redundancy check code.

[0030] The present application also provides a data storage device, which includes:

[0031] A parameter determination module, used to obtain a first parameter of a first register and a second parameter of a second register corresponding to the i-th bit of a target cyclic redundancy check code to be generated, wherein the first parameter is used to mark the bit of the data participating in the XOR logic operation, and the second parameter is used to mark the bit of the current cyclic redundancy check code participating in the XOR logic operation;

[0032] A logic operation module, used to determine the valid data bits and valid check bits participating in the operation according to the first parameter and the second parameter, and determine the values ​​of the valid data bits and the valid check bits according to the input data and the current cyclic redundancy check code, and perform an exclusive OR logic operation on the values ​​of the valid data bits and the valid check bits to generate the value of the i-th bit of the target cyclic redundancy check code, wherein the valid data bits are the bits of the data participating in the exclusive OR logic operation, and the valid check bits are the bits of the current cyclic redundancy check code participating in the exclusive OR logic operation;

[0033] A generating module, configured to determine the target cyclic redundancy check code according to the values ​​of all bits of the target cyclic redundancy check code;

[0034] The sending module is used to send the data and the target cyclic redundancy check code to the storage node, so that the storage node stores the data after completing the verification of the data according to the target cyclic redundancy check code.

[0035] Some embodiments of the present application provide another cyclic redundancy check code generation device, the device comprising a data register, a current check code register, a target check code register and N groups of generation circuits, wherein the value of N is the same as the bit width of the target check code register and the current check code register;

[0036] Each group of generating circuits includes a first register, a second register, an XOR gate circuit and a plurality of AND gate circuits, the bit width of the first register is the same as the bit width of the data register, and the bit width of the second register is the same as the bit width of the current check code register;

[0037] The input end of the AND gate circuit inputs the j-th bit of the data register and the j-th bit of the first register, or inputs the k-th bit of the current check code register and the k-th bit of the second register, the output end of the AND gate circuit is connected to the input end of the XOR gate circuit, and the output end of the XOR gate circuit is output to the i-th bit of the target check code register.

[0038] Some embodiments of the present application provide another cyclic redundancy check code generation device, the device comprising a data register, a current check code register, a target check code register and N groups of generation circuits, wherein the value of N is the same as the bit width of the target check code register and the current check code register;

[0039] Each group of generating circuits includes a first register, a second register, a plurality of AND gate circuits and a multi-level XOR gate circuit, the bit width of the first register is the same as the bit width of the data register, and the bit width of the second register is the same as the bit width of the current check code register;

[0040] The input end of the AND gate circuit inputs the j-th bit of the data register and the j-th bit of the first register, or inputs the k-th bit of the current check code register and the k-th bit of the second register, the output end of the AND gate circuit is connected to the input end of the first-level XOR gate circuit, the output end of each level of XOR gate circuit is connected to the input end of the next level of XOR gate circuit, and the input end of the last level of XOR gate circuit is output to the i-th bit of the target check code register.

[0041] Some embodiments of the present application also provide a computing device, wherein the device includes a memory for storing computer program instructions and a processor for executing computer program instructions, wherein when the computer program instructions are executed by the processor, the device is triggered to execute the aforementioned cyclic redundancy check code generation method or data storage method.

[0042] Some other embodiments of the present application further provide a computer-readable medium having computer program instructions stored thereon, wherein the computer-readable instructions can be executed by a processor to implement the cyclic redundancy check code generation method or the data storage method.

[0043] In a cyclic redundancy check code generation scheme provided in an embodiment of the present application, firstly, the first parameter of the first register and the second parameter of the second register corresponding to the i-th bit of the target cyclic redundancy check code to be generated are obtained, and the valid data bit and the valid check bit are determined according to the first parameter and the second parameter, and then the values ​​of the valid data bit and the valid check bit are determined according to the input data and the current cyclic redundancy check code, and the values ​​of the valid data bit and the valid check bit are subjected to an XOR logic operation to generate the value of the i-th bit of the target cyclic redundancy check code, and the target cyclic redundancy check code can be determined after the values ​​of all the bits are generated. Since the present scheme adds a first register and a second register for each bit of the target cyclic redundancy check code to be generated, wherein the first parameter of the first register is used to mark the bit of the data participating in the XOR logic operation, and the second parameter of the second register is used to mark the bit of the current cyclic redundancy check code participating in the XOR logic operation, when the standard of the cyclic redundancy check code changes, the bits participating in the operation can be adjusted by changing the parameters in the first register and the second register to make them suitable for the changed standard. BRIEF DESCRIPTION OF THE DRAWINGS

[0044] Other features, objects and advantages of the present application will become more apparent by reading the detailed description of non-limiting embodiments made with reference to the following drawings:

[0045] Figure 1 A processing flow chart of a method for generating a cyclic redundancy check code provided in an embodiment of the present application;

[0046] Figure 2 A circuit implementation diagram for calculating the i-th bit of a cyclic redundancy check code in an embodiment of the present application;

[0047] Figure 3 Another circuit implementation diagram for calculating the i-th bit of a cyclic redundancy check code in an embodiment of the present application;

[0048] Figure 4 A schematic diagram of the structure of a cyclic redundancy check code generation device provided in an embodiment of the application;

[0049] Figure 5 Another structural schematic diagram of a cyclic redundancy check code generation device provided in an embodiment of the application;

[0050] Figure 6 A schematic diagram of the structure of a computing device for realizing cyclic redundancy check code generation provided in an embodiment of the present application;

[0051] The same or similar reference numerals in the drawings represent the same or similar components. DETAILED DESCRIPTION

[0052] Embodiments of the present invention are described in detail below, examples of which are shown in the accompanying drawings, wherein the same or similar reference numerals throughout represent the same or similar elements or elements having the same or similar functions. The embodiments described below with reference to the accompanying drawings are exemplary and are only used to explain the present invention, and cannot be interpreted as limiting the present invention.

[0053] It will be understood by those skilled in the art that, unless expressly stated, the singular forms "one", "said", and "the" used herein may also include plural forms. It should be further understood that the term "comprising" used in the specification of the present invention refers to the presence of the features, integers, steps, operations, elements and / or components, but does not exclude the presence or addition of one or more other features, integers, steps, operations, elements, components and / or groups thereof. It should be understood that when we refer to an element as being "connected" or "coupled" to another element, it may be directly connected or coupled to the other element, or there may be intermediate elements. In addition, the "connection" or "coupling" used herein may include wireless connection or wireless coupling. The term "and / or" used herein includes all or any unit and all combinations of one or more associated listed items.

[0054] An embodiment of the present application provides a method for generating a cyclic redundancy check code. The method adds a first register and a second register for each bit of the target cyclic redundancy check code to be generated, wherein the first parameter of the first register is used to mark the bit of the data participating in the exclusive OR logic operation, and the second parameter of the second register is used to mark the bit of the current cyclic redundancy check code participating in the exclusive OR logic operation. Therefore, when the standard of the cyclic redundancy check code changes, the parameters in the first register and the second register can be changed to adjust the bits participating in the operation to make it suitable for the changed standard.

[0055] Figure 1 The present invention shows a processing flow of a method for generating a cyclic redundancy check code provided in an embodiment of the present application. The method includes at least the following processing steps:

[0056] Step S101, obtaining a first parameter of a first register and a second parameter of a second register corresponding to the i-th bit of a target cyclic redundancy check code to be generated. Wherein, i represents any bit, for example, for an 8-bit target cyclic redundancy check code newcrc[7:0], it includes bits 0 to 7, namely newcrc[0], newcrc[1], newcrc[2], newcrc[3], newcrc[4], newcrc[5], newcrc[6] and newcrc[7]. For each bit of the target cyclic redundancy check code, a corresponding set of registers can be set. For example, if the target cyclic redundancy check code has 8 bits, 8 sets of registers can be set, and each set of registers includes a first register and a second register.

[0057] The first parameter of the first register is used to mark the bit of the data involved in the XOR logic operation, and the second parameter of the second register is used to mark the bit of the current cyclic redundancy check code involved in the XOR logic operation. Among them, the current cyclic redundancy check code is the cyclic redundancy check code obtained by the previous cycle processing, and the target cyclic redundancy check code is the cyclic redundancy check code obtained by the current processing cycle processing. Therefore, the number of bits of the current cyclic redundancy check code is consistent with the number of bits of the target cyclic redundancy check code. If the target cyclic redundancy check code has 8 bits, the current cyclic redundancy check code also has 8 bits.

[0058] In some embodiments of the present application, the bit width of the first register is the same as the bit width of the data participating in the XOR logic operation, and the bit width of the second register is the same as the bit width of the current cyclic redundancy check code participating in the XOR logic operation. For example, the input data is 4 bits, represented as din[3:0], and accordingly, the bit width of the first register can also be 4 bits. At this time, the value of the first register (i.e., the first parameter) is also 4 bits, which can be represented as Rd[3:0]. Similarly, if the previous cyclic redundancy check code is 8 bits, represented as c[7:0], the bit width of the second register can also be 8 bits. At this time, the value of the second register (i.e., the second parameter) is also 8 bits, which can be represented as Rc[7:0].

[0059] Step S102, determining valid data bits and valid check bits according to the first parameter and the second parameter. The valid data bits are bits of data participating in the XOR logic operation, that is, several bits marked by the first parameter in the data. When marking the bits of data participating in the XOR logic operation, the first parameter can also be used to determine which bits of the input data participate in the XOR logic operation in the current cycle, and these determined bits are valid data bits.

[0060] In some embodiments of the present application, the method for determining the valid data bit can be based on the value of each bit in the first parameter, that is, when the value of the j-th bit in the first parameter meets the preset condition, the j-th bit of the data is determined to be a valid data bit. Wherein, j represents any bit in the first parameter, for example, for the 4-bit first parameter Rd[3:0], it includes the following bits 0 to 3, Rd[0], Rd[1], Rd[2], Rd[3]. For the 0th bit in the 8-bit target cyclic redundancy check code newcrc[7:0], that is, newcrc[0], the first parameter of the corresponding first register is 2'b0101, that is, the binary value 0101. It can be seen that Rd[0]=1, Rd[1]=0, Rd[2]=1, Rd[3]=0. If the preset condition is that the value of this bit is 1, and the data input in the current cycle is represented as din[3:0], it can be determined that the valid data bits of the data are the 0th and 2nd bits, that is, din[0] and din[2].

[0061] The valid check bits are the bits of the current cyclic redundancy check code participating in the XOR logic operation, that is, the bits marked by the second parameter in the current cyclic redundancy check code. When marking the bits of the current cyclic redundancy check code participating in the XOR logic operation, the second parameter can be used to determine which bits of the current cyclic redundancy check code participate in the XOR logic operation in the current cycle, and these determined bits are the valid check bits.

[0062] In some embodiments of the present application, the method for determining the valid check bit can be based on the value of each bit in the second parameter, that is, when the value of the kth bit in the second parameter meets the preset condition, the kth bit of the data is determined to be a valid check bit. Wherein, k represents any bit in the second parameter, for example, for the 8-bit second parameter Rc[7:0], including the following 0th to 7th bits, Rc[0], Rc[1], Rc[2], Rc[3], Rc[4], Rc[5], Rc[6], Rc[7]. For the 0th bit in the 8-bit target cyclic redundancy check code newcrc[7:0], i.e., newcrc[0], the first parameter of the corresponding first register is 2'b01010000, i.e., the binary value 0101000. It can be seen that Rc[0]=0, Rc[1]=0, Rc[2]=0, Rc[3]=0, Rc[4]=1, Rc[5]=0, Rc[6]=1, Rc[7]=0. If the preset condition is that the value of the bit is 1, the current cyclic redundancy check code of the current cycle is expressed as c[7:0], then it can be determined that the valid check bits of the data are the 4th and 6th bits, i.e., c[4] and c[6].

[0063] Step S103, determining the values ​​of the valid data bits and the valid check bits according to the input data and the current cyclic redundancy check code, and performing an XOR logic operation on the values ​​of the valid data bits and the valid check bits to generate the value of the i-th bit of the target cyclic redundancy check code.

[0064] Step S104: determining the target cyclic redundancy check code according to the values ​​of all bits of the target cyclic redundancy check code.

[0065] Taking the 0th bit newcrc[0] in the aforementioned target cyclic redundancy check code newcrc[7:0] as an example, when the first parameter is 2'b0101 and the second parameter is 2'b01010000, the valid data bits of the data involved in the XOR logic operation are din[0] and din[2], and the valid check bits of the current cyclic redundancy check code involved in the XOR logic operation are c[4] and c[6]. It can be seen that in, Represents an exclusive-OR logic operation. After traversing and processing each bit of the target cyclic redundancy check code, the values ​​of all bits of the target cyclic redundancy check code are determined.

[0066] In actual scenarios, when determining the valid data and the valid check, the preset condition can be judged by AND logic operation, that is, before performing the XOR operation, the corresponding bits of the data and the first parameter, and the current cyclic redundancy check code and the corresponding bits of the second parameter are first ANDed. Thus, the value of the i-th bit of the target cyclic redundancy check code is:

[0067]

[0068]

[0069] in, represents an XOR logic operation, & represents an AND logic operation, Wd is the bit width of the first parameter and the input data, and Wc is the bit width of the second parameter and the current cyclic redundancy check code. Figure 2 A circuit implementation for calculating the value of the i-th bit is shown. Taking the aforementioned 8-bit target cyclic redundancy check code as an example, the value of its 0th bit is:

[0070]

[0071] After substituting the first parameter 2'b0101 and the second parameter 2'b01010000, the value of the 0th bit is:

[0072]

[0073] When the first and second parameters change, the valid data bits and valid check bits involved in the operation will also change. For example, when the first parameter of newcrc[0] is 2'b1101, the corresponding valid data bits are din[0], din[2], and din[3]. When the second parameter of newcrc[0] is 2'b01010011, the corresponding valid check bits are c[0], c[1], c[4], and c[6]. Similarly, the remaining bits of the target cyclic redundancy check code can be traversed to generate a complete target cyclic redundancy check code.

[0074] Therefore, by configuring different first parameters and second parameters for each bit of the target cyclic redundancy check code, and writing them into the first register and the second register respectively, different valid data bits and valid check bits can be determined, so as to construct different expressions for each bit of each target cyclic redundancy check code, which is applicable to different generating polynomials and supports cyclic redundancy check codes of different standards. For example, taking an 8-bit cyclic redundancy check code with a generating polynomial of x^8+x^6+x^3+1 as an example, for each bit of the target cyclic redundancy check code, the values ​​of the first parameter and the second parameter can be set as follows:

[0075] newcrc[0]:Rd[3:0]=2'b0101 Rc[7:0]=2'b01010000

[0076] newcrc[1]:Rd[3:0]=2'b1010 Rc[7:0]=2'b10100000

[0077] newcrc[2]:Rd[3:0]=2'b0100 Rc[7:0]=2'b01000000

[0078] newcrc[3]:Rd[3:0]=2'b1101 Rc[7:0]=2'b11010000

[0079] newcrc[4]:Rd[3:0]=2'b1010 Rc[7:0]=2'b10100001

[0080] newcrc[5]:Rd[3:0]=2'b0100 Rc[7:0]=2'b01000010

[0081] newcrc[6]:Rd[3:0]=2'b1101 Rc[7:0]=2'b11010100

[0082] newcrc[7]:Rd[3:0]=2'b1010 Rc[7:0]=2'b10101000

[0083] When it is necessary to support cyclic redundancy check codes of other standards, different first parameters and second parameters can be configured according to the corresponding generating polynomial, so that the device can generate the cyclic redundancy check code of the corresponding standard after obtaining the first parameter and the second parameter.

[0084] In some embodiments of the present application, when performing an XOR logic operation on the values ​​of the valid data bits and the valid check bits to generate the value of the i-th bit of the target cyclic redundancy check code, a multi-level processing method can be adopted, that is, performing a multi-level XOR logic operation on the values ​​of the valid data bits and the valid check bits to generate the value of the i-th bit of the target cyclic redundancy check code.

[0085] For example, taking the i-th bit newcrc[i] of the aforementioned target cyclic redundancy check code as an example, we can use Figure 3 The multi-stage processing method shown in the figure. The processing process divides the XOR logic operation into two levels. First, the values ​​of the valid data bits and valid check bits are divided into multiple groups, and the XOR logic operation is performed on the values ​​of the valid data bits and / or valid check bits in each group to determine the intermediate operation result of each group, and the intermediate operation result of each group is recorded as part_crc. Then, the XOR logic operation is performed on the intermediate operation results of all groups to generate the value of the i-th bit of the target cyclic redundancy check code.

[0086] Here, those skilled in the art should understand that the specific method of the above-mentioned hierarchical processing is only an example, and other existing or future methods that are applicable to the present invention should also be included in the protection scope of the present invention and are included here by reference. For example, more levels can be used, that is, the intermediate operation results of the previous level are grouped here and XOR logic operations are performed separately to obtain the intermediate operation results of the next level, until the value of the i-th bit of the target cyclic redundancy check code is obtained.

[0087] In addition, in order to improve processing efficiency, before obtaining the first parameter of the first register and the second parameter of the second register corresponding to the i-th bit of the target cyclic redundancy check code to be generated, the bit width of the input data can be increased so that the corresponding target cyclic redundancy check code can be calculated for more data within one cycle.

[0088] In other embodiments of the present application, the cyclic redundancy check code generation method can also be applied to cloud computing storage scenarios, so this embodiment can provide a data storage method, which uses the aforementioned generation method to generate a target cyclic redundancy check code corresponding to the data, and then sends the data and the target cyclic redundancy check code to a storage node. After receiving the data and the corresponding target cyclic redundancy check code, the storage node can verify the data according to the target cyclic redundancy check code, and store the data after completing the verification.

[0089] Based on the same inventive concept, an embodiment of the present application also provides a cyclic redundancy check code generation device and a data storage device, and the methods corresponding to the devices are respectively the cyclic redundancy check code generation method and the data storage method in the aforementioned embodiments, and the principles of solving the problems are similar to those of the methods.

[0090] A cyclic redundancy check code generation device provided in an embodiment of the present application adds a first register and a second register for each bit of a target cyclic redundancy check code to be generated, wherein the first parameter of the first register is used to mark the bit of the data participating in the exclusive OR logic operation, and the second parameter of the second register is used to mark the bit of the current cyclic redundancy check code participating in the exclusive OR logic operation. Therefore, when the standard of the cyclic redundancy check code changes, the parameters in the first register and the second register can be changed to adjust the bits participating in the operation to make it suitable for the changed standard.

[0091] Figure 4 The structure of a cyclic redundancy check code generation device provided in an embodiment of the present application is shown, including a parameter determination module 410, a logic operation module 420 and a generation module 430. The parameter determination module 410 is used to obtain the first parameter of the first register and the second parameter of the second register corresponding to the i-th bit of the target cyclic redundancy check code to be generated. The logic operation module 420 is used to determine the valid data bit and the valid check bit according to the first parameter and the second parameter, and then determine the value of the valid data bit and the valid check bit according to the input data and the current cyclic redundancy check code, and perform an exclusive OR logic operation on the value of the valid data bit and the valid check bit to generate the value of the i-th bit of the target cyclic redundancy check code. The generation module 430 is used to determine the target cyclic redundancy check code according to the values ​​of all bits of the target cyclic redundancy check code.

[0092] Wherein, i represents any bit. For example, for an 8-bit target cyclic redundancy check code newcrc[7:0], it includes bits 0 to 7, namely newcrc[0], newcrc[1], newcrc[2], newcrc[3], newcrc[4], newcrc[5], newcrc[6] and newcrc[7]. For each bit of the target cyclic redundancy check code, a corresponding set of registers can be set. For example, if the target cyclic redundancy check code has 8 bits, 8 sets of registers can be set, and each set of registers includes a first register and a second register.

[0093] The first parameter of the first register is used to mark the bit of the data involved in the XOR logic operation, and the second parameter of the second register is used to mark the bit of the current cyclic redundancy check code involved in the XOR logic operation. Among them, the current cyclic redundancy check code is the cyclic redundancy check code obtained by the previous cycle processing, and the target cyclic redundancy check code is the cyclic redundancy check code obtained by the current processing cycle processing. Therefore, the number of bits of the current cyclic redundancy check code is consistent with the number of bits of the target cyclic redundancy check code. If the target cyclic redundancy check code has 8 bits, the current cyclic redundancy check code also has 8 bits.

[0094] In some embodiments of the present application, the bit width of the first register is the same as the bit width of the data participating in the XOR logic operation, and the bit width of the second register is the same as the bit width of the current cyclic redundancy check code participating in the XOR logic operation. For example, the input data is 4 bits, represented as din[3:0], and accordingly, the bit width of the first register can also be 4 bits. At this time, the value of the first register (i.e., the first parameter) is also 4 bits, which can be represented as Rd[3:0]. Similarly, if the previous cyclic redundancy check code is 8 bits, represented as c[7:0], the bit width of the second register can also be 8 bits. At this time, the value of the second register (i.e., the second parameter) is also 8 bits, which can be represented as Rc[7:0].

[0095] The valid data bits are the bits of the data participating in the XOR logic operation, that is, the bits marked by the first parameter in the data. When marking the bits of the data participating in the XOR logic operation, the first parameter can also be used to determine which bits of the input data participate in the XOR logic operation in the current cycle, and these determined bits are the valid data bits.

[0096] In some embodiments of the present application, the method for determining the valid data bit can be based on the value of each bit in the first parameter, that is, when the value of the jth bit in the first parameter meets the preset condition, the logic operation module determines that the jth bit of the data is a valid data bit. Wherein, j represents any bit in the first parameter, for example, for the 4-bit first parameter Rd[3:0], it includes the following bits 0 to 3, Rd[0], Rd[1], Rd[2], Rd[3]. For the 0th bit in the 8-bit target cyclic redundancy check code newcrc[7:0], that is, newcrc[0], the first parameter of the corresponding first register is 2'b0101, that is, the binary value 0101. It can be seen that Rd[0]=1, Rd[1]=0, Rd[2]=1, Rd[3]=0. If the preset condition is that the value of this bit is 1, and the data input in the current cycle is represented as din[3:0], it can be determined that the valid data bits of the data are the 0th and 2nd bits, that is, din[0] and din[2].

[0097] The valid check bits are the bits of the current cyclic redundancy check code participating in the XOR logic operation, that is, the bits marked by the second parameter in the current cyclic redundancy check code. When marking the bits of the current cyclic redundancy check code participating in the XOR logic operation, the second parameter can be used to determine which bits of the current cyclic redundancy check code participate in the XOR logic operation in the current cycle, and these determined bits are the valid check bits.

[0098] In some embodiments of the present application, the method for determining the valid check bit can be based on the value of each bit in the second parameter, that is, when the value of the kth bit in the second parameter meets the preset condition, the logic operation module determines that the kth bit of the data is a valid check bit. Wherein, k represents any bit in the second parameter, for example, for the 8-bit second parameter Rc[7:0], including the following 0th to 7th bits, Rc[0], Rc[1], Rc[2], Rc[3], Rc[4], Rc[5], Rc[6], Rc[7]. For the 0th bit in the 8-bit target cyclic redundancy check code newcrc[7:0], i.e., newcrc[0], the first parameter of the corresponding first register is 2'b01010000, i.e., the binary value 0101000. It can be seen that Rc[0]=0, Rc[1]=0, Rc[2]=0, Rc[3]=0, Rc[4]=1, Rc[5]=0, Rc[6]=1, Rc[7]=0. If the preset condition is that the value of the bit is 1, the current cyclic redundancy check code of the current cycle is expressed as c[7:0], then it can be determined that the valid check bits of the data are the 4th and 6th bits, i.e., c[4] and c[6].

[0099] After determining the valid data bits and valid check bits, the logic operation module can calculate the value of the i-th bit of the target cyclic redundancy check code. Taking the 0th bit newcrc[0] in the aforementioned target cyclic redundancy check code newcrc[7:0] as an example, when the first parameter is 2'b0101 and the second parameter is 2'b01010000, the valid data bits of the data involved in the XOR logic operation are din[0] and din[2], and the valid check bits of the current cyclic redundancy check code involved in the XOR logic operation are c[4] and c[6]. It can be seen that in, Represents an exclusive-OR logic operation. After traversing and processing each bit of the target cyclic redundancy check code, the values ​​of all bits of the target cyclic redundancy check code are determined.

[0100] In actual scenarios, when determining the valid data and the valid check, the preset condition can be judged by AND logic operation, that is, before performing the XOR operation, the corresponding bits of the data and the first parameter, and the current cyclic redundancy check code and the corresponding bits of the second parameter are first ANDed. Thus, the value of the i-th bit of the target cyclic redundancy check code is:

[0101]

[0102] in, represents an XOR logic operation, & represents an AND logic operation, Wd is the bit width of the first parameter and the input data, and Wc is the bit width of the second parameter and the current cyclic redundancy check code. Figure 2 A circuit implementation for calculating the value of the i-th bit is shown. Taking the aforementioned 8-bit target cyclic redundancy check code as an example, the value of its 0th bit is:

[0103]

[0104] After substituting the first parameter 2'b0101 and the second parameter 2'b01010000, the value of the 0th bit is:

[0105]

[0106] When the first and second parameters change, the valid data bits and valid check bits involved in the operation will also change. For example, when the first parameter of newcrc[0] is 2'b1101, the corresponding valid data bits are din[0], din[2], and din[3]. When the second parameter of newcrc[0] is 2'b01010011, the corresponding valid check bits are c[0], c[1], c[4], and c[6]. Similarly, the remaining bits of the target cyclic redundancy check code can be traversed to generate a complete target cyclic redundancy check code.

[0107] Therefore, by configuring different first parameters and second parameters for each bit of the target cyclic redundancy check code, and writing them into the first register and the second register respectively, different valid data bits and valid check bits can be determined, so as to construct different expressions for each bit of each target cyclic redundancy check code, which is applicable to different generating polynomials and supports cyclic redundancy check codes of different standards. For example, taking an 8-bit cyclic redundancy check code with a generating polynomial of x^8+x^6+x^3+1 as an example, for each bit of the target cyclic redundancy check code, the values ​​of the first parameter and the second parameter can be set as follows:

[0108] newcrc[0]:Rd[3:0]=2'b0101 Rc[7:0]=2'b01010000

[0109] newcrc[1]:Rd[3:0]=2'b1010 Rc[7:0]=2'b10100000

[0110] newcrc[2]:Rd[3:0]=2'b0100 Rc[7:0]=2'b01000000

[0111] newcrc[3]:Rd[3:0]=2'b1101 Rc[7:0]=2'b11010000

[0112] newcrc[4]:Rd[3:0]=2'b1010 Rc[7:0]=2'b10100001

[0113] newcrc[5]:Rd[3:0]=2'b0100 Rc[7:0]=2'b01000010

[0114] newcrc[6]:Rd[3:0]=2'b1101 Rc[7:0]=2'b11010100

[0115] newcrc[7]:Rd[3:0]=2'b1010 Rc[7:0]=2'b10101000

[0116] When it is necessary to support cyclic redundancy check codes of other standards, different first parameters and second parameters can be configured according to the corresponding generating polynomial, so that the device can generate the cyclic redundancy check code of the corresponding standard after obtaining the first parameter and the second parameter.

[0117] In some embodiments of the present application, when the logic operation module performs an exclusive-OR logic operation on the values ​​of the valid data bits and the valid check bits to generate the value of the i-th bit of the target cyclic redundancy check code, a multi-level processing approach can be adopted, that is, a multi-level exclusive-OR logic operation is performed on the values ​​of the valid data bits and the valid check bits to generate the value of the i-th bit of the target cyclic redundancy check code.

[0118] For example, taking the i-th bit newcrc[i] of the aforementioned target cyclic redundancy check code as an example, we can use Figure 3 The multi-stage processing method shown in the figure. The processing process divides the XOR logic operation into two levels. First, the values ​​of the valid data bits and valid check bits are divided into multiple groups, and the XOR logic operation is performed on the values ​​of the valid data bits and / or valid check bits in each group to determine the intermediate operation result of each group, and the intermediate operation result of each group is recorded as part_crc. Then, the XOR logic operation is performed on the intermediate operation results of all groups to generate the value of the i-th bit of the target cyclic redundancy check code.

[0119] Here, those skilled in the art should understand that the specific method of the above-mentioned hierarchical processing is only an example, and other existing or future methods that are applicable to the present invention should also be included in the protection scope of the present invention and are included here by reference. For example, more levels can be used, that is, the intermediate operation results of the previous level are grouped here and XOR logic operations are performed separately to obtain the intermediate operation results of the next level, until the value of the i-th bit of the target cyclic redundancy check code is obtained.

[0120] In addition, in order to improve processing efficiency, the parameter determination module can increase the bit width of the input data before obtaining the first parameter of the first register and the second parameter of the second register corresponding to the i-th bit of the target cyclic redundancy check code to be generated, so that the corresponding target cyclic redundancy check code can be calculated for more data within one cycle.

[0121] In some other embodiments of the present application, the cyclic redundancy check code generation scheme can also be applied to cloud computing storage scenarios, so this embodiment can provide a data storage device, which includes a parameter determination module, a logic operation module, a generation module and a sending module. Among them, after the parameter determination module, the logic operation module and the generation module use the target cyclic redundancy check code corresponding to the aforementioned generation scheme data, the sending module can send the data and the target cyclic redundancy check code to the storage node. After receiving the data and the corresponding target cyclic redundancy check code, the storage node can verify the data according to the target cyclic redundancy check code, and store the data after completing the verification.

[0122] In some embodiments of the present application, the cyclic redundancy check code generation device can be implemented in the form of a logic circuit. In this case, the structure of the logic circuit is as follows: Figure 5 As shown, it may include a data register 510, a current check code register 520, a target check code register 530 and N groups of generation circuits 540, where the value of N is the same as the bit width of the target check code register and the current check code register. Each group of generation circuits 540 includes a first register, a second register, an XOR gate circuit and a plurality of AND gate circuits, the bit width of the first register is the same as the bit width of the data register, and the bit width of the second register is the same as the bit width of the current check code register.

[0123] The XOR gate circuit and multiple AND gate circuits in the generation circuit are based on Figure 2 The circuit structure shown implements the process of logic processing, that is, the input end of the AND gate circuit inputs the j-th bit of the data register and the j-th bit of the first register, or inputs the k-th bit of the current check code register and the k-th bit of the second register, the output end of the AND gate circuit is connected to the input end of the XOR gate circuit, and the output end of the XOR gate circuit is output to the i-th bit of the target check code register.

[0124] In some embodiments of the present application, a multi-level XOR logic operation can be used in each group of generating circuits to reduce the number of fan-in during processing and avoid excessive fan-in affecting the overall processing frequency. In this embodiment, each group of generating circuits includes a first register, a second register, a plurality of AND gate circuits, and a multi-level XOR gate circuit. The XOR gate circuit and the plurality of AND gate circuits in the generating circuit are based on the following example: Figure 3 The circuit structure shown implements the process of logic processing, that is, the input end of the AND gate circuit inputs the j-th bit of the data register and the j-th bit of the first register, or inputs the k-th bit of the current check code register and the k-th bit of the second register, the output end of the AND gate circuit is connected to the input end of the first-level XOR gate circuit, the output end of each level of XOR gate circuit is connected to the input end of the next level of XOR gate circuit, and the input end of the last level of XOR gate circuit is output to the i-th bit of the target check code register.

[0125] In addition, the generating device may further include an intermediate result register, and during the processing of the multi-stage XOR logic operation, the intermediate result register is used to store the input value of the XOR gate circuit.

[0126] In actual scenarios, when multi-level logic operations are used, the efficiency of generating cyclic redundancy check codes will be reduced because the circuit performs one level of calculation in each clock cycle. Therefore, the bit width of the input data can be adjusted. After increasing the bit width, although the cycle of generating a target cyclic redundancy check code will be extended, the actual processing efficiency will not be reduced due to the increase in the bit width of the input data.

[0127] In addition, a part of the present application may be applied as a computer program product, such as a computer program instruction, which, when executed by a computer, can call or provide the method and / or technical solution according to the present application through the operation of the computer. The program instruction for calling the method of the present application may be stored in a fixed or removable recording medium, and / or transmitted through a data stream in a broadcast or other signal-bearing medium, and / or stored in a working memory of a computer device that runs according to the program instruction. Here, some embodiments of the present application include a Figure 6 The computing device shown includes one or more memories 610 storing computer-readable instructions and a processor 620 for executing the computer-readable instructions, wherein when the computer-readable instructions are executed by the processor, the device executes the methods and / or technical solutions based on the aforementioned multiple embodiments of the present application.

[0128] In addition, some embodiments of the present application further provide a computer-readable medium on which computer program instructions are stored. The computer-readable instructions can be executed by a processor to implement the methods and / or technical solutions of the aforementioned multiple embodiments of the present application.

[0129] It should be noted that the present application can be implemented in software and / or a combination of software and hardware, for example, can be implemented using an application specific integrated circuit (ASIC), a general purpose computer or any other similar hardware device. In an embodiment, the software program of the present application can be executed by a processor to implement the above steps or functions. Similarly, the software program of the present application (including related data structures) can be stored in a computer-readable recording medium, for example, a RAM memory, a magnetic or optical drive or a floppy disk and similar devices. In addition, some steps or functions of the present application can be implemented using hardware, for example, as a circuit that cooperates with a processor to perform each step or function.

[0130] Those skilled in the art will appreciate that each block in these structure diagrams and / or block diagrams and / or flow charts and combinations of blocks in these structure diagrams and / or block diagrams and / or flow charts can be implemented using computer program instructions. Those skilled in the art will appreciate that these computer program instructions can be provided to a general-purpose computer, a professional computer, or a processor of other programmable data processing methods to implement, thereby executing the scheme specified in the block or multiple blocks of the structure diagram and / or block diagram and / or flow chart disclosed in the present invention through the processor of the computer or other programmable data processing method.

[0131] Those skilled in the art will appreciate that the various operations, methods, steps, measures, and schemes discussed in the present invention may be alternated, modified, combined, or deleted. Further, other steps, measures, and schemes in the various operations, methods, and schemes discussed in the present invention may also be alternated, modified, rearranged, decomposed, combined, or deleted. Further, the steps, measures, and schemes in the prior art that are similar to those disclosed in the present invention may also be alternated, modified, rearranged, decomposed, combined, or deleted.

[0132] It is obvious to those skilled in the art that the present application is not limited to the details of the exemplary embodiments described above, and that the present application can be implemented in other specific forms without departing from the spirit or essential features of the present application. Therefore, the embodiments should be regarded as exemplary and non-limiting in all respects, and the scope of the present application is defined by the appended claims rather than the above description, and it is intended that all changes falling within the meaning and scope of the equivalent elements of the claims be included in the present application. Any reference numeral in a claim should not be regarded as limiting the claim to which it relates.

Claims

1. A method for generating a cyclic redundancy check code, wherein: The method includes: Obtain a first parameter of a first register and a second parameter of a second register corresponding to the i-th bit of a target cyclic redundancy check code to be generated, wherein the first parameter is used to mark the bit of data participating in an exclusive OR logic operation, and the second parameter is used to mark the bit of a current cyclic redundancy check code participating in an exclusive OR logic operation; Determine a valid data bit and a valid check bit according to the first parameter and the second parameter, wherein the valid data bit is a bit of data participating in an exclusive OR logic operation, and the valid check bit is a bit of a current cyclic redundancy check code participating in the exclusive OR logic operation; Determine the values ​​of the valid data bit and the valid check bit according to the input data and the current cyclic redundancy check code, and perform an exclusive OR logic operation on the values ​​of the valid data bit and the valid check bit to generate the value of the i-th bit of the target cyclic redundancy check code; The target cyclic redundancy check code is determined according to values ​​of all bits of the target cyclic redundancy check code.

2. The method according to claim 1, wherein: The bit width of the first register is the same as the bit width of the data participating in the XOR logic operation, and the bit width of the second register is the same as the bit width of the current cyclic redundancy check code participating in the XOR logic operation; Determining valid data bits and valid check bits involved in the operation according to the first parameter and the second parameter includes: When the value of the j-th bit in the first parameter meets the preset condition, determining the j-th bit of the data as a valid data bit; When the value of the k-th bit in the second parameter meets a preset condition, it is determined that the k-th bit of the current cyclic redundancy check code is a valid data bit.

3. The method according to claim 1, wherein: Performing an XOR logic operation on the values ​​of the valid data bit and the valid check bit to generate the value of the i-th bit of the target cyclic redundancy check code includes: A multi-level XOR logic operation is performed on the values ​​of the valid data bits and the valid check bits to generate the value of the i-th bit of the target cyclic redundancy check code.

4. The method according to claim 3, wherein: Performing a multi-level XOR logic operation on the values ​​of the valid data bits and the valid check bits to generate the value of the i-th bit of the target cyclic redundancy check code, including: Dividing the values ​​of the valid data bits and the valid check bits into a plurality of groups, and performing an exclusive OR logic operation on the values ​​of the valid data bits and / or the valid check bits in each group to determine an intermediate operation result of each group; Perform an XOR logic operation on the intermediate operation results of all groups to generate the value of the i-th bit of the target cyclic redundancy check code.

5. The method according to claim 1, wherein: Before obtaining the first parameter of the first register and the second parameter of the second register corresponding to the i-th bit of the target cyclic redundancy check code to be generated, the method further includes: Increase the bit width of the input data.

6. A data storage method, wherein: The method includes: Obtain a first parameter of a first register and a second parameter of a second register corresponding to the i-th bit of a target cyclic redundancy check code to be generated, wherein the first parameter is used to mark the bit of data participating in an exclusive OR logic operation, and the second parameter is used to mark the bit of a current cyclic redundancy check code participating in an exclusive OR logic operation; Determine a valid data bit and a valid check bit according to the first parameter and the second parameter, wherein the valid data bit is a bit of data participating in an exclusive OR logic operation, and the valid check bit is a bit of a current cyclic redundancy check code participating in the exclusive OR logic operation; Determine the values ​​of the valid data bit and the valid check bit according to the input data and the current cyclic redundancy check code, and perform an exclusive OR logic operation on the values ​​of the valid data bit and the valid check bit to generate the value of the i-th bit of the target cyclic redundancy check code; Determining the target cyclic redundancy check code according to the values ​​of all bits of the target cyclic redundancy check code; The data and the target cyclic redundancy check code are sent to a storage node, so that the storage node stores the data after completing verification of the data according to the target cyclic redundancy check code.

7. A device for generating a cyclic redundancy check code, wherein: The equipment includes: A parameter determination module, used to obtain a first parameter of a first register and a second parameter of a second register corresponding to the i-th bit of a target cyclic redundancy check code to be generated, wherein the first parameter is used to mark the bit of the data participating in the XOR logic operation, and the second parameter is used to mark the bit of the current cyclic redundancy check code participating in the XOR logic operation; A logic operation module, used to determine the valid data bits and valid check bits participating in the operation according to the first parameter and the second parameter, and determine the values ​​of the valid data bits and the valid check bits according to the input data and the current cyclic redundancy check code, and perform an exclusive OR logic operation on the values ​​of the valid data bits and the valid check bits to generate the value of the i-th bit of the target cyclic redundancy check code, wherein the valid data bits are the bits of the data participating in the exclusive OR logic operation, and the valid check bits are the bits of the current cyclic redundancy check code participating in the exclusive OR logic operation; A generating module is used to determine the target cyclic redundancy check code according to the values ​​of all bits of the target cyclic redundancy check code.

8. The device according to claim 7, wherein: The bit width of the first register is the same as the bit width of the data participating in the XOR logic operation, and the bit width of the second register is the same as the bit width of the current cyclic redundancy check code participating in the XOR logic operation; The logic operation module is used to determine that the j-th bit of the data is a valid data bit when the value of the j-th bit in the first parameter meets the preset conditions; and to determine that the k-th bit of the current cyclic redundancy check code is a valid data bit when the value of the k-th bit in the second parameter meets the preset conditions.

9. The device according to claim 7, wherein: The logic operation module is used to perform a multi-level XOR logic operation on the values ​​of the valid data bits and the valid check bits to generate the value of the i-th bit of the target cyclic redundancy check code.

10. The device according to claim 9, wherein: The logic operation module is used to divide the values ​​of the valid data bits and valid check bits into multiple groups, and perform an exclusive OR logic operation on the values ​​of the valid data bits and / or valid check bits in each group to determine the intermediate operation results of each group; and perform an exclusive OR logic operation on the intermediate operation results of all groups to generate the value of the i-th bit of the target cyclic redundancy check code.

11. The device according to claim 7, wherein: The parameter determination module is further used to increase the bit width of the input data before obtaining the first parameter of the first register and the second parameter of the second register corresponding to the i-th bit of the target cyclic redundancy check code to be generated.

12. A data storage device, wherein: The equipment includes: A parameter determination module, used to obtain a first parameter of a first register and a second parameter of a second register corresponding to the i-th bit of a target cyclic redundancy check code to be generated, wherein the first parameter is used to mark the bit of the data participating in the XOR logic operation, and the second parameter is used to mark the bit of the current cyclic redundancy check code participating in the XOR logic operation; A logic operation module, used to determine the valid data bits and valid check bits participating in the operation according to the first parameter and the second parameter, and determine the values ​​of the valid data bits and the valid check bits according to the input data and the current cyclic redundancy check code, and perform an exclusive OR logic operation on the values ​​of the valid data bits and the valid check bits to generate the value of the i-th bit of the target cyclic redundancy check code, wherein the valid data bits are the bits of the data participating in the exclusive OR logic operation, and the valid check bits are the bits of the current cyclic redundancy check code participating in the exclusive OR logic operation; A generating module, configured to determine the target cyclic redundancy check code according to the values ​​of all bits of the target cyclic redundancy check code; The sending module is used to send the data and the target cyclic redundancy check code to the storage node, so that the storage node stores the data after completing the verification of the data according to the target cyclic redundancy check code.

13. A computing device, wherein: The device comprises a memory for storing computer program instructions and a processor for executing the computer program instructions, wherein when the computer program instructions are executed by the processor, the device is triggered to execute the method according to any one of claims 1 to 6.

14. A computer readable medium having computer program instructions stored thereon, wherein the computer program instructions can be executed by a processor to implement the method according to any one of claims 1 to 6.

15. A device for generating a cyclic redundancy check code, wherein: The device includes a data register, a current check code register, a target check code register and N groups of generation circuits, wherein the value of N is the same as the bit width of the target check code register and the current check code register; Each group of generating circuits includes a first register, a second register, an XOR gate circuit and a plurality of AND gate circuits, the bit width of the first register is the same as the bit width of the data register, the bit width of the second register is the same as the bit width of the current check code register; the first parameter of the first register is used to mark the bit of the data involved in the XOR logic operation, and the second parameter of the second register is used to mark the bit of the current cyclic redundancy check code involved in the XOR logic operation; The input ends of some of the multiple AND gate circuits input the j-th bit of the data register and the j-th bit of the first register, the input ends of another part of the multiple AND gate circuits input the k-th bit of the current check code register and the k-th bit of the second register, the output ends of the AND gate circuits are connected to the input ends of the XOR gate circuits, and the output ends of the XOR gate circuits are output to the i-th bit of the target check code register; j represents any bit in the first parameter, and k represents any bit in the second parameter.

16. A device for generating a cyclic redundancy check code, wherein: The device includes a data register, a current check code register, a target check code register and N groups of generation circuits, wherein the value of N is the same as the bit width of the target check code register and the current check code register; Each group of generating circuits includes a first register, a second register, a plurality of AND gate circuits and a multi-level XOR gate circuit, the bit width of the first register is the same as the bit width of the data register, the bit width of the second register is the same as the bit width of the current check code register; the first parameter of the first register is used to mark the bit of the data involved in the XOR logic operation, and the second parameter of the second register is used to mark the bit of the current cyclic redundancy check code involved in the XOR logic operation; The input ends of some of the multiple AND gate circuits input the j-th bit of the data register and the j-th bit of the first register, the input ends of another part of the multiple AND gate circuits input the k-th bit of the current check code register and the k-th bit of the second register, the output ends of the AND gate circuits are connected to the input ends of the first-level XOR gate circuits, the output ends of each level of XOR gate circuits are connected to the input ends of the next level of XOR gate circuits, and the input ends of the last level of XOR gate circuits are output to the i-th bit of the target check code register; j represents any bit in the first parameter, and k represents any bit in the second parameter.

17. The apparatus according to claim 16, wherein: The device further comprises an intermediate result register, and the intermediate result register is used to store the input value of the XOR gate circuit.

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