Method of manufacturing a semiconductor device

Abstract

The present disclosure relates to a method of manufacturing a semiconductor device. In the method of manufacturing a semiconductor device according to one embodiment, after a semiconductor wafer including a nonvolatile memory, a pad, and an insulating film including an organic material is provided, a probe contacts a surface of the pad located in a second region, and data is written to the nonvolatile memory. Here, the insulating film is formed by performing a first heat treatment on the organic material. Also, after a second heat treatment is performed on the semiconductor wafer and the nonvolatile memory in which the data is written is inspected, a barrier layer and a first solder material are formed on a surface of the pad located in a first region by using a plating method. Furthermore, a bump electrode is formed in the first region by performing a third heat treatment on the first solder material.

Description

[0001] Cross Reference to Related Applications

[0002] The disclosure of Japanese Patent Application No. 2020-031649 filed on February 27, 2020, including the specification, drawings and abstract, is incorporated herein by reference in its entirety. TECHNICAL FIELD

[0003] The present application relates to a semiconductor device and a manufacturing method thereof, and more particularly, the present application can be applied to a semiconductor chip having a nonvolatile memory which has passed a wafer test process and a bump electrode which is electrically connected to the nonvolatile memory and further includes tin (Sn), and to a manufacturing method of the semiconductor chip. BACKGROUND

[0004] The disclosed technology is listed below.

[0005] [Patent Literature 1] Japanese Unexamined Patent Application Publication No. 2009-246218

[0006] [Patent Literature 2] Japanese Unexamined Patent Application Publication No. 2016-92305

[0007] [Patent Literature 3] Japanese Unexamined Patent Application Publication No. 2020-17642

[0008] There is a semiconductor chip including a pad having an area to be contacted with a probe and an area on which a bump electrode is formed via a conductive film formed by using an electroplating method (for example, see FIG. 34 of Patent Literature 1). Further, in order to avoid data written to a memory circuit from disappearing due to heat treatment (heating temperature) at the time of forming an insulating film including an organic material, there is a method of manufacturing a semiconductor device including: after forming the insulating film by performing heat treatment on the organic material, bringing the probe into contact with a surface of the pad, and writing data to the memory circuit (for example, see FIG. 1 of Patent Literature 2). Figure 3 Further, there is a semiconductor chip including a semiconductor substrate on which an insulating film is formed, the insulating film having an opening portion exposing an area to be contacted with a probe, and an opening portion exposing an area on which a conductive film is formed by using an electroplating method (for example, see FIG. 1 of Patent Literature 3). Figure 13 SUMMARY

[0009] ​The present inventors have studied miniaturization (specifically, "thinning") of a semiconductor chip having a nonvolatile memory subjected to a wafer test process, and a bump electrode electrically connected to the nonvolatile memory and further including tin (Sn). In addition, the present inventors have found that, according to the miniaturization of the semiconductor chip, there is a possibility that data written to the nonvolatile memory in the wafer test process will be lost.

[0010] Other objects and novel features will become apparent from the description and the accompanying drawings.

[0011] Typical embodiments disclosed in the present application will be described briefly below.

[0012] A method of manufacturing a semiconductor device according to one embodiment includes: (a) providing a semiconductor wafer including a nonvolatile memory, a pad, and an insulating film including an organic material. Here, a surface of the pad has a first region and a second region. Also, the insulating film is formed by performing a first heat treatment on the organic material. Further, the method includes: (b) after (a), bringing a probe into contact with the surface of the pad located in the second region, and writing data to the nonvolatile memory. Further, the method includes: (c) after (b), performing a second heat treatment on the semiconductor wafer, and checking the nonvolatile memory in which the data is written. Here, a temperature of the second heat treatment is lower than a temperature of the first heat treatment. Also, a time of each of the second heat treatments is longer than a time of each of the first heat treatments. Further, the method includes: (d) after (c), forming a barrier layer on the surface of the pad located in the first region by using an electroplating method. Further, the method includes: (e) after (d), forming a first solder material on the barrier layer by using the electroplating method. Furthermore, the method includes: (f) after (e), forming a bump electrode on the surface of the pad located in the first region via the barrier layer by performing a third heat treatment on the first solder material. Here, a temperature of the third heat treatment is lower than the temperature of the first heat treatment. Also, a time of each of the third heat treatments is shorter than a time of each of the second heat treatments.

[0013] Further, a method of manufacturing a semiconductor device according to another embodiment includes: (a) providing a semiconductor wafer including a nonvolatile memory, a pad, and an insulating film including an organic material. Here, a surface of the pad has a first region and a second region. Also, the insulating film is formed by performing a first heat treatment on the organic material. Also, a temperature of the first heat treatment is 300°C to 400°C. Further, a time of each of the first heat treatments is 30 minutes to 2 hours. Also, the method includes: (b) after (a), bringing a probe into contact with the surface of the pad located in the second region, and writing data to the nonvolatile memory. Also, the method includes: (c) after (b), performing a second heat treatment on the semiconductor wafer, and checking the nonvolatile memory in which the data is written. Here, a temperature of the second heat treatment is 200°C to 280°C. Also, a time of each of the second heat treatments is 6 hours to 50 hours. Also, the method includes: (d) after (c), forming a conductive film on the surface of the pad located in the first region by using an electroplating method. Also, the method includes: (e) after (d), forming a first solder material on the conductive film by using the electroplating method. Also, the method includes: (f) after (e), forming a bump electrode on the surface of the pad located in the first region via the conductive film by performing a third heat treatment on the first solder material. Here, a temperature of the third heat treatment is 100°C to 270°C. Also, a time of each of the third heat treatments is several tens of seconds to 5 minutes. Further, the method includes: (g) after (f), obtaining a semiconductor chip having the bump electrode, the conductive film, the pad, and the nonvolatile memory by dicing the semiconductor wafer.

[0014] According to the method of manufacturing a semiconductor device in one embodiment, the reliability of the semiconductor device can be improved.

[0015] According to the method of manufacturing a semiconductor device in another embodiment, the reliability of the semiconductor device can be improved. BRIEF DESCRIPTION OF DRAWINGS

[0016] Figure 1 is a cross-sectional view illustrating a configuration of a semiconductor device according to the present embodiment.

[0017] Figure 2 is an enlarged cross-sectional view at "A" portion of Figure 1

[0018] Figure 3 is an enlarged plan view of a semiconductor chip at "A" portion of Figure 1

[0019] Figure 4 is an enlarged cross-sectional view at "B" portion of Figure 2 ​​​

[0020] Figure 5 is a process flow chart showing a manufacturing process of a semiconductor device according to the present embodiment.

[0021] Figure 6 is a plan view of a semiconductor wafer according to the present embodiment.

[0022] Figure 7 is an enlarged cross-sectional view of the semiconductor chip at the "A" portion of Figure 1 .

[0023] Figure 8 is an enlarged cross-sectional view during the manufacturing process of the semiconductor device of Figure 7 .

[0024] Figure 9 is an enlarged cross-sectional view during the manufacturing process of the semiconductor device of Figure 8 .

[0025] Figure 10 is an enlarged cross-sectional view during the manufacturing process of the semiconductor device of Figure 9 .

[0026] Figure 11 is an enlarged cross-sectional view during the manufacturing process of the semiconductor device of Figure 10 .

[0027] Figure 12 is an enlarged cross-sectional view during the manufacturing process of the semiconductor device of Figure 11 .

[0028] Figure 13 is an enlarged cross-sectional view during the manufacturing process of the semiconductor device of Figure 12 .

[0029] Figure 14 is an enlarged cross-sectional view during the manufacturing process of the semiconductor device of Figure 13 .

[0030] Figure 15 is an enlarged cross-sectional view during the manufacturing process of the semiconductor device of Figure 14 .

[0031] Figure 16 is a cross-sectional view illustrating a flip chip mounting process according to the present embodiment.

[0032] Figure 17 is an enlarged cross-sectional view during the manufacturing process of the semiconductor device of Figure 16 .

[0033] Figure 18 is a partial enlarged plan view of a semiconductor device according to a modified example.

[0034] Figure 19 is an enlarged cross-sectional view during a manufacturing process of a semiconductor device according to the present embodiment. DETAILED DESCRIPTION

[0035] In the following embodiments, when necessary for convenience, description will be made by being divided into a plurality of chapters or embodiments, but unless specifically stated, they are not independent of each other, but are a modified example, a detail, a supplementary explanation, etc. of a part or all of the other embodiments. In the following embodiments, the number of elements, etc. (including the number of elements, numerical values, quantities, ranges, etc.) is not limited to a specific number, but can be not less than or equal to the specific number, unless the number is specifically indicated and is essentially limited to the specific number. Further, in the following embodiments, it goes without saying that the elements constituting the elements (including the steps of elements, etc.) are not essential, unless they are specifically indicated and are essentially considered to be obviously necessary. Similarly, in the following embodiments, when the shape, positional relationship, etc. of an assembly, etc. is mentioned, it is assumed that the shape, etc. is substantially similar or approximate to the shape, etc., unless they are specifically indicated and are essentially considered to be obviously necessary, etc. The same applies to the above-mentioned numerical values and ranges.

[0036] The following embodiments will be described based on the drawings. In all the drawings used to describe the embodiments, members having the same function are denoted by the same reference numerals and hatching, and repetitive description thereof is omitted. In the following embodiments, description of the same or similar parts will not be repeated essentially unless necessary. In the drawings used in the embodiments, even in the case of cross-sectional views, section lines can be omitted so that the drawings are easier to see. Further, even in the case of plan views, section lines can be used so that the drawings are easier to see.

[0037] (Embodiment)

[0038] <Semiconductor Device SMD According to the Present Embodiment>

[0039] First, a semiconductor device SMD according to the present embodiment will be described with reference to Figures 1-2 A semiconductor device SMD according to the present embodiment will be described. Incidentally, Figure 1 is a cross-sectional view illustrating the configuration of a semiconductor device according to the present embodiment. In addition, Figure 2 is an enlarged cross-sectional view at "A" portion of Figure 1

[0040] As Figure 1 ​As shown, the semiconductor device SMD includes an interposer WSB and a semiconductor chip CP mounted on the interposer WSB. Here, in this embodiment, the interposer WSB is a wiring substrate having multiple wiring layers (all not shown) and an insulating layer (not shown). Furthermore, although not shown, the planar shape of each of the semiconductor chip CP and the interposer WSB is square.

[0041] In addition, such as Figure 1 As shown, the semiconductor chip CP is mounted on the upper surface WSBU of the interposer layer WSB via bump electrodes BE. Then, as... Figure 1 As shown, the semiconductor chip CP and the interposer WSB are sealed with resin SR. The bump electrode BE in this embodiment includes, for example, tin (Sn). More specifically, the bump electrode BE is a solder bump comprising a so-called binary alloy of tin (Sn) and silver (Ag). Furthermore, the resin SR in this embodiment is made of epoxy resin having various fillers.

[0042] On the other hand, such as Figure 1 As shown, a boss BUL is formed on the lower surface WSBL of the interposer WSB, opposite to the upper surface WSBU. Then, an external connection terminal EXT is formed on the boss BUL. Incidentally, the external connection terminal EXT in this embodiment includes, for example, tin (Sn). More specifically, the external connection terminal EXT is a solder ball of a so-called ternary alloy comprising tin (Sn), silver (Ag), and copper (Cu). Furthermore, the boss BUL is formed from a wiring pattern in the lowest wiring layer among the aforementioned plurality of wiring layers. The boss BUL in this embodiment is, for example, Cu.

[0043] Next, we will refer to Figures 2-3 Describe the details of the junction between the semiconductor chip CP and the interposer WSB.

[0044] like Figure 2 As shown, a solder lead BOL, to which a bump electrode BE is connected, is formed on the upper surface WSBU of the interposer WSB. A solder mask SRF is formed on the upper surface WSBU of the interposer WSB to expose a portion of the solder lead BOL. Incidentally, the solder lead BOL is made of a wiring pattern formed in the wiring layer located on the uppermost of the plurality of wiring layers. In addition, the solder lead BOL in this embodiment includes, for example, copper (Cu). Furthermore, the solder mask SRF is made of an insulating component.

[0045] In addition, such as Figure 2 As shown, the semiconductor chip CP has a semiconductor substrate SSB, pads BP formed on the semiconductor substrate SSB, and an insulating film IF formed on the semiconductor substrate SSB. More specifically, as Figure 2As shown in FIG. 1, a plurality of wiring layers (not all shown) and a plurality of wiring layers (not all shown) are alternately laminated on a semiconductor substrate SSB, forming a multilayer wiring layer MWL. The pad BP is formed of a wiring pattern formed on a wiring layer at the uppermost layer among the plurality of wiring layers. That is, the pad BP is one of the components that make up the multilayer wiring layer MWL. The pad BP of the present embodiment includes, for example, aluminum (Al). Furthermore, the semiconductor chip CP of the present embodiment has a plurality of pads BP. Then, although not shown, the plurality of pads BP are placed along each side of the semiconductor chip CP (i.e., the semiconductor substrate SSB).

[0046] Furthermore, in the present embodiment, a nonvolatile memory NVM is formed in the semiconductor substrate SSB (e.g., Figure 2 , Part B). Then, the above-described pad BP is electrically connected to the nonvolatile memory NVM via the plurality of wiring layers that make up the multilayer wiring layer MWL. More specifically, although not shown, a plurality of nonvolatile memories NVM are formed in the semiconductor substrate SSB, and one memory circuit is formed by the plurality of nonvolatile memories NVM. The configuration of the nonvolatile memory of the present embodiment will be described later with reference to Figure 4

[0047] Furthermore, as shown in Figure 2 and Figure 3 , the surface BPS of the pad BP of the present embodiment is a region RG1 exposed in the opening OPl of the insulating film IF, and a region RG2 exposed in an opening OP2 of the insulating film IF different from the opening OPl. Note that the region RG1 is a region (also referred to as a "bump electrode formation region") on the surface of which the above-described bump electrode BE is formed. On the other hand, the region RG2 is a region (also referred to as a "probe region") that comes into contact with a probe PBP (see Figure 5 ) during wafer testing. Thus, as shown in Figure 2 , a probe mark PBD formed by contact with the probe PBP is formed on the surface BPS of the pad BP in the region RG2.

[0048] As shown in Figure 2 , the insulating film IF of the present embodiment is formed on the semiconductor substrate SSB, and includes a passivation film PVF made of an inorganic material and a protective film PIF including an organic material and formed on the passivation film PVF. As shown in Figure 2 and Figure 3 , the passivation film PVF and the protective film PIF are formed not only on the peripheral region of the front surface BPS of the pad BP, but also on a region between the two regions RG1, RG2. In the present embodiment, as shown in Figure 2 and Figure 3 , the passivation film PVF and the protective film PIF are formed not only on the peripheral region of the front surface BPS of the pad BP, but also on a region between the two regions RG1, RG2. In the present embodiment, as shown inAs shown in FIG. 1, the diameter (long side) of each opening OP1, OP2 formed in the protective film PIF and exposing the surface BPS of the pad BP is smaller (shorter) than the diameter (short side) of each opening formed in the passivation film PVF and exposing the surface BPS of the pad BP.

[0049] Further, in the present embodiment, as Figure 2 As shown in FIG. 1, the conductive film UBM is formed on the surface BPS of the pad BP located in the region RG1. Then, as Figure 2 As shown in FIG. 1, the bump electrode BE is formed on the surface BPS of the pad BP located in the region RG1 via the conductive film UBM. Incidentally, the conductive film UBM of the present embodiment is formed on the surface BPS of the pad BP, and has a seed layer SDL including copper (Cu) and a barrier layer BRL formed on the seed layer SDL, and the barrier layer BRL includes nickel (Ni). Further, although a detailed manufacturing process will be described later, each of the conductive film UBM and the bump electrode BE is formed using a plating method, that is, so-called plated layer (plated film).

[0050] Further, as described above, the pad BP electrically connected to the nonvolatile memory has the region RG1 whose surface BPS is covered with the conductive film UBM and the region RG2 whose surface BPS is exposed without being covered with the conductive film UBM. Therefore, as Figure 1 and Figure 2 As shown in FIG. 1, the resin SR for sealing between the semiconductor chip CP and the interposer WSB is in contact with the surface BPS of the pad BP located in the region RG2 (that is, the probe mark PBD), but not in contact with the surface BPS of the pad BP located in the region RG1.

[0051] <Details of the Pad BP According to the Present Embodiment>

[0052] Next, details of the pad BP according to the present embodiment will be described with reference to Figure 2 and Figure 3

[0053] As shown in FIG. 1, the planar shape of the bump electrode BE of the present embodiment is substantially circular. On the other hand, as shown in FIG. 1, the planar shape of the conductive film UBM of the present embodiment is octagonal. Then, as shown in FIG. 1, the bump electrode BE is in contact not only with the surface of the conductive film UBM, but also with the side surface of the conductive film UBM. That is, as shown in FIG. 1, the diameter of the bump electrode BE is larger than the diameter of the conductive film UBM (the interval of the two sides facing each other). Figure 3 Figure 3 Figure 2 Figure 3 Figure 3 ​​​​​As shown in FIG. 1, the portion of the pad BP on which the bump electrode BE is formed thereover, i.e., the portion having the region RG1 but not the region RG2, has a substantially octagonal shape in a plan view. Similarly, the planar shape of the opening of the passivation film PVF and the protective film PIF exposed on the surface BPS of the pad BP located in the region RG1 is octagonal.

[0054] Further, as shown in FIG. 1, the pad BP on which the wiring layer is formed has a lead-out wiring LOL connected also to the via wiring VA. Then, as shown in FIG. 1, the lead-out wiring LOL is not connected to the portion of the pad BP on which the bump electrode BE is formed thereover (the portion having the region RG1 but not the region RG2), but is connected to the portion of the pad BP on which the bump electrode BE is not formed thereover (the portion having the region RG2 but not the region RG1). That is, the bump electrode BE is electrically connected to the non-volatile memory NVM via the lead-out wiring LOL connected to the pad BP, and the via wiring VA connected to the lead-out wiring LOL. Figure 3 Figure 3 Further, as shown in FIG. 1, the pad BP on which the wiring layer is formed has a lead-out wiring LOL connected also to the via wiring VA. Then, as shown in FIG. 1, the lead-out wiring LOL is not connected to the portion of the pad BP on which the bump electrode BE is formed thereover (the portion having the region RG1 but not the region RG2), but is connected to the portion of the pad BP on which the bump electrode BE is not formed thereover (the portion having the region RG2 but not the region RG1). That is, the bump electrode BE is electrically connected to the non-volatile memory NVM via the lead-out wiring LOL connected to the pad BP, and the via wiring VA connected to the lead-out wiring LOL. Figure 3

[0055] Further, as shown in FIG. 1, the pad BP on which the wiring layer is formed has a lead-out wiring LOL connected also to the via wiring VA. Then, as shown in FIG. 1, the lead-out wiring LOL is not connected to the portion of the pad BP on which the bump electrode BE is formed thereover (the portion having the region RG1 but not the region RG2), but is connected to the portion of the pad BP on which the bump electrode BE is not formed thereover (the portion having the region RG2 but not the region RG1). That is, the bump electrode BE is electrically connected to the non-volatile memory NVM via the lead-out wiring LOL connected to the pad BP, and the via wiring VA connected to the lead-out wiring LOL. Figure 3 Figure 3 Further, as shown in FIG. 1, the pad BP on which the wiring layer is formed has a lead-out wiring LOL connected also to the via wiring VA. Then, as shown in FIG. 1, the lead-out wiring LOL is not connected to the portion of the pad BP on which the bump electrode BE is formed thereover (the portion having the region RG1 but not the region RG2), but is connected to the portion of the pad BP on which the bump electrode BE is not formed thereover (the portion having the region RG2 but not the region RG1). That is, the bump electrode BE is electrically connected to the non-volatile memory NVM via the lead-out wiring LOL connected to the pad BP, and the via wiring VA connected to the lead-out wiring LOL.

[0056] As described above, the non-volatile memory NVM in the semiconductor substrate SSB includes the semiconductor chip CP electrically connected to the pad BP electrically connected to the non-volatile memory NVM via the bump electrode BE formed on the front surface BPS of the pad BP located in the region RG1 via the conductive film UBM, and the soldering lead BOL formed on the upper surface WSBU of the interposer WSB. Then, the soldering lead BOL is electrically connected to the bump BUL (a bump corresponding to the soldering lead BOL) formed on the lower surface WSBL of the interposer WSB via the wiring layer constituting the interposer WSB (not shown). That is, the region RG1 of the pad BP is also a main path for signal transmission between the semiconductor chip CP and an external device.

[0057] <Non-volatile memory NVM according to the present embodiment>

[0058] Next, the non-volatile memory NVM according to the present embodiment will be described with reference to Figure 4 FIG. 2.​​​Figure 4 is Figure 2 an enlarged cross-sectional view at "B" portion of

[0059] First, the non-volatile memory NVM of the present embodiment includes a field effect transistor. More specifically, as shown in Figure 4 , the non-volatile memory NVM includes a semiconductor substrate SSB, a floating gate electrode FG formed on the semiconductor substrate SSB through a tunnel oxide film TOX, a control gate electrode GE formed on the floating gate electrode FG through an interlayer dielectric ILI, a source region SSR formed in a portion of the semiconductor substrate SSB on a side of the floating gate electrode FG, and a drain region SDR formed in a portion of the semiconductor substrate SSB on the other side of the floating gate electrode FG. The tunnel oxide film TOX is made of, for example, silicon oxide (SiO). The floating gate electrode FG is also made of, for example, polysilicon. Further, the interlayer dielectric ILI is made of silicon oxide (SiO) or silicon oxide (SiO) and silicon nitride (SiN). In addition, the control gate electrode GE is made of polysilicon or metal silicide. The thickness of the tunnel oxide film TOX of the present embodiment is, for example, 10 nm or less.

[0060] Further, as shown in Figure 4 , the control gate electrode GE and the floating gate electrode FG are covered with a contact interlayer dielectric layer CIL. Then, a wiring WL formed on the contact interlayer dielectric layer CIL is electrically connected to the drain region SDR or the source region SSR via a contact plug PLG that penetrates the contact interlayer dielectric layer CIL. Note that N-type or P-type impurity ions are implanted into each of the source region SSR and the drain region SDR. Then, each of the contact interlayer dielectric layer CIL, the contact plug PLG, the wiring WL, and the interlayer dielectric layer IL that covers the wiring WL is one of the materials that constitute the above-described multilayer wiring layer MWL.

[0061] To write data into the non-volatile memory NVM, hot electrons generated by heating of electrons flowing from the source region SSR toward the drain region SDR near the drain region SDR are moved (injected) into the floating gate electrode FG as a charge storage region through the tunnel oxide film TOX. On the other hand, to erase data written into the non-volatile memory NVM, electrons accumulated in the floating gate electrode FG are extracted from the floating gate electrode FG by applying a high electric field between the source region SSR and the floating gate electrode FG.

[0062] <Effects of the semiconductor device SMD according to the present embodiment>

[0063] Next, the effects of the semiconductor device SMD according to the present embodiment will be described.

[0064] First, in the present embodiment, as shown in Figure 1 and Figure 2 each, the semiconductor chip CP is electrically connected to the interposer WSB via the bump electrode BE. That is, the bump electrode BE is used as a means for electrically connecting the semiconductor chip CP and the interposer WSB. Therefore, compared to a configuration in which the semiconductor chip and the interposer are electrically connected via a solder wire such as, for example, Patent Literature 3, the transmission rate of a signal can be improved.

[0065] Further, in the present embodiment, as shown in Figure 2 , the bump electrode BE including tin (Sn) is formed on the pad BP including aluminum (Al) via the conductive film UBM including nickel (Ni). That is, the bump electrode BE including tin (Sn) does not directly contact the pad BP including aluminum (Al). Therefore, diffusion of tin (Sn) constituting the bump electrode BE to the pad BP can be suppressed.

[0066] In the present embodiment, as shown in Figure 2 , the probe mark PBD is formed on the surface BPS of the pad BP located in the region RG2. That is, the probe mark PBD is not formed on the surface BPS of the pad BP located in the region RG1. Therefore, a decrease in the joining reliability between the conductive film UBM and the pad BP can be suppressed.

[0067] In the present embodiment, as shown in Figure 2 , the probe mark PBD is formed on the surface BPS of the pad BP located in the region RG2. That is, the probe mark PBD is not formed on the surface of the conductive film UBM. Therefore, a decrease in the joining reliability between the bump electrode BE and the conductive film UBM can be suppressed.

[0068] In the present embodiment, as shown in Figure 3 , the planar shape of the portion of the pad BP (the portion having the region RG2 but not the region RG1) that contacts the probe PBP is a substantially rectangular shape whose width is smaller than the diameter of the portion of the pad BP on which the bump electrode BE is formed above. Therefore, the area occupied by each pad BP can be reduced. That is, miniaturization or multi-pin of the semiconductor chip can be achieved.

[0069] Further, in the present embodiment, as shown in Figure 3 , the lead-out wiring LOL is not connected to the portion (the portion having the region RG2 but not the region RG1) that the probe PBP is to contact, but is connected to the portion (the portion having the region RG1 but not the region RG2) on which the bump electrode BE is formed. That is, on the main path through which a signal is transmitted between the semiconductor chip CP and an external device, the probe mark PBD is not formed. Therefore, a high-speed semiconductor device can be achieved.

[0070] <Method of manufacturing semiconductor device SMD according to the present embodiment>

[0071] Next, the manufacturing method of the semiconductor device SMD according to the present embodiment will be described with reference to Figures 5-17 Figure 5 is a process flow chart showing the manufacturing process of the semiconductor device according to the present embodiment.

[0072] 1. Wafer preparation Figure 5 (step S1)

[0073] First, as step S1 in Figure 5 , a semiconductor wafer SWF is provided. As shown in Figure 6 , the semiconductor wafer SWF has a plurality of chip forming portions CFP arranged in a matrix. Incidentally, each chip forming portion CFP, which will become a semiconductor chip CP, is obtained by performing a wafer cutting step (step S6 in Figure 5 , which will be described later.

[0074] In the present embodiment, the respective manufacturing steps of the semiconductor device SMD will be described using one of the above-mentioned plurality of chip forming portions CFP. Further, in the present embodiment, as shown in Figure 7 , the state after the above-mentioned insulating film IF (in particular, the protective film PIF) and the respective openings OP1, OP2 are formed on the semiconductor substrate SSB on which the semiconductor wafer SWF is made will be described. Incidentally, Figure 7 is an enlarged cross-sectional view of the semiconductor chip at the "A" portion of Figure 1 . The protective film PIF of the present embodiment is formed by placing (supplying) an organic material on the semiconductor substrate SSB and then performing heat treatment on the organic material. More specifically, the protective film PIF of the present embodiment is made of a thermosetting polyimide resin having fluidity before curing. Further, the heat treatment temperature at the time of curing the organic material is, for example, 300°C to 400°C. The heat treatment time each time is, for example, 30 minutes to 2 hours.

[0075] 2. Wafer test Figure 5 (step S2)

[0076] Next, the wafer test is performed as step S2 in Figure 5 . In the wafer test of the present embodiment, as shown in Figure 8 , the probe PBP is brought into contact with the surface BPS of the pad BP located in the region RG2, thereby writing desired data into the nonvolatile memory NVM formed in the semiconductor substrate SSB. By performing this process, as shown in Figure 8 ​As shown, a probe mark PBD is formed on the surface BPS of the pad BP located in region RG2 by contacting the probe PBP.

[0077] 3. Screening test ( Figure 5 Step S3)

[0078] Next, the screening test (also known as the "acceleration test") is used as... Figure 3 Step S3. In the screening test of this embodiment, firstly, the semiconductor substrate SSB (i.e., semiconductor wafer SWF) on which data is written to the non-volatile memory NVM during the above-described wafer testing process is subjected to heat treatment. Note that the heat treatment temperature in this screening test step is lower than the heat treatment temperature during the formation of the above-described protective film PIF, and in this embodiment, it is, for example, 200°C to 280°C. The heat treatment time for each step is longer than the heat treatment time during the formation of the above-described protective film PIF, for example, 6 hours to 50 hours.

[0079] Next, check whether the data written to the non-volatile memory (NVM) can be read or check the non-volatile memory (NVM) that has been written to during the above-mentioned wafer testing process, that is, the memory circuit is accessed.

[0080] 4. Formation of conductive film ( Figure 5 Step S4)

[0081] Next, as Figure 5 Step S4 in the process forms the base portion of the conductive film UBM. (Refer to...) Figures 9-11 Describe a method for forming a conductive film UBM.

[0082] First, such as Figure 9 As shown, a seed layer SDL made of, for example, copper (Cu) is formed on a semiconductor substrate SSB (i.e., semiconductor wafer SWF). In this embodiment, the seed layer SDL is formed by, for example, a PVD (physical vapor deposition) method. Therefore, the seed layer SDL is formed not only on the surface BPS of the pads BP located at each region RG1, RG2, but also on the insulating film IF, as shown. Figure 9 As shown. Figure 9 As shown, the probe marker PBD is covered by the seed layer SDL.

[0083] Next, as Figure 10 As shown, a resist pattern RSM is formed on a semiconductor substrate SSB. More specifically, first, resist material is placed on an insulating film IF to cover regions RG1 and RG2, and then the resist material is processed, for example by photolithography, to expose a seed layer SDL formed on the front surface BPS of the pad BP located on region RG1. As a result, as... Figure 10As shown in FIG. 6, the region RG2 is covered with the resist pattern RSM, and the portion of the seed layer SDL formed on the region RG1 is exposed from the opening OP3 of the resist pattern RSM.

[0084] Next, as Figure 11 As shown in FIG. 6, the barrier layer BRL made of, for example, nickel is formed on the portion of the seed layer SDL including the portion formed on the region RG1. In the present embodiment, for example, the barrier layer BRL is formed by electroplating using the resist pattern RSM as a mask. More specifically, as Figure 11 As shown in FIG. 6, the step of forming the barrier layer BRL is performed in a state in which the surface BPS of the pad BP located in the region RG2 is covered with the resist pattern RSM, and in a state in which the seed layer SDL formed on the surface BPS of the pad BP located in the region RG1 is exposed from the resist pattern RSM.

[0085] By the above process, the base portion of the conductive film UBM composed of the seed layer SDL and the barrier layer BRL is formed on the front surface BPS of the pad BP located in the region RG1.

[0086] 5. Bump electrode formation Figure 5 in the step S5

[0087] Next, as Figure 5 the step S5 in FIG. 6, the bump electrode BE including tin (Sn) is formed. Incidentally, in the present embodiment, the bump electrode BE is formed using an electrolytic plating method similarly to the barrier layer BRL constituting the conductive film UBM. In the present embodiment, the resist pattern RSM used in the step of forming the conductive film UBM continues to be used as a mask in the present step.

[0088] More specifically, as Figure 12 shown in FIG. 7, the solder material SM1 of a so-called binary alloy including tin (Sn) and silver (Ag) is supplied to the inside of the opening OP3 of the resist pattern RSM, so that the opening OP3 of the resist pattern RSM is closed with the solder material.

[0089] Thereafter, as Figure 13 shown in FIG. 8, the resist pattern RSM is removed. As a result, as Figure 13 shown in FIG. 8, the portion of the seed layer SDL formed on the insulating film IF, which was covered with the resist pattern RSM, is exposed.

[0090] Next, as Figure 14As shown in FIG. 6, a portion of the seed layer SDL exposed from the solder material SM1 and the barrier layer BRL is removed from the seed material SDL using the solder material SM1 and the barrier layer BRL as masks. In this embodiment, the unnecessary portion of the seed layer SDL is removed by wet etching. As a result, the conductive film UBM including the seed layer SDL and the barrier layer BRL is formed.

[0091] After the unnecessary portion of the seed layer SDL is removed, the solder material SM1 formed in the above step is subjected to heat treatment. Thus, as shown in FIG. 7, the solder material SM1 is melted and the solder material SM1 is formed in a spherical shape. The heat treatment temperature in this step is lower than the heat treatment temperature at the time of formation of the above protective film PIF, and in this embodiment, the temperature is, for example, 100°C to 270°C. In addition, the heat treatment time is shorter than the heat treatment time in the above screening test step, and is, for example, several tens of seconds to 5 minutes. Figure 15

[0092] 6. Wafer dicing Figure 5 Step S6 in FIG. 6

[0093] Next, as Step S6 of FIG. 6, the plurality of chip formation portions CFP are separated from each other by dicing the semiconductor wafer SWF. More specifically, the plurality of chip formation portions CFP are separated from each other by passing a dicing blade (not shown) between two chip formation portions CFP adjacent to each other among the plurality of chip formation portions CFP shown in FIG. 6. Then, each chip formation portion CFP is obtained to obtain a semiconductor chip CP having the bump electrode BE, the conductive film UBM, the pad BP, and the nonvolatile memory NVM. Figure 6 Figure 6 7. Flip chip mounting Step S7 in FIG. 6

[0094] Figure 5 Next, as Step S7 of FIG. 6, the semiconductor chip CP having the bump electrode BE obtained by the above steps is mounted on the interposer WSB via the bump electrode BE. More specifically, as shown in FIG. 7, the semiconductor chip CP is placed on the interposer WSB with the surface (also referred to as "main surface") of the semiconductor substrate SSB constituting the semiconductor chip CP, which is on the side on which the bump electrode BE is formed, facing the upper surface WSBU of the interposer WSB. Then, as shown in FIG. 8, the semiconductor chip CP is heated to a temperature higher than the heat treatment temperature in Step S6 of FIG. 6, and the solder material SM1 is melted to form a solder bump SB. The heat treatment temperature in this step is, for example, 100°C to 270°C. In addition, the heat treatment time is, for example, several tens of seconds to 5 minutes.

[0095] Figure 5 Figure 16 Figure 16 ​​​​​As shown, while heating the interposer layer WSB (particularly the bump electrode BE) of the semiconductor substrate SSB that makes up the semiconductor chip CP and each of the semiconductor chip CP, the bump electrode BE is not formed on the surface (also referred to as the "back surface") located on one side of the pressing and bonding tool BT. That is, as Figure 16 As shown, a vertical load (in the direction of the arrow) is applied to the semiconductor chip CP. Therefore, the semiconductor chip CP (specifically, the "pad BP") is electrically connected to the interposer WSB (specifically, the "bond lead BOL") via the thermally melted bump electrode BE. The heat treatment temperature during flip chip mounting is lower than the heat treatment temperature during the formation of the protective film PIF, and in this embodiment, this temperature is, for example, 220°C to 260°C. Furthermore, the heat treatment time for each step is shorter than the heat treatment time in the screening test step described above, for example, from a few seconds to one minute.

[0096] 8. Resin supply ( Figure 5 Step S8)

[0097] Next, resin SR is used to seal between the semiconductor chip CP and the interposer WSB. More specifically, as... Figure 17 As shown, a nozzle NZL is placed near the semiconductor chip CP between the semiconductor chip CP and the interposer WSB, and a resin SR containing various fillers is supplied from the nozzle NZL. Heat is applied to the resin SR supplied between the semiconductor chip CP and the interposer WSB to cure the resin SR. Note that the heat treatment temperature in this resin supply step is lower than the heat treatment temperature during the formation of the protective film PIF described above, and in this embodiment, it is, for example, 100°C to 200°C. In addition, the heat treatment time for each step is shorter than the heat treatment time in the screening test process described above, for example, 10 seconds to 2 hours.

[0098] 9. External connection terminal formation ( Figure 5 Step S9)

[0099] After that, as Figure 5 In step S9, an external connection terminal EXT including tin (Sn) is formed (see... Figure 1 More specifically, a solder material comprising a so-called ternary alloy of tin (Sn), silver (Ag), and copper (Cu) is placed on corresponding bosses BUL formed on the lower surface WSBL of the interposer WSB. The solder material is then subjected to heat treatment. As a result, a generally spherical external connection terminal EXT is formed on each boss BUL. The heat treatment temperature in the external connection terminal formation step is lower than the heat treatment temperature during the formation of the protective film PIF described above, and in this embodiment, this temperature is, for example, 100°C to 270°C. Furthermore, the heat treatment time for each step is shorter than the heat treatment time in the screening test step described above, for example, tens of seconds to 5 minutes.

[0100] By the above steps, the semiconductor device SMD is mounted on the interposer WSB by manufacturing the bump electrode BE with the semiconductor chip CP. The complete semiconductor device SMD is later mounted on a mother board via external connection terminals EXT. Incidentally, among the temperatures of the heat treatments performed after the formation of the pad BP on the semiconductor wafer SWF (i.e., the semiconductor substrate SSB) before the mounting of the semiconductor device SMD on the mother board, the heat treatment temperature of the organic material constituting the protective film PIF is the highest. Further, among the times of the heat treatments performed after the formation of the pad BP on the semiconductor wafer SWF (i.e., the semiconductor substrate SSB) before the mounting of the semiconductor device SMD on the mother board, the time of the heat treatment in the screening test step is the longest.

[0101] <Effects of the method of manufacturing the semiconductor device SMD according to the present embodiment>

[0102] Next, the effects of the method of manufacturing the semiconductor device SMD according to the present embodiment will be described.

[0103] First, in the present embodiment, as shown in FIG. 1, the wafer test (step S2) and the screening test (step S3) are performed after the wafer preparation step (step S1) in the manufacturing process of the semiconductor device SMD. Figure 5 Figure 5 Figure 5 Figure 5 ​​​step S3) in FIG. 10. That is, in the present embodiment, after data is written in the nonvolatile memory NVM, heat treatment is performed on the semiconductor wafer SWF (i.e., the semiconductor substrate SSB) on which the nonvolatile memory NVM is formed, and then, after heat treatment is performed on the organic material constituting the insulating film IF (i.e., the protective film PIF), the inspection step of the nonvolatile memory NVM on which data is written is performed. Here, as described above, the heat treatment performed on the organic material constituting the protective film PIF is at a temperature of at least 300°C or higher. In addition, the heat treatment is for a time of at least several tens of minutes or more. Further, under the heat treatment conditions of 300°C or higher and several tens of minutes or more, data written in the nonvolatile memory NVM is easily lost. In particular, when the thickness of the tunnel oxide film TOX constituting the nonvolatile memory NVM is reduced, data loss becomes significant. On the other hand, under heat treatment conditions of several seconds, data is hardly lost even if the thickness of the tunnel oxide film is reduced and even if the temperature of the heat treatment is less than 300°C or greater than or equal to 300°C. Then, in the present embodiment, as described above, heat treatment for forming the protective film PIF is completed before data is written in the nonvolatile memory NVM. Therefore, even if the thickness of the tunnel oxide film TOX making up the nonvolatile memory NVM is reduced (specifically, "thinned") in order to achieve miniaturization of the semiconductor device, data written in the nonvolatile memory NVM can be prevented from disappearing due to the heat treatment conditions (particularly, the temperature) performed on the organic material.

[0104] In the present embodiment, the wafer test (step S2) in FIG. 10 and the screening test (step S3) in FIG. 10 are performed after the wafer preparation step (step S1) in FIG. 10 and before the bump electrode formation step (step S5) in FIG. 10, as shown in FIG. 11. That is, in the present embodiment, after data is written in the nonvolatile memory NVM, heat treatment is performed on the semiconductor wafer SWF (i.e., the semiconductor substrate SSB) on which the nonvolatile memory NVM is formed, and then, after heat treatment is performed on the organic material constituting the insulating film IF (i.e., the protective film PIF), the nonvolatile memory NVM on which data is written is inspected. As a result, even if the thickness of the tunnel oxide film TOX constituting the nonvolatile memory NVM is reduced, not only can the loss of data written in the nonvolatile memory NVM be prevented, but also oxidation of the surface of the bump electrode BE including tin (Sn) (i.e., degradation of the joining reliability between the bump electrode BE and the soldering lead BOL of the interposer WSB) can be suppressed. Figure 5 Figure 5 In the present embodiment, the wafer test (step S2) in FIG. 10 and the screening test (step S3) in FIG. 10 are performed after the wafer preparation step (step S1) in FIG. 10 and before the bump electrode formation step (step S5) in FIG. 10, as shown in FIG. 11. That is, in the present embodiment, after data is written in the nonvolatile memory NVM, heat treatment is performed on the semiconductor wafer SWF (i.e., the semiconductor substrate SSB) on which the nonvolatile memory NVM is formed, and then, after heat treatment is performed on the organic material constituting the insulating film IF (i.e., the protective film PIF), the nonvolatile memory NVM on which data is written is inspected. As a result, even if the thickness of the tunnel oxide film TOX constituting the nonvolatile memory NVM is reduced, not only can the loss of data written in the nonvolatile memory NVM be prevented, but also oxidation of the surface of the bump electrode BE including tin (Sn) (i.e., degradation of the joining reliability between the bump electrode BE and the soldering lead BOL of the interposer WSB) can be suppressed. Figure 5 Figure 5 In the present embodiment, the wafer test (step S2) in FIG. 10 and the screening test (step S3) in FIG. 10 are performed after the wafer preparation step (step S1) in FIG. 10 and before the bump electrode formation step (step S5) in FIG. 10, as shown in FIG. 11. That is, in the present embodiment, after data is written in the nonvolatile memory NVM, heat treatment is performed on the semiconductor wafer SWF (i.e., the semiconductor substrate SSB) on which the nonvolatile memory NVM is formed, and then, after heat treatment is performed on the organic material constituting the insulating film IF (i.e., the protective film PIF), the nonvolatile memory NVM on which data is written is inspected. As a result, even if the thickness of the tunnel oxide film TOX constituting the nonvolatile memory NVM is reduced, not only can the loss of data written in the nonvolatile memory NVM be prevented, but also oxidation of the surface of the bump electrode BE including tin (Sn) (i.e., degradation of the joining reliability between the bump electrode BE and the soldering lead BOL of the interposer WSB) can be suppressed. Figure 5

[0105] ​​​In addition to the above, in this embodiment, in the wafer fabrication step ( Figure 5 After step S1) and in the conductive film formation step ( Figure 5 Before step S4, perform wafer testing ( Figure 5 Step S2) and screening test ( Figure 5 Step S3 in the process, such as Figure 5 As shown in the diagram. During the conductive film formation process ( Figure 5 After step S4), the bump electrode formation step is performed. Figure 5 Step S5 in the process. In this embodiment, during the bump electrode formation step ( Figure 5 Before step S5) and in the conductive film formation step ( Figure 5 After step S4, the screening test step is not performed. Figure 5 Step S3 in the process. Therefore, oxidation of the surface of the conductive film UBM caused by heat treatment in the screening test step, especially oxidation of the barrier layer BRL, can be suppressed. In addition, as described above, due to the conductive film formation step ( Figure 5 After step S4), the bump electrode formation step is performed. Figure 5 In step S5), the degradation of the bonding reliability between the bump electrode BE and the conductive film UBM can be suppressed. Furthermore, in the bump electrode formation step ( Figure 5 In step S5), due to the conductive film formation step ( Figure 5 The resist pattern RSM used in step S4) continues to be used as a mask, thus further simplifying the manufacturing process.

[0106] In this embodiment, as Figure 5 and Figure 2 As shown, the insulating film IF (specifically, the passivation film PVF and the protective film PIF) is formed not only on the peripheral area of ​​the front surface BPS of the pad BP, but also on the area located between the two regions RG1 and RG2. Here, if the insulating film IF is not formed on the area between the two regions RG1 and RG2, then during heat treatment during bump electrode formation, as... Figure 15 As shown, the center C1 of the bump electrode BE1 to be formed is offset from the desired position (center C). That is, the height of the formed bump electrode BE1 is reduced. Furthermore, in some cases, solder material molten by heat treatment may wet and diffuse onto the surface BPS of the pad BP located on region RG2. Incidentally, if the bump electrode is not formed into the desired shape (i.e., the height of the bump electrode is lower), the gap between the semiconductor chip and the interposer becomes narrower. As a result, in Figure 19In the resin supplying step S8 in the middle, it is difficult to supply resin between the semiconductor chip and the interposer. On the other hand, in the present embodiment, as described above, the insulating film IF is also formed on the region located between the two regions RG1, RG2. Therefore, in the Figure 5 In the bump electrode forming step S5, the bump electrode BE can be formed in a desired shape.

[0107] Further, in the present embodiment, as described above, the insulating film IF is formed not only on the pad BP but also on the region located between the two regions RG1, RG2. Therefore, in the Figure 5 and Figure 2 As shown in each of the above-described embodiments, along the edge of the opening OPl of the insulating film IF, a conductive film UBM is formed on the insulating film IF. Therefore, when a normal load is applied to the semiconductor chip CP in the subsequent flip chip mounting step (step S7 in the Figure 3 , stress transmitted to the region of the multilayer wiring layer MWL overlapping the bump electrode BE can be homogenized. Therefore, as the insulating layer constituting the multilayer wiring layer MWL, for example, even when a low dielectric constant film such as a silicon oxide film (SiOC) to which carbon is added is used, a crack can be suppressed from being formed in the insulating layer due to stress.

[0108] The invention made by the present inventors has been described in detail above based on the embodiments, but the invention is not limited to the above-described embodiments, and needless to say, various modifications can be made without departing from the gist thereof. As a specific example, a modification example of the above-described embodiments will be described below.

[0109] (Modification Example 1)

[0110] First, in the above embodiments, when the junction of the semiconductor chip CP and the interposer WSB was described in detail, it has been described based on the pad BP electrically connected to the nonvolatile memory. Further, as shown in Figure 5 the semiconductor chip of the above-described embodiments has other pads in addition to the above-described pad BP (i.e., electrically connected to the field effect transistor constituting another circuit pad). The configuration of the other pads is also the same as that of the pad BP. However, for the pad which does not need the wafer test process (i.e., the process of contacting the probe PBP) as described above, the probe region RG2 can not be provided as in the above embodiments. Therefore, a multi-pin or small semiconductor chip can be further realized.

[0111] (Modification Example 2)

[0112] Further, in the above embodiments, it has been described that the planar shape of the portion of the pad BP on which the bump electrode BE is formed (the portion having the region RG1 but not the region RG2) is a substantially octagonal shape, as shown in Figure 1 However, the planar shape of the portion is not limited to a polygon, and it can be circular.

[0113] (Modification Example 3)

[0114] Further, in the above embodiment, the organic material constituting the protective film PIF is heat-treated at a time after the organic material is placed (supplied) on the semiconductor substrate SSB, but it is also possible to perform (start) the heat treatment at a time before the organic material is disposed on the semiconductor substrate SSB. However, if the semiconductor substrate SSB is heated before the organic material is placed on the semiconductor substrate SSB, it is possible to cure the organic material before the organic material placed on the semiconductor substrate SSB becomes a desired configuration. Therefore, when a thermosetting polyimide resin having fluidity is used as a constituent material of the protective film PIF before curing, it is preferable to place (supply) the organic material on the semiconductor substrate SSB and then perform heat treatment as in the above embodiment.

[0115] (Modification Example 4)

[0116] Further, in the above embodiment, it has been described that each of the wafer test (step S2 in Figure 3 and the screening test (step S3 in Figure 5 is performed once, but the wafer test, the screening test, or both the wafer test and the screening test can be performed multiple times.

[0117] (Modification Example 5)

[0118] Further, in the above embodiment, it has been described that each of the barrier layer BRL and the solder material SM1 formed using an electrolytic plating method, but it is also possible to form using a chemical plating method.

[0119] (Modification Example 6)

[0120] Further, in the above embodiment, although it has been described that a wet etching method is used as a method of removing the seed layer SDL, it is also possible to use a dry etching method.

[0121] (Modification Example 7)

[0122] Further, in the above embodiment, a configuration in which the semiconductor chip CP is mounted on the interposer WSB through the bump electrode BE, that is, a so-called FCBGA (flip chip ball grid array), is described as the semiconductor device SMD. However, it is also possible to regard a state in which the semiconductor chip CP (that is, Figure 5 step S6 in

[0123] (Modification Example 8)

[0124] Further, in the above embodiment, as a method of sealing between the semiconductor chip CP and the interposer WSB with the resin SR, a method in which the resin SR is supplied to the semiconductor chip CP and the interposer WSB and then heat treatment is performed is described. However, it is also possible to use a method in which the resin SR is supplied to the semiconductor chip CP and the interposer WSB and then heat treatment is performed.Figure 5 As shown in FIG. 1, a so-called underfill method has been described in which a nozzle NZL is placed near the semiconductor chip CP, and from the nozzle NZL, the resin SR is supplied between the semiconductor chip CP and the interposer WSB. However, a so-called transfer mold method can be used in which the interposer WSB on which the semiconductor chip CP is mounted on the upper surface is set in a mold to form a sealing body made of the resin SR on the interposer WSB so as to cover the semiconductor chip CP.

[0125] (Modification Example 9)

[0126] Further, in the above embodiment, a plurality of pads BP arranged along each side of the semiconductor chip CP (i.e., the semiconductor substrate SSB) has been described. However, as Figure 17 As shown in FIG. 1, a plurality of pads BP, BPE, BPN, along each side CPS of the semiconductor chip CPI, can be arranged in a matrix. Incidentally, stress can concentrate in a peripheral portion of the semiconductor chip compared to a central portion of the semiconductor chip. Therefore, as Figure 18 As shown in FIG. 1, it is preferable to arrange the pads BP such that a region ("probe region") RG2 of each pad BP is closer to the side surface CPS of the corresponding semiconductor chip CPI than a region ("bump electrode formation region") RGl of each pad BP. Incidentally, as Figure 18 As shown in FIG. 1, among the plurality of pads BP arranged in a matrix, BPE, BPN, for pads BPE located in the outermost peripheral row of the respective regions RGl, RG2, the pads BPE can be arranged along the side surface CPS of the semiconductor chip CPI adjacent thereto. Further, as Figure 18 Figure 18 As shown in FIG. 1, it is preferable to arrange pads BPN having no region ("probe region") RG2 on the diagonal line DGL of the semiconductor chip CPI.

[0127] (Modification Example 10)

[0128] Further, in the above embodiment, the bump electrode BE has been described as a solder bump of a so-called binary alloy including tin (Sn) and silver (Ag), and the external connection terminal EXT is a solder ball of a so-called ternary alloy including tin (Sn), silver (Ag), and copper (Cu), respectively. However, as long as a material having tin (Sn) as a main component, a material other than the solder material made of each of the above components can be used. For example, the external connection terminal EXT can be a solder ball of a so-called binary alloy including tin (Sn) and copper (Cu). Similarly, if a material has aluminum (Al) as a main component, an alloy material obtained by adding copper (Cu), silicon (Si), or the like to aluminum (Al) can be used as a pad.

[0129] (Modification Example 11)

[0130] Further, in the above embodiment, the external connection terminal EXT formed directly on the protrusion BUL has been described. However, for example, the external connection terminal EXT can be formed on the protrusion BUL by a plated film formed of a layer made of nickel (Ni) (a nickel layer), a layer formed on the nickel layer and made of palladium (Pd) (a palladium layer), and a layer formed on the palladium layer and made of gold (Au) (a gold layer).

[0131] (Modified Example 12)

[0132] Further, a part or all of the above-described modified examples can be applied in combination within a range not deviating from the gist of the above-described modified examples.

Claims

1. A method of manufacturing a semiconductor device, comprising: (a) providing a semiconductor wafer, the semiconductor wafer including: a semiconductor substrate; a nonvolatile memory formed in the semiconductor substrate; a pad formed on the semiconductor substrate and electrically connected with the nonvolatile memory, and the pad including aluminum; and an insulating film formed on the semiconductor substrate and including an organic material, wherein a surface of the pad has: a first region exposed in a first opening portion of the insulating film; and a second region exposed in a second opening portion of the insulating film different from the first opening portion, and wherein the insulating film is formed by performing a plurality of first heat treatments on the organic material; (b) after the (a), writing data to the nonvolatile memory by causing a probe to contact the surface of the pad located in the second region; (c) after the (b), performing a plurality of second heat treatments on the semiconductor wafer, and checking the nonvolatile memory to which the data is written in the (b), wherein a temperature of the second heat treatments is lower than a temperature of the first heat treatments, and wherein a time of each of the second heat treatments is longer than a time of each of the first heat treatments; (d) after the (c), forming a barrier layer including nickel on the surface of the pad located in the first region by using an electroplating method; (e) after the (d), forming a first solder material including tin on the barrier layer by using the electroplating method; and (f) after the (e), forming a bump electrode on the surface of the pad located in the first region via the barrier layer by performing a plurality of third heat treatments on the first solder material, wherein a temperature of the third heat treatments is lower than the temperature of the first heat treatments, and wherein a time of each of the third heat treatments is shorter than the time of each of the second heat treatments.

2. The method according to claim 1, wherein the nonvolatile memory includes: a floating gate electrode formed on the semiconductor substrate via a tunnel oxide film including silicon oxide; a control gate electrode formed on the floating gate electrode via one of an interlayer insulating film made of silicon oxide and an interlayer insulating film made of silicon oxide and silicon nitride; a source region formed in a first portion of the semiconductor substrate located on one side of the floating gate electrode; and a drain region formed in a second portion of the semiconductor substrate located on another side of the floating gate electrode, and wherein a thickness of the tunnel oxide film is less than or equal to 10 nm.

3. The method according to claim 2, further comprising: (g) after the (c) and before the (d), forming a seed layer on the semiconductor substrate by using a PVD (Physical Vapor Deposition) method, ​ wherein each of the (d) and the (e) is performed in a state where the surface of the pad located in the second region is covered with a mask, and in a state where the surface of the pad located in the first region is exposed from the mask, and wherein after the (e) and before the (f), a portion of the seed layer exposed from each of the first solder material and the barrier layer is removed.

4. The method according to claim 3, further comprising: (h) after the (f), obtaining a semiconductor chip having the bump electrode, the barrier layer, the pad, and the nonvolatile memory by dicing the semiconductor wafer; and (i) after the (h), mounting the semiconductor chip obtained by the (h) on an interposer via the bump electrode, wherein in the (i), a vertical load is applied to the semiconductor chip.

5. The method according to claim 4, further comprising: (j) after the (i), sealing a gap between the semiconductor chip and the interposer with a resin having a plurality of fillers.

6. The method according to claim 5, wherein the interposer has: an upper surface on which the semiconductor chip is mounted; and a lower surface, opposite the upper surface; a boss formed on the lower surface, wherein the method according to claim 5 further comprises: (k) after the (j), forming a second solder material including tin on the boss; and (l) after the (k), forming an external connection terminal on the boss by performing a plurality of fourth heat treatments on the second solder material, wherein a temperature of the fourth heat treatment is 100°C to 270°C, and wherein a time of each of the fourth heat treatments is several tens of seconds to 5 minutes.

7. A method of manufacturing a semiconductor device, comprising: (a) providing a semiconductor wafer including: a semiconductor substrate; a nonvolatile memory formed in the semiconductor substrate; a pad formed on the semiconductor substrate and electrically connected to the nonvolatile memory, and the pad including aluminum; and an insulating film formed on the semiconductor substrate and including an organic material, wherein a surface of the pad has: a first region exposed in a first opening portion of the insulating film; and a second region exposed in a second opening portion of the insulating film different from the first opening portion, wherein the insulating film is formed by performing a plurality of first heat treatments on the organic material after the organic material is disposed on the semiconductor substrate, wherein a temperature of the first heat treatment is 300°C to 400°C, and wherein a time of each of the first heat treatments is 30 minutes to 2 hours; (b) after the (a), writing data to the nonvolatile memory by bringing a probe into contact with the surface of the pad located in the second region; (c) after the (b), performing a plurality of second heat treatments on the semiconductor wafer, and checking the nonvolatile memory to which the data is written in the (b), (d) after the (c), forming a seed layer on the pad located in the first region by performing a third heat treatment on the semiconductor wafer, wherein a temperature of the third heat treatment is 100°C to 270°C, and wherein a time of the third heat treatment is several tens of seconds to 5 minutes; (e) after the (d), forming a first solder material including tin on the pad located in the first region by performing a fourth heat treatment on the semiconductor wafer, wherein a temperature of the fourth heat treatment is 100°C to 270°C, and wherein a time of the fourth heat treatment is several tens of seconds to 5 minutes; and (f) after the (e), forming a barrier layer on the pad located in the first region by performing a fifth heat treatment on the semiconductor wafer, wherein a temperature of the fifth heat treatment is 100°C to 270°C, and wherein a time of the fifth heat treatment is several tens of seconds to 5 minutes. wherein the second heat treatment has a temperature of 200°C to 280°C, and wherein the second heat treatment has a time of 6 hours to 50 hours each time; (d) after the (c), forming a conductive film including nickel on the surface of the pad located in the first region by using an electroplating method; (e) after the (d), forming a first solder material including tin on the conductive film by using the electroplating method; (f) after the (e), forming a bump electrode on the surface of the pad located in the first region via the conductive film by performing a plurality of third heat treatments on the first solder material, the third heat treatment has a temperature of 100°C to 270°C, and wherein the third heat treatment has a time of several tens of seconds to 5 minutes each time; and (g) after the (f), obtaining a semiconductor chip having the bump electrode, the conductive film, the pad, and the nonvolatile memory by dicing the semiconductor wafer.

8. The method according to claim 7, wherein the nonvolatile memory includes: a floating gate electrode formed on the semiconductor substrate via a tunnel oxide film made of silicon oxide; a control gate electrode formed on the floating gate electrode via one of an interlayer insulating film made of silicon oxide and an interlayer insulating film made of silicon oxide and silicon nitride; a source region formed in a first portion of the semiconductor substrate located on one side of the floating gate electrode; and a drain region formed in a second portion of the semiconductor substrate located on the other side of the floating gate electrode, and wherein a thickness of the tunnel oxide film is less than or equal to 10 nm.

9. The method according to claim 7, wherein the conductive film includes: a seed layer formed on the surface of the pad and including copper; and a barrier layer formed on the seed layer and including nickel, wherein the (d) includes: (d1) forming the seed layer on the semiconductor substrate by using a PVD (Physical Vapor Deposition) method, (d2) after the (d1), forming the barrier layer on the seed layer by using an electroplating method, wherein each of the (d2) and the (e) is performed in a state where the surface of the pad located in the second region is covered with a mask, and in a state where the surface of the pad located in the first region is exposed from the mask, and wherein a portion of the seed layer exposed from each of the first solder material and the barrier layer is removed after the (e) and before the (f).

10. The method according to claim 9, further comprising: (h) after the (g), mounting the semiconductor chip obtained by the (g) on an interposer via the bump electrode, wherein in the (h), a vertical load is applied to the semiconductor chip.

11. The method according to claim 10, further comprising: ​ (i) after the (h), sealing a gap between the semiconductor chip and the interposer with a resin having a plurality of fillers.

12. The method according to claim 11, wherein the interposer has: an upper surface on which the semiconductor chip is mounted; a lower surface opposite to the upper surface; and a bump formed on the lower surface, wherein the method further comprises: (j) after the (i), forming a second solder material including tin on the bump; and (k) after the (j), forming an external connection terminal on the bump by performing a plurality of fourth heat treatments on the second solder material, wherein a temperature of the fourth heat treatments is 100°C to 270°C, and wherein a time of each of the fourth heat treatments is several tens of seconds to 5 minutes.

13. The method according to claim 7, wherein the insulating film includes: a passivation film made of an inorganic material and formed on the semiconductor substrate, and a protective film made of the organic material and formed on the passivation film.

14. The method according to claim 7, wherein the semiconductor wafer includes a plurality of wiring layers formed on the semiconductor substrate, wherein a wiring layer located in an uppermost layer of the plurality of wiring layers includes: the pad; and a lead-out wiring connected to the pad, wherein the lead-out wiring is led out from the first region of the pad but is not led out from the second region of the pad, and wherein the bump electrode is electrically connected to the nonvolatile memory via (1) the lead-out wiring connected to the pad and (2) a via wiring connected to the lead-out wiring.

15. The method according to claim 7, wherein the pad has: a first portion having the first region on which the bump electrode is formed; and a second portion having the second region on which the bump electrode is not formed, wherein a shape of the first portion in a plan view is octagonal, and wherein a shape of the second portion in a plan view is quadrangular having a width smaller than a diameter of the first portion. ​

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