Semiconductor structure and method for manufacturing the same

Abstract

The present disclosure relates to a semiconductor structure and a method for manufacturing the same. The semiconductor interconnect structure includes a conductive circuit electrically coupled to an active semiconductor device, a first etch stop layer formed on the conductive circuit; a first dielectric layer formed on the first etch stop layer; a second etch stop layer formed on the first dielectric layer; a second dielectric layer formed on the second etch stop layer; and an interconnect structure electrically coupled to the conductive circuit and extending through the first etch stop layer, the first dielectric layer, the second etch stop layer, and the second dielectric layer. The interconnect structure includes a through hole extending through the first etch stop layer, the second etch stop layer, and the first dielectric layer; and a trench extending through the second dielectric layer.

Description

Technical Field

[0001] The disclosed embodiments relate to semiconductor devices and methods for manufacturing the same, and more particularly to interconnect structures formed during an integrated circuit manufacturing process. Background Art

[0002] Semiconductor devices are used in a variety of electronic units, and there is a general need to improve the performance and yield of semiconductor devices. As these devices continue to shrink, it becomes a challenge to create efficient and viable interconnect structures. Summary of the invention

[0003] One embodiment of the present disclosure is a semiconductor structure. The semiconductor structure includes a conductive circuit electrically coupled to an active semiconductor device, a first etch stop layer formed on the conductive circuit; a first dielectric layer formed on the first etch stop layer; a second etch stop layer formed on the first dielectric layer; a second dielectric layer formed on the second etch stop layer; and an interconnect structure electrically coupled to the conductive circuit and extending through the first etch stop layer, the first dielectric layer, the second etch stop layer, and the second dielectric layer. The interconnect structure includes a through hole extending through the first etch stop layer, the second etch stop layer, and the first dielectric layer; and a trench extending through the second dielectric layer.

[0004] Another embodiment of the present disclosure is a method for manufacturing a semiconductor structure. The method includes: forming a first etch stop layer on a conductive circuit, and the conductive circuit is electrically coupled to an active semiconductor device; forming a first dielectric layer on the first etch stop layer; forming a second etch stop layer on the first dielectric layer; removing a portion of the second etch stop layer to expose a portion of the first dielectric layer; forming a second dielectric layer on the second etch stop layer and the first dielectric layer; removing a portion of the second dielectric layer, a portion of the first dielectric layer, and a portion of the first etch stop layer to form an opening and expose the conductive circuit; and filling the opening with a conductive material.

[0005] Another embodiment of the present disclosure is another method for manufacturing a semiconductor structure. The method includes: forming a first etch stop layer on a conductive circuit, and the conductive circuit is electrically coupled to an active semiconductor device; forming a first dielectric layer on the first etch stop layer; forming a second etch stop layer on the first dielectric layer; forming an insulating layer on the second etch stop layer; removing a first portion of the insulating layer and a portion of the second etch stop layer to expose a portion of the first dielectric layer; forming a second dielectric layer on the second etch stop layer and the first dielectric layer; removing a portion of the second dielectric layer, a portion of the first dielectric layer, a second portion of the insulating layer, and a portion of the first etch stop layer to form an opening and expose the conductive circuit; and filling the opening with a conductive material. BRIEF DESCRIPTION OF THE DRAWINGS

[0006] Figure 1is a cross-sectional view of an internal connection structure in some embodiments.

[0007] Figure 2 In some embodiments, Figure 1 Another cross-sectional view of the internal connection structure.

[0008] Figure 3A In some embodiments, the production Figure 1 Flowchart of the process for manufacturing the internal wiring structure.

[0009] Figures 3B to 3H In some embodiments, Figure 1 The internal connection structure of Figure 3A Cross-sectional views of various steps in the manufacturing process.

[0010] Figure 4A In some embodiments, the production Figure 1 Flowchart of another process for manufacturing an internal interconnect structure.

[0011] Figures 4B to 4J In some embodiments, Figure 1 The internal connection structure of Figure 4A Cross-sectional views of various steps in the manufacturing process.

[0012] The reference numerals are described as follows:

[0013] W1, W2: Width

[0014] 100: Internal connection structure

[0015] 102, 104: Through hole

[0016] 112, 114: Groove

[0017] 121, 122, 123, 124, 125, 126, 127, 128: Conductive circuits

[0018] 130: Conductive filling layer

[0019] 142: First etching stop layer

[0020] 144: Second etching stop layer

[0021] 146: Third etching stop layer

[0022] 150: Interlayer dielectric layer

[0023] 162, 164, 166: Intermetallic dielectric layer

[0024] 170: Insulation layer

[0025] 300, 400: Process

[0026] 301, 302, 303, 304, 305, 306, 307, 401, 402, 403, 404, 405, 406, 407, 408, 409: Steps

[0027] 310, 320: Photoresist

[0028] 342, 344: Buffer layer

[0029] 352: Mask layer

[0030] 502, 504, 602, 604, 702, 704: Open

[0031] 802: First Opening

[0032] 804: Second opening DETAILED DESCRIPTION

[0033] The following detailed description may be accompanied by drawings to facilitate understanding of various aspects of the present disclosure. It is worth noting that the various structures are only for illustrative purposes and are not drawn to scale, as is common in the industry. In fact, the dimensions of the various structures may be increased or decreased arbitrarily for clarity of description.

[0034] It should be understood that the following disclosure provides many different embodiments or examples to implement different structures of the present disclosure. The embodiments of specific components and arrangements are used to simplify the present disclosure rather than to limit the present disclosure. For example, the description of forming a first component on a second component includes direct contact between the two, or there are other additional components between the two instead of direct contact. In addition, multiple examples of the present disclosure may repeatedly use the same number for simplicity, but the elements with the same number in multiple embodiments and / or settings do not necessarily have the same corresponding relationship.

[0035] In addition, spatially relative terms such as "below," "beneath," "below," "above," "above," or similar terms may be used to simplify the description of the relative relationship of one element to another element in a diagram. Spatially relative terms may be extended to elements used in other orientations, not limited to the orientation shown in the diagram. Elements may also be rotated 90° or other angles, so directional terms are only used to describe the orientation shown in the diagram.

[0036] The disclosed embodiments provide an interconnect structure to facilitate electrical connection of semiconductor devices in an integrated circuit. The interconnect structure includes an additional etch stop layer formed around the junction of a through hole and a trench of the interconnect structure. The additional etch stop layer can serve as a hard mask, and the additional etch stop layer can be patterned before removing a major portion of the dielectric material for filling with a conductive material. The interconnect structure can improve the crystal plane control of the through hole, especially as the critical dimensions of the semiconductor device continue to shrink. As the critical dimensions continue to shrink, challenges such as loss of mask material, limited process tolerances, and inconsistency with the through hole profile will be faced.

[0037] Figure 1 1 is a cross-sectional view of an interconnect structure 100 in some embodiments. The method for forming the interconnect structure 100 is generally a back-end process of an integrated circuit manufacturing process. The interconnect structure 100 is generally useful for electrically connecting individual semiconductor devices (such as transistors) and circuits in an integrated circuit.

[0038] The interconnect structure 100 includes an interlayer dielectric layer 150 and a plurality of conductive lines such as a conductive line 121, a conductive line 122, a conductive line 123, a conductive line 124, a conductive line 125, a conductive line 126, a conductive line 127, and a conductive line 128. The interlayer dielectric layer 150 may be made of a dielectric material with a low dielectric constant such as an oxide of tetraethoxysilane, silicon oxide, or other suitable materials. The interlayer dielectric layer 150 generally provides electrical isolation between the closely arranged conductive lines 121, the conductive lines 122, the conductive lines 123, the conductive lines 124, the conductive lines 125, the conductive lines 126, the conductive lines 127, and the conductive lines 128. The interlayer dielectric layer 150 is formed of a dielectric material with a low dielectric constant, so that the interlayer dielectric layer 150 can minimize the capacitive coupling (crosstalk) between the conductive lines 121, 122, 123, 124, 125, 126, 127, and 128 while providing electrical isolation. Each of the conductive lines 121, 122, 123, 124, 125, 126, 127, and 128 can be connected to one or more active devices (such as transistors or the like) formed in the front end of the integrated circuit manufacturing process. For example, the conductive lines 121, 122, 123, 124, 125, 126, 127, and 128 can be connected to a conductive contact electrically coupled to a transistor gate.

[0039] The interconnect structure 100 also includes a through hole 102 and a groove 112. The through hole 102 is a common through hole structure, which can be electrically connected to the conductive line 122 and the groove 112. The groove 112 is a common conductive groove such as a copper interconnect. The through hole 102 and the groove 112 can be composed of a variety of suitable conductive materials or combinations thereof, such as copper, aluminum, or other conductive materials. Figure 1 In the embodiment, the through hole 102 has a width W1, and the trench 112 has a width W2. In some embodiments, the width W1 is 5 nm to 15 nm, but other widths outside this range may also be implemented. In some embodiments, the width W2 is 15 nm to 20 nm, but other widths outside this range may also be implemented. The through hole 102 and the trench 112 may be formed by a variety of suitable processes, such as a dual damascene process. The manufacturing process of the through hole 102 and the trench 112 will be described in detail as follows.

[0040] The interconnect structure 100 also includes a through hole 104 and a groove 114. The through hole 104 is a common through hole structure, which can be electrically connected to the conductive line 126 and the groove 114. The groove 114 is a common conductive groove such as a copper interconnect. The composition of the through hole 104 and the groove 114 can adopt a variety of suitable conductive materials or combinations thereof, such as copper, aluminum, or other conductive materials. Some embodiments are similar to the through hole 102, and the width of the through hole 104 is 5nm to 15nm, but other widths outside this range can also be implemented. In addition, some embodiments are similar to the through hole 104, and the width of the groove 114 is 15nm to 20nm, but other widths outside this range can also be implemented. The method for forming the through hole 104 and the groove 114 can adopt a variety of suitable processes such as a dual damascene process. The manufacturing process for forming the through hole 104 and the groove 114 will be described in detail as follows.

[0041] The interconnect structure 100 includes a first etch stop layer 142, a second etch stop layer 144, and a third etch stop layer 146. The materials of the first etch stop layer 142, the second etch stop layer 144, and the third etch stop layer 146 generally have different etching characteristics from surrounding materials (such as the intermetallic dielectric layer 162, the intermetallic dielectric layer 164, the intermetallic dielectric layer 166, and the insulating layer 170). Since the first etch stop layer 142, the second etch stop layer 144, and the third etch stop layer 146 have different etching characteristics (such as different etching selectivities) from the surrounding materials, various etching processes used to fabricate the interconnect structure 100 can be improved. The materials of the first etch stop layer 142, the second etch stop layer 144, and the third etch stop layer 146 can be silicon nitride, silicon oxide, silicon carbide, other suitable materials, or combinations thereof. In some embodiments, the first etch stop layer 142, the second etch stop layer 144, and the third etch stop layer 146 may be made of aluminum oxide, and the thickness of each of the first etch stop layer 142, the second etch stop layer 144, and the third etch stop layer 146 is to However, thicknesses outside this range may also be implemented. The second etch stop layer 144 is particularly useful for improving the crystal plane control of the vias 102 and 104 , and can be used as a hard mask when patterning the vias 102 and 104 .

[0042] The interconnect structure 100 also includes an intermetallic dielectric layer 162, an intermetallic dielectric layer 164, and an intermetallic dielectric layer 166. A variety of materials or combinations thereof may be used to form the intermetallic dielectric layer 162, the intermetallic dielectric layer 164, and the intermetallic dielectric layer 166, such as extremely low dielectric constant materials such as oxides, nitrides, or other suitable materials. The intermetallic dielectric layer 162 is formed between the first etch stop layer 142 and the second etch stop layer 144. The intermetallic dielectric layer 164 is formed between the insulating layer 170 and the third etch stop layer 146. The intermetallic dielectric layer 166 is formed on the third etch stop layer 146 and is at least partially formed around the conductive fill layer 130.

[0043] The interconnect structure 100 also includes an insulating layer 170. The insulating layer may be made of a variety of suitable materials, such as a low-k dielectric material, a high-k dielectric material, other suitable materials, or a combination thereof. For example, the insulating layer may be made of silicon oxide, silicon nitride, or other suitable materials. In some embodiments, the insulating layer 170 may be made of silicon oxide, and its thickness may be to However, other thicknesses outside this range may also be implemented. The interconnect structure 100 also includes a conductive filling layer 130 formed on the IMD layer 166 to electrically connect different layers of the integrated circuit.

[0044] It should be understood that Figure 1 Additional layers and materials beyond those described above may be used to implement the interconnect structure 100. For example, various barrier metal layers, seed layers, conductive layers, dielectric layers, and other types of layers and materials suitable for integrated circuits may be implemented in the interconnect structure 100, depending on the intended application. Figure 1 Predetermined embodiments are shown, and a person skilled in the art should understand that various suitable methods applicable to this implementation belong to the scope of the embodiments of the present disclosure.

[0045] Figure 2 FIG. 1 is another cross-sectional view of the interconnect structure 100 in some embodiments. Figure 2 As shown, before patterning the IMD layer 162 and the IMD layer 164 to fill the conductive material, an opening (such as the opening 602 described below) is formed into the insulating layer 170 and the second etch stop layer 144 for the via 102. This process will be described in detail below. The second etch stop layer 144 can protect the angle of the via 102 because the via 102 is not limited by the process of patterning the IMD layer 162 and the IMD layer 164. Figure 2 As shown, the mask layer 352 is located between the buffer layer 342 and the buffer layer 344. In some embodiments, the mask layer 352 is a hard mask composed of titanium nitride, and the buffer layer 342 and the buffer layer 344 are composed of tetraethoxysilane oxide. However, other materials or combinations thereof can also be used to form the mask layer 352, the buffer layer 342, and the buffer layer 344. Figure 2 As shown, the mask layer 352 and the buffer layers 342 and 344 are protected because the openings used for forming the through hole 102 are formed in the insulating layer 170 and the second etch stop layer 144 before forming openings in the IMD layer 162 and the IMD layer to fill the conductive material.

[0046] Figure 3A is a flow chart of a process 300 for fabricating the interconnect structure 100 . FIG. 3B to FIG. 3H 3 is a cross-sectional view of the interconnect structure 100 at each step of the process 300. Generally speaking, the process 300 includes forming openings for the vias 102 and 104, which may be patterned into the second etch stop layer 144, before forming openings to fill with conductive materials to ultimately form the vias 102 and 104 and the trenches and trenches 114.

[0047] Step 301 forms a first dielectric layer, a second etching stop layer, and an insulating layer on the first etching stop layer ( Figure 3B ).like Figure 3BAs shown, an intermetallic dielectric layer 162 is formed on the first etch stop layer 142, a second etch stop layer 144 is formed on the intermetallic dielectric layer 162, and an insulating layer 170 is formed on the second etch stop layer 144. The method for forming the intermetallic dielectric layer 162 on the first etch stop layer 142 can adopt a variety of suitable processes such as chemical vapor deposition, physical vapor deposition, atomic layer deposition, other suitable processes, or a combination of the above. The method for forming the second etch stop layer 144 on the first etch stop layer 142 can adopt a variety of suitable processes such as chemical vapor deposition, physical vapor deposition, atomic layer deposition, other suitable processes, or a combination of the above. The method for forming the insulating layer 170 on the second etch stop layer 144 can adopt a variety of suitable processes such as chemical vapor deposition, physical vapor deposition, atomic layer deposition, other suitable processes, or a combination of the above.

[0048] Step 302: Apply photoresist on the insulating layer ( Figure 3C ).like Figure 3C As shown, a photoresist 310 is applied on the insulating layer 170. Figure 3C As shown, opening 502 and opening 504 are formed on photoresist 310. Prior to applying photoresist 310 in step 302, various protective layers may be applied to insulating layer 170, such as a bottom anti-reflective coating. A grinding step and other preparatory steps may also be performed. The method of applying photoresist 310 to insulating layer 170 may adopt a variety of suitable processes, including spin coating, other suitable processes, or a combination of the above. The mask may be aligned with opening 502 and opening 504 to be exposed to ultraviolet light during the photolithography process, which ultimately facilitates the formation of through-hole openings in strategic locations of insulating layer 170 to place through-hole 102 and through-hole 104, respectively, as described below.

[0049] Step 303: Patterning the insulation layer ( Figure 3D ).like Figure 3D As shown, the insulating layer 170 is patterned to form an opening 602 and an opening 604. In step 302, photolithography is performed to form the opening 602 corresponding to the opening 502. In step 303, the opening 602 is patterned according to the desired profile of the through hole 102. Similarly, in step 303, the opening 604 is patterned according to the desired profile of the through hole 104. The patterning process in step 303 can adopt a variety of suitable processes, including dry etching and wet etching processes. The second etch stop layer 144 facilitates the patterning of the insulating layer 170 in step 303. For example, step 303 can remove a portion of the insulating layer 170 downward to the second etch stop layer 144 (or near the second etch stop layer 144). Depending on the intended application, the patterning performed in step 303 can be adapted to conform to different profiles.

[0050] Step 303 may use a variety of etchants to pattern the insulating layer 170, including a carbon fluorine-based etchant with a flow rate of 20 sccm to 50 sccm, a carbon fluorine-based etchant with a flow rate of 20 sccm to 50 sccm, a nitrogen-based etchant with a flow rate of 0 sccm to 100 sccm, an oxygen-based etchant with a flow rate of 0 sccm to 25 sccm, an argon-based etchant with a flow rate of 600 sccm to 1200 sccm, a hydrogen-based etchant with a flow rate of 0 sccm to 100 sccm, and a carbon hydrogen fluorine-based etchant with a flow rate of 0 sccm to 100 sccm. The parameters used in the patterning process may include a high radio frequency with a source power of 200 watts to 1000 watts, or a low radio frequency with a source power of 200 watts to 500 watts. The parameters used in the patterning process may also include a temperature of 0°C to 50°C, a pressure of 20mtorr to 80mtorr, a DC voltage of 0V to 500V, and a deviation of the depth of the line center and the edge groove less than However, other etchants as well as flow rates, source powers, pressures, temperatures, voltages, and biases outside of these ranges may also be implemented.

[0051] Step 304 removes a portion of the second etch stop layer ( Figure 3E ).like Figure 3E As shown, a first portion of the second etch stop layer 144 is removed according to the desired profile of the through hole 102, and a second portion of the second etch stop layer 144 is removed according to the desired profile of the through hole 104. The method of removing a portion of the second etch stop layer 144 can adopt a variety of suitable processes such as wet etching and dry etching processes. In step 304, the opening 602 is extended to pass through the second etch stop layer 144 to form an opening for the through hole 102, and the opening 604 is also extended to pass through the second etch stop layer 144. It is worth noting that before the opening of the first opening 802 and the second opening 804 is formed as described below, step 304 extends the opening 602 and the opening 604 to pass through the second etch stop layer 144, thereby improving the through hole crystal plane integrity, especially when the critical dimensions of semiconductor devices and integrated circuits continue to decrease.

[0052] Step 305 forms a second dielectric layer and a mask layer on the insulating layer ( Figure 3F ).like Figure 3FAs shown, an intermetallic dielectric layer 164 is formed on the insulating layer 170 and in the openings 602 and 604. In addition, a mask layer 352 is formed on the intermetallic dielectric layer 164 and between the buffer layer 342 and the buffer layer 344. The mask layer 352 is patterned to form an opening 702 and an opening 704 in the mask layer 352. The opening 702 and the opening 704 are formed on the opening 602 and the opening 604, respectively. The mask layer 352 is used as an etching mask in step 306 to facilitate the formation of trenches, as described below. The trenches will then be filled to form the through hole 102, the trench 112, the through hole 104, and the trench 114. The method of forming the IMD layer 164 , the buffer layer 342 , and the mask layer 352 of the buffer layer 344 on the insulating layer 170 may adopt a variety of suitable processes such as chemical vapor deposition, physical vapor deposition, atomic layer deposition, other suitable processes, or a combination of the above.

[0053] Step 306 removes portions of the first dielectric layer, the second dielectric layer, the first etch stop layer, and the insulating layer to form an opening ( Figure 3G ).like Figure 3G As shown, the intermetallic dielectric layer 162, the intermetallic dielectric layer 164, the first etch stop layer 142, and the portion of the insulating layer 170 are removed to form a first opening 802 and a second opening 804. Fig. 4I As shown, removing a portion of the first etch stop layer 142 can expose the conductive line 122. The method for forming the first opening 802 and the second opening 804 can adopt a variety of suitable removal processes or combinations thereof, including a variety of linear removal processes, wet etching processes, dry etching processes, or similar processes. Since the first opening 802 and the second opening 804 are generated after the through hole profile is formed in step 304, the profiles of the openings 602 and 604 are not affected by the process variation of removing a portion of the intermetallic dielectric layer 164 in step 306, thereby improving the crystal plane integrity. Step 306 can also remove the buffer layer 342.

[0054] Step 307: Fill the opening with conductive material ( Figure 3H ).like Figure 3H As shown, the conductive material used to form the through hole 102 and the trench 112 is in the first opening 802, and the conductive material used to form the through hole 104 and the trench 114 is in the second opening 804. In some embodiments, the method used to fill the first opening 802 and the second opening 804 can adopt a dual damascene process, but other suitable processes such as a single damascene process can also be implemented. It should be understood that step 307 can use barrier layers, seed layers, and other materials and layers to facilitate the formation of the through hole 102, the trench 112, the through hole 104, and the trench 114. In addition, as shown in FIG. Figure 3HAs shown, the mask layer 352 and the buffer layer 344 are removed, and a third etch stop layer 146 is formed on the intermetallic dielectric layer 164, the trench 112, and the trench 114. In addition, an intermetallic dielectric layer 166 is formed on the third etch stop layer 146, and a conductive filling layer 130 is formed on the intermetallic dielectric layer 166. After step 307, the interconnect structure 100 is substantially completed.

[0055] Figure 4A FIG. 4 is a flow chart of another process 400 for fabricating the interconnect structure 100 . FIG. 4B to FIG. 4J 4 is a cross-sectional view of the interconnect structure 100 at each step of the process 400. In the process 400, before forming openings to fill the conductive material to finally form the through holes 102 and 104 and the trenches 112 and 114, the openings for the through holes 102 and 104 can be patterned into the second etch stop layer 144. In addition, the process 400 is different from the process 300 in that two photoresists are used separately to pattern the openings for the through holes 102 and 104 into the second etch stop layer 144. Using photoresists separately can provide flexibility in the manufacturing process to form different through hole profiles. Using photoresists separately can further improve accuracy, especially in applications with small structure sizes.

[0056] Step 401 forms a second etching stop layer, a first dielectric layer, and an insulating layer on the first etching stop layer ( Figure 4B ).like Figure 4B As shown, an intermetallic dielectric layer 162 is formed on the first etch stop layer 142, a second etch stop layer 144 is formed on the intermetallic dielectric layer 162, and an insulating layer 170 is formed on the second etch stop layer 144. The method of forming the intermetallic dielectric layer 162 on the first etch stop layer 142 may adopt a variety of suitable processes such as chemical vapor deposition, physical vapor deposition, atomic layer deposition, other suitable processes, or a combination of the above. The method of forming the second etch stop layer 144 on the intermetallic dielectric layer 162 may adopt a variety of suitable processes such as chemical vapor deposition, physical vapor deposition, atomic layer deposition, other suitable processes, or a combination of the above. The method of forming the insulating layer 170 on the second etch stop layer 144 may adopt a variety of suitable processes such as chemical vapor deposition, physical vapor deposition, atomic layer deposition, other suitable processes, or a combination of the above.

[0057] Step 402: Apply photoresist on the insulating layer ( Figure 4C ).like Figure 4C As shown, a photoresist 310 is applied on the insulating layer 170. Figure 4CAs shown, step 402 forms opening 502 on photoresist 310, but does not form opening 504. Prior to applying photoresist 310 in step 402, various protective layers may be applied to insulating layer 170, such as a bottom anti-reflective coating. A grinding step and other preparatory steps may also be performed. The method of applying photoresist 310 to insulating layer 170 may use a variety of suitable processes, including spin coating, other suitable processes, or combinations thereof. Thereafter, the mask may be aligned with opening 502 to be exposed to ultraviolet light during a photolithography process, which ultimately facilitates forming a via opening in a strategic location of insulating layer 170 to place via 102, as described below.

[0058] Step 403: Patterning the insulation layer ( Figure 4D ).like Figure 4D As shown, the insulating layer 170 is patterned to form an opening 602. In step 402, photolithography is performed to form the opening 602 corresponding to the opening 502. In step 403, the opening 602 is patterned according to the desired profile of the through hole 102. The patterning process in step 403 can adopt a variety of suitable processes, including dry etching and wet etching processes. The second etch stop layer 144 facilitates the patterning of the insulating layer 170 in step 403. Depending on the intended application, the patterning performed in step 403 can be adapted to conform to different profiles.

[0059] Step 404: Apply a second photoresist on the insulating layer ( Figure 4E ).like Figure 4E As shown, a photoresist 320 is applied on the insulating layer 170. Figure 4E As shown, an opening 504 is formed on the photoresist 320. Prior to applying the photoresist 320 in step 404, various protective layers may be applied to the insulating layer 170, such as a bottom anti-reflective coating. A grinding step and other preparatory steps may also be performed. The method of applying the photoresist 320 to the insulating layer 170 may use a variety of suitable processes, including spin coating, other suitable processes, or a combination of the above. The mask may then be aligned with the opening 504 to be exposed to ultraviolet light during a photolithography process, which ultimately facilitates the formation of a via opening in a strategic location of the insulating layer 170 to place the via 102, as described below.

[0060] Step 405: Patterning the insulation layer ( Figure 4F ).like Figure 4FAs shown, the insulating layer 170 is patterned to form an opening 604. Step 402 performs photolithography to form the opening 604 corresponding to the opening 504. Step 405 patterns the opening 604 according to the desired profile of the through hole 104. The patterning performed in step 405 can be performed using a variety of suitable processes, including dry etching and wet etching processes. The second etch stop layer 144 facilitates the patterning of the insulating layer 170 in step 405. Depending on the intended application, the patterning process performed in step 405 can be adapted to conform to different profiles. For example, some applications require a large width of the opening 604, while other applications require a narrower width of the opening 604.

[0061] Step 405 may use a variety of etchants to pattern the insulating layer 170, including a carbon fluorine-based etchant with a flow rate of 20 sccm to 50 sccm, a nitrogen-based etchant with a flow rate of 0 sccm to 100 sccm, an oxygen-based etchant with a flow rate of 0 sccm to 25 sccm, an argon-based etchant with a flow rate of 600 sccm to 1200 sccm, a hydrogen-based etchant with a flow rate of 0 sccm to 100 sccm, and a carbon hydrogen fluorine-based etchant with a flow rate of 0 sccm to 100 sccm. The parameters used in the patterning process may include a high radio frequency with a source power of 200 watts to 1000 watts, or a low radio frequency with a source power of 200 watts to 500 watts. The parameters used in the patterning process may also include a temperature of 0°C to 50°C, a pressure of 20mtorr to 80mtorr, a DC voltage of 0V to 500V, and a deviation of the groove depth between the center of the line and the edge is less than However, other etchants as well as flow rates, source powers, pressures, temperatures, voltages, and biases outside of these ranges may also be implemented.

[0062] Step 406 removes a portion of the second etch stop layer ( Figure 4G ).like Figure 4G As shown, a first portion of the second etch stop layer 144 is removed according to the desired profile of the through hole 102, and a second portion of the second etch stop layer 144 is removed according to the desired profile of the through hole 104. The method of removing a portion of the second etch stop layer 144 can adopt a variety of suitable processes such as wet etching and dry etching processes. Step 406 extends the opening 602 through the second etch stop layer 144 to form an opening for the through hole 102, and also extends the opening 604 through the second etch stop layer 144. It is worth noting that before the opening of the first opening 802 and the second opening 804 described below is formed, step 406 extends the opening 602 and the opening 604 to pass through the second etch stop layer 144, thereby improving the through hole crystal plane integrity, especially when the critical dimensions of semiconductor devices and integrated circuits continue to decrease.

[0063] Step 407 forms a second dielectric layer and a mask layer on the insulating layer ( Figure 4H ).like Figure 4HAs shown, an IMD layer 164 is formed on the insulating layer 170 and in the openings 602 and 604. In addition, a mask layer 352 is formed on the IMD layer 164 and between the buffer layer 342 and the buffer layer 344. The mask layer 352 is patterned to form the openings 702 and 704 in the mask layer 352. The mask layer 352 is used as an etching mask to facilitate the formation of trenches in step 407, as described below. The trenches can then be filled to form the through hole 102, the trench 112, the through hole 104, and the trench 114. The mask layer 352 added to the IMD layer 164, the buffer layer 342, and the buffer layer 344 is formed on the insulating layer 170 by a variety of suitable processes such as chemical vapor deposition, physical vapor deposition, atomic layer deposition, other suitable processes, or combinations thereof.

[0064] Step 408 removes portions of the first dielectric layer, the second dielectric layer, the first etch stop layer, and the insulating layer to form a first opening and a second opening ( Fig. 4I ).like Fig. 4I As shown, the intermetallic dielectric layer 162, the intermetallic dielectric layer 164, the first etch stop layer 142, and the portion of the insulating layer 170 are removed to form a first opening 802 and a second opening 804. Fig. 4I As shown, removing a portion of the first etch stop layer 142 can expose the conductive line 122. The first opening 802 and the second opening 804 can be formed by a variety of suitable removal processes or combinations thereof, including a variety of linear removal processes, wet etching processes, dry etching processes, or similar processes. Since the first opening 802 and the second opening 804 are generated after the through hole profile is formed in step 406, the through hole crystal plane integrity can be improved. Step 408 can also remove the buffer layer 342.

[0065] Step 409: Fill the first opening and the second opening with conductive material ( Figure 4J ).like Figure 4J As shown, the conductive material used to form the through hole 102 and the trench 112 and the conductive material used to form the through hole 104 and the trench 114 are in the second opening 804. In some embodiments, a dual damascene process is used to fill the first opening 802 and the second opening 804, but other suitable processes such as a single damascene process may also be implemented. It should be understood that step 409 may use a barrier layer, a seed layer, and other materials to facilitate the formation of the through hole 102, the trench 112, the through hole 104, and the trench 114. In addition, as shown in FIG. Figure 4J As shown, the mask layer 352 and the buffer layer 344 are removed, and a third etch stop layer 146 is formed on the intermetallic dielectric layer 164, the trench 112, and the trench 114. On the other hand, the intermetallic dielectric layer 166 can be formed on the third etch stop layer 146, and the conductive filling layer 130 can be formed on the intermetallic dielectric layer 166. After step 409, the interconnect structure 100 is substantially completed.

[0066] It should be understood that the above-described processes 300 and 400 are embodiments, and that various adjustments may be made to these processes to improve the through-hole surface integrity, which also falls within the scope of the embodiments of the present disclosure. For example, more than two through holes may be formed in the interconnect structure, depending on the intended application. In addition, it should be understood that the interconnect structure 100 may generally provide a portion of a complete interconnect structure in an integrated circuit or other integrated circuit, so that those with ordinary knowledge in the art can understand the structures and techniques described herein.

[0067] As described above, the embodiments of the present disclosure provide an interconnect structure to facilitate electrical connection of semiconductor devices in an integrated circuit. The interconnect structure includes an additional etch stop layer formed around the junction of the through hole and the trench of the interconnect structure. The additional etch stop layer acts as a hard mask, and the additional etch stop layer can be patterned before removing a major portion of the dielectric material for filling with the conductive material. The interconnect structure can improve the crystal plane control of the through hole, especially when the critical dimensions of the semiconductor device continue to shrink. As the critical dimensions continue to shrink, challenges such as mask material loss, limited process tolerances, and inconsistency with the through hole profile will be faced.

[0068] One embodiment of the present disclosure is a semiconductor structure. The semiconductor structure includes a conductive circuit electrically coupled to an active semiconductor device, a first etch stop layer formed on the conductive circuit; a first dielectric layer formed on the first etch stop layer; a second etch stop layer formed on the first dielectric layer; a second dielectric layer formed on the second etch stop layer; and an interconnect structure electrically coupled to the conductive circuit and extending through the first etch stop layer, the first dielectric layer, the second etch stop layer, and the second dielectric layer. The interconnect structure includes a through hole extending through the first etch stop layer, the second etch stop layer, and the first dielectric layer; and a trench extending through the second dielectric layer.

[0069] In some embodiments, the second etch stop layer surrounds the junction of the via and the trench.

[0070] In some embodiments, the semiconductor structure further includes an insulating layer formed between the second etch stop layer and the second dielectric layer.

[0071] In some embodiments, the second etch stop layer is composed of aluminum oxide.

[0072] In some embodiments, the width of the vias is 5 nm to 15 nm.

[0073] In some embodiments, the width of the trench is 15 nm to 20 nm.

[0074] In some embodiments, the thickness of the second etch stop layer is to

[0075] Another embodiment of the present disclosure is a method for manufacturing a semiconductor structure. The method includes forming a first etch stop layer on a conductive circuit, and the conductive circuit is electrically coupled to an active semiconductor device; forming a first dielectric layer on the first etch stop layer; forming a second etch stop layer on the first dielectric layer; removing a portion of the second etch stop layer to expose a portion of the first dielectric layer; forming a second dielectric layer on the second etch stop layer and the first dielectric layer; removing a portion of the second dielectric layer, a portion of the first dielectric layer, and a portion of the first etch stop layer to form an opening and expose the conductive circuit; and filling the opening with a conductive material.

[0076] In some embodiments, the method further includes forming an insulating layer on the second etch stop layer.

[0077] In some embodiments, the step of removing a portion of the second dielectric layer, a portion of the first dielectric layer, and a portion of the first etch stop layer to form an opening further includes removing a portion of the insulating layer to form the opening.

[0078] In some embodiments, the method further includes applying a photoresist on the insulating layer before removing the portion of the second etch stop layer to expose the portion of the first dielectric layer.

[0079] In some embodiments, the method further includes applying a photoresist on the second etch stop layer before removing the portion of the second etch stop layer to expose the portion of the first dielectric layer.

[0080] In some embodiments, the method further includes forming a third etch stop layer on the second dielectric layer and the conductive material.

[0081] In some embodiments, the step of filling the opening with a conductive material includes forming a via and a trench in the opening.

[0082] Another embodiment of the present disclosure is another method for manufacturing a semiconductor structure. The method includes forming a first etch stop layer on a conductive circuit, and the conductive circuit is electrically coupled to an active semiconductor device; forming a first dielectric layer on the first etch stop layer; forming a second etch stop layer on the first dielectric layer; forming an insulating layer on the second etch stop layer; removing a first portion of the insulating layer and a portion of the second etch stop layer to expose a portion of the first dielectric layer; forming a second dielectric layer on the second etch stop layer and the first dielectric layer; removing a portion of the second dielectric layer, a portion of the first dielectric layer, a second portion of the insulating layer, and a portion of the first etch stop layer to form an opening and expose the conductive circuit; and filling the opening with a conductive material.

[0083] In some embodiments, the method further includes applying a photoresist on the insulating layer after removing the portion of the insulating layer and the portion of the second etch stop layer to expose the portion of the first dielectric layer.

[0084] In some embodiments, the method further includes forming a third etch stop layer on the second dielectric layer and the conductive material.

[0085] In some embodiments, the method further includes forming a third dielectric layer on the third etch stop layer.

[0086] In some embodiments, the method further includes forming additional conductive material on the third dielectric layer.

[0087] In some embodiments, the step of filling the opening with a conductive material includes forming a via and a trench in the opening.

[0088] The features of the above embodiments are helpful for those with ordinary knowledge in the art to understand the present disclosure. Those with ordinary knowledge in the art should understand that the present disclosure can be used as a basis to design and change other processes and structures to achieve the same purpose and / or the same advantages of the above embodiments. Those with ordinary knowledge in the art should also understand that these equivalent substitutions do not depart from the spirit and scope of the present disclosure, and can be changed, replaced, or modified without departing from the spirit and scope of the present disclosure.

Claims

1. A semiconductor structure comprising: a conductive circuit; a first etch stop layer formed on the conductive line; a first dielectric layer formed on the first etch stop layer; a second etch stop layer formed on the first dielectric layer; a second dielectric layer formed on the second etch stop layer; as well as an interconnect structure electrically coupled to the conductive line and extending through the first etch stop layer, the first dielectric layer, the second etch stop layer, and the second dielectric layer, and the interconnect structure comprises: a through hole extending through the first etch stop layer, the second etch stop layer, and the first dielectric layer; a trench extending through the second dielectric layer; and An insulating layer is formed between the second etch stop layer and the second dielectric layer, wherein a junction between the through hole and the trench is aligned with an interface between the second etch stop layer and the insulating layer. 2 . The semiconductor structure as claimed in claim 1 , wherein the second etch stop layer surrounds the junction between the via and the trench. 3 . The semiconductor structure as claimed in claim 1 , wherein the second etching stop layer is made of aluminum oxide. The semiconductor structure as claimed in claim 1 , wherein a width of the through hole is 5 nm to 15 nm. The semiconductor structure as claimed in claim 1 , wherein a width of the trench is 15 nm to 20 nm.

6. The semiconductor structure as claimed in claim 1, wherein the thickness of the second etch stop layer is to 7. A method for manufacturing a semiconductor structure, comprising: forming a first etching stop layer on a conductive circuit; forming a first dielectric layer on the first etch stop layer; forming a second etch stop layer on the first dielectric layer; forming an insulating layer on the second etch stop layer; removing a portion of the second etch stop layer to expose a portion of the first dielectric layer; forming a second dielectric layer on the second etch stop layer and the first dielectric layer; removing a portion of the second dielectric layer, a portion of the first dielectric layer, and a portion of the first etching stop layer to form an opening and expose the conductive circuit; as well as A conductive material is filled into the opening to form a through hole and a trench, wherein a junction of the through hole and the trench is aligned with an interface between the second etching stop layer and the insulating layer.

8. The method for manufacturing a semiconductor structure according to claim 7, wherein the step of removing the portion of the second dielectric layer, the portion of the first dielectric layer, and the portion of the first etching stop layer to form the opening further comprises: A portion of the insulating layer is removed to form the opening.

9. The method for manufacturing a semiconductor structure according to claim 7, further comprising: A photoresist is applied on the insulating layer before removing the portion of the second etch stop layer to expose the portion of the first dielectric layer.

10. The method for manufacturing a semiconductor structure according to claim 7, further comprising: Before removing the portion of the second etch stop layer to expose the portion of the first dielectric layer, a photoresist is applied on the second etch stop layer.

11. The method for manufacturing a semiconductor structure according to claim 7, further comprising: A third etch stop layer is formed on the second dielectric layer and the conductive material.

12. A method for manufacturing a semiconductor structure, comprising: forming a first etch stop layer on a conductive circuit, and the conductive circuit is electrically coupled to an active semiconductor device; forming a first dielectric layer on the first etch stop layer; forming a second etch stop layer on the first dielectric layer; forming an insulating layer on the second etch stop layer; removing a first portion of the insulating layer and a portion of the second etch stop layer to expose a portion of the first dielectric layer; forming a second dielectric layer on the second etch stop layer and the first dielectric layer; removing a portion of the second dielectric layer, a portion of the first dielectric layer, a second portion of the insulating layer, and a portion of the first etch stop layer to form an opening and expose the conductive line; as well as A conductive material is filled into the opening to form a through hole and a trench, wherein a junction of the through hole and the trench is aligned with an interface between the second etching stop layer and the insulating layer.

13. The method for manufacturing a semiconductor structure according to claim 12, further comprising: After removing the portion of the insulating layer and the portion of the second etch stop layer to expose the portion of the first dielectric layer, a photoresist is applied on the insulating layer.

14. The method for manufacturing a semiconductor structure according to claim 12, further comprising: A third etch stop layer is formed on the second dielectric layer and the conductive material.

15. The method for manufacturing a semiconductor structure according to claim 14, further comprising: A third dielectric layer is formed on the third etching stop layer.

16. The method for manufacturing a semiconductor structure according to claim 15, further comprising: Additional conductive material is formed on the third dielectric layer.

Images