Magnetic memory device and method of forming the same

Abstract

The magnetic memory device includes a spin-orbit torque (SOT)-sensing spin Hall electrode and a free layer of a magnetic tunnel junction (MTJ) stack disposed on the spin Hall electrode, the free layer being a synthetic antiferromagnetic structure. The free layer has a magnetic moment that is tilted relative to the long axis of the MTJ stack and tilted relative to the direction in which current flows through the spin Hall electrode. A magnetic field is generated inside the MTJ stack to switch the state of the free layer. The free layer includes a first layer separated from a second layer by a spacer layer, wherein the first layer and the second layer may have the same or different crystal structures. Embodiments of the present application provide a magnetic memory device and a method for forming the same.

Description

Technical Field

[0001] Embodiments of the present application relate to a magnetic memory device and a method of forming the same. Background Art

[0002] Magnetic random access memory (MRAM) offers performance comparable to volatile static random access memory (SRAM) with power consumption comparable to volatile dynamic random access memory (DRAM). Compared to non-volatile memory (NVM) flash memory, MRAM offers faster access times and experiences minimal degradation over time, whereas flash memory can only be rewritten a limited number of times. One type of MRAM is spin transfer torque magnetic random access memory (STT-MRAM). STT-MRAM utilizes a magnetic tunnel junction (MTJ) that is written at least in part by a current driven through the MTJ. Another type of MRAM is spin-orbit torque (SOT) MRAM (SOT-MRAM), which typically requires lower switching current than STT-MRAM. Summary of the Invention

[0003] An embodiment of the present application provides a magnetic memory device, comprising: a spin Hall electrode (SHE), the SHE comprising a spin Hall metal; a magnetic tunnel junction (MTJ) stack disposed above the SHE, the MTJ comprising a synthetic antiferromagnetic free layer bonded to the SHE, the synthetic antiferromagnetic free layer comprising a first magnetic layer, a second magnetic layer, and a spacer layer inserted between the first magnetic layer and the second magnetic layer; a first wire coupled to a first end of the SHE; and a second wire coupled to a second end of the SHE.

[0004] An embodiment of the present application provides a magnetic memory device, comprising: a spin Hall electrode (SHE); and a top-pinned magnetic tunnel junction (MTJ) stack, arranged above the SHE, the MTJ stack comprising: a spacer layer inserted between a first free layer of the MTJ stack and a second free layer of the MTJ stack, the first free layer and the second free layer being magnetically coupled by an antiferromagnetic configuration, a reference layer structure, arranged above the second free layer, and a barrier layer inserted between the second free layer and the reference layer structure.

[0005] An embodiment of the present application provides a method comprising: depositing a spin Hall metal layer on an interlayer dielectric of an interconnect; depositing a series of layers of a magnetic tunnel junction (MTJ) film stack, the deposition comprising: depositing a synthetic antiferromagnetic free layer structure above the spin Hall metal, depositing a blocking layer above the free layer structure, and depositing a reference layer structure on the blocking layer; patterning the MTJ film stack into at least one MTJ pillar; and for each of the at least one MTJ pillar, patterning the spin Hall metal layer into a spin Hall electrode.

[0006] Embodiments of the present application provide a magnetic tunnel junction with a synthetic free layer for SOT-MRAM. BRIEF DESCRIPTION OF THE DRAWINGS

[0007] Various aspects of the present disclosure will be best understood from the following detailed description when read in conjunction with the accompanying drawings. Note that, in accordance with standard industry practice, the various components are not drawn to scale. In fact, the dimensions of the various components may be arbitrarily increased or reduced for clarity.

[0008] Figure 1-Figure 3 is a schematic diagram of a SOT-MRAM cell according to some embodiments.

[0009] Figure 4A 、 Figure 4B and Figure 4C is a schematic diagram of an MTJ film stack according to various embodiments.

[0010] Figure 5 is a cross-sectional view of a SOT-MRAM device according to some embodiments.

[0011] Figures 6 to 21 is an intermediate step for forming a SOT-MRAM device according to some embodiments.

[0012] Figure 22 is a cross-sectional view of a SOT-MRAM device according to some embodiments.

[0013] Figure 23 is a perspective view of a SOT-MRAM device according to some embodiments.

[0014] Figure 24 is a circuit diagram of a SOT-MRAM device according to some embodiments.

[0015] Figure 25 The operation of a SOT-MRAM cell according to some embodiments is shown. DETAILED DESCRIPTION

[0016] The following disclosure provides many different embodiments or examples of different components for implementing the present invention. Specific examples of components and arrangements are described below to simplify the present disclosure. Of course, these are merely examples and are not intended to be limiting. For example, in the description below, the formation of a first component above or on a second component may include an embodiment in which the first and second components are formed in direct contact, and may also include an embodiment in which an additional component is formed between the first component and the second component so that the first and second components may not be in direct contact. In addition, the present disclosure may repeat reference numbers and / or letters in various examples. This repetition is for the purpose of simplicity and clarity and does not, in itself, indicate a relationship between the various embodiments and / or configurations discussed.

[0017] In addition, for ease of description, spatially relative terms such as "under," "beneath," "lower," "above," and "upper" may be used herein to easily describe the relationship of one element or component to another (or other) elements or components as shown in the figures. In addition to the orientation shown in the figures, spatially relative terms are intended to include different orientations of the device during use or operation. The device can be oriented in other ways (rotated 90 degrees or in other orientations), and the spatially relative descriptors used herein can be interpreted accordingly. In addition, the term "made of" can mean "comprising" or "consisting of." Moreover, in subsequent manufacturing processes, there may be one or more additional operations between / between the described operations, and the order of operations may change. In this disclosure, the phrase "one of A, B, and C" means "A, B, and / or C" (A, B, C, A and B, A and C, B and C, or A, B and C), and does not mean one element from A, one element from B, and one element from C, unless otherwise specified. Materials, configurations, dimensions, processes, and / or operations described with respect to one embodiment may be adopted in other embodiments, and detailed descriptions thereof may be omitted.

[0018] Embodiments utilize a synthetic free layer in the MTJ film stack, rather than a single free layer. The synthetic free layer comprises a pair of magnetic layers separated by a spacer layer. When current flows through a spin Hall electrode to induce SOT in the free layer, the resulting magnetic field is tilted about the x-axis. When the orientation of the spin Hall electrode is fixed, this tilt can be used to switch the free layer magnetization without requiring an external magnetic field and without manually tilting the spin Hall electrode or the MTJ elliptical pattern.

[0019] Spin torque transfer magnetic random access memory (STT-MRAM) is one of the next-generation memory technologies for CMOS integrated circuits (ICs). However, fast access applications such as low-level caches require faster speeds, and write speeds are much slower than read speeds. Cache applications for central processing units (CPUs) and / or microcontrollers (MCUs) also require low power consumption. However, STT-RAM requires a large amount of current to change the magnetization state during write operations. An STT-MRAM cell typically includes a magnetic tunnel junction (MTJ) film stack having a free magnetic layer, a reference or pinned magnetic layer, and a tunnel barrier layer made of a non-ferromagnetic material (e.g., MgO). The free layer is a magnetic layer with two energetically equivalent magnetic states, where the magnetization in the free layer is parallel or antiparallel to the magnetization of the reference layer. By applying a current perpendicular to the MTJ film stack, the magnetic orientation (torque) of the free magnetic layer can be changed, thereby writing data to the STT-MRAM cell.

[0020] In contrast, spin-orbit transfer (or spin-orbit torque) (SOT) magnetic switches have the potential to provide orders of magnitude improvements in write current and speed. SOT has broad application prospects in high-speed, low-power memory caches.

[0021] In SOT-MRAM, the magnetic moment of the free magnetic layer of the MTJ film stack is switched using the spin-orbit interaction effect caused by the flow of current adjacent to the MTJ film stack. This current can flow in a spin Hall electrode (SHE). Manipulating the free magnetic layer causes a change in the resistance of the entire free magnetic layer, which can be used to determine the data value in the cell. The magnetic moment of the free magnetic layer can be switched using only the spin-orbit interaction effect, or a combination of effects can be used to switch the magnetic moment of the free magnetic layer.

[0022] There are three general types of SOT-MRAM, which vary depending on the shape and orientation of the MTJ stack relative to the current flowing through the spin Hall electrode. A magnetic field is required to switch the magnetic moment of the free layer using the SOT, and this field can be generated internally or externally. Externally generated SOT-MRAM devices are not ideal due to the complexity, space, and power required to use an externally generated field. X-type SOT-MRAM has an MTJ film stack elongated in the x-direction and a magnetic moment parallel to the current through the spin Hall electrode, and typically requires an externally generated magnetic field that is orthogonal to the plane of the current in the spin Hall electrode. Y-type SOT-MRAM has an MTJ film stack elongated in the y-direction and a magnetic moment perpendicular to the direction of current through the spin Hall electrode but in the same plane. Z-type SOT-MRAM has an MTJ film stack that is typically circular (although it can be elliptical) and a magnetic moment orthogonal to the plane of current through the spin Hall electrode.

[0023] Each of the different types of SOT-MRAM devices has certain advantages and disadvantages. X-type SOT-MRAM is ideal because it requires minimal power to operate and occupies the least space. However, it typically requires an externally generated magnetic field to assist in free layer switching. Various modifications to the x-type SOT-MRAM design have been attempted to eliminate the need for an externally generated magnetic assist field. In other words, these modifications are intended to provide an internally generated assist field. In one such variation, the MTJ stack, typically aligned with its longest axis along the x-axis and aligned with the current passing through the spin Hall electrode, is tilted or rotated about the z-axis, while the magnetic field from the current passing through the spin Hall electrode remains along the x-axis, generating a magnetic moment with x and y components. Any rotation angle between 0° and 90° can be achieved, and in some embodiments, the rotation angle can be between approximately 5° and 45°, although other angles can be used. These complex fields can be used to switch the free layer without the need for an external assist field. However, because the MTJ stack is rotated, it occupies more space, thereby reducing memory density.

[0024] As described above, embodiments disclosed herein use a synthetic free layer consisting of two magnetic layers separated by a spacer layer. This arrangement provides a magnetic moment offset from the x-axis, encompassing both x and y magnitudes, without requiring rotation of the MTJ stack about the z-axis, thereby providing greater storage density than some devices. The resulting magnetic moment can be switched via spin-orbit torque without the need for an external magnetic assist field.

[0025] Although the present disclosure generally relates to x-type SOT-MRAM, certain aspects discussed herein may be transferable to other types of SOT-MRAM devices.

[0026] Figure 1 A SOT-MRAM cell 90 according to some embodiments of the present disclosure is shown (see Figure 3 ) is a schematic diagram of the functional elements of a SOT-MRAM. These elements may include a bottom electrode 5, a spin Hall electrode 10, an MTJ film stack 100, an optional capping layer 70 above the MTJ film stack 100, and a top electrode 75 above the capping layer 70. The layers may include multiple sublayers containing different materials, which will be discussed in detail below. The spin Hall electrode 10 serves as a spin-orbit interaction active layer to provide a sensing influence on the MTJ film stack 100.

[0027] Although the basic structure of the MTJ film stack 100 and the spin Hall electrode 10 is the same for the various embodiments discussed herein, several configurations may be used that differ in the materials used in the different layers and their respective crystal structures. A synthetic free layer 30 is disposed above the spin Hall electrode 10, a barrier layer 40 is disposed above the synthetic free layer 30, and a reference layer structure 50 is disposed above the barrier layer 40. An antiferromagnetic layer 60 is disposed above the reference layer structure 50. In some embodiments, a capping layer 70 may be disposed on the antiferromagnetic layer 60. The reference layer structure 50 may include a reference layer 52 and a pinned layer 56 with a spacer interposed between the reference layer 52 and the pinned layer 56. In some embodiments, the antiferromagnetic layer 60 may be used as a pinned layer instead of a separate pinned layer 56. Figure 1 The arrangement shown in is considered a “top pinned” device because the pinned layer is located on top of the MTJ stack 100 .

[0028] refer to Figure 1 , using the spin-orbit interaction effect to switch the magnetic moment of the synthetic free layer 30. In some embodiments, only the spin-orbit interaction effect is used to switch the magnetic moment of the synthetic free layer 30. In other embodiments, a combination of effects is used to switch the magnetic moment of the synthetic free layer 30. For example, the magnetic moment of the synthetic free layer 30 is switched using spin transfer torque as the primary effect, which can be assisted by the torque caused by the spin-orbit interaction. In other embodiments, the primary switching mechanism is the torque caused by the spin-orbit interaction. In such embodiments, another effect including but not limited to spin transfer torque can assist in switching.

[0029] The spin Hall electrode 10 can be formed on the optional bottom electrode 5. The bottom electrode 5 can include one or more layers of Ta, TiN, TaN, Ru, Au, W, or Cu. The bottom electrode 5 can be deposited by any suitable process, such as by metal damascene in the case of a Cu bottom electrode 5, or by depositing a metal plug in the case of a W bottom electrode 5. An optional buffer layer 7 is interposed between the bottom electrode 5 and the spin Hall electrode 10. The electrode 5 and the spin Hall electrode 10 can include a thin layer of deposited insulating material, such as magnesium oxide, deposited to a thickness between 2 angstroms and 9 angstroms.

[0030] As described above, the spin Hall electrode 10 is a spin-orbit active interface having a strong spin-orbit interaction and can be used to switch the magnetic moment of the synthetic free layer 30. The spin Hall electrode 10 is used to generate a spin-orbit magnetic field H y (See Figure 2 ). More specifically, the current Jc is driven in the plane through the spin Hall electrode 10. Due to the spin Hall effect, the spin-orbit magnetic field H y The spin-orbit magnetic field H is generated perpendicular to the direction of the current Jc. y= T in the synthetic free magnetic layer 30 = −γ[M×H y ]. Therefore, the torque and magnetic field are interchangeably referred to as spin-magnetic field and spin-orbit torque. This reflects the fact that the spin-orbit interaction is the origin of the spin-orbit torque and the spin-orbit field. For the current Jc driven in the plane of the spin Hall electrode 10 and the spin-orbit interaction, the spin-orbit torque occurs. In contrast, the spin transfer torque is generated due to the perpendicular plane current flowing through the synthetic free layer 30, the barrier layer 40 and the reference layer structure 50, which injects spin-polarized charge carriers into the synthetic free layer 30. The orbital torque T can quickly deflect the magnetic moment of the synthetic free layer 30 from its equilibrium state. And due to the structure of the synthetic free layer, the equilibrium state is tilted from the easy axis. The spin-orbit torque T can tilt the magnetization of the synthetic free layer 30 much faster than a conventional STT torque with a similar maximum amplitude. In some embodiments, the spin-orbit torque can be used to accomplish switching. In other embodiments, another mechanism such as spin transfer can be used to accomplish switching. Therefore, the generated spin-orbit field / spin-orbit torque can be used to switch the magnetic moment of the synthetic free layer 30.

[0031] Regarding the spin Hall effect of the spin Hall electrode 10, in the plane of the spin Hall electrode 10 (i.e., the current in the plane, substantially in Figure 1 In other words, the current Jc is driven perpendicular to the stacking direction of the film including the spin Hall electrode 10 and the synthetic free layer 30 (ie, perpendicular to the normal to the surface, Figure 1 The current Jc is driven in the z direction (in the z direction) of the spin Hall electrode 10. Charge carriers with spins that are specifically oriented perpendicular to the current direction (y direction) accumulate on the surface of the spin Hall electrode 10. Most of these spin-polarized carriers diffuse into the synthetic free layer 30. As described above, since the torque T on the magnetization of the synthetic free layer 30 is equal to the magnetization T. Therefore, since the torque on the magnetization is equal to the effective magnetic field on the magnetization, the spin accumulation equivalently generates a magnetic field H on the synthetic free layer 30. y The spin-orbit field of the spin Hall effect is the cross product of the spin-orbit polarization and the magnetic moment of the synthetic free layer 30. Thus, the magnitude of the torque is proportional to the in-plane current density Jc and the spin polarization of the carriers. When the polarization caused by the spin Hall effect is parallel to the easy axis of the synthetic free layer 30 (the deviation from the equilibrium magnetic moment of the synthetic free layer 30), the spin Hall effect can be used to switch Figure 1 To obtain the spin-orbit torque T, a current pulse is driven in-plane through the spin Hall electrode 10. The resulting spin-orbit torque T cancels the damping torque, causing the magnetization of the synthetic free layer 30 to switch in a manner similar to conventional STT switching.

[0032] The synthetic free layer 30 is a data storage layer with a switchable magnetic moment. Within the MTJ film stack 100 of the SOT-MRAM cell 90, the synthetic free layer 30 serves as a state holding layer, and its magnetic state determines the state of the SOT-MRAM cell 90. The synthetic free layer 30 is controllable (for example, by controlling the current flowing in the spin Hall electrode 10), and by controlling the magnetic moment of the synthetic free layer 30 in this way, the resistance of the SOT-MRAM cell 90 can be set to a high resistance state or a low resistance state. Whether the SOT-MRAM cell 90 is in a high resistance state or a low resistance state depends on the relative orientation of the spin polarization of the synthetic free layer 30 and the reference layer structure 50 (see below for more details on reference).

[0033] The following description of the composite free layer 30, barrier layer 40, and reference layer structure 50 is for reference only. Figure 4A 、 Figure 4B and Figure 4C All embodiments discussed in more detail are common. Figure 4A 、 Figure 4B and Figure 4C The discussion elaborates on Figure 1 Details discussed.

[0034] The synthetic free layer 30 can be formed from one or more ferromagnetic materials, such as cobalt iron boron (CoFeB), cobalt / palladium (CoPd), cobalt iron (CoFe), cobalt iron boron tungsten (CoFeBW), iron boron (FeB), Co, alloys thereof, or combinations thereof, and one or more non-ferromagnetic materials, such as W, Ta, Mo, Cr, Ru, or combinations thereof. The synthetic free layer 30 is configured to be antiferromagnetic by including at least two layers of ferromagnetic materials, such as ferrite. FL1 32 and FL2 36 are separated by a spacer layer 34 of non-ferromagnetic material. For example, the first magnetic layer FL1 32 can be coupled to the second magnetic layer FL2 36 via RKKY (Ruderman-Kittel-Kasuya-Yosida) coupling. When the spacer layer 34 is within a certain thickness range, the coupling will be antiferromagnetic. When such a synthetic free layer operates in an antiferromagnetic manner, it can be referred to as a synthetic antiferromagnetic free layer. For example, the spacer layer 34 can include W, Ta, Mo, Cr, or Ru.

[0035] As the thickness of spacer layer 34 increases, the magnetic coupling between FL1 32 and FL2 36 switches from parallel to antiparallel, then back to parallel, and so on. Therefore, if the thickness of spacer layer 34 is too thin, the coupling will be parallel (or ferromagnetic), but if the thickness of spacer layer 34 is thicker, the magnetic coupling between FL1 32 and FL2 36 may be antiparallel (or antiferromagnetic). As the thickness of spacer layer 34 increases, when the spacer is greater than approximately 25 angstroms and approximately 30 angstroms, the coupling strength (whether ferromagnetic or antiferromagnetic) between the first magnetic layer FL1 32 and the second magnetic layer FL2 36 decreases and effectively decouples. The effective thickness of spacer layer 34 for antiferromagnetic coupling varies depending on the materials of FL1 32, spacer layer 34, and FL2 36. Several embodiments are discussed below. For example, in some embodiments, such as when spacer layer 34 is W and FL1 32 and FL2 36 are CoFeB, spacer layer 34 may be between approximately 4 angstroms and approximately 8 angstroms, for example, between approximately 5 angstroms and approximately 7 angstroms. Although other values ​​are contemplated (depending on the material used for the spacer layer 34), they may be used. The first magnetic layer FL1 32 and the second magnetic layer FL2 36 may have a specific crystal structure that, together with the spacer layer 34, enhances or reduces their antiferromagnetic effect. For example, in some embodiments, FL1 32 and FL2 36 may have the same crystal structure, such as face-centered cubic (fcc), body-centered cubic (bcc), or hexagonal closest packed (hcp), and in other embodiments, FL1 32 may have one crystal structure and FL2 36 may have another crystal structure. In such embodiments, the spacer layer 34 may serve as a structural barrier between FL1 32 and FL2 36, such that the crystal structures of each of FL1 32 and FL2 36 may be different.

[0036] The thickness of the FL1 32 layer may be between about 0.5 nm and 2.5 nm, the thickness of the FL2 32 layer may be between about 1.0 nm and 2.5 nm, and the total thickness of the synthetic free layer 30 may be between about 1.5 nm and about 5.0 nm.

[0037] In some embodiments, the barrier layer 40 is formed of one or more materials, such as magnesium oxide, aluminum oxide (AlOx) (e.g., Al2O3), MgAl2O4, or even a semi-metal, or a combination thereof. In some embodiments, the material of the barrier layer 40 includes a crystalline material deposited to have a specific crystal structure (e.g., bcc, fcc, or hcp structure), while in other embodiments, the material of the barrier layer 40 may be deposited amorphously. In some embodiments, the material of the barrier layer 40 may be deposited to have the same crystal structure as the FL236 of the synthetic free layer 30. In some embodiments, the barrier layer 40 may have a thickness between about 0.5 nm and about 1.5 nm. In some cases, controlling the thickness of the barrier layer 40 may control the resistance (RMTJ) of the MTJ film stack 100. For example, a thicker barrier layer 40 may increase the resistance of the MTJ film stack 100. By controlling the resistance RMTJ of the MTJ film stack 100 to match the parasitic resistance of the circuit connected to the SOT-MRAM cell 90, the resistance of the SOT-MRAM cell 90 may be improved. This approach can increase the range of operating conditions under which the SOT-MRAM cell 90 can be read. The barrier layer 40 can be thin enough to allow electrons to tunnel through the barrier layer 40 .

[0038] Reference layer structure 50 may be a synthetic antiferromagnetic structure similar to synthetic free layer 30. However, the magnetic moment of reference layer structure 50 remains unchanged. Reference layer structure 50 may be made of any material similar to synthetic free layer 30 described above and may have the same material composition as synthetic free layer 30. In some embodiments, reference layer structure 50 includes one or more layers of magnetic material. In some embodiments, reference layer structure 50 includes reference layer RL 52, which may include Co, Fe, Ni, CoFe, NiFe, FeB, CoFeB, CoFeBW, alloys thereof, or combinations thereof. In some embodiments, reference layer structure 50 may also include pinned layer PL 56, which may also include Co, Fe, Ni, CoFe, NiFe, FeB, CoFeB, CoFeBW, alloys thereof, or combinations thereof and may or may not be the same material as RL 52. Spacer layer 54 is interposed between RL 52 and pinned layer 56. Spacer layer 54 can be made of any suitable non-ferromagnetic material, such as Cu, Cr, Ru, Ir, Rh, Re, V, Nb, W, Ta, Mo, or the like, or combinations thereof. Each layer of reference layer structure 50 comprises a crystalline material deposited to have a specific crystal structure, such as an fcc, bcc, or hcp structure. In some embodiments, the material of reference layer RL 52 can be deposited to have the same crystal structure type as barrier layer 40. In some embodiments, spacer layer 54 can serve as a physical barrier, allowing pinned layer 56 to have a different crystal structure type than reference layer 52. In some embodiments, reference layer 52 has a thickness ranging from approximately 2 nm to approximately 5 nm; spacer layer 54 has a thickness ranging from approximately 0.2 nm to approximately 1.5 nm. Pinned layer 56 has a thickness ranging from approximately 2 nm to approximately 5 nm. In some embodiments, pinned layer 56 can be omitted, and antiferromagnetic layer 60 can serve as pinned layer 56.

[0039] The antiferromagnetic (AFM) layer 60 is a hard bias layer for pinning the magnetization direction of the reference layer structure 50 in a fixed direction and can be referred to as a pinned layer. The AFM layer 60 and the reference layer structure 50 can together avoid generating stray fields that may interfere with the synthetic free layer 30 of the SOT-MRAM cell 90 or an adjacent SOT-MRAM cell 90. The magnetization direction of the pinned reference layer structure reference map 50 or reference layer 52 allows the SOT-MRAM cell 90 to switch between a low resistance state and a high resistance state by changing the magnetization direction of the synthetic free layer 30 relative to the reference layer 52. The AFM layer 60 can be a layer of one or more metals having antiferromagnetic properties. For example, the AFM layer 60 can be made of platinum manganese (PtMn), iridium manganese (IrMn), iron manganese (FeMn), or a combination thereof deposited to have an fcc crystal structure. In some embodiments, the AFM layer 60 can have a thickness between about 10 nm and about 30 nm. In some embodiments, a thicker AFM layer 60 may have stronger antiferromagnetic properties, or may be more robust against external magnetic fields or thermal fluctuations.

[0040] The capping layer 70 can be a single layer or a multilayer structure, which is used to protect the layers below the capping layer 70 during subsequent processes. In some embodiments, the capping layer 70 can also be used to provide a top electrode for connecting to a via or metal line thereon. The capping layer 70 can be formed of a non-ferromagnetic material, such as Cu, Ru, Cr, Pt, W, Ta, Mo, Ti, TaN, TiN, etc., or a combination thereof. In some embodiments, the capping layer 70 can include two non-ferromagnetic material layers sandwiching another non-ferromagnetic material layer, such as another of Cu, Ru, Cr, Pt, W, Ta, Mo, Ti, TaN, TiN, or the like. For example, in some embodiments, the capping layer can include Ta or Ti sandwiched between two layers of Ru. The thickness of the capping layer 70 can be between about 3 nm and about 10 nm, but other thicknesses are contemplated. In embodiments using multiple layers as the capping layer 70, each layer can be between about 1 nm and about 5 nm.

[0041] A separate top electrode 75 may be provided on the capping layer 70. The top electrode 75 may be used to provide electrical connection to a conductive pattern coupled to the top of the MTJ film stack 100. The top electrode 75 may be made of any suitable material, such as titanium, titanium nitride, tantalum, tantalum nitride, tungsten, or the like, or a combination thereof. The capping layer 70 and / or the top electrode 75 may be collectively referred to as a layer 80.

[0042] Figure 2A simplified top view schematic diagram of a SOT-MRAM cell 90 according to an embodiment of the present disclosure is shown. For clarity, some elements have been omitted or simplified. The MTJ film stack 100 is shown as having an elliptical shape in the xy plane, where the major axis of the ellipse is parallel to the x-axis. The bottom electrodes 5 are shown on either side of the MTJ film stack 100 and are positioned so that the current flowing from one of the bottom electrodes 5 to the other bottom electrode 5 (shown by arrow 92) also flows parallel to the x-axis. Due to the antiferromagnetic arrangement of the synthetic free layer 30, the magnetic moment 94 of FL1 34 can be inherently rotated from the x-axis by an angle θ1 between about 5° and about 45°. The magnetic moment 96 of FL2 36 can also be rotated from the x-axis by an angle θ2, which can be between about 5° and about 45°. Due to the offset of the magnetic moments 94 and 96 relative to the x-axis, the current Jc can provide a spin-orbit torque to switch the synthetic free layer 30 in the absence of an external field. The offset magnetic moments 94 and 96 generate x and y components, with the y component contributing to switching in the absence of an external field. Rather than rotating the MTJ film stack 100 to cause the rotational magnetic moment to occur, the long axis of the MTJ film stack 100 remains parallel to the x-axis, thereby eliminating the need for additional lateral space to implement the embodiments disclosed herein.

[0043] Figure 3 A simplified schematic diagram of a SOT-MRAM cell 90 according to an embodiment of the present disclosure is shown. Figure 1 The materials, configurations, dimensions, processes, and / or operations described herein are described using similar references, and detailed descriptions thereof may be omitted.

[0044] In some embodiments, one end of the spin Hall electrode 10 is coupled to a switching device (e.g., a field effect transistor (FET)), referred to herein as FET110. In some embodiments, the spin Hall electrode 10 is coupled to the drain (or source) of FET 110 (or FET1) via one or more conductive patterns (e.g., vias, wires, traces, and / or pads), and the gate of the FET is coupled to a word line WL1120 via one or more conductive patterns. The source (or drain) of FET1 is coupled to a source line SL1125 via one or more conductive patterns. The other end of the spin Hall electrode 10 is coupled to another switching device (e.g., a field effect transistor (FET)), also referred to herein as FET 110 (or FET2). In some embodiments, the spin Hall electrode 10 is coupled to the drain (or source) of FET2 via one or more conductive patterns, and the gate of FET2 is coupled to a word line WL2120 via one or more conductive patterns. The source (or drain) of FET2 is coupled to a source line SL2125 via one or more conductive patterns.

[0045] The MTJ film stack 100 is arranged in a vertical direction (film stack direction) (Z direction) above the spin Hall electrode 10. The bit line 160 is electrically coupled to the top of the MTJ film stack 100 through one or more conductive patterns.

[0046] In some embodiments, the MTJ film stack 100 may be inverted and the spin Hall electrode 10 may be disposed above the MTJ film stack 100. In such embodiments, the capping layer 70 may be omitted, and the top electrode 75 (see FIG. Figure 1 ) can become the bottom electrode 5, and the bottom electrode 5 can become the top electrode 75. The synthetic free layer 30 of the MTJ film stack 100 can be set on top of the inverted MTJ film stack 100. The wiring arrangement can remain the same, with the drain (or source) of the FET1 FET 110 coupled to one end of the spin Hall electrode 10 through a conductive pattern, and the drain (or source) of the FET2 FET 110 coupled to the other end of the spin Hall electrode 10 through a conductive pattern. Similarly, the bit line 160 can be coupled to the now bottom of the MTJ film stack 100 through one or more conductive patterns. Figure 1 , the MTJ film stack 100 is inverted and a spin Hall electrode is placed on the inverted MTJ film stack 100 so that the top electrode 75 is now at the bottom; the AFM layer 60 is above the top (now bottom) electrode 75; the reference layer structure 50 is above the AFM layer 60; the blocking layer 40 is above the reference layer structure 50; the free layer 30 is above the blocking layer 40; the spin Hall electrode 10 is above the free layer 30; and above the spin Hall electrode 10 is the bottom (now top) electrode 5, which is connected to the FET 110 at either end of the spin Hall electrode 10.

[0047] Use as Figure 3 With the arrangement of elements shown, the SOT-MRAM cell 90 can implement an x-type storage element without using an external field to assist in switching the synthetic free layer 30 and without rotating the MTJ film stack 100. In addition, by utilizing the SOT-MRAM cell 90 instead of the STT-MRAM cell, the power requirements are smaller, thereby also reducing the transistor size of the FET 110 (FET1 and FET2). In some embodiments, the area size of the SOT-MRAM device 300 can be approximately 50% to 75% of the area size of the same type of SRAM device and is approximately the same size as the STT-MRAM device, while requiring less power, thereby providing faster switching and longer life (increased number of switching cycles).

[0048] If the word line WL1120 is positively biased and the word line WL2 is positively biased, the gates of the FETs 110 (FET1 and FET2) will be turned on. Then, the current Jc can flow through the spin Hall electrode 10 in one direction, causing the synthetic free layer 30 to change its magnetization direction. If the current direction is reversed, the current Jc can flow through the spin Hall electrode 10 in the opposite direction, causing the synthetic free layer 30 to change its magnetization in the opposite direction. However, if any one of the transistors FET 110 (FET1 or FET2) is not turned on, then the current will not flow through the spin Hall electrode 10, and a read operation can be performed at the bit line 160 through the MTJ film stack 100. The read and write operations will be discussed in more detail below.

[0049] Figure 4A 、 Figure 4B and Figure 4C Various configurations of the MTJ film stack 100 according to various embodiments are shown. The spin Hall electrode 10 is a spin-orbit active layer that induces a strong spin-orbit interaction with the synthetic free layer 30.

[0050] exist Figure 4A In the embodiment of the present invention, the spin Hall electrode 10 has an fcc crystal structure, while the barrier layer 40 can have a bcc or amorphous crystal structure. The first layer FL1 32 of the synthetic free layer 30 has a crystal structure that follows the crystal structure of the spin Hall electrode 10. The spacer layer 34 can serve as a structural barrier between the crystal structure of the FL1 32 layer (which follows the crystal structure of the spin Hall electrode 10) and the FL2 36 layer (which allows the FL2 36 layer to match the crystal structure of the barrier layer 40). The spacer layer 34 can be amorphous or have a bcc crystal structure. The FL2 36 layer can then have a bcc crystal structure. The barrier layer 40 can be bcc or amorphous, and the reference layer 52 of the reference layer structure 50 can also be bcc. The spacer layer 54 of the reference layer structure 50 can be hcp (for example, if it is Ru) or fcc (for example, if it is Ir), and the pinned layer 56 of the reference layer structure 50 can be fcc or bcc. The AFM 60 can be fcc.

[0051] The material of the spin Hall electrode 10 can be formed of platinum, palladium, gold, tantalum, tungsten, a combination thereof, or other suitable materials, and can be formed to have a thickness between about 3 nm and about 10 nm. Although other values ​​can be envisioned and used. The FL132 of the synthetic free layer 30 can be formed of CoFeB, CoFe, FeB, or NiFe, and can be between about 0.5 nm and about 2.5 nm, but other values ​​can be envisioned and used. The spacer layer 34 of the synthetic free layer 30 can be formed of W, Ta, Mo, Cr, etc., or a combination thereof, and can have a thickness between about 3 angstroms and 15 angstroms (this thickness depends on the material used, and as discussed above, its size is designed to maintain antiferromagnetic coupling between FL132 and FL236). The barrier layer 40 can be formed of crystalline magnesium oxide or amorphous aluminum oxide (e.g., AlOx) or other suitable materials, and can have a thickness between about 0.5 nm and about 1.5 nm. In some embodiments, the reference layer 52 of the reference layer structure 50 can be formed of a combination of CoFeB, FeB, Co, and CoFe. For example, a layer of CoFeB may contact barrier layer 40, and a layer of CoFe may be formed on the layer of CoFeB and bonded to spacer layer 54 of reference layer structure 50. The layer of CoFeB may be between approximately 1.5 nm and 1.5 nm. The total thickness of reference layer 52 may be between approximately 3.5 nm and 3.5 nm, and the layer of CoFe may be between approximately 0.5 nm and 1.5 nm, with the total thickness of reference layer 52 being between approximately 2 nm and 5 nm. Spacer layer 54 of reference structure 50 may be made of Ru or Ir and may have a thickness between approximately 2 angstroms and approximately 15 angstroms. Pinning layer 56 of reference layer structure 50 may be made of CoFe or a combination of CoFe and Co and may have a total thickness between approximately 2 nm and approximately 4 nm. Although CoFe generally has a bcc crystal structure, when AFM layer 60 is formed of platinum manganese, for example, this structure may be influenced by the structure of the overlying AFM layer 60 to have an fcc crystal structure. The AFM layer 60 may be formed of any suitable material, such as platinum manganese, iridium manganese, or iron manganese, and may have a thickness between about 10 nm and about 30 nm. The total thickness of the MTJ film stack 100 may be between about 20 nm and about 35 nm.

[0052] exist Figure 4BIn the embodiment of the present invention, the spin Hall electrode 10 has a bcc crystal structure and can match the crystal structure of the barrier layer 40 (bcc). In some embodiments, the barrier layer 40 can be amorphous. The first layer FL1 32 of the synthetic free layer 30 has a crystal structure that follows the spin Hall electrode 10. The spacer layer 34 can be amorphous or have a bcc crystal structure. The FL2 36 layer can have a bcc crystal structure. The barrier layer 40 can be bcc or amorphous, and the reference layer 52 of the reference layer structure 50 can also be bcc. The spacer layer 54 of the reference layer structure 50 can be hcp (for example, if it is Ru) or fcc (for example, if it is Ir), and the pinned layer 56 of the reference layer structure 50 can be fcc or bcc. The AFM 60 can be fcc. Because the crystal structures of FL1 32 and FL2 36 can be the same as the crystal structure of the barrier layer 40, the structural consistency improves the magnetoresistance ratio of the MTJ film stack 100 during the read operation.

[0053] The magnetoresistance ratio (MR ratio) is the resistance ratio equal to the antiparallel resistance (Rap) of the free and reference layers combined minus the parallel resistance (Rp) of the free and reference layers combined, divided by the parallel resistance (Rp) of the free and reference layers combined. MR ratio = (Rap – Rp) / Rp.

[0054] The material of the spin Hall electrode 10 can be formed of tungsten, tantalum, platinum, other suitable materials, or combinations thereof, and can be formed to have a thickness between about 3 nm and about 10 nm, although other values ​​are contemplated and can be used. Figure 4A Similar materials and constructions as listed are used to form the remaining layers.

[0055] exist Figure 4C In the example, the spacer layer 34 is made of Ru, which enhances the antiferromagnetic coupling between FL1 32 and FL2 36. Greater antiferromagnetic coupling reduces the write current, so a smaller write transistor can be used. However, Ru may interact negatively with B, thereby reducing the antiferromagnetic coupling in the synthetic free layer 30. Therefore, in Figure 4CIn the embodiment of the present invention, the spacer layer 34 is sandwiched between two thin layers of CoFe, which are sandwiched between two thin layers of CoFeB. Therefore, FL132 includes a CoFeB layer (layer 32B) bonded to the spin Hall electrode 10, and then a CoFe layer (layer 32A) on the CoFeB is bonded to the spacer layer 34 of the synthetic free layer 30. FL236 is formed in the opposite manner. The CoFe layer (layer 36A) is bonded to the spacer layer 34, and then a CoFeB layer (layer 36B) is formed on the CoFe layer. In FL132, the CoFeB layer 32B may have a thickness between about 0.4nm and 2.4nm, the CoFe layer 32A may have a thickness between about 0.1nm and about 0.4nm, and the total thickness of FL132 may be between about 0.5nm and about 2.5nm. In FL 236 , CoFe layer 36A may have a thickness of about 0.1 nm to about 0.4 nm, CoFeB layer 36B may have a thickness of about 0.9 nm to about 2.4 nm, and the total thickness of FL 236 may be between about 1 nm and about 2.5 nm.

[0056] Similar to the above Figure 4A As described elsewhere, barrier layer 40 may be bcc, and reference layer 52 of reference layer structure 50 may also be bcc. Spacer layer 54 of reference layer structure 50 may be hcp, and pinning layer 56 of reference layer structure 50 may be fcc or bcc. AFM 60 may be fcc.

[0057] Still refer to Figure 4C The spin Hall electrode 10 may be made of platinum, tungsten, tantalum, palladium, or gold and may be formed to have a thickness between about 3 nm and about 10 nm, but other values ​​may also be considered and used. Figure 4A Similar materials and constructions as listed are used to form the remaining layers.

[0058] Figure 5 、 Figure 21 and Figure 22 are schematic cross-sectional views of portions of a SOT-MRAM device 300 according to various embodiments. Some aspects of the illustrated layers of the SOT-MRAM device 300 may be planarized into these cross-sectional views, and it should be understood that certain layers may actually exist in other cross-sections. Figure 23 yes Figure 5 、 Figure 21 and Figure 22 A 3D representation of the SOT-MRAM device shown. Figure 24 is with Figure 5 、 Figure 21 and Figure 22 The circuit diagrams are consistent with those shown in the accompanying drawings.

[0059] In the following embodiments, the Figures 1 to 3 The materials, configurations, dimensions, processes and / or operations described herein may be omitted for clarity. Figure 5 、 Figure 14 and Figure 15 In some embodiments, the SOT-MRAM device includes a layered structure having a multi-wiring layer structure. In some embodiments, the multi-layer wiring layer structure includes "Mx" (x = 0, 1, 2, 3, ...) metal wiring layers, which are located at various levels arranged above the substrate; and "Vy" (y = 0, 1, 2, 3, ...) vias (contacts) connecting the My metal wiring layer to the My+1 metal wiring layer. The metal wiring layer includes metal lines embedded in a dielectric material layer. The vias include conductive plugs embedded in an interlayer dielectric (ILD) material that separates adjacent metal wiring layers. For the purpose of illustration and labeling, elements ending with "A" correspond to the level of x = 0, y = 0, elements ending with "B" correspond to the level of x = 1, y = 1, elements ending with "C" correspond to the level of x = 3, y = 3, and so on. In some embodiments, the even-numbered metal wiring layers extend in one direction (e.g., X), while the odd-numbered metal wiring layers extend in another direction (e.g., Y) that intersects one direction. In some embodiments, the spacing of the metal wiring can generally increase with increasing levels. For example, the metal routing pitch in levels M3 and M4 may be the same, and the pitch for metal routing in M5 or higher levels may be the same and may be greater than the pitch for metal routing in M3 and M4.

[0060] In some embodiments, the metal wiring and vias are made of one or more of aluminum, cobalt, copper, copper alloys, tungsten, titanium, titanium nitride, tantalum, tantalum nitride, alloys thereof, or combinations thereof. The vias may also include a barrier layer or adhesion material layer surrounding the sides of the vias and formed of one or more layers of titanium, titanium nitride, tantalum, tantalum nitride, tungsten nitride, ruthenium, rhodium, platinum, other precious metals, other refractory metals, their nitrides, combinations thereof, or the like.

[0061] In some embodiments, the ILD layer is formed of any suitable dielectric material, including, for example, nitrides (such as silicon nitride), oxides (such as silicon oxide, SiOC and SiOCN), SiCN, phosphosilicate glass (PSG), borosilicate glass (BSG), boron-doped phosphosilicate glass (BPSG), etc., or combinations thereof.

[0062] Contact plug 118 connects the source region 112S or drain region 112D of FET 110 to the M0 metal wiring layer (e.g., conductive line 130A) through dielectric layer 104. Source line SL1 125 is located in M0 metal wiring layer 110 and is coupled to the source region 112S of FET 110 (FET1). Source line SL2 125 is located in M0 metal wiring layer and is coupled to the source region 112S of FET 110 (FET2). The drain region 112D of FET 110 (FET1) is coupled to one end of the SOT sensing structure 10. The drain region 112D of FET 110 (FET2) is coupled to the other end of the SOT sensing structure 10. Bit line BL 160 is coupled to the top of the MTJ film stack 100 in the upper MJ metal stack 100. The word line WL1 is coupled to the gate electrode of the FET 110 (FET1), and the word line WL2 is coupled to the gate electrode of the FET 110 (FET2).

[0063] It should also be understood that Figure 5 The schematic diagram in is merely an illustration of one embodiment and may be changed without departing from the spirit of the present disclosure. For example, it will be understood that multiple intermediate layers may be included as needed to accommodate any desired wiring layout. In particular, when a particular element is described as being in a particular metal wiring layer, the present disclosure contemplates that any desired number of metal wiring layers may be inserted between the described metal wiring layers. For example, where one element is described as being in an M2 metal wiring layer and another element is described as being in an M3 metal wiring layer, there may be any number of metal wiring layers between the M2 metal wiring layer and the M3 metal wiring. Furthermore, as described above, the MTJ film stack 100 may be formed such that the SOT sensing structure 10 is disposed above the MTJ film stack 100.

[0064] In some embodiments, FET 110 is a planar FET, a fin FET, or a gate-all-around FET. Electrode 80 is coupled to drain region 112D of FET 110, and source region 112S of FET 110 is coupled to source line SL125. In some embodiments, source region 112S is shared by two adjacent FETs 110 (see FIG. Figure 22 In some embodiments, a pair of FETs 110 (FET1 and FET2) is connected by a dummy gate structure 121 to another pair of FETs 110 (e.g., Figure 5 The word line WL 120 is coupled to the gate of the FET 110 and switches whether current can flow from the source line SL 125 through the MTJ film stack 100 to the bit line BL 160.

[0065] Reference Figure 5, shows two SOT-MRAM cells 90 of the SOT-MRAM device 300, including MC1 and MC2. Figure 5 As shown, the source regions 112S of adjacent SOT-MRAM cells 90 may be separated by a dummy gate structure 121, similar to the separation of the drain regions 112D of the FETs 110 (FET1 and FET2) by the dummy gate structure 121. In some embodiments, two adjacent SOT-MRAM cells 90 may share a common source region 112S (e.g., see Figure 22 ).

[0066] The spin Hall electrode 10 can be set in the M1 metal wiring layer and can be coupled to the drain region 112D (or source region) of each FET 110 of MC1. The MTJ film stack 100 can be set on the spin Hall electrode 10 in the V1 layer, for example in the bottom V1A of the V1 layer. The through hole 126B can connect the top of the MTJ film stack 100 to the bit line BL160 in the M2 metal wiring layer. The source line SL1 and the source line SL2 can be set in the M0 metal wiring layer and can be coupled to the source region 112S (or drain region) of each FET110 (FET1 and FET2, respectively). The word line WL1 and the word line WL2 are respectively connected to the gate electrode of each FET 110 (FET1 and FET2, respectively). These connections can enter the metal wiring layer through the through holes and wiring patterns in another cross section. As Figure 5 As shown, the source lines (eg, SL1 and SL2 ) are each directed in the Y direction and have a small cross section along the X direction.

[0067] In some embodiments, the MTJ film stack 100 , the spin Hall electrode 10 , the source line SL 125 , and the bit line BL 160 may each be shifted down a metal wiring layer or shifted up one or more metal wiring layers.

[0068] Figures 6 to 21 Shown Figure 5 The SOT-MRAM device 300 is an intermediate step in the formation of the SOT-MRAM device 300. Materials that can be used to form various structures and elements of the SOT-MRAM device 300 have been described above and are not repeated here.

[0069] Figure 6 A cross-sectional view of a substrate 102 and a plurality of FETs 110 formed on the substrate 102 is shown in accordance with some embodiments. The FETs 110 are part of a subsequently formed SOT-MRAM cell 90 of the SOT-MRAM device 300. Figure 6Some exemplary FETs 110 are shown in FIG. The substrate 102 can be a semiconductor substrate, such as silicon, doped or undoped, or an active layer of a semiconductor-on-insulator (SOI) substrate. The semiconductor substrate can include other semiconductor materials, such as germanium; a compound semiconductor including silicon carbide, gallium arsenide, gallium phosphide, gallium nitride, indium phosphide, indium arsenide, and / or indium antimonide; an alloy semiconductor including silicon germanium (SiGe), GaAsP, AlInAs, AlGaAs, GaInAs, GaInP, and / or GaInAsP; or combinations thereof. Other substrates, such as multilayer or gradient substrates, can also be used.

[0070] In some embodiments, FET 110 is a fin field effect transistor (FinFET) that includes a fin (or channel region) 116, a gate structure 114, and source and drain regions 112S and 112D. Figure 6 As shown, fins 116 are formed on substrate 102 and may include the same material as substrate 102 or a different material. In some embodiments, dummy fins (not shown) may be formed between some of the fins 116 to improve process uniformity. Gate structures 114 are formed on multiple fins 116 and extend in a direction perpendicular to the fins 116. In some embodiments, spacers (not shown) may be provided on the sidewalls of gate structures 114. Gate structures 121 may be formed between some of the gate structures 114 to improve process uniformity. In some embodiments, dummy gate structures 121 may be considered "pseudo transistors" or "pseudo FinFETs." Some gate structures 114 serve as word lines in the SOT-MRAM device 300 (described in more detail below) and are accordingly labeled "WL," such as "WL2." Source regions 112S and drain regions 112D are formed in the fins 116 on either side of the gate structure 114. The source regions 112S and drain regions 112D may be, for example, implanted regions of the fins 116 or epitaxial material grown therein. exist Figure 6 In the illustrated embodiment, one side of each fin 116 is adjacent to the source region 112S, and the other side of each fin 116 is adjacent to the drain region 112D.

[0071] The FET 110 shown in the figure is representative, and certain components of the FET 110 may have been omitted from the figure for clarity. In other embodiments, the arrangement, configuration, size, or shape of components such as the fin 116, the dummy fin, the gate structure 114, the dummy gate structure 21, the source region 112S, the drain region 112D, or other components may differ from that shown. In other embodiments, the FET 110 may be another type of transistor, such as a planar transistor.

[0072] exist Figure 7In some embodiments, a dielectric layer 104 is formed over the substrate 102 and patterned to expose the source region 112S and the drain region 112D. The dielectric layer 104 may cover the FET 110 and, in some embodiments, may be considered an interlayer dielectric (ILD). The dielectric layer 104 may be formed of any suitable dielectric material, including, for example, any of the materials listed above for the ILD. The dielectric layer 104 may be formed using any acceptable deposition process, such as spin coating, physical vapor deposition (PVD), chemical vapor deposition (CVD), or the like, or a combination thereof. In some embodiments, the dielectric layer 104 may be a low-k dielectric material, for example, a dielectric material having a dielectric constant (k value) less than about 3.0.

[0073] The dielectric layer 104 may be patterned to form openings 106 that expose the source region 112S and the drain region 112D for subsequent formation of contact plugs 118 (see FIG. Figure 3 ). Dielectric layer 104 can be patterned using appropriate photolithography and etching processes. For example, a photoresist structure (not shown) can be formed on dielectric layer 104 and patterned. Dielectric layer 104 can be etched using the patterned photoresist structure as an etching mask to form opening 106. Dielectric layer 104 can be etched using an appropriate etching process, such as a wet etching process or a dry etching process.

[0074] Steering Figure 8 According to some embodiments, contact plugs 118 are formed to form electrical connections with source region 112S and drain region 112D. In some embodiments, contact plugs 118 are formed by depositing a barrier layer (not separately shown) extending into opening 106, depositing a conductive material over the barrier layer, and performing a planarization process or a grinding process such as a chemical mechanical polishing (CMP) process to remove excess portions covering the conductive barrier layer and the conductive material. The barrier layer or the conductive material of contact plugs 118 can be formed using a suitable process such as chemical vapor deposition (CVD), physical vapor deposition (PVD), atomic layer deposition (ALD), plating, etc. If a barrier layer is used, the barrier layer can be formed of any suitable material, such as TiN, Ti, TaN, Ta, etc., or a combination thereof.

[0075] Go to Figure 9 , forming a conductive line 130A to electrically connect the contact plug 118 and provide electrical wiring within the SOT-MRAM device. The conductive line 130A may be formed in a dielectric layer 128A formed above the dielectric layer 104. The dielectric layer 128A may be the same as that described above for the dielectric layer 104 (see Figure 7 ) and can be deposited using similar methods. In some embodiments, dielectric layer 128A can be considered an intermetallic dielectric layer (IMD).

[0076] The conductive line 130A may be formed using a suitable technique such as damascene, dual damascene, electroplating, deposition, or the like, or a combination thereof. In some embodiments, the conductive line 130A is formed by first depositing a dielectric layer 128A and patterning the dielectric layer 128A to form an opening (e.g., using a suitable photolithography and etching process), and then filling the opening in the dielectric layer 128A with a conductive material. For example, the conductive line 130A may be formed by depositing an optional blanket barrier layer (not separately shown) on the patterned dielectric layer 128A, depositing a conductive material on top of the blanket barrier layer, and performing a planarization process such as a CMP process. A grinding process is performed to remove excess portions covering the conductive barrier layer and the conductive material. The barrier layer or conductive material may be similar to the pin-bonded contact plug 118 (see FIG. 1 ). Figure 8 ) and can be deposited using similar techniques. In some embodiments, for example, if a dual damascene process is used to form the contact plug 118 and the conductive line 130A, the conductive materials of the contact plug 118 and the conductive line 130A can be deposited in the same step.

[0077] In some embodiments, conductive line 130A is formed by first depositing an optional blanket barrier layer on dielectric layer 104 and contact plug 118, depositing a conductive material over the blanket barrier layer, and then patterning the barrier layer and the conductive material (e.g., using appropriate photolithography and etching processes). Dielectric layer 128A may be deposited over conductive line 130A, and a planarization process may be performed to expose conductive line 130A.

[0078] exist Figure 10 In some embodiments, a via 126A is formed within the dielectric layer 124A to form an electrical connection with the conductive line 130A. In some embodiments, the dielectric layer 124A is first formed over the conductive line 130A and the dielectric layer 128A. The dielectric layer 124A can be a material similar to that described above for the dielectric layer 104, and the via 126A can be formed using a process and material similar to that described above for the pin-bonded contact plug 118. In some embodiments, the via 126A formed under the SOT sensing structure 10 can be formed from copper, tungsten, or titanium nitride using a single damascene process and can serve as the bottom electrode 5 of the SOT sensing structure 10 (see FIG. 5 ). Figure 1 As discussed above with respect to contact plug 118, an optional barrier layer may also be used to prevent the material of contact plug 118 from diffusing into the surrounding dielectric layer 124A. In some embodiments, an additional wiring layer is included between the M0 layer and the V0 layer, which represents the layer immediately below the subsequently formed SHE 10. The process of forming conductive lines and vias is repeated to form the desired number of metal wiring layers.

[0079] like Figure 10As shown, after forming the through hole 126A, the spin Hall electrode 10 can be formed. In some embodiments, the through hole 126A can be used as the bottom electrode 5 (in other figures, for example Figure 1 In some embodiments, the buffer layer 7 may be formed over the through hole 126A using any suitable process, such as CVD, PVD, etc., and combinations thereof (see FIG. Figure 1 In embodiments utilizing a buffer layer, the buffer layer may include MgO, etc., deposited to a thickness between approximately 0.2 and 0.9 nm. The bottom electrode 5 may be formed using the techniques discussed above with respect to the formation of the conductive line 130A.

[0080] After forming the buffer layer 7 (if used), the spin Hall electrode 10 can be formed. Figure 1 The spin Hall electrode 10 is formed using the processes and materials discussed above. In some embodiments, after the spin Hall electrode 10 is deposited, the MTJ film stack 100 is sequentially deposited without cracking, as described below. Vacuum is maintained throughout the deposition process of the optional buffer layer 7, the spin Hall electrode 10, and the MTJ film stack 100.

[0081] Reference Figure 11 ,according to Figure 4A , Figure 4B and Figure 4C The embodiment shown, in such Figure 1 The MTJ film stack 100 is deposited in successive layers as shown. The layers for the MTJ film stack 100 are formed on the spin Hall electrode 10, including the synthetic free layer 30, the barrier layer 40, the reference layer structure 50, and the AFM layer 60. Layer 80 may be formed next, which may include a capping layer 70 and a top electrode 75 (see FIG. Figure 1). In some embodiments, the top electrode 75 can be formed as part of a hard mask layer 95. In some embodiments, the hard mask layer 95 can include a composite film stack that includes a metal layer and a dielectric layer above the metal layer. The hard mask layer 95 can be deposited using any suitable process and can be formed from a first layer of any suitable material (e.g., silicon nitride) or a conductive metal layer (e.g., tantalum, tungsten, titanium nitride, etc.) and a second layer of a dielectric such as silicon nitride, or a combination thereof. As described below, when the hard mask layer 95 is used to form the MTJ film stack 100, the dielectric layer of the hard mask layer 95 may be substantially consumed, and the remaining metal layer can be used as the top electrode 75. Each of the MTJ film stack 100, layer 80 and hard mask layer 95 can be formed by a suitable film formation method, including physical vapor deposition (PVD) including sputtering; molecular beam epitaxy (MBE); pulsed laser deposition (PLD); atomic layer deposition (ALD); electron beam (e-beam) epitaxy; chemical vapor deposition (CVD); or a derivative CVD process further including low pressure CVD (LPCVD), ultra-high vacuum CVD (UHVCVD), reduced pressure CVD (RPCVD); electroplating or any combination thereof.

[0082] Reference Figure 12 The hard mask layer 95 is patterned to protect the areas of the SOT-MRAM device 300 where the pillars of the MTJ film stack 100 are to be formed. The patterning may be accomplished by any suitable process, such as a photolithography process.

[0083] Figure 13 The SOT-MRAM device 300 is shown after patterning the MTJ film stack 100. The MTJ film stack 100 can be patterned by any suitable process, such as by etching through each successive layer with a suitable etchant using a dry etching process, such as by reactive ion etching (RIE) and / or ion beam etching (IBE). In some embodiments, all or a portion of the hard mask layer 95 can be removed by the etching process or by a subsequent removal process. As described above, in some embodiments, the dielectric layer can be completely or mostly consumed during etching, and the underlying metal layer can be retained to serve as the top electrode 75 or part of the top electrode 75. The hard mask layer 95 is a metal layer that can be retained after the etching process and can be retained in the final device structure. After patterning the MTJ film stack 100, the cross-section of each MTJ film stack 100 can have a conical shape or a mesa shape. Moreover, as Figure 2As shown, each MTJ film stack 100 may have an elliptical shape in a top view, having a major axis that is parallel to the x-axis and parallel to the direction of current flow in the spin Hall electrode 10. Patterning the MTJ film stack 100 with its major axis parallel to the x-axis allows for greater storage density compared to the case where the MTJ film stack 100 is rotated about the z-axis.

[0084] However, because the MTJ film stack 100 utilizes a synthetic free layer 30, the natural magnetic moment of the synthetic free layer 30 rotates about the z-axis, causing it to be skewed relative to the x-axis, which is parallel to the direction of current flow through the spin Hall electrode 10. As described above, this does not require rotating the MTJ film stack 100. Due to the skewed magnetic moment, switching of the synthetic free layer 30 can be accomplished through spin-orbit torque only, without the need for an external magnetic field.

[0085] exist Figure 14 In the embodiment, a conformal insulating layer 210 is deposited to encapsulate the patterned MTJ film stack 100 and is located above the spin Hall electrode 10. The conformal insulating layer 210 can be formed of any suitable insulating material, such as a nitride, such as silicon nitride, silicon carbide, or the like, or a combination thereof. The conformal insulating layer 210 can be formed by any suitable deposition process, such as physical vapor deposition (PVD) including sputtering; molecular beam epitaxy (MBE); pulsed laser deposition (PLD); atomic layer deposition (ALD); electron beam (e-beam) epitaxy; chemical vapor deposition (CVD), etc.

[0086] exist Figure 15 , a mask 215 may then be deposited on the spin Hall electrode 10 and the MTJ film stack 100. The mask 215 may include any suitable photosensitive material and may be deposited using any suitable process, including spin coating or other processes. In some embodiments, the mask 215 may include a non-photosensitive material and may be patterned by a separate photomask formed over the mask 215, which is used to etch the mask 215.

[0087] exist Figure 16 In the embodiment of the present invention, the mask 215 is patterned to protect the remaining area of ​​the spin Hall electrode 10. The mask 215 can be patterned using an acceptable photopatterning technique, which can be applied to the mask 215 itself or to a separate overlying mask that is then used to etch the mask 215.

[0088] exist Figure 17In the embodiment of the present invention, the insulating layer 210 and the spin Hall electrode 10 are etched to form the shape and structure of the spin Hall electrode 10. The spin Hall electrode 10 can be patterned by any suitable process, such as by using a dry etching process to etch through each successive layer with a suitable etchant. The buffer layer 7 (if used) can also be etched using the mask 215 so that the buffer layer 7 has the same shape and footprint as the spin Hall electrode 10.

[0089] In some embodiments, annealing can be performed, for example, before or after patterning the MTJ film stack 100 and the spin Hall electrode 10. The annealing can be performed at a temperature between about 350° C. and about 425° C., and other values ​​can be used. Additionally, the annealing can be performed under a vacuum between about 1e-7 Torr and about 1e-6 Torr and optionally in the presence of a magnetic field. For example, the annealing can be performed in an in-situ plane (horizontal) magnetic field of about 0.5 Tesla to about 5 Tesla to set the AFM 60.

[0090] exist Figure 18 In the embodiment shown, after the spin Hall electrode 10 is patterned, the mask 215 is removed. For example, the mask 215 can be removed by an ashing process or wet etching. Next, the ILD 128B is deposited. The ILD 128B can be deposited above and around the spin Hall electrode 10 and the MTJ film stack 100. In the embodiment shown, the upper portion of the ILD 128B is represented as ILD 124B, or other ILD layers (ILD 124B) can be deposited in a separate process. The ILD 124B can be planarized after deposition by a planarization process (such as a CMP process) to remove protrusions of the MTJ film stack 100 that may be present in the upper surface of the ILD 124B after deposition.

[0091] According to some embodiments, Figures 19 to 20 An alternative process is shown in . In the process shown, layer 80 is simply the capping layer 70 and has been relabeled as such. A separate top electrode 75 is formed in the process shown. An opening may be formed in the ILD 124B and a top electrode 75 of metal is deposited in the opening. In some embodiments, the top electrode 75 may be a single metal layer, and in other embodiments, the top electrode may be a multilayer structure, such as noted above. In some embodiments, the top electrode 75 may utilize a TiN plug, a W plug, or a Cu plug formed as a single damascene. The top electrode 75 may be deposited by any suitable process, such as by physical vapor deposition (PVD) including sputtering; molecular beam epitaxy (MBE); pulsed laser deposition (PLD); atomic layer deposition (ALD); electron beam (e-beam) epitaxy; chemical vapor deposition (CVD); and the like. In . Figure 20In the embodiment, the top electrode 75 metal is planarized so that the upper surface of the top electrode 75 is flush with the upper surface of the ILD 124B.

[0092] Figure 21 Shown according to Figure 18 Examples of treatment processes, however, it should be understood that Figure 21 and subsequent additional features shown can be integrated into Figure 19 and Figure 20 In the embodiment shown, for example, by depositing an additional ILD 124B layer and then performing the corresponding operations. For example, after forming the ILD 124B, additional vias (e.g., Figure 21 The through-hole 126B is formed in the capping layer 70 to electrically couple to the top of the MTJ film stack 100. In some embodiments, the through-hole 126B can contact the top electrode 75 (which can be formed as part of the hard mask 95), while in other embodiments, the through-hole 126B can serve as part of the top electrode 75, but the through-hole 126B does not extend through the capping layer 70, which remains as protection for the MTJ film stack 100.

[0093] exist Figure 21 124B. In the SOT-MRAM device 300, conductive line 130C is formed to electrically connect via 126B and provide electrical routing to bit line 160. Conductive line 130C may be formed within, and dielectric layer 128C may be formed over, ILD 124B. Dielectric layer 128C may be a material similar to that described above for dielectric layer 104 and may be deposited using techniques similar to those used for dielectric layer 104. In some embodiments, dielectric layer 128C may be considered an intermetallic dielectric (IMD).

[0094] Figure 22 An embodiment of a SOT-MRAM device 400 is shown in which the source region 112S of an adjacent FET 110 is shared between two SOT-MRAM cells 90 (e.g., MC1 and MC2). Sharing source lines SL (e.g., SL2 / 3 as shown) and source regions 112S allows for greater device density. The SOT-MRAM device 400 can be formed using processes and materials similar to those used to form the SOT-MRAM device 300.

[0095] Figure 23 According to some embodiments Figure 21 A three-dimensional view of a SOT-MRAM cell 90 (eg, MCl) of a SOT-MRAM device 300. Figures 1 to 21Materials, configurations, dimensions, processes, and / or operations are described, and detailed descriptions thereof may be omitted.

[0096] In some embodiments, word line 120 (coupled to the gate of FET 110) extends in the Y direction, and source lines 125SL1 and SL2 extend in the X direction. The spin Hall electrode 10 is located above the source or drain region of two adjacent FETs 110 and is coupled to the respective source or drain regions of the two adjacent FETs 110 at either end through vias and metal wiring layers. In some embodiments, the SOT sensing structure 10 can have an orientation primarily in the X direction.

[0097] like Figure 23 As shown, the MTJ film stack 100 is disposed above the spin Hall electrode 10. The MTJ film stack 100 may have a circular column or an elliptical column that may taper as shown in other figures. The bit line 160 is electrically coupled to the top of the MTJ film stack 100 through a through hole and / or a top electrode of the MTJ film stack and may extend in the X direction.

[0098] Figure 24 is a portion of a circuit diagram of a SOT-MRAM device consistent with a SOT-MRAM device 300 according to some embodiments. Figures 1 to 21 Materials, configurations, dimensions, processes, and / or operations are described, and detailed descriptions thereof may be omitted.

[0099] In some embodiments, the bit lines BL and source lines (e.g., SL1 and SL2) extend in the row direction, while the word lines (e.g., WL1 and WL2) extend in the column direction. In some embodiments, the SOT-MRAM cell is arranged at a location defined by the bit line BL, two word lines WL1 and WL2, and two source lines SL1 and SL2. The number of memory cells coupled to the same word line and / or the same bit line is not limited to three or four and can be greater than three, for example, 4, 8, 16, 32, 64, 128, 256, 512, 512, or 1024 or more. The word lines WL1 / WL2 are coupled to a word driver circuit (row decoder), and the source lines SL1 / SL2 (a bundle of N lines represented by a single line) are coupled to a current source circuit, which also functions as a write driver circuit together with the word driver circuit. One end of the spin Hall electrode 10 is coupled to the source or drain of the FET 110, and the other end of the spin Hall electrode 10 is coupled to the other source or drain of the FET 110. One end of the MTJ film stack M is coupled to a spin Hall electrode 10 located between two connections coupled to FETs 110 to control the direction of current flow. The other end of the MTJ film stack M is coupled to a corresponding bit line BL. The gate of the FET 110 is coupled to word lines WL1 / WL2, and the drain or source of the corresponding FET 110 is coupled to source lines SL1 / SL2.

[0100] exist Figure 24 In some embodiments, vertically adjacent SOT-MRAM cells along the column direction are coupled to the same word lines WL1 / WL2. Horizontally adjacent SOT-MRAM cells along the row direction are coupled to the same bit line BL and separate source lines SL1 / SL2. In some embodiments, adjacent FETs 110 in adjacent SOT-MRAM cells along the row direction share the same source lines SL1 and SL2.

[0101] Figure 25 The operation of the SOT-MRAM cell according to an embodiment of the present disclosure is shown. In a write operation, a write current flows through the spin Hall electrode 10. When a first type of data (e.g., "0") is written to the MTJ film stack 100, the word line WL1 and the word line WL2 are set to the gate electrode of the turn-on FET 110. The first source line SL1 is set to apply a first potential (e.g., a write voltage Vw), and the second source line SL2 is set to a second potential (e.g., ground or 0V), the first potential being greater than the second potential. The bit line BL can be floating ("f"). The electrons flowing in the spin Hall metal of the spin Hall electrode 10 have a positive spin Hall angle and induce SOT on the synthetic free layer 30, thereby causing the spin characteristics of the electrons of the synthetic free layer 30 to change.

[0102] When writing the second type of data (e.g., "1") to the MTJ film stack 100, the word line WL1 and the word line WL2 are set to the gate electrode of the conduction FET 110. SL1 is set to a second potential (e.g., ground or 0V), and the second source line SL2 is set to a first potential (e.g., a write voltage "Vw") that is greater than the second potential. The bit line BL can be floating ("f"). Electrons flowing in the opposite direction in the spin Hall metal of the spin Hall electrode 10 have a negative spin Hall angle and cause SOT on the synthetic free layer 30, thereby causing the spin characteristics of the electrons of the synthetic free layer 30 to change.

[0103] When reading data from the MTJ film stack 100, the read operation can be performed in several different ways. Either word line WL1 or WL2 is turned on on the corresponding FET 110, while the other is disconnected. SL1 or SL2 connected to the cutoff gate can float ("f"), while SL1 or SL2 connected to the on gate is coupled to a current source. The potential Vread at the bit line BL can be used to calculate the resistance of the spin Hall electrode 10 and the MTJ film stack 100, thereby determining whether the MTJ is set to a "1" state or a "0" state. In some embodiments, the amplitude of Vread is about 1 / 10 to about 1 / 30 of Vw. In other embodiments, the read current flows from the bit line BL to the source line SL1 or SL2 from the MTJ film stack 100 to the spin Hall electrode 10 in the opposite direction, in other words, from the read bit line BL to the source line SL. In this case, Vread is higher than the source line voltage (for example, Vread is positive).

[0104] Embodiments advantageously utilize a synthetic free layer of a SOT MRAM device that is configured to be antiferromagnetic and provides a magnetic moment that is misaligned (i.e., tilted) with the direction of current passing through the underlying spin Hall metal. In this way, the spin-orbit torque can be used to switch the free layer without an external auxiliary field, thereby switching the resistance of the MTJ film stack between states. Embodiments utilize crystal structures and spacer materials to achieve the antiferromagnetic effect while also improving the magnetoresistance ratio of the MTJ film stack. In this way, an x-type SOT-MRAM device can be provided that does not require a rotating MTJ film stack and uses less current to operate.

[0105] One embodiment is a magnetic memory device including a spin Hall electrode (SHE), which may include a spin Hall metal. The magnetic memory device also includes a magnetic tunnel junction (MTJ) stack disposed above the SHE, which may include a synthetic antiferromagnetic free layer bonded to the SHE. The synthetic antiferromagnetic free layer may include a first magnetic layer, a second magnetic layer, and a spacer layer interposed between the first and second magnetic layers. The device also includes a first wire coupled to a first end of the SHE. The device also includes a second wire coupled to a second end of the SHE. In one embodiment, the magnetic memory device includes the SHE including tungsten, platinum, or tantalum, and the spacer layer including tungsten having a thickness between 4 and 8 angstroms. In one embodiment, the first and second magnetic layers are in a synthetic antiferromagnetic configuration. In one embodiment, the crystal structure of the barrier layer of the MTJ stack matches the crystal structure of the SHE. In one embodiment, the spacer layer is configured to prevent the crystal structure of the first magnetic layer from propagating to the second magnetic layer, wherein the crystal structure of the first magnetic layer is different from the crystal structure of the second magnetic layer. In one embodiment, the spacer layer may include ruthenium, tungsten, tantalum, molybdenum, or chromium. In one embodiment, the spacer layer may include ruthenium, and the first magnetic layer may include a first sublayer of CoFe bonded to the spacer layer and a second sublayer of CoFeB bonded to the SHE. In one embodiment, the MTJ stack has an elliptical shape in a top view, and the long axis of the MTJ stack is parallel to the direction of current flow between the first end of the SHE and the second end of the SHE. In one embodiment, the synthetic antiferromagnetic free layer has a default magnetic moment that is tilted from the long axis of the MTJ stack.

[0106] Another embodiment is a magnetic memory device including a spin Hall electrode (SHE). The magnetic memory device also includes a top fixed magnetic tunnel junction (MTJ) stack disposed above the SHE. The MTJ stack may include: a spacer layer between a first free layer of the MTJ stack and a second free layer of the MTJ stack. The first free layer and the second free layer are magnetically coupled via an antiferromagnetic structure. A reference layer structure is disposed above the second free layer. The reference layer structure may include a synthetic antiferromagnetic structure and a barrier layer between the second free layer. Structure of the free layer and the reference layer. In one embodiment, the MTJ stack has an elongated shape, wherein the axis of the MTJ stack is parallel to the direction of current flow through the SHE. In one embodiment, the first free layer and the second free layer have a magnetic moment having a non-zero x-component and a non-zero y-component. In one embodiment, the thickness of the spacer layer is configured such that the first free layer and the second free layer are in an antiferromagnetic configuration, and the thickness is between 4 angstroms and 8 angstroms. In one embodiment, the reference layer structure includes a reference layer adjacent to the barrier layer, a pinned layer, and a second spacer layer interposed between the reference layer and the pinned layer, wherein the reference layer structure is in an antiferromagnetic configuration. In one embodiment, the MTJ stack may further include an antiferromagnetic layer above the reference layer stack. In one embodiment, the first free layer may include a first layer of CoFeB bonded to the SHE and a second layer of CoFe bonded to the spacer layer, and the spacer layer may include ruthenium.

[0107] Another embodiment is a method that includes depositing a spin Hall metal layer over an interlayer dielectric of an interconnect. The method also includes depositing a series of layers of a magnetic tunnel junction (MTJ) film stack, the deposition including: depositing a synthetic antiferromagnetic free layer structure on the spin Hall metal, depositing a barrier layer on the free layer structure, and depositing a reference layer structure on the barrier layer. The MTJ film stack is patterned into at least one MTJ pillar. For each of the at least one MTJ pillar, the spin Hall metal layer is patterned into a spin Hall electrode. In one embodiment, depositing the synthetic antiferromagnetic free layer may include: depositing a first magnetic material layer on the spin Hall metal layer; and depositing the first magnetic material layer on the spin Hall metal layer. Depositing a spacer layer on the first magnetic material layer; and depositing a second magnetic material layer on the spacer layer, wherein the spacer layer has a first thickness that causes the first magnetic material layer and the second magnetic material layer to be antiferromagnetic. In one embodiment, depositing the first magnetic material layer may include depositing the first magnetic material layer to have a first crystal structure, wherein depositing the second magnetic material layer may include depositing the second magnetic material layer to have a second crystal structure that is different from the first magnetic material layer. Crystal structure. In one embodiment, depositing the spin Hall metal layer may include depositing the spin Hall metal layer to have a first crystal structure, wherein depositing the barrier layer may include depositing the barrier layer to have a second crystal structure different from the first crystal structure. In one embodiment, the method may include: providing a current from a first end of the spin Hall electrode to a second end of the spin Hall electrode, the current causing a spin-orbit interaction in the spin Hall electrode to induce a corresponding spin-orbit torque in the free magnetic layer structure, the spin-orbit torque causing the magnetic moment of the free magnetic layer structure to change from a first state to a second state, the first state corresponding to a magnetic moment deflection of the free magnetic layer structure from the direction of current flow.

[0108] Embodiments of the present application provide a magnetic memory device comprising: a spin Hall electrode (SHE) comprising a spin Hall metal; a magnetic tunnel junction (MTJ) stack disposed above the SHE, the MTJ comprising a synthetic antiferromagnetic free layer coupled to the SHE, the synthetic antiferromagnetic free layer comprising a first magnetic layer, a second magnetic layer, and a spacer layer interposed between the first and second magnetic layers; a first conductive wire coupled to a first end of the SHE; and a second conductive wire coupled to a second end of the SHE. In some embodiments, the SHE comprises tungsten, platinum, or tantalum, and the spacer layer comprises tungsten having a thickness between 4 angstroms and 8 angstroms. In some embodiments, the first magnetic layer and the second magnetic layer are arranged in a synthetic antiferromagnetic configuration. In some embodiments, the crystal structure of the barrier layer of the MTJ stack matches the crystal structure of the SHE. In some embodiments, the spacer layer is configured to prevent the crystal structure of the first magnetic layer from propagating to the second magnetic layer, wherein the crystal structure of the first magnetic layer differs from the crystal structure of the second magnetic layer. In some embodiments, the spacer layer comprises ruthenium, tungsten, tantalum, molybdenum, or chromium. In some embodiments, the spacer layer comprises ruthenium, and the first magnetic layer comprises a first sublayer of CoFe bonded to the spacer layer and a second sublayer of CoFeB bonded to the SHE. In some embodiments, the MTJ stack is elliptical in top view, and the long axis of the MTJ stack is parallel to the direction of current flow between the first end of the SHE and the second end of the SHE. In some embodiments, the synthetic antiferromagnetic free layer has a default magnetic moment that is tilted from the long axis of the MTJ stack.

[0109] Embodiments of the present application provide a magnetic memory device comprising: a spin Hall electrode (SHE); and a top-pinned magnetic tunnel junction (MTJ) stack disposed above the SHE, the MTJ stack comprising: a spacer layer interposed between a first free layer of the MTJ stack and a second free layer of the MTJ stack, the first free layer and the second free layer being magnetically coupled in an antiferromagnetic configuration; a reference layer structure disposed above the second free layer; and a barrier layer interposed between the second free layer and the reference layer structure. In some embodiments, the MTJ stack has an elongated shape, wherein an axis of the MTJ stack is parallel to a direction of current flow through the SHE. In some embodiments, the first free layer and the second free layer have magnetic moments, the magnetic moments having a non-zero x-component and a non-zero y-component. In some embodiments, the thickness of the spacer layer is configured to position the first free layer and the second free layer in an antiferromagnetic configuration, the thickness being between 4 angstroms and 8 angstroms. In some embodiments, a reference layer structure includes a reference layer adjacent to the barrier layer, a pinned layer, and a second spacer layer interposed between the reference layer and the pinned layer, wherein the reference layer structure is in an antiferromagnetic configuration. In some embodiments, a first free layer includes a first layer of CoFeB bonded to the SHE and a second layer of CoFe bonded to the spacer layer, wherein the spacer layer includes ruthenium.

[0110] Embodiments of the present application provide a method comprising: depositing a spin Hall metal layer on an interlayer dielectric of an interconnect; depositing a series of layers of a magnetic tunnel junction (MTJ) film stack, wherein the depositing comprises: depositing a synthetic antiferromagnetic free layer structure above the spin Hall metal, depositing a barrier layer above the free layer structure, and depositing a reference layer structure on the barrier layer; patterning the MTJ film stack into at least one MTJ pillar; and patterning the spin Hall metal layer into a spin Hall electrode for each of the at least one MTJ pillar. In some embodiments, depositing the synthetic antiferromagnetic free layer comprises: depositing a first magnetic material layer on the spin Hall metal layer; depositing a spacer layer on the first magnetic material layer; and depositing a second magnetic material layer on the spacer layer, wherein the spacer layer has a first thickness, the first thickness causing the first magnetic material layer and the second magnetic material layer to be antiferromagnetic. In some embodiments, depositing the first magnetic material layer comprises depositing the first magnetic material layer to have a first crystal structure, wherein depositing the second magnetic material layer comprises depositing the second magnetic material layer to have a second crystal structure different from the first crystal structure. In some embodiments, depositing the spin Hall metal layer includes depositing the spin Hall metal layer to have a first crystal structure, wherein depositing the barrier layer includes depositing the barrier layer to have a second crystal structure different from the first crystal structure. In some embodiments, the method further includes providing a current from a first end of the spin Hall electrode to a second end of the spin Hall electrode, wherein the current induces a spin-orbit torque in the spin Hall electrode to induce a corresponding spin-orbit torque in the free magnetic layer structure, wherein the spin-orbit torque causes the magnetic moment of the free magnetic layer structure to change from a first state to a second state, wherein the first state corresponds to the magnetic moment of the free magnetic layer structure being deflected from the direction of flow of the current.

[0111] The foregoing summarizes the features of several embodiments so that those skilled in the art can better understand the various aspects of the present disclosure. Those skilled in the art will appreciate that they can easily use this disclosure as a basis for designing or modifying other processes and structures to achieve the same purposes and / or achieve the same advantages as the embodiments described herein. Those skilled in the art will also appreciate that such equivalent constructions do not depart from the spirit and scope of the present disclosure, and that they may undergo various changes, substitutions, and modifications without departing from the spirit and scope of the present disclosure.

Claims

1. A magnetic storage device comprising: a spin Hall electrode, wherein the spin Hall electrode comprises a spin Hall metal; a magnetic tunnel junction stack disposed above the spin Hall electrode, the magnetic tunnel junction comprising a synthetic antiferromagnetic free layer coupled to the spin Hall electrode, the synthetic antiferromagnetic free layer comprising a first magnetic layer, a second magnetic layer, and a spacer layer interposed between the first magnetic layer and the second magnetic layer; a first wire coupled to a first end of the spin Hall electrode; as well as a second wire coupled to a second end of the spin Hall electrode, wherein the first end and the second end are opposite to each other; The magnetic tunnel junction stack is elliptical in a top view, and the long axis of the magnetic tunnel junction stack is parallel to the current flow direction between the first end of the spin Hall electrode and the second end of the spin Hall electrode. The magnetic moment of the first magnetic layer and the magnetic moment of the second magnetic layer rotate in opposite directions starting from the long axis of the magnetic tunnel junction stack. The first conductive line is electrically connected to the source / drain of the first transistor, the second conductive line is electrically connected to the source / drain of the second transistor, and one end of the magnetic tunnel junction stack opposite to the spin Hall electrode is connected to the bit line of the magnetic memory device through a conductive pattern. The first conductive line and the second conductive line are configured such that a current flowing from the first conductive line to the second conductive line is parallel to a long axis of the magnetic tunnel junction stack.

2. The magnetic memory device according to claim 1, wherein The spin Hall electrode comprises tungsten, platinum, or tantalum, and the spacer layer comprises tungsten with a thickness between 4 angstroms and 8 angstroms.

3. The magnetic memory device according to claim 1, wherein The first magnetic layer and the second magnetic layer are in a synthetic antiferromagnetic configuration.

4. The magnetic memory device according to claim 1, wherein The crystal structure of the barrier layer of the magnetic tunnel junction stack matches the crystal structure of the spin Hall electrode.

5. The magnetic memory device according to claim 1, wherein The spacer layer is configured to prevent a crystal structure of the first magnetic layer from propagating to the second magnetic layer, wherein the crystal structure of the first magnetic layer is different from the crystal structure of the second magnetic layer. The magnetic memory device according to claim 1 , wherein: The spacer layer includes ruthenium, tungsten, tantalum, molybdenum, or chromium.

7. The magnetic memory device according to claim 6, wherein The spacer layer includes ruthenium, and the first magnetic layer includes a first sublayer of CoFe bonded to the spacer layer and a second sublayer of CoFeB bonded to the spin Hall electrode.

8. The magnetic memory device according to claim 1, wherein The barrier layer of the magnetic tunnel junction stack has the same crystal structure as the first magnetic layer and the second magnetic layer.

9. The magnetic memory device according to claim 1, wherein The synthetic antiferromagnetic free layer has a default magnetic moment that is tilted from a long axis of the magnetic tunnel junction stack.

10. A magnetic memory device comprising: Spin Hall electrode; a first wire coupled to a first end of the spin Hall electrode; as well as a second wire coupled to a second end of the spin Hall electrode, wherein the first end and the second end are opposite to each other; as well as A top-pinned magnetic tunnel junction stack is disposed above the spin Hall electrode, the magnetic tunnel junction stack comprising: a spacer layer interposed between a first free layer of the magnetic tunnel junction stack and a second free layer of the magnetic tunnel junction stack, the first free layer and the second free layer being magnetically coupled via an antiferromagnetic configuration, a reference layer structure disposed above the second free layer, and a barrier layer interposed between the second free layer and the reference layer structure, wherein the magnetic tunnel junction stack has an elongated shape, wherein the axis of the magnetic tunnel junction stack is parallel to the direction of current flow through the spin Hall electrode, wherein the magnetic moment of the first free layer and the magnetic moment of the second free layer rotate in opposite directions respectively starting from the axis of the magnetic tunnel junction stack; The first end of the spin Hall electrode is electrically connected to the source / drain of the first transistor, the second end of the spin Hall electrode is electrically connected to the source / drain of the second transistor, the first end is opposite to the second end, and the end of the magnetic tunnel junction stack opposite to the spin Hall electrode is connected to the bit line of the magnetic memory device through a conductive pattern. The first conductive line and the second conductive line are configured such that a current flowing from the first conductive line to the second conductive line is parallel to an axis of the magnetic tunnel junction stack.

11. The magnetic memory device according to claim 10, wherein The barrier layer of the magnetic tunnel junction stack has a crystal structure that is the same as the first free layer and the second free layer.

12. The magnetic memory device according to claim 10, wherein The magnetic moment of the first free layer and the magnetic moment of the second free layer each have a non-zero x-component and a non-zero y-component.

13. The magnetic memory device according to claim 10, wherein The spacer layer has a thickness configured to position the first free layer and the second free layer in an antiferromagnetic configuration, the thickness being between 4 angstroms and 8 angstroms.

14. The magnetic memory device according to claim 10, wherein The reference layer structure includes a reference layer adjacent to the barrier layer, a pinned layer, and a second spacer layer interposed between the reference layer and the pinned layer, wherein the reference layer structure is in an antiferromagnetic configuration.

15. The magnetic memory device according to claim 10, wherein The first free layer includes a first layer of CoFeB bonded to the spin Hall electrode and a second layer of CoFe bonded to the spacer layer, the spacer layer including ruthenium.

16. A method of forming a magnetic memory device, comprising: depositing a spin Hall metal layer on an interlayer dielectric of the interconnect; Depositing a series of layers of a magnetic tunnel junction film stack, the depositing comprising: Depositing a synthetic antiferromagnetic free layer structure on the spin Hall metal, wherein the synthetic antiferromagnetic free layer structure includes a first magnetic material layer, a second magnetic material layer and a spacer layer between the first magnetic material layer and the second magnetic material layer, and depositing a barrier layer on the free layer structure; and depositing a reference layer structure on the barrier layer; patterning the magnetic tunnel junction film stack into at least one magnetic tunnel junction pillar; For each of the at least one magnetic tunnel junction pillar, the spin Hall metal layer is patterned into a spin Hall electrode, forming a first conductive line at a first end of the spin Hall electrode; and forming a second wire at a second end of the spin Hall electrode, wherein the first end and the second end are opposite to each other; wherein the at least one magnetic tunnel junction column has an elongated shape, wherein an axis of the at least one magnetic tunnel junction column is parallel to a direction of current flow through the spin Hall electrode, The magnetic moment of the first magnetic material layer and the magnetic moment of the second magnetic material layer rotate in opposite directions starting from the axis of the at least one magnetic tunnel junction column. The first end of the spin Hall electrode is electrically connected to the source / drain of the first transistor, the second end of the spin Hall electrode is electrically connected to the source / drain of the second transistor, the first end is opposite to the second end, and the end of the at least one magnetic tunnel junction pillar opposite to the spin Hall electrode is connected to the bit line of the magnetic memory device through a conductive pattern. The first conductive line and the second conductive line are configured such that a current flowing from the first conductive line to the second conductive line is parallel to an axis of the at least one magnetic tunnel junction pillar.

17. The method of forming a magnetic memory device according to claim 16, wherein depositing the synthetic antiferromagnetic free layer structure comprises: depositing the first magnetic material layer on the spin Hall metal layer; depositing the spacer layer on the first magnetic material layer; as well as The second magnetic material layer is deposited on the spacer layer, wherein the spacer layer has a first thickness that causes the first magnetic material layer and the second magnetic material layer to be antiferromagnetic.

18. The method of forming a magnetic memory device according to claim 17, wherein depositing the first magnetic material layer comprises depositing the first magnetic material layer to have a first crystal structure, and wherein depositing the second magnetic material layer comprises depositing the second magnetic material layer to have a second crystal structure different from the first crystal structure.

19. The method of forming a magnetic memory device according to claim 16, wherein depositing the spin Hall metal layer comprises depositing the spin Hall metal layer to have a first crystal structure, and wherein depositing the barrier layer comprises depositing the barrier layer to have a second crystal structure different from the first crystal structure.

20. The method of forming a magnetic memory device according to claim 16, further comprising: A current is provided from the first end of the spin Hall electrode to the second end of the spin Hall electrode, the current causing a spin-orbit torque in the spin Hall electrode to induce a corresponding spin-orbit torque in the free magnetic layer structure, the spin-orbit torque causing the magnetic moment of the free magnetic layer structure to change from a first state to a second state, the first state corresponding to the magnetic moment of the free magnetic layer structure being deflected from the direction of flow of the current.

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