Semiconductor device and method of manufacturing the same

Abstract

The semiconductor device according to the technical solution of the present application includes: a first semiconductor chip; a second semiconductor chip; a first metal plate disposed on the upper surface of the first semiconductor chip; a second metal plate disposed on the upper surface of the second semiconductor chip; and a packaging resin that covers the first semiconductor chip, the second semiconductor chip, the first metal plate, and the second metal plate. In the packaging resin, a groove extending downward from the upper surface of the packaging resin is formed between the first metal plate and the second metal plate. The first metal plate has a first exposed portion exposed from the side surface of the packaging resin forming the groove at an end portion opposite to the second metal plate. The second metal plate has a second exposed portion exposed from the side surface of the packaging resin forming the groove at an end portion opposite to the first metal plate.

Description

Technical Field

[0001] The present invention relates to a semiconductor device and a method of manufacturing the semiconductor device. Background Art

[0002] In Patent Document 1, there is disclosed a semiconductor device in which metal electrodes of a semiconductor chip are internally wired to a conductor pattern through internal connection terminals and aluminum wires. In addition, a plurality of external lead terminals are led out from the conductor pattern to the upper surface of a resin case. The internal connection terminals and the external lead terminals are constituted by a lead frame formed by processing a copper plate.

[0003] Patent Document 1: International Publication No. 2012 / 157583 Summary of the Invention

[0004] In Patent Document 1, the external lead terminals and the internal connection terminals are separate bodies. Therefore, the positioning accuracy of the internal connection terminals may decrease.

[0005] The present invention has been made to solve the above problems, and an object thereof is to obtain a semiconductor device and a method of manufacturing the semiconductor device capable of improving the positioning accuracy of a metal plate inside a package.

[0006] The semiconductor device according to the first aspect of the present application includes: a first semiconductor chip; a second semiconductor chip; a first metal plate provided on the upper surface of the first semiconductor chip; a second metal plate provided on the upper surface of the second semiconductor chip; and a packaging resin that covers the first semiconductor chip, the second semiconductor chip, the first metal plate, and the second metal plate. In the packaging resin, a groove extending downward from the upper surface of the packaging resin is formed between the first metal plate and the second metal plate. The first metal plate has a first exposed portion exposed from the side surface of the packaging resin forming the groove at an end portion facing the second metal plate. The second metal plate has a second exposed portion exposed from the side surface of the packaging resin forming the groove at an end portion facing the first metal plate.

[0007] The semiconductor device according to the second aspect of the present application includes: a first semiconductor chip; a second semiconductor chip; a first metal plate provided on the upper surface of the first semiconductor chip; a second metal plate provided on the upper surface of the second semiconductor chip; and a packaging resin that covers the first semiconductor chip, the second semiconductor chip, the first metal plate, and the second metal plate. An end portion of the first metal plate facing the second metal plate extends toward the upper surface of the packaging resin and is exposed from the upper surface of the packaging resin. An end portion of the second metal plate facing the first metal plate extends toward the upper surface of the packaging resin and is exposed from the upper surface of the packaging resin.

[0008] The semiconductor device according to the third aspect of the present application includes: a first semiconductor chip; a second semiconductor chip; a first metal plate that electrically connects the upper surface of the first semiconductor chip to the back surface of the second semiconductor chip; a first electrode terminal that is provided separately from the first metal plate and electrically connects to the back surface of the second semiconductor chip; a housing that has a housing portion for housing the first semiconductor chip, the second semiconductor chip, and the first metal plate and an outer peripheral portion that surrounds the housing portion; and a potting resin that encapsulates the housing portion. The first electrode terminal extends to the outside of the housing portion, and the first metal plate is fixed to the housing.

[0009] The manufacturing method of the semiconductor device according to the fourth aspect of the present application is to mount a frame in which the first metal plate and the second metal plate are integrated via a connecting portion by providing the first metal plate on the upper surface of the first semiconductor chip and the second metal plate on the upper surface of the second semiconductor chip, cover the frame, the first semiconductor chip, and the second semiconductor chip with a potting resin, and form a notch in the connecting portion and a groove in the potting resin together with the potting resin so that the first metal plate and the second metal plate are separated.

[0010] The manufacturing method of the semiconductor device according to the fifth aspect of the present application includes the following steps: fixing a first electrode terminal and a plurality of signal terminals to the outer peripheral portion of a housing having a housing portion and an outer peripheral portion that surrounds the housing portion; a housing step of housing a first semiconductor chip and a second semiconductor chip in the housing portion and electrically connecting the first electrode terminal to the back surface of the second semiconductor chip; a connecting step of, after the housing step, connecting a signal terminal connecting portion provided on the upper surface of the first semiconductor chip and a signal terminal connecting portion provided on the upper surface of the second semiconductor chip to the respective plurality of signal terminals through wires; and after the connecting step, fixing a first metal plate to the housing and electrically connecting the upper surface of the first semiconductor chip to the back surface of the second semiconductor chip through the first metal plate.

[0011] Effects of the Invention

[0012] Regarding the semiconductor device according to the first aspect of the present application, it is possible to cover the first metal plate and the second metal plate with a potting resin in a state where the first metal plate and the second metal plate are integrated via a connecting portion, and then form a groove in the potting resin to remove the connecting portion. Therefore, the positioning accuracy of the metal plate inside the package can be improved.

[0013] Regarding the semiconductor device according to the second aspect of the present application, in a state where the first metal plate and the second metal plate are integrated via a connection portion, the first metal plate and the second metal plate can be covered with a packaging resin, and then the connection portion exposed from the upper surface of the packaging resin can be removed. Therefore, the positioning accuracy of the metal plates inside the package can be improved.

[0014] Regarding the semiconductor device according to the third aspect of the present application, the first metal plate is fixed to the housing. Therefore, the positioning accuracy of the metal plates inside the package can be improved.

[0015] Regarding the manufacturing method of the semiconductor device according to the fourth aspect of the present application, in a state where the first metal plate and the second metal plate are integrated via a connection portion, the first metal plate and the second metal plate are covered with a packaging resin. Then, together with the packaging resin, a cut is formed in the connection portion, and the connection portion is removed. Therefore, the positioning accuracy of the metal plates inside the package can be improved.

[0016] Regarding the manufacturing method of the semiconductor device according to the fifth aspect of the present application, after wire bonding is performed on the signal terminal connection portion and the signal terminal, the first metal plate is fixed to the housing. Therefore, the positioning accuracy of the first metal plate can be improved. Description of the Drawings

[0017] Figure 1 It is a top view of the semiconductor device according to Embodiment 1.

[0018] Figure 2 It is a cross-sectional view of the semiconductor device according to Embodiment 1.

[0019] Figure 3 It is a diagram showing a state where a frame is mounted on a semiconductor chip.

[0020] Figure 4 It is a diagram for explaining the packaging process.

[0021] Figure 5 It is a diagram for explaining the removal process.

[0022] Figure 6 [[ID=�5]]It is a cross-sectional view of the semiconductor device according to the first modification of Embodiment 1.

[0023] Figure 7 It is a cross-sectional view of the semiconductor device according to the second modification of Embodiment 1.

[0024] Figure 8 It is a cross-sectional view of the semiconductor device according to the third modification of Embodiment 1.

[0025] Figure 9This is a cross-sectional view of a semiconductor device according to a fourth modification of the first embodiment.

[0026] Figure 10 This is a top view of a semiconductor device according to a fifth modification of the first embodiment.

[0027] Figure 11 A diagram illustrating a method for manufacturing a semiconductor device according to the second embodiment.

[0028] Figure 12 This is a cross-sectional view of a semiconductor device according to a second embodiment.

[0029] Figure 13 This is a top view of a semiconductor device according to a third embodiment.

[0030] Figure 14 This is a top view of a semiconductor device according to a first modification of the third embodiment.

[0031] Figure 15 This is a top view of a semiconductor device according to a second variation of the third embodiment.

[0032] Figure 16 This is a top view of a semiconductor device according to a third modification of the third embodiment.

[0033] Figure 17 A diagram illustrating a method for manufacturing a semiconductor device according to a fourth variation of the third embodiment. DETAILED DESCRIPTION

[0034] A semiconductor device and a method for manufacturing a semiconductor device according to an embodiment of the present invention will be described with reference to the accompanying drawings. Identical or corresponding components are denoted by the same reference numerals, and duplicate descriptions may be omitted.

[0035] Implementation method 1.

[0036] Figure 1 It is a top view of the semiconductor device 100 according to the first embodiment. Figure 2 This is a cross-sectional view of a semiconductor device 100 according to Embodiment 1. The semiconductor device 100 is, for example, a power conversion device. In this embodiment, the semiconductor device 100 constitutes a three-phase inverter. The semiconductor device 100 has a DLB (Direct Lead Bonding) structure.

[0037] In semiconductor device 100, multiple semiconductor chips are mounted on an insulating substrate 10. Insulating substrate 10 includes an insulating layer 10b, a conductive layer 10a provided on the back surface of insulating layer 10b, and first to fifth conductive layers 11 to 15 provided on the top surface of insulating layer 10b. First to fifth conductive layers 11 to 15 form conductive patterns.

[0038] On the upper surface of the first conductive layer 11, a first semiconductor chip 21a, a third semiconductor chip 23a, and a fourth semiconductor chip 24a are provided. In addition, a first diode 21b, a third diode 23b, and a fourth diode 24b are provided on the upper surface of the first conductive layer 11. On the upper surface of the second conductive layer 12, a second semiconductor chip 22a and a second diode 22b are provided. In addition, a fifth semiconductor chip 25a and a fifth diode 25b are provided on the upper surface of the fourth conductive layer 14. On the upper surface of the fifth conductive layer 15, a sixth semiconductor chip 26a and a sixth diode 26b are provided.

[0039] The first semiconductor chip 21a to the sixth semiconductor chip 26a are, for example, IGBTs (Insulated Gate Bipolar Transistors). The first semiconductor chip 21a to the sixth semiconductor chip 26a may also be MOSFETs (Metal-Oxide-Semiconductor Field-Effect Transistors). The first diode 21b to the sixth diode 26b are freewheeling diodes.

[0040] The first conductive layer 11 is electrically connected to the collectors of the first semiconductor chip 21a, the third semiconductor chip 23a, and the fourth semiconductor chip 24a. In addition, the first conductive layer 11 is electrically connected to the cathodes of the first diode 21b, the third diode 23b, and the fourth diode 24b. The second conductive layer 12 is electrically connected to the collector of the second semiconductor chip 22a and the cathode of the second diode 22b. The fourth conductive layer 14 is electrically connected to the collector of the fifth semiconductor chip 25a and the cathode of the fifth diode 25b. The upper surface of the fifth conductive layer 15 is electrically connected to the collector of the sixth semiconductor chip 26a and the cathode of the sixth diode 26b.

[0041] A first metal plate 31 is provided on the upper surface of the first semiconductor chip 21a and the upper surface of the first diode 21b. The first metal plate 31 connects the upper surface of the first semiconductor chip 21a and the upper surface of the first diode 21b to the upper surface of the second conductive layer 12. That is, the first metal plate 31 electrically connects the upper surface of the first semiconductor chip 21a to the back surface of the second semiconductor chip 22a.

[0042] A second metal plate 32 is provided on the upper surfaces of the second semiconductor chip 22a, the second diode 22b, the fifth semiconductor chip 25a, the fifth diode 25b, the sixth semiconductor chip 26a, and the sixth diode 26b. The second metal plate 32 connects the upper surfaces of the second semiconductor chip 22a, the second diode 22b, the fifth semiconductor chip 25a, the fifth diode 25b, the sixth semiconductor chip 26a, and the sixth diode 26b to the upper surface of the third conductive layer 13.

[0043] A third metal plate 33 is provided on the upper surface of the third semiconductor chip 23a and the upper surface of the third diode 23b. The third metal plate 33 connects the upper surface of the third semiconductor chip 23a and the upper surface of the third diode 23b to the upper surface of the fourth conductive layer 14. That is, the third metal plate 33 electrically connects the upper surface of the third semiconductor chip 23a to the back surface of the fifth semiconductor chip 25a.

[0044] A fourth metal plate 34 is provided on the upper surface of the fourth semiconductor chip 24a and the upper surface of the fourth diode 24b. The fourth metal plate 34 connects the upper surface of the fourth semiconductor chip 24a and the upper surface of the fourth diode 24b to the upper surface of the fifth conductive layer 15. That is, the fourth metal plate 34 electrically connects the upper surface of the fourth semiconductor chip 24a to the back surface of the sixth semiconductor chip 26a.

[0045] The first metal plate 31 to the fourth metal plate 34 are electrically connected to the emitters of the first semiconductor chip 21a to the sixth semiconductor chip 26a, respectively. In addition, the first metal plate 31 to the fourth metal plate 34 are electrically connected to the anodes of the first diode 21b to the sixth diode 26b, respectively. The first metal plate 31 to the fourth metal plate 34 are inner frames provided inside the package.

[0046] The semiconductor device 100 has first electrode terminals 35 to fifth electrode terminals 39. The first electrode terminal 35 is provided on the upper surface of the second conductive layer 12 and is electrically connected to the back surface of the second semiconductor chip 22a. The first electrode terminal 35 is at the same potential as the first metal plate 31 and is provided separately from the second semiconductor chip 22a and the first metal plate 31.

[0047] The second electrode terminal 36 is provided on the upper surface of the first conductive layer 11. The second electrode terminal 36 is electrically connected to the back surfaces of the first semiconductor chip 21a, the third semiconductor chip 23a, and the fourth semiconductor chip 24a. The second electrode terminal 36 is provided separately from the first semiconductor chip 21a, the third semiconductor chip 23a, and the fourth semiconductor chip 24a.

[0048] The third electrode terminal 37 is provided on the upper surface of the third conductive layer 13. The third electrode terminal 37 is at the same potential as the second metal plate 32 and is provided separately from the second metal plate 32.

[0049] The fourth electrode terminal 38 is provided on the upper surface of the fourth conductive layer 14 and is electrically connected to the back surface of the fifth semiconductor chip 25a. The fourth electrode terminal 38 is at the same potential as the third metal plate 33 and is provided separately from the fifth semiconductor chip 25a and the third metal plate 33.

[0050] The fifth electrode terminal 39 is provided on the upper surface of the fifth conductive layer 15 and is electrically connected to the back surface of the sixth semiconductor chip 26a. The fifth electrode terminal 39 is at the same potential as the fourth metal plate 34 and is provided separately from the sixth semiconductor chip 26a and the fourth metal plate 34.

[0051] The semiconductor device 100 has a plurality of signal terminals 40. The first semiconductor chip 21a to the sixth semiconductor chip 26a have signal terminal connection portions on the upper surface that are connected to the plurality of signal terminals 40 through wires 42. The signal terminal connection portions are the gate electrodes of the first semiconductor chip 21a to the sixth semiconductor chip 26a. Signals for turning on and off the first semiconductor chip 21a to the sixth semiconductor chip 26a are respectively input to the plurality of signal terminals 40.

[0052] The first electrode terminal 35 to the fifth electrode terminal 39 are main electrode frames for inputting and outputting power to and from the outside. In the present embodiment, the second electrode terminal 36 is the P terminal of the inverter. In addition, the third electrode terminal 37 is the N terminal of the inverter. In addition, the first electrode terminal 35, the fourth electrode terminal 38, and the fifth electrode terminal 39 are the AC output terminals of the inverter.

[0053] The first semiconductor chip 21a, the third semiconductor chip 23a, and the fourth semiconductor chip 24a form an upper bridge arm. The second semiconductor chip 22a, the fifth semiconductor chip 25a, and the sixth semiconductor chip 26a form a lower bridge arm. The semiconductor chips of the lower bridge arm are arranged between the metal plate connected to the semiconductor chips of the upper bridge arm and the AC output terminal. The first electrode terminal 35 to the fifth electrode terminal 39 are connected to the conductive layer and do not pass through the semiconductor chips.

[0054] The insulating substrate 10, the first semiconductor chip 21a to the sixth semiconductor chip 26a, the first diodes 21b to 26b, the first metal plate 31 to the fourth metal plate 34, the first electrode terminal 35 to the fifth electrode terminal 39, and the plurality of signal terminals 40 are covered with a packaging resin 50. The packaging resin 50 forms a package of the semiconductor device 100.

[0055] The first electrode terminal 35 to the fifth electrode terminal 39 and the plurality of signal terminals 40 extend to the outside of the packaging resin 50. Therefore, the first electrode terminal 35 to the fifth electrode terminal 39 and the plurality of signal terminals 40 can be connected from the outside of the semiconductor device 100.

[0056] At the encapsulation resin 50, a groove 51 extending downward from the upper surface of the encapsulation resin 50 is formed between the first metal plate 31, the third metal plate 33, the fourth metal plate 34, and the second metal plate 32. In the present embodiment, the first semiconductor chip 21a, the third semiconductor chip 23a, and the fourth semiconductor chip 24a are arranged along the long side direction of the package on the upper surface of the first conductive layer 11. Similarly, the second semiconductor chip 22a, the fifth semiconductor chip 25a, and the sixth semiconductor chip 26a are arranged along the long side direction of the package. The groove 51 extends along the arrangement direction of the first semiconductor chip 21a, the third semiconductor chip 23a, and the fourth semiconductor chip 24a.

[0057] The first metal plate 31 has a first exposed portion 31b exposed from the side surface of the encapsulation resin 50 where the groove 51 is formed at the end portion facing the second metal plate 32. The second metal plate 32 has a second exposed portion 32b exposed from the side surface of the encapsulation resin 50 where the groove 51 is formed at the end portion facing the first metal plate 31. Similarly, the third metal plate 33 has a third exposed portion 33b exposed from the side surface of the encapsulation resin 50 where the groove 51 is formed at the end portion facing the second metal plate 32. In addition, the fourth metal plate 34 has a fourth exposed portion 34b exposed from the side surface of the encapsulation resin 50 where the groove 51 is formed at the end portion facing the second metal plate 32. The first exposed portion 31b, the third exposed portion 33b, and the fourth exposed portion 34b face the second exposed portion 32b with the groove therebetween.

[0058] Next, a method for manufacturing the semiconductor device 100 will be described. First, the frame 30 is mounted on the first semiconductor chip 21a to the sixth semiconductor chip 26a. Figure 3 FIG. shows a state in which the frame 30 is mounted on the semiconductor chip. In the frame 30, the first metal plate 31 to the fourth metal plate 34, the first electrode terminal 35 to the fifth electrode terminal 39, and the plurality of signal terminals 40 are integrated via the connection portion 41.

[0059] The connection portion 41 has an external connection portion 41a and an internal connection portion 41b. The external connection portion 41a connects the first electrode terminal 35 to the fifth electrode terminal 39 and the plurality of signal terminals 40 to each other outside the package. The internal connection portion 41b connects the first metal plate 31 to the fourth metal plate 34 to each other inside the package. The connection portion 41 is also referred to as a guide plate member.

[0060] The first metal plate 31 to the fourth metal plate 34, the first electrode terminal 35 to the fifth electrode terminal 39, the plurality of signal terminals 40, and the connection portion 41 are formed of a conductive metal. The conductive metal is, for example, copper.

[0061] Here, the frame 30 is mounted in such a way that the first metal plate 31 is provided on the upper surface of the first semiconductor chip 21a, and the second metal plates 32 are provided on the upper surfaces of the second semiconductor chip 22a, the fifth semiconductor chip 25a, and the sixth semiconductor chip 26a. Similarly, the third metal plate 33 and the fourth metal plate 34 are respectively provided on the upper surfaces of the third semiconductor chip 23a and the fourth semiconductor chip 24a.

[0062] Next, a packaging process is performed. Figure 4 This is a diagram for explaining the packaging process. In the packaging process, the insulating substrate 10, the first semiconductor chip 21a to the sixth semiconductor chip 26a, and the frame 30 are covered with the packaging resin 50. The packaging resin 50 is formed of, for example, epoxy resin.

[0063] Next, a removal process is performed. Figure 5 This is a diagram for explaining the removal process. In the removal process, the packaging resin 50 and the internal connection portion 41b are cut simultaneously. As a result, together with the packaging resin 50, a cut is formed in the internal connection portion 41b, and a groove 51 is formed in the packaging resin 50. In the removal process, the first metal plate 31, the third metal plate 33, and the fourth metal plate 34 are separated from and insulated from the second metal plate 32 to form a circuit. In addition, in the removal process, the external connection portion 41a is also removed, and the first electrode terminals 35 to the fifth electrode terminals 39 and the plurality of signal terminals 40 are separated from each other. Cutting is performed, for example, using a cutter. Here, the width of the groove 51 can also be increased to ensure sufficient insulation distance.

[0064] In addition, it can also be as Figure 4 shown, the internal connection portion 41b is provided at a position higher than the portion adjacent to the internal connection portion 41b on the frame 30. The first metal plate 31 has a front end portion 31a extending upward at the end portion opposite to the second metal plate 32. The internal connection portion 41b connects the front end portion 31a to the second metal plate 32 at a position higher than the portion provided on the upper surface of the second conductive layer 12 in the first metal plate 31. In this case, the first exposed portion 31b is provided at a position higher than the portion provided on the upper surface of the second conductive layer 12 in the first metal plate 31.

[0065] According to this structure, when cutting the internal connection portion 41b, it is not necessary to cut deep into the insulating substrate 10, and damage to the insulating substrate 10 can be prevented. Therefore, the internal connection portion 41b can be easily cut, and the size of the semiconductor device 100 can be easily controlled. Therefore, the assembly property, mounting yield, and reliability can be improved. In addition, the groove 51 can be made shallow, so the processing time can be reduced. In addition, an external device can also be connected to the front end portion 31a to perform voltage detection.

[0066] In the present embodiment, the connecting portion 41 of the frame 30 can have a positioning function with respect to the jig. Thus, the first metal plate 31 to the fourth metal plate 34 can be arranged with high precision. Further, in a state where the first metal plate 31 to the fourth metal plate 34 are integrated via the connecting portion 41, resin encapsulation is performed, and then a groove 51 is provided in the encapsulating resin 50 to remove the connecting portion 41. Since the connecting portion 41 is cut in a state fixed by the encapsulating resin 50, it can be cut with high precision. In addition, displacement of the first metal plate 31 to the fourth metal plate 34 can be prevented. Therefore, the positioning accuracy of the metal plates inside the package can be improved.

[0067] Further, in the case of a structure in which the main electrode terminals are directly connected to the semiconductor element, when the semiconductor element operates under an overload, the main electrode terminals may be thermally interfered with by the semiconductor element. At this time, there is a concern that the temperature of the main electrode terminals approaches the use temperature limit of the product. In response to this, in the present embodiment, the first electrode terminal 35 to the fifth electrode terminal 39 are directly bonded to the first conductive layer 11 to the fifth conductive layer 15 close to the heat dissipation surface. Here, the heat dissipation surface is, for example, the back surface of the insulating substrate 10. Therefore, the temperature of the main electrode terminals can be suppressed.

[0068] Further, in the present embodiment, since the first electrode terminal 35 to the fifth electrode terminal 39 are directly bonded to the first conductive layer 11 to the fifth conductive layer 15, a housing may not be provided. Therefore, the semiconductor device 100 can also be miniaturized by a structure in which the main electrode terminals are insert-molded in the housing.

[0069] Figure 6 It is a cross-sectional view of the semiconductor device 200 according to the first modification of the first embodiment. Regarding the semiconductor device 200, a base plate 260 is provided on the back surface of the insulating substrate 10. Higher heat dissipation can be ensured by the base plate 260. In addition, warping of the semiconductor device 200 can be suppressed.

[0070] Figure 7 It is a cross-sectional view of the semiconductor device 300 according to the second modification of the first embodiment. Regarding the semiconductor device 300, the first conductive layer 311 and the second conductive layer 312 are conductive plates. Similarly, the third conductive layer to the fifth conductive layer are also formed of conductive plates. An insulating sheet 310b is provided on the back surfaces of the first conductive layer 311 and the second conductive layer 312. The insulating sheet 310b may also be an insulating plate. By using a conductive plate instead of a conductive pattern, heat dissipation can be improved. In addition, warping of the semiconductor device 300 can be suppressed.

[0071] Figure 8It is a cross-sectional view of the semiconductor device 400 according to the third modification of Embodiment 1. The semiconductor device 400 has a base plate 460 and a housing 470 provided above the base plate 460 for accommodating the insulating substrate 10. The position of the encapsulation resin 50 can be determined by the housing 470. Therefore, it is not necessary to prepare a mold for determining the position of the encapsulation resin 50.

[0072] Figure 9 It is a cross-sectional view of the semiconductor device 500 according to the fourth modification of Embodiment 1. In the semiconductor device 500, the side surface of the encapsulation resin 50 forming the groove 51 is covered with an insulating tape 552. That is, the first exposed portions 31b to the fourth exposed portions 34b are covered with the insulating tape 552. Insulation can be ensured by pasting the insulating tape 552.

[0073] In addition, not limited to the insulating tape 552, an insulating encapsulation material can also be applied. The encapsulation material provided in the groove 51 is, for example, epoxy resin or silicone gel. The encapsulation material is provided by potting.

[0074] Figure 10 It is a top view of the semiconductor device 100a according to the fifth modification of Embodiment 1. In the semiconductor device 100a, the first semiconductor chips 21 to 6th semiconductor chips 26 are provided instead of the first semiconductor chips 21a to 6th semiconductor chips 26a and the first diodes 21b to 6th diodes 26b. The first semiconductor chips 21 to 6th semiconductor chips 26 are RC (Reverse-conducting)-IGBTs. In addition, the first semiconductor chips 21 to 6th semiconductor chips 26 can also be MOSFETs, and freewheeling can be performed by body diodes.

[0075] In the semiconductor device 100a, as the first semiconductor chips 21 to 6th semiconductor chips 26, those that perform on / off and freewheeling with one chip are used. Thereby, the semiconductor device 100a can be miniaturized. In addition, usually when performing on / off and freewheeling with one chip, the thermal interference to the main electrode terminal becomes larger. The structure of the present embodiment can improve the heat dissipation and suppress the temperature of the main electrode terminal as described above. Therefore, it is particularly effective in the case of on / off and freewheeling with one chip such as the semiconductor device 100a.

[0076] In addition, at least one of the first semiconductor chips 21a to 6th semiconductor chips 26a and the first diodes 21b to 6th diodes 26b may be formed of a wide-bandgap semiconductor. The wide-bandgap semiconductor is silicon carbide, gallium nitride-based material, or diamond. It is usually difficult to expand the effective area of the wide-bandgap semiconductor. Therefore, by adopting the DLB structure capable of directly bonding the metal layer, the assembly property can be improved.

[0077] In addition, the switching element and the diode element, which are usually formed of a wide-bandgap semiconductor, have high breakdown voltage and high allowable current density. Therefore, the semiconductor device 100 can be further miniaturized.

[0078] In addition, in the present embodiment, the groove 51 extends along the arrangement direction of the first semiconductor chip 21a, the third semiconductor chip 23a, and the fourth semiconductor chip 24a. However, it is not limited thereto, and a plurality of grooves 51 may be respectively provided in the portions of the package sandwiched between the first metal plate 31 and the second metal plate 32, the portions sandwiched between the third metal plate 33 and the second metal plate 32, and the portions sandwiched between the fourth metal plate 34 and the second metal plate 32.

[0079] In addition, in the present embodiment, an example in which the semiconductor device 100 is a three-phase inverter is shown. However, it is not limited thereto, and the semiconductor device 100 may be any semiconductor device having a DLB structure. In addition, the semiconductor device 100 of the present embodiment has six semiconductor chips. The semiconductor device 100 is not limited thereto, as long as it has two or more semiconductor chips. The semiconductor device 100 may also be a single-phase inverter or the like.

[0080] These modifications can be appropriately applied to the semiconductor device and the manufacturing method of the semiconductor device according to the following embodiments. In addition, regarding the semiconductor device and the manufacturing method of the semiconductor device according to the following embodiments, since there are many common points with Embodiment 1, the description will be centered on the differences from Embodiment 1.

[0081] Embodiment 2.

[0082] Figure 11 FIG. is a diagram for explaining the manufacturing method of the semiconductor device 600 according to Embodiment 2. In the present embodiment, the structure of the frame 630 is different from that of Embodiment 1. Regarding the frame 630, the end portion of the first metal plate 31 facing the second metal plate 32 extends toward the upper surface of the encapsulation resin 50 and is exposed from the upper surface of the encapsulation resin 50. In addition, the end portion of the second metal plate 32 facing the first metal plate 31 extends toward the upper surface of the encapsulation resin 50 and is exposed from the upper surface of the encapsulation resin 50. The end portion of the first metal plate 31 and the end portion of the second metal plate 32 extend upward in parallel.

[0083] Similarly, the end portion of the third metal plate 33 facing the second metal plate 32 extends toward the upper surface of the encapsulation resin 50 and is exposed from the upper surface of the encapsulation resin 50. The end portion of the fourth metal plate 34 facing the second metal plate 32 extends toward the upper surface of the encapsulation resin 50 and is exposed from the upper surface of the encapsulation resin 50.

[0084] The internal connection portion 641b connects the portion of the first metal plate 31 exposed from the encapsulation resin 50 to the portion of the second metal plate 32 exposed from the encapsulation resin 50. Similarly, the internal connection portion 641b connects the portions of the third metal plate 33 and the fourth metal plate 34 exposed from the encapsulation resin 50 to the portion of the second metal plate 32 exposed from the encapsulation resin 50. In the embodiment, the internal connection portion 641b is provided at a position higher than the upper surface of the encapsulation resin 50. In the removal process, the internal connection portion 641b is cut without cutting the encapsulation resin 50.

[0085] Figure 12 It is a cross-sectional view of the semiconductor device 600 according to Embodiment 2. For the semiconductor device 600, the end portion of the first metal plate 31 is exposed from the upper surface of the encapsulation resin 50, thereby forming the first exposed portion 631b. In addition, the end portion of the second metal plate 32 is exposed from the upper surface of the encapsulation resin 50, thereby forming the second exposed portion 632b. Similarly, the end portions of the third metal plate 33 and the fourth metal plate 34 are exposed from the upper surface of the encapsulation resin 50, thereby forming the third exposed portion and the fourth exposed portion.

[0086] In the present embodiment, since the encapsulation resin 50 is not cut, resin debris that becomes a foreign object is not generated. Therefore, the reliability can be improved.

[0087] In the present embodiment, the metal plate is exposed from the upper surface of the encapsulation resin 50. However, the metal plate may also be exposed from the side surface of the encapsulation resin 50.

[0088] Embodiment 3.

[0089] Figure 13 It is a top view of the semiconductor device 700 according to Embodiment 3. The semiconductor device 700 has a housing 770. The housing 770 has a receiving portion 771 and an outer peripheral portion 772 surrounding the receiving portion 771. The receiving portion 771 houses the insulating substrate 10, the first semiconductor chips 21a to 6th semiconductor chips 26a, the first diodes 21b to 6th diodes 26b, and the first metal plate 31 to the fourth metal plate 34. The receiving portion 771 is encapsulated by the encapsulation resin 50. In Figure 13 For convenience, the encapsulation resin 50 is omitted. The encapsulation resin 50 is formed of, for example, epoxy resin or silicone gel.

[0090] The first electrode terminals 35 to the fifth electrode terminals 39 extend to the outside of the receiving portion 771. The first electrode terminals 35 to the fifth electrode terminals 39 and the signal terminal 40 are fixed to the outer peripheral portion 772.

[0091] The housing 770 has a fixing portion 773. The fixing portion 773 is provided in a strip shape along the arrangement direction of the first semiconductor chip 21a, the third semiconductor chip 23a, and the fourth semiconductor chip 24a. The fixing portion 773 is provided above the first metal plate 31, the third metal plate 33, and the fourth metal plate 34. The fixing portion 773 fixes the first metal plate 31, the third metal plate 33, and the fourth metal plate 34 to the housing 770.

[0092] In addition, the fixing portion 732a extends from the second metal plate 32 toward the outer peripheral portion 772. Through the fixing portion 732a, the second metal plate 32 is fixed to the housing 770. Thus, the first metal plate 31 to the fourth metal plate 34 are fixed to the housing 770.

[0093] In the present embodiment, the first metal plate 31 to the fourth metal plate 34 and the first electrode terminal 35 to the fifth electrode terminal 39 are integrated with the housing 770. Thus, the size of the semiconductor device 700 can be easily controlled. In addition, the mounting yield and reliability of the semiconductor device 700 can be improved. In addition, since there is no need for a removal process of the connecting portion 41, the semiconductor device 700 can be easily assembled.

[0094] In addition, when the first metal plate 31 to the fourth metal plate 34 are independent of the housing 770, generally, positioning by a jig is required for assembly. In the present embodiment, a jig for positioning is not required, and the assembly cost can be reduced.

[0095] In addition, the strip-shaped fixing portion 773 may be provided above the second metal plate 32 to fix the second metal plate 32 to the housing 770.

[0096] Figure 14 It is a top view of the semiconductor device 700a according to the first modification of Embodiment 3. For the semiconductor device 700a, the thicknesses of the first metal plate 31 to the fourth metal plate 34 are different from the thicknesses of the first electrode terminal 35 to the fifth electrode terminal 39. In the present embodiment, the first metal plate 31 to the fourth metal plate 34 and the first electrode terminal 35 to the fifth electrode terminal 39 are not connected by the connecting portion 41 but are provided separately. Therefore, the thicknesses of the first metal plate 31 to the fourth metal plate 34 and the thicknesses of the first electrode terminal 35 to the fifth electrode terminal 39 can be set separately.

[0097] For example, the first electrode terminal 35 to the fifth electrode terminal 39 may be formed thick, and the first metal plate 31 to the fourth metal plate 34 may be formed thin. Thus, large current conduction can be achieved through the thick first electrode terminal 35 to the fifth electrode terminal 39. In addition, the stress applied to the semiconductor chip can be reduced through the thin first metal plate 31 to the fourth metal plate 34.

[0098] Such a configuration is particularly effective when the semiconductor chip is formed of SiC. Generally, the Young's modulus of SiC is high, and the stress applied to the semiconductor chip from the first to fourth metal plates 31 to 34 tends to increase. In the case of the semiconductor device 700a, by making the first to fourth metal plates 31 to 34 thin, the stress can be reduced and the reliability can be improved.

[0099] Alternatively, the first to fourth metal plates 31 to 34 can be made thick. Thereby, the heat dissipation of the semiconductor chip can be improved.

[0100] Figure 15 It is a top view of the semiconductor device 800 according to the second modification of Embodiment 3. The housing 870 has a positioning portion 874. The positioning portion 874 has a plurality of openings 874a for accommodating and fixing the first to fourth metal plates 31 to 34. The shapes of the plurality of openings 874a respectively correspond to the shapes of the first to fourth metal plates 31 to 34. In the case of the semiconductor device 800, a jig for positioning is not required, and the assembly cost can be reduced.

[0101] In addition, the signal terminal connection portions of the first to sixth semiconductor chips 21a to 26a are exposed from the positioning portion 874 so that wire bonding with the signal terminals 40 can be achieved.

[0102] Figure 16 It is a top view of the semiconductor device 900 according to the third modification of Embodiment 3. The semiconductor device 900 has a housing 970. Each of the first to fourth metal plates 31 to 34 has a convex portion 931a to 934a extending toward the outer peripheral portion 972 of the housing 970. A plurality of concave portions 972a are formed in the outer peripheral portion 972 to be respectively engaged with the convex portions 931a to 934a.

[0103] By engaging the convex portions 931a to 934a with the plurality of concave portions 972a, the first to fourth metal plates 31 to 34 are positioned relative to the housing 970. In the case of the semiconductor device 900, a jig for positioning is not required, and the assembly cost can be reduced.

[0104] Figure 17 It is a diagram for explaining the manufacturing method of the semiconductor device 800 according to the fourth modification of Embodiment 3. In Figure 17 For convenience, the positioning portion 874 is omitted. The semiconductor device 800 can also be manufactured as follows. First, the first to fifth electrode terminals 35 to 39 and a plurality of signal terminals 40 are fixed to the outer peripheral portion 872 of the housing 870.

[0105] Next, an accommodation process is performed. In the accommodation process, the first semiconductor chip 21a to the sixth semiconductor chip 26a are accommodated in the accommodation portion 871. As a result, the first electrode terminal 35 is electrically connected to the back surface of the second semiconductor chip 22a. In addition, the second electrode terminal 36 is electrically connected to the back surfaces of the first semiconductor chip 21a, the third semiconductor chip 23a, and the fourth semiconductor chip 24a. In addition, the fourth electrode terminal 38 and the fifth electrode terminal 39 are each electrically connected to the back surfaces of the fifth semiconductor chip 25a and the sixth semiconductor chip 26a.

[0106] After the accommodation process, a connection process is performed. In the connection process, a plurality of signal terminal connection portions provided on the upper surfaces of the first semiconductor chip 21a to the sixth semiconductor chip 26a and the plurality of signal terminals are each connected by a wire. In Figure 17 it, as an example, the signal terminal connection portion 21c of the first semiconductor chip 21a is illustrated.

[0107] After the connection process, the first metal plate 31 to the fourth metal plate 34 are fixed to the housing 870. That is, the first metal plate 31 to the fourth metal plate 34 are each accommodated in the plurality of openings 874a. As a result, the upper surface of the first semiconductor chip 21a is electrically connected to the back surface of the second semiconductor chip 22a by the first metal plate 31. Similarly, the upper surfaces of the second semiconductor chip 22a, the fifth semiconductor chip 25a, and the sixth semiconductor chip 26a are connected to the upper surface of the third conductive layer 13 by the second metal plate 32. In addition, the upper surface of the third semiconductor chip 23a is electrically connected to the back surface of the fifth semiconductor chip 25a by the third metal plate 33, and the upper surface of the fourth semiconductor chip 24a is electrically connected to the back surface of the sixth semiconductor chip 26a by the fourth metal plate 34.

[0108] Regarding the semiconductor device 800, after the insulating substrate 10 is accommodated in the housing 870, the first metal plate 31 to the fourth metal plate 34 can be mounted on the housing 870. Therefore, after wire bonding between the semiconductor chip and the signal terminal 40 is performed, the first metal plate 31 to the fourth metal plate 34 can be mounted on the housing 870. As a result, the distance between the first metal plate 31 to the fourth metal plate 34 and the signal terminal connection portion of the semiconductor chip can be made narrow. The distance between the signal terminal connection portion 21c and the first metal plate 31 is, for example, less than or equal to 1 mm.

[0109] Regarding the semiconductor device 800, by reducing the distance between the signal terminal connection portion and the metal plate, the area of the main current conduction portion of the semiconductor chip can be enlarged. Therefore, the current density can be increased. In addition, the manufacturing method of the fourth modification example can also be applied to the semiconductor device 900.

[0110] In addition, the technical features described in each embodiment can also be used in appropriate combination.

[0111] Description of reference numerals

[0112] 100, 100a, 200, 300, 400, 500, 600, 700, 700a, 800, 900 semiconductor devices, 10b insulating layer, 11 to 15 first to fifth conductive layers, 21 to 26, 21a to 26a first to sixth semiconductor chips, 21c signal terminal connection portion, 30, 630 frames, 31 to 34 first to fourth metal plates, 31b, 631b first exposed portions, 32b, 632b second exposed portions, 33b third exposed portion, 34b fourth exposed portion, 35 to 39 first to fifth electrode terminals, 40 signal terminals, 41 connection portion, 42 wire, 50 encapsulation resin, 51 groove, 552 insulating tape, 470, 770, 870, 970 housings, 771, 871 receiving portions, 772, 872, 972 outer peripheral portions, 874a opening, 931a to 934a convex portions, 972a concave portion

Claims

1. A semiconductor device, characterized in that, comprising: a first semiconductor chip; a second semiconductor chip; a first metal plate disposed on the upper surface of the first semiconductor chip; a second metal plate disposed on the upper surface of the second semiconductor chip; and a packaging resin that covers the first semiconductor chip, the second semiconductor chip, the first metal plate, and the second metal plate, at the packaging resin, a groove extending downward from the upper surface of the packaging resin is formed between the first metal plate and the second metal plate, the first metal plate has a first exposed portion exposed from the side surface of the packaging resin where the groove is formed at an end opposite to the second metal plate, the second metal plate has a second exposed portion exposed from the side surface of the packaging resin where the groove is formed at an end opposite to the first metal plate.

2. The semiconductor device according to claim 1, wherein it has a first electrode terminal that extends outside the packaging resin, is disposed separately from the first metal plate, and is electrically connected to the back surface of the second semiconductor chip, the first metal plate electrically connects the upper surface of the first semiconductor chip to the back surface of the second semiconductor chip.

3. The semiconductor device according to claim 1, wherein comprising: an insulating layer; a first conductive layer disposed above the insulating layer, and the first semiconductor chip is disposed on the upper surface of the first conductive layer; a second conductive layer disposed above the insulating layer, and the second semiconductor chip is disposed on the upper surface of the second conductive layer; a third conductive layer disposed above the insulating layer; a first electrode terminal disposed on the upper surface of the second conductive layer and extending outside the packaging resin; a second electrode terminal disposed on the upper surface of the first conductive layer and extending outside the packaging resin; and a third electrode terminal disposed on the upper surface of the third conductive layer and extending outside the packaging resin, the first metal plate connects the upper surface of the first semiconductor chip to the upper surface of the second conductive layer, the second metal plate connects the upper surface of the second semiconductor chip to the upper surface of the third conductive layer, the first electrode terminal is disposed on the upper surface of the second conductive layer, separately from the first metal plate and the second semiconductor chip, the second electrode terminal is disposed separately from the first semiconductor chip, the third electrode terminal is disposed separately from the second metal plate.

4. The semiconductor device according to claim 3, wherein comprising: a fourth conductive layer and a fifth conductive layer disposed above the insulating layer; a third semiconductor chip and a fourth semiconductor chip disposed on the upper surface of the first conductive layer; a fifth semiconductor chip disposed on the upper surface of the fourth conductive layer; a sixth semiconductor chip disposed on the upper surface of the fifth conductive layer; a third metal plate that connects the upper surface of the third semiconductor chip to the upper surface of the fourth conductive layer; and a fourth metal plate that connects the upper surface of the fourth semiconductor chip to the upper surface of the fifth conductive layer, The second metal plate connects the upper surfaces of the fifth semiconductor chip and the sixth semiconductor chip to the upper surface of the third conductive layer. The third metal plate has a third exposed portion exposed from the side surface of the encapsulation resin forming the groove. The fourth metal plate has a fourth exposed portion exposed from the side surface of the encapsulation resin forming the groove. The third exposed portion and the fourth exposed portion face the second exposed portion across the groove.

5. The semiconductor device according to claim 4, wherein: The first semiconductor chip, the third semiconductor chip, and the fourth semiconductor chip are arranged on the upper surface of the first conductive layer. The groove extends along the arrangement direction of the first semiconductor chip, the third semiconductor chip, and the fourth semiconductor chip.

6. The semiconductor device according to any one of claims 3 to 5, wherein: The first exposed portion is provided at a position higher than the portion provided on the upper surface of the second conductive layer in the first metal plate.

7. The semiconductor device according to any one of claims 1 to 5, wherein: The side surface of the encapsulation resin forming the groove is covered with an insulating tape or an encapsulation material.

8. A semiconductor device, characterized in that, Having: A first semiconductor chip; A second semiconductor chip; A first metal plate disposed on the upper surface of the first semiconductor chip; A second metal plate disposed on the upper surface of the second semiconductor chip; And An encapsulation resin that covers the first semiconductor chip, the second semiconductor chip, the first metal plate, and the second metal plate. The end portion of the first metal plate facing the second metal plate extends toward the upper surface of the encapsulation resin and is exposed from the upper surface of the encapsulation resin. The end portion of the second metal plate facing the first metal plate extends toward the upper surface of the encapsulation resin and is exposed from the upper surface of the encapsulation resin.

9. The semiconductor device according to any one of claims 1 to 5, 8, wherein: At least one of the first semiconductor chip or the second semiconductor chip is formed of a wide-bandgap semiconductor.

10. The semiconductor device according to claim 9, wherein: The wide-bandgap semiconductor is silicon carbide, gallium nitride-based material, or diamond.

11. A method for manufacturing a semiconductor device, wherein: A frame integrating the first metal plate and the second metal plate via a connection portion is mounted in such a manner that the first metal plate is disposed on the upper surface of the first semiconductor chip and the second metal plate is disposed on the upper surface of the second semiconductor chip. The frame, the first semiconductor chip, and the second semiconductor chip are covered with an encapsulation resin. Together with the encapsulation resin, a cut is formed in the connection portion and a groove is formed in the encapsulation resin so that the first metal plate and the second metal plate are separated.

12. The method for manufacturing a semiconductor device according to claim 11, wherein: The connection portion is provided at a position higher than the portion adjacent to the connection portion in the frame.

Images