fast blocking switch

Abstract

A fast blocking switch is disclosed. The fast blocking switch (200) includes, for example, an energy storage device (212), a first power switch (216), and a second power switch (218). The energy storage device stores charge for fast activation of the switch. The first switch (216) is operable to couple an input current to an output OUT in response to a potential supplied by the stored charge coupled to a control terminal of the first switch (216). The second switch (220) is operable to couple a limited input current to the output OUT in response to a potential supplied by the stored charge coupled to a control terminal of the second switch (220).

Description

[0001] This application is a divisional application of Chinese Patent Application No. 201610133496.9, filed on March 9, 2016, entitled "Fast Blocker Switch". BACKGROUND

[0002] Many integrated circuit applications are implemented in integrated systems that include multiple power supplies. In some of these applications, two or more such power supplies are arranged in a "wire-OR" configuration, in which at least one voltage output of each power supply is coupled together to provide a voltage output that can supply more current than any one of the participating power supplies can supply. During operation of the integrated system, different amounts of current are required at different points in time. At various points in time, the required current can be greater or less than the amount provided by a given participating power supply. Accordingly, during operation at different points in time, participating power supplies are turned off (to conserve power consumption) or turned on (to provide more power) as needed. Blocker circuitry is combined with the participating power supplies to minimize voltage disturbances (e.g., which can adversely affect operation of the integrated system) that occur when the participating power supplies are turned on and off. However, such blocker circuitry often increases the cost, complexity, and power consumption of the integrated system. SUMMARY

[0003] The above problems can be solved using a fast blocker switch, which includes, for example, an energy storage device, a first power switch, and a second power switch. The energy storage device stores charge for fast activation of the switch. The first switch is operable to couple input current to an output terminal in response to a potential supplied by the stored charge coupled to a control terminal of the first switch. The second switch is operable to couple a limited amount of input current to the output terminal in response to a potential supplied by the stored charge coupled to a control terminal of the second switch; wherein the second switch is different from the first switch. The control terminal of the second switch is also operable to provide (e.g., additional) charge to the control terminal of the first switch (e.g., as a charge storage element) (e.g., for faster turn-on of the first switch).

[0004] It is to be understood that the submitted summary is not intended to be used to limit or otherwise define the scope or meaning of the claims. Further, the summary is not intended to identify key or essential features of the claimed subject matter, nor is it intended to be used to aid in determining the scope of the claimed subject matter. BRIEF DESCRIPTION OF DRAWINGS

[0005] According to example embodiments of the present disclosure, Figure 1 An illustrative electronic device is shown.

[0006] According to example embodiments of the present disclosure, Figure 2 A schematic diagram of a fast blocker switch.

[0007] According to example embodiments of the present disclosure, Figure 3 is a pin-out diagram for a fast break switch.

[0008] According to example embodiments of the present disclosure, Figure 4 is a block diagram of two line- or fast break switches. DETAILED DESCRIPTION

[0009] The following discussion is presented to aid in the understanding of various embodiments of the application. Although one or more of these embodiments can be preferred, the disclosed embodiments should not be construed as limiting the scope of the present disclosure, including the claims. In addition, those skilled in the art will understand that the description given herein is intended as an example only and is not intended to limit the scope of the application, including the claims, in any way.

[0010] Throughout the following description- and claims- specific terminology is used. As one skilled in the art will appreciate, multiple names can be used to refer to an element or system. Accordingly, the use of a name herein does not necessarily refer to a different element than another name that is functionally identical. In addition, a system can be a subsystem of another system. In the following discussion and in the claims, the terms "including" and "comprising" are used in an open-ended fashion, and thus should be interpreted to mean "including, but not limited to... Also, the term "coupled" or "coupling" (or the like) is intended to mean either an indirect or direct electrical connection. Thus, if a first device is coupled to a second device, that connection can be achieved by a direct electrical connection, or by an indirect electrical connection via other devices and connections. The term "portion" can mean all or less than all of a portion. The term "calibration" can include the meaning of the word "test". The term "input" can mean the source or drain of a PMOS (P-type metal oxide semiconductor) or NMOS (N-type metal oxide semiconductor) transistor (or even a control input, such as a gate, as context dictates). The term "pulse" can mean a portion of a waveform, such as a "square" or "sawtooth" waveform.

[0011] According to example embodiments of the present disclosure, Figure 1 An illustrative computing device 100 is shown. For example, the computing device 100 is, or is incorporated into, or is coupled (e.g., connected) to an electronic system 129, such as a computer, an electronic control "box" or display, a communication device (including a transmitter or receiver), or any type of electronic system operable to process information.

[0012] In some embodiments, the computing device 100 includes a monolithic unit or system on a chip (SoC) that includes control logic such as a CPU 112 (central processing unit), memory 114 (e.g., random access memory (RAM)), and a power supply 110. The CPU 112 can be, for example, a CISC-type (complex instruction set computer) CPU, a RISC-type CPU (reduced instruction set computer), a MCU-type (microcontroller unit), or a digital signal processor (DSP). The memory 114, which can be a memory such as an on-processor cache, off-processor cache, RAM, flash memory, or disk storage, stores one or more software applications 130 (e.g., embedded applications) that perform any suitable functions associated with the computing device 100 when executed by the CPU 112.

[0013] The CPU 112 includes memory and logic that stores information that is frequently accessed from the memory 114. The computing device 100 is often controlled by a user using a UI (user interface) 116 that provides output to and receives input from the user during execution of the software applications 130. Output is provided using a display 118, indicator lights, speakers, vibration, and the like. Input is received using audio and / or video input (using, for example, speech or image recognition), as well as electrical and / or mechanical devices such as a keypad, switches, proximity detectors, gyroscopes, accelerometers, and the like.

[0014] The CPU 112 and the power supply 110 are coupled to an I / O (input-output) port 128 that provides an interface configured to receive input from (and / or provide output to) a network device 131. The network device 131 can include any device (including test equipment) capable of communicating with the computing device 100 point-to-point and / or networked. The computing device 100 is typically coupled to external equipment and / or computing devices, including tangible, persistent media (e.g., flash memory) and / or wired or wireless media. These and other input and output devices are selectively coupled to the computing device 100 through external devices that are connected with wireless or wired connections. The memory 114 is accessible, for example, through the network device 131. The CPU 112, the memory 114, and the power supply 110 are all optionally coupled to an external power source (not shown) that is configured to receive power from a power source (e.g., a battery, a solar cell, a "live" power cord, an inductive field, a fuel cell, a capacitor, and the like).

[0015] The computing device 100 includes a power module 138. The power module 138 includes at least two power sources, such as power sources 110 and 111. The power sources 110 and 111 use fast block switches (fast B-gates) 140 and 141 in a line-or configuration arrangement having at least one voltage output, where each output is coupled (e.g., connected) to one another. The fast block switches are arranged to provide fast turn-on of blocking FETs to minimize voltage droop at the voltage output that initially occurs when the outputs of the power sources involved are coupled together. The fast block switches are turned on quickly using charge selectively coupled from an internal capacitor reservoir. In one embodiment, the use of one or more internal capacitors avoids the costs, pin outs, complexity, and size associated with external capacitors.

[0016] The power sources 110 and 111 include power generation and control elements for generating power to enable the computing device 100 to run the software application 130. For example, the power sources 110 and 111 provide one or more power switches, each of which can be independently controlled, that are operable to provide power at different voltages to different elements of the computing device 100. The power sources 110 and 111 are optionally in the same physical assembly as one another.

[0017] The computing device 100 is optionally operable in a variety of power- saving modes, such as a sleep mode, in which various voltages of the power sources 110 and 111 are supplied (and / or turned off) in response to a power control signal. The power control signal is generated by (or in response to) a power controller (e.g., the CPU 112) in accordance with system operating requirements. In response to the power control signal, the power sources 110 and 111 are able to be individually and selectively turned on or off.

[0018] In accordance with embodiments of the present disclosure, Figure 2 is a schematic diagram of a fast block switch. The fast block switch 200 is a fast block switch such as the fast block switch 140 or 141. The fast block switch 200 includes an internal charge pump 210, an internal capacitor 212, a small internal charge pump 214, an NMOS block switch 216, an NMOS current limit switch 218, a B-gate switch 220, an H-gate switch 222, an inverter 226, a B-gate disconnect switch 224, a monoshot (e.g., monoshot pulse generator) 228, and an H-gate disconnect switch 230. Such included elements are typically formed on a common substrate.

[0019] The fast block switch 200 is operable to store charge in one or more internal capacitors and to apply the stored charge to the gates of the NMOS block switch 216 and the NMOS current limit switch 218 when the switches 216 and 218 are energized (e.g., closed). The stored charge quickly helps overcome the relatively high source-to-gate capacitance associated with the NMOS block switch 216. (The term "switch" as used herein includes the meaning of a device operable to limit a variable current flow, including a device that generates a continuous variable current flow in response to a control signal).

[0020] In operation, the fast block switch 200 receives power at the node IN from an engaged power source. The blocked power source is, for example, a voltage output that is blocked by the NMOS block switch 216 of the fast block switch 200. In an initial state (e.g., at the time of power blockage), the NMOS block switch 216 is closed (e.g., in a blocking state) in response to the closure of the B-Gate-Off switch 224. The NMOS current limit switch 218 is opened (e.g., in a non-conducting state) in response to the small internal charge pump 214 pulling up the control terminal 218 and the H-Gate-Off switch 230 opening. Thus, the fast block switch 200 supplies power at the node OUT (e.g., only) through the body diode of the NMOS block switch 216 and the engaged power source is blocked.

[0021] The power received at the node IN is used by the fast block switch 200 to power the internal charge pump 210. When powered, the internal charge pump 210 provides charge to charge the internal capacitor 212 and provides current to power the small internal charge pump 214. The small internal charge pump 214 provides a relatively small current that, if accumulated, opens (and / or keeps open) the NMOS current limit switch 218 (e.g., slowly).

[0022] When the blocked power source is "brought on-line" (e.g., has power coupled to the node OUT), the Open B-Gate (Open BGATE) signal is asserted in response to a power control signal (e.g., the power control signal is generated in response to system power requirements). In response to the assertion of the Open B-Gate signal, the B-Gate switch 220 is closed, which couples the charge stored by the internal capacitor 212 to the gate of the NMOS block switch 216. The inverter 226 de-asserts the Open B-Gate signal and opens the B-Gate-Off switch 220 in response. However, because the internal capacitor 212 is relatively small (e.g., compared to the high source-to-gate capacitance associated with the NMOS block switch 216), the internal capacitor 212 does not store enough charge by itself to open the NMOS block switch 216 (e.g., even when the switch 220 is open).

[0023] In response to the assertion of the Open B-Gate signal, the one-shot 228 holds (e.g., closes and holds) the H-Gate switch 222 in a closed state for a selected time period by generating a pulse having a transient active time period of the selected time period. Upon expiration of the selected time period, the one-shot 228 opens the H-Gate switch 222. When the H-Gate switch 222 is closed, the charge stored in the source-to-gate region of the NMOS current limit switch 218 helps overcome the capacitance associated with the source-to-gate region of the NMOS block switch 216, such that the NMOS block switch 216 can turn on more quickly.

[0024] The charge supplied by the internal NMOS current limit switch 218 is applied to the gate of the NMOS block switch 216 at a rate (e.g., current level) that is substantially higher than the current supplied by the small internal charge pump 214. In one embodiment, the gate of the NMOS block switch 216 is charged at a rate that is at least about 10 times the rate at which the small internal charge pump 214 charges the gate of the NMOS current limit switch 218.

[0025] According to example embodiments of the present disclosure, Figure 3 is a pin-out diagram of a fast block switch. The fast block switch 300 is a fast block switch, such as the fast block switch 200. The fast block switch 300 includes a substrate 302 on which the block switch 300 is formed. The fast block switch 300 includes pins 310, 312, 314, 316, 318, 320, 322, 324, 326, 328, 330, and 332. Such pins each optionally include a plurality of terminals arranged in parallel.

[0026] The pin 310 (IN) is coupled to an output of a power supply and is arranged to receive current from the power supply. The number of amperes (e.g., amount of current) provided by the participating power supply is detected by a sensor 340, and an indication of the amperes is communicated to a controller 346. The controller 346 is arranged to control a block switch 342 and a current limit switch 344. The switches 342 and 344 are arranged in series (e.g., with the drain of the switch 342 connected to the drain of the switch 344) and work together to block and / or limit current (received at the pin 310) coupled to the pin 322 (OUT).

[0027] Each pin (e.g., the pins 310 and 322) is optionally a plurality of physical pins arranged in parallel. For example, the pins 310 and 322 each include 4 physical pins arranged in parallel, such that, for example, the resistive effects of a high current path (e.g., including any of pins, terminals, pads, traces, wires, nodes, lines, etc.) are minimized.

[0028] Pin 310 (IN) is operable to support internal under-voltage lockout (UVLO) circuitry. When the IN terminal voltage drops below an internal UVLO threshold (V UVR ), control circuitry (e.g., including controller 346) is arranged to disable the fast block switch. The internal UVLO threshold typically has a hysteresis of 115 mV.

[0029] Pin 312 is a terminal used to program the enable and adjust under-voltage lockout (EN / UVLO) feature, where the voltage on pin 312 (e.g., in the range of approximately 0.6 < V EN / UVLO <1.0 volts) turns off (e.g., opens) the internal MOSFET, which disconnects (e.g., blocks) pin 310 (IN) from pin 322 (OUT). Further, the application of a voltage below 0.6 V turns off the fast block switch 300, so the fast block switch 300 enters a shutdown mode. During shutdown, the quiescent current (I Q ) is less than about 20 uA (microamperes), so power loss is minimized.

[0030] Pin 312 (EN / UVLO) is programmable for "low under-voltage lockout" operation by using an external resistor divider to separate the supply to EN / UVLO and GND. Thus, pin 312 has multiple functions and can be used to operate as, for example, an under-voltage monitor, as well as to facilitate fast shutdown of the internal FETs in the event of a power failure or under-voltage event. In such events, the fast block switch 300 also asserts a fault (FLTb) flag, which is presented at pin 328.

[0031] Thus, the fast block switch 300 is suitable for a power line- or application (e.g., an application that combines current from separate power generation supplies), where the output pins of multiple (e.g., "N", N is an integer greater than 1) fast block switches (e.g., fast block switch 300) are coupled together. The current through a particular fast block switch is communicated to an external controller (e.g., formed on a substrate external to substrate 302), which is operable to individually control each of the multiple fast block switches (e.g., see below Figure 4 ).

[0032] The fast block switch 300 is operable to control inrush current to a load (e.g., coupled to the output pin 322) after plugging a circuit card into a live backplane or other "hot" power supply. Limiting inrush current (e.g., via the current limit switch 344) is to limit voltage droop of the supply voltage of the backplane, thereby avoiding "brownouts" and system power induced auto-restart. Likewise, controlling slew rate (e.g., first derivative of time for the output voltage: dV / dT) helps to minimize conducted and radiated interference. For systems that present a load upon start-up, the current is limited to a maximum current limit set by the current limit resistor, which is chosen according to the particular application. The current limit resistor is coupled externally between the ILIM (current limit) pin 326 and ground.

[0033] High inrush currents often occur upon "hot plug" (e.g., plugging a device into a system while the system is in a powered up state). The fast block switch 300 is operable to regulate inrush current according to a programmable output slew rate. For example, an external capacitor connected between pin 318 (dV / dT) to the ground pin 320 (GND) defines the slew rate of the output voltage upon power up. The slew rate at start-up can be expressed as:

[0034]

[0035] where I dVdT = 1 μA (typical), and GAIN dVdT is the gain (e.g., ratio 12) of dV / dT to the output.

[0036] The total ramp time (T dVdT ) of the output voltage V OUT from 0 volts to V IN can be calculated according to the following equation:

[0037] T dVdT = 8.3*10 4 *V IN *C dVdT (2)

[0038] where C is the external capacitor coupled to pin 318 (dV / dT). The dV / dT terminal (pin 318) is optionally left unconnected (e.g., "floating left") to obtain a predetermined slew rate of the output V OUT . When pin 318 is left floating, the fast block switch 300 assumes a predetermined internal ramp rate of 12 V / ms for the output voltage (V OUT ).

[0039] The fast block switch 300 monitors the load current by sensing the voltage across an internal sense resistor 340 (e.g., a resistor). The current through the FETs of switches 342 and 344 is monitored during start-up operation and normal operation. During an (e.g., potential and / or actual) overcurrent event, the fast block switch 300 keeps the current level below the current limit threshold (I ILIM ) programmed by an external resistor R OL ) coupled to the ILIM pin 326). The current limit is determined according to the following equation:

[0040]

[0041] In the event that the current exceeds the overload current limit (IOL), a timer is optionally used to extend the time of the fast block switch operation.

[0042] The fast block switch 300 includes an input overvoltage protection circuit that protects the system (e.g., including the fast block switch 300) during overvoltage conditions. A first end of a resistor is coupled to the overvoltage protection (OVP) pin 314 end that is used to program the fast block switch 300 overvoltage level. A voltage greater than V OVPR is applied to the pin 314, thereby turning off the FET switches 342 and 344. An internal resistor divider is coupled between the supply and GND, and has a center node coupled to the pin 314, the internal resistor divider programs the overvoltage threshold and provides overvoltage protection for any downstream loads. When the overvoltage level is not programmed, the pin 314 is tied to GND.

[0043] The fault response (FTLb) pin 328 is an open drain output that is asserted (active low) under under-voltage, over-voltage, reverse voltage / or current, and thermal shutdown conditions. Optionally, the pin 328 is asserted for overcurrent conditions when the overcurrent condition exceeds the length of the fault timeout period (TCBdly). The pin 328 is held asserted until the fault condition is cleared and the device resumes normal operation.

[0044] The fast block switch 300 includes a current monitoring and reporting function. The fast block switch 300 generates a scaled analog output current in response to the sensed amount of current through the switches 342 and / or 344. The output of pin 324 (IMON) originates from a current source arranged to be proportional to the current flowing from IN to OUT. Thus, the output of pin 324 is used by external power supply control logic to monitor the current flowing through the system.

[0045] An external pull-down resistor (R IMON), which is connected from the IMON terminal to GND, is used to programmably scale the size of the current limit. The voltage generated at this terminal (VIMON) is proportional to the current flowing through switches 342 and 344. The maximum voltage range (V IMONMAX ) is limited to VIN below 2.2V to ensure linear output and should not exceed 6.5V as the maximum value in absolute. The maximum value of the RIMON resistor is determined according to the following equation:

[0046]

[0047] When V IN <8.7V, and

[0048]

[0049] When V IN >8.7V, and where GAIN IMON is a gain factor determined according to the ratio of the current at the indicated pin 324 (IMON) to the current at the output pin (IOUT) 322.

[0050] The output voltage at pin 324 is calculated from the following equation:

[0051] V IMON = I OL * GAIN IMON * R IMON (6)

[0052] where R IMON is a pull-down resistor used to programmably scale the size of the current limit as described above.

[0053] The "power good threshold" (PGTH) pin 332 is coupled to the positive input of the "power good" comparator and can be coupled to the input signal to monitor the input or output of the fast block switch 300. The negative input of the power good comparator is coupled to an internal reference voltage of 0.99V (V PGTHR ) to verify the voltage of the signal coupled to pin 332. The power good comparator has an output coupled to the "power good" (PGOOD) pin 330. Pin 330 provides the power good comparator verification indication to the "downstream" dc-dc converter and system monitoring circuitry for coordination of status and control interface.

[0054] Pin 330 (PGOOD) provides an open drain high level active signal that can be used to indicate the status of the monitored signal to the downstream unit. When the internal gate signal is off and the voltage on pin 332 (PGTH) is higher than the internal reference (V PGTHR) the pin 330 is asserted high. The PGOOD signal has a deglitch time incorporated to ensure that the gate is sufficiently boosted before a heavy load (e.g., by a downstream power converter) is coupled to the pin 322 (OUT). The delay of the rising edge of the PGOOD signal is determined according to the following equation:

[0055] T PGOOD_Degl = 3.5 * 10 6 *C dVdT (7)

[0056] where C dVdT is the value of the capacitor coupled to the dV / dT pin. When the result of equation (7) is less than the default value T PGOODDegl , the default value is used.

[0057] As discussed above, all of the OUT terminals of the pins 322 are connected together and to a load. The voltage at the pin 322 (OUT) in the ON state depends on the total ON resistance of the internal MOSFETs 342 and 344 (R ON ) which is defined according to the following equation:

[0058] V OUT = V IN -(R ON *I OUT ) (8)

[0059] The ground (GND) pin 320 is normally the maximum negative voltage in a fast block switch and is used as a reference point when other voltages are measured.

[0060] According to example embodiments of the present disclosure, Figure 4 is a block diagram of a configuration of two line- or fast block switches. The configuration 400 includes a fast block switch 410 and a fast block switch 420 arranged in a line- or configuration, where each OUT terminal is coupled together and to a system load 430 and / or a capacitive load C OUT .

[0061] The fast block switch 410 has an input (IN) coupled to the output of a primary power supply, while the fast block switch 420 has an input (IN) coupled to the output of a secondary power supply. When both switches 410 and 420 are in the ON state, both the primary power supply and the secondary power supply are involved in providing power.

[0062] The fast block switch 410 is programmed and configured using external components C VIN , R1, R2, R3, and R5, C dVdT , R ILIM , and R IMON , while the fast block switch 420 is programmed and configured using external components C VIN, R4, C dVdT , and R ILIM The fast block switch 420 is programmed and configured.

[0063] According to the block FET control mode, the output FLTb of the fast block switch 410 is coupled to the input ENBLKb of the fast block switch 420. Such configuration provides independent ON / OFF control of the internal block FETs (e.g., 342 and 344). The input ENBLKb is used in such power-multiplexing applications to smoothly switch between the primary and secondary (e.g., auxiliary) supply (and vice versa). The input ENBLKb is a low active with internal pull-down. A high value shown at the input ENBLKb turns off the block FET, which prevents reverse current conduction (from OUT to IN) through the fast block switch 420. When the block FET is disabled (e.g., in the OFF state), the overload current limit is set to 50% of the current limit determined by R ILIM .

[0064] The fast reverse comparator optionally controls the internal block FET. When the forward voltage drops V IN-OUT below 100 mV, the block FET is turned on (typically) in less than 4 us, and when V IN-OUT falls below -10 mV, it is turned off (typically) in 1 us. When the block FET is turned on, there is a momentary inrush current draw as the MOSFET turns on and charges the bus capacitance (e.g., C OUT ), or the input supply. In addition, the block FET can be independently turned on or off through the ENBLKb pin.

[0065] In an N+1 configuration, multiple fast block switches (e.g., 410 and 420) can be used to combine multiple power supplies to a common bus. To achieve higher capacity, redundancy, or both, an N+1 power supply configuration is used in which multiple power supplies are connected in parallel. If N power supplies are used to drive a load, adding one or more additional identical units in parallel allows the load to continue to operate in the event of failure of any one of the N power supplies. The fast block switch emulates the function of a diode and provides protection under hot plug, over voltage, under voltage, over current, and short circuit conditions, such as rail isolation.

[0066] In one embodiment, a controller (e.g., such as a microcontroller or digital signal processor) is used to control one or more properties of the fast blocking switch. Some of the variables are software programmable, which allows for more flexibility in implementing the disclosed control schemes and provides enhanced ability to adaptively adjust to dynamically changing conditions to optimize system performance. Other variables can be programmed during manufacturing (e.g., to compensate for many characteristics) by trimming a trimmable resistor to increase operational stability and accuracy.

[0067] In various embodiments, the above-described elements can be implemented in hardware or software, internally or externally, and share functionality with other modules and components as described herein. For example, the switching portion of the fast blocking switch can be implemented externally to the device and / or substrate on which the switch controller is formed.

[0068] The various embodiments described above are provided by way of illustration only and should not be construed to limit the appended claims in any manner. Those skilled in the art will readily recognize various modifications and changes that can be made without departing from the spirit and scope of the claims that follow.

Claims

1. A switching circuit comprising: an input terminal; an output terminal; an energy storage device configured to store a first charge; a first switch coupled between the input terminal and the output terminal, the first switch including a control terminal coupled to the energy storage device to receive the first charge; a second switch coupled between the input terminal and the output terminal, the second switch configured to be turned on in response to a first current being provided to a control terminal of the second switch to store a second charge; and a gate switch coupled between the control terminal of the first switch and the control terminal of the second switch, wherein the gate switch is configured to be turned on to provide the second charge stored in the second switch from the control terminal of the second switch to the control terminal of the first switch, the second charge being added to the first charge to turn on the first switch.

2. The circuit of claim 1, wherein the first switch and the second switch are arranged in series.

3. The circuit of claim 1, further comprising: a first charge pump coupled between the input terminal and the energy storage device and configured to store the first charge to the energy storage device based on an input current received at the input terminal; and a second charge pump coupled between the first charge pump and the control terminal of the second switch and configured to store the second charge to the second switch based on a second current received from the first charge pump, wherein the second charge pump is configured to provide the first current to the control terminal of the second switch, the first current being less than the second current. the second switch is configured to store the second charge at a first rate, and the second charge is provided to the control terminal of the first switch at a second rate higher than the first rate.

5. The circuit of claim 1, wherein the input terminal, the output terminal, and the first switch and the second switch are formed in a same substrate.

4. The circuit of claim 1, wherein, 6. The circuit of claim 5, wherein the substrate is an integrated circuit substrate.

7. The circuit of claim 5, wherein the energy storage device is a capacitor formed in the same substrate.

8. A switching circuit comprising: a first switch including a control terminal to receive a first charge from an energy storage device; and a second switch configured to be turned on in response to a first current being provided to a control terminal of the second switch to store a second charge; and a gate switch coupled between the control terminal of the first switch and the control terminal of the second switch, wherein the gate switch is configured to be turned on to provide the second charge stored in the second switch from the control terminal of the second switch to the control terminal of the first switch, the second charge being added to the first charge to turn on the first switch. ​ ​ ​ ​ 9. The circuit of claim 8, comprising a controller configured to couple the energy storage device to the control terminal of the first switch to provide the first charge to the control terminal of the first switch.

10. The circuit of claim 9, wherein the controller is configured to control the gate switch to couple the control terminal of the second switch to the control terminal of the first switch for a period of time in response to a signal to turn on the first switch.

11. The circuit of claim 9, wherein the controller comprises a one-shot circuit configured to generate a pulse to temporarily provide the second charge stored in a source-to-gate capacitance of the second switch to the control terminal of the first switch so that the first switch turns on faster.

12. An electronic system comprising: a system output; a first power supply; and a first switch circuit comprising: a first input and a first output, the first output coupled to the system output; a first energy storage device configured to store a first charge; a first switch coupled between the first input and the first output, the first switch comprising a control terminal coupled to the first energy storage device to receive the first charge; a second switch coupled between the first input and the first output, the second switch configured to turn on in response to a first current being provided to a control terminal of the second switch to store a second charge; and a gate switch coupled between the control terminal of the first switch and the control terminal of the second switch, wherein the gate switch is configured to be turned on to provide the second charge stored in the second switch from the control terminal of the second switch to the control terminal of the first switch, the second charge added to the first charge to turn on the first switch.

13. The system of claim 12, wherein the first switch and the second switch are arranged in series.

14. The system of claim 13, wherein the first switch and the second switch are field effect transistors (FETs), and wherein the first switch circuit further comprises: a first charge pump coupled between the first input and the energy storage device and configured to store the first charge to the energy storage device based on an input current received at the first input; and a second charge pump coupled between the first charge pump and the control terminal of the second switch and configured to store the second charge to the second switch based on a second current received from the first charge pump, wherein the second charge pump is configured to provide the first current to the control terminal of the second switch, the first current less than the second current.

15. The system of claim 12, comprising: a second power supply; and a second switch circuit comprising: a second input and a second output, the second output coupled to the system output; a second energy storage device configured to store a third charge; a third switch coupled between the second input terminal and the second output terminal, the third switch including a control terminal coupled to the second energy storage device to receive the third charge; and a fourth switch coupled between the second input terminal and the second output terminal, the fourth switch configured to turn on in response to a third current being provided to a control terminal of the fourth switch and to provide a fourth charge to the control terminal of the third switch, the fourth charge being added to the third charge to turn on the third switch.

16. The system of claim 15, wherein the first switch circuit includes a fault indication terminal configured to generate a fault flag signal indicative of a fault event of the first switch circuit, and the second switch circuit includes an enable terminal configured to receive the fault flag signal, wherein the second switch circuit is enabled to conduct current from the second power source to the system output terminal when the first switch circuit has the fault event.

17. The system of claim 12, wherein the second switch of the first switch circuit is operable to control an inrush current from the first power source to the first output terminal.

18. A method of operating a switch circuit, the switch circuit including a first switch and a second switch coupled between an input terminal and an output terminal of the switch circuit, the method comprising: storing a first charge in an energy storage device; providing the first charge to a control terminal of the first switch; providing a first current to a control terminal of the second switch to turn on the second switch and store a second charge to the second switch; and coupling the control terminal of the second switch to the control terminal of the first switch to provide the second charge from the control terminal of the second switch to the control terminal of the first switch, the second charge being added to the first charge to turn on the first switch.

19. The method of claim 18, comprising: providing a second current to store the first charge to the energy storage device, wherein the first current is generated based on an input current received at the input terminal.

20. The method of claim 19, wherein based on the second current, the first current is provided to the control terminal of the second switch, the first current being less than the second current. ​

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