A digital radio frequency transmitter

Abstract

The present invention discloses a digital radio frequency transmitter, comprising a digital logic mixer, a digital power amplifier, and an antenna. The output of the digital logic mixer is connected to the input of the digital power amplifier, which in turn is connected to the antenna. The digital logic mixer is configured to logically mix baseband data input to the digital radio frequency transmitter with a radio frequency local oscillator clock signal to generate radio frequency data. The digital power amplifier is configured to convert the radio frequency data into an analog power signal. The antenna is configured to transmit the analog power signal. The digital radio frequency transmitter proposed in the present invention can effectively reduce circuit layout area and circuit operation power consumption.

Description

Technical Field

[0001] The present invention relates to the field of communication technology, and in particular to a digital radio frequency transmitter. Background Art

[0002] Wireless radio frequency communication is increasingly used in daily life. The implementation of wireless radio frequency protocols used in different applications, such as Wi-Fi, Bluetooth, and Ultra Wideband (UWB), relies on chips that can receive and transmit wireless radio frequency signals. Figure 1 As shown in the figure, the traditional wireless RF transmitter chip architecture includes a digital-to-analog converter (DAC) 101, a low-pass filter (LPF) 102, a mixer 103, a power amplifier 104, and an antenna 105. These modules are typically implemented using analog circuits. This results in a complex circuit structure, a large layout area, and high power consumption. Furthermore, noise generated by the analog circuits and leakage of the RF clock from the mixer input to the mixer output can affect the quality of the RF transmitter's output signal.

[0003] The disclosure of the above background technology content is only used to assist in understanding the concept and technical solution of the present invention. It does not necessarily belong to the prior art of this patent application. In the absence of clear evidence that the above content has been disclosed on the filing date of this patent application, the above background technology should not be used to evaluate the novelty and creativity of this application. Summary of the Invention

[0004] In order to solve the above-mentioned problems of the conventional radio frequency transmitter, the present invention proposes a digital radio frequency transmitter, which can effectively reduce the circuit layout area and the power consumption of the circuit operation.

[0005] In order to achieve the above object, the present invention adopts the following technical solutions:

[0006] The present invention discloses a digital radio frequency transmitter, comprising a digital logic mixer, a digital power amplifier and an antenna. The output end of the digital logic mixer is connected to the input end of the digital power amplifier, and the output end of the digital power amplifier is connected to the antenna. The digital logic mixer is used to perform logical mixing on baseband data and a radio frequency local oscillator clock signal input to the digital radio frequency transmitter to generate radio frequency data. The digital power amplifier is used to convert the radio frequency data into an analog power signal. The antenna is used to transmit the analog power signal.

[0007] Preferably, the baseband data input to the digital radio frequency transmitter is data digitally filtered by a digital filtering algorithm.

[0008] Preferably, the digital logic mixer includes a first logic AND gate and a first multiplexer, wherein the first input end of the first logic AND gate is the baseband data, the second input end is connected to the output end of the first multiplexer, and the output end outputs the RF data; the first input end of the first multiplexer is connected to the RF local oscillator clock signal, and the second input end is connected to the inverted signal of the RF local oscillator clock signal; the first multiplexer is used to select the RF local oscillator clock signal or the inverted signal of the RF local oscillator clock signal according to the sign bit of the baseband data.

[0009] Preferably, the digital logic mixer also includes a second logic AND gate and a second multiplexer, wherein the first input end of the second logic AND gate is the baseband data, the second input end is connected to the output end of the second multiplexer, and the output end outputs the RF data; the first input end of the second multiplexer is connected to the inverted signal of the RF local oscillator clock signal, and the second input end is connected to the RF local oscillator clock signal; the second multiplexer is used to select the inverted signal of the RF local oscillator clock signal or the RF local oscillator clock signal according to the sign bit of the baseband data.

[0010] Preferably, the digital power amplifier includes a transformer and 2 n -1 identical amplifier unit, where n is the number of bits of the radio frequency data, and the i-th radio frequency data controls 2 i amplifier units, 0≤i≤n-1.

[0011] Preferably, each amplifier unit includes a switching tube, a current regulation module and an isolation module, the input end of the switching tube is connected to the RF data, the current regulation module is connected to the switching tube for regulating the current of each amplifier unit, and the isolation module is connected between the input end of the transformer and the output end of the switching tube for isolating the switching tube and the transformer.

[0012] Preferably, each amplifier unit includes a first MOS transistor, a second MOS transistor, a third MOS transistor and a fourth MOS transistor, the gates of the first MOS transistor and the second MOS transistor are respectively connected to the RF data, and the gates of the third MOS transistor and the fourth MOS transistor are respectively connected to the voltage V B The source and drain of the first MOS tube are connected to the ground and the third MOS tube respectively, the source and drain of the second MOS tube are connected to the ground and the fourth MOS tube respectively, and the source and drain of the third MOS tube are connected to the first MOS tube and the positive output V OP The source and drain of the fourth MOS tube are connected to the second MOS tube and the negative output V ON , positive output V OP and the negative output VON The positive and negative terminals of the primary terminal of the transformer are connected respectively; wherein the 2 i The gates of the corresponding MOS tubes in the amplifier units are connected to each other respectively.

[0013] Preferably, the voltage V B is a fixed power supply voltage terminal or an adjustable power supply voltage terminal, where the voltage V B When the power supply voltage terminal is fixed, the power supply voltage of the transformer is an adjustable power supply voltage terminal.

[0014] Preferably, the digital power amplifier further includes a current mirror, and each amplifier unit further includes a fifth MOS transistor. The current mirror is composed of a sixth MOS transistor and the fifth MOS transistor included in each amplifier unit. The source and drain of the fifth MOS transistor are connected between the first MOS transistor, the second MOS transistor, and the ground. The gate of the fifth MOS transistor is connected to the gate of the sixth MOS transistor. The source and drain of the sixth MOS transistor are respectively connected to the ground and the gates of the fifth and sixth MOS transistors and the bias current. Wherein, the 2 i The gates of the fifth MOS transistors in the amplifier units are respectively connected.

[0015] Preferably, the first MOS transistor and the second MOS transistor are thin-oxygen low-pressure tubes, and the third MOS transistor and the fourth MOS transistor are thick-oxygen medium-pressure tubes.

[0016] Preferably, the parasitic capacitance of the first MOS transistor and the second MOS transistor is smaller than the parasitic capacitance of the third MOS transistor and the fourth MOS transistor.

[0017] Compared with the prior art, the beneficial effect of the present invention is that the digital radio frequency machine disclosed in the present invention adopts a modular digital method to realize logic mixing and power amplification, which can effectively reduce the circuit layout area and circuit power consumption.

[0018] In a further solution, the digital logic mixer incorporates digital logic gates, effectively preventing clock leakage to the power amplifier output, improving the quality of the RF transmitter's output signal. The digital power amplifier combines the functions of a digital-to-analog converter and a power amplifier, simplifying the RF transmitter's structure. Furthermore, the RF transmitter's digital baseband input data can be digitally filtered, saving the cost of analog filters.

[0019] In a further solution, the first MOS transistor and the second MOS transistor adopt thin-oxygen low-voltage transistors, which can effectively reduce the capacitive load driven by the RF data; the third MOS transistor and the fourth MOS transistor adopt thick-oxygen medium-voltage transistors, which can isolate the low-voltage transistor from the transformer to protect the working safety of the low-voltage transistor. BRIEF DESCRIPTION OF THE DRAWINGS

[0020] Figure 1 It is a schematic diagram of the structure of a traditional radio frequency transmitter;

[0021] Figure 2 1 is a structural diagram of a digital radio frequency transmitter according to a preferred embodiment of the present invention;

[0022] Figure 3 1 is a schematic diagram of the circuit structure of a digital logic mixer according to a preferred embodiment of the present invention;

[0023] Figure 4 yes Figure 3 Schematic diagram of the input and output signals of the digital logic mixer;

[0024] Figure 5 1 is a schematic structural diagram of a digital power amplifier according to an embodiment of the present invention;

[0025] Figure 6 FIG. 4 is a structural diagram of a digital power amplifier according to another embodiment of the present invention. DETAILED DESCRIPTION

[0026] The following is a detailed description of the embodiments of the present invention. It should be emphasized that the following description is only exemplary and is not intended to limit the scope of the present invention and its application.

[0027] It should be noted that when an element is referred to as being "fixed to" or "disposed on" another element, it can be directly on the other element or indirectly on the other element. When an element is referred to as being "connected to" another element, it can be directly connected to the other element or indirectly connected to the other element. In addition, connection can be used for both fixing and circuit / signal communication.

[0028] It should be understood that the terms "length", "width", "up", "down", "front", "back", "left", "right", "vertical", "horizontal", "top", "bottom", "inside", "outside", etc., indicating the orientation or position relationship, are based on the orientation or position relationship shown in the accompanying drawings, and are only for the convenience of describing the embodiments of the present invention and simplifying the description, and do not indicate or imply that the device or element referred to must have a specific orientation, be constructed and operate in a specific orientation, and therefore cannot be understood as limiting the present invention.

[0029] Furthermore, the terms "first" and "second" are used for descriptive purposes only and should not be understood to indicate or imply relative importance or implicitly specify the number of technical features indicated. Thus, a feature defined as "first" or "second" may explicitly or implicitly include one or more of such features. In the description of the embodiments of the present invention, "plurality" means two or more, unless otherwise specifically defined.

[0030] like Figure 2 As shown, a preferred embodiment of the present invention discloses a digital RF transmitter, including a digital logic mixer 20, a digital power amplifier 10 and an antenna 30. The output end of the digital logic mixer 20 is connected to the input end of the digital power amplifier 10, and the output end of the digital power amplifier 10 is connected to the antenna 30. The digital logic mixer 20 is used to perform logical mixing on the baseband data and the RF local oscillator clock signal input to the digital RF transmitter to generate RF data. The digital power amplifier 10 is used to convert the RF data into an analog power signal. The antenna 30 is used to transmit the analog power signal.

[0031] like Figure 3 As shown, the digital logic mixer 20 includes n first logic AND gates 21 and n first multiplexers 22. The n first logic AND gates 21 can respectively convert the baseband data a n-1 ...a0 is mixed to RF data b n-1 ...b0; wherein the first input terminal of the first logic AND gate 21 is a certain baseband data a i The second input terminal is connected to the output terminal of the first multiplexer 22, and the output terminal outputs the corresponding radio frequency data b i The first input terminal (0 terminal) of the first multiplexer 22 is connected to the RF local oscillator clock signal clk, and the second input terminal (1 terminal) is connected to the inverted signal of the RF local oscillator clock signal The first multiplexer 22 receives the baseband data a i The sign bit s selects the RF local oscillator clock signal clk or the inverted signal of the RF local oscillator clock signal b i The frequency is the RF local oscillator clock frequency, b i The phase of the input baseband data a i symbol.

[0032] For a differential output RF transmitter, it is necessary to output RF data b at the same time. i and Furthermore, the digital logic mixer 20 further includes n second logic AND gates 23 and n second multiplexers 24. The n second logic AND gates 23 can respectively convert the baseband data a n-1 ...a0 mixed to RF data The first input terminal of the second logic AND gate 23 is a certain bit of baseband data a i The second input terminal is connected to the output terminal of the second multiplexer 24, and the output terminal outputs a corresponding radio frequency data The first input terminal (terminal 0) of the second multiplexer 24 is connected to the inverted signal of the RF local oscillator clock signal. The second input terminal (terminal 1) is connected to the RF local oscillator clock signal clk; the second multiplexer 24 is connected to the baseband data a i The sign bit s selects the inverted signal of the RF local oscillator clock signal Or the radio frequency local oscillator clock signal clk. The frequency is the RF local oscillator clock frequency, The phase of the input baseband data a i symbol. The RF output signal is inverted and its phase is the same as the positive RF output signal b. i On the contrary, Figure 4 shown.

[0033] The digital power amplifier 10 combines the functions of a digital-to-analog converter and a power amplifier, which converts the input RF data into n-1 ...b0 is converted into an analog power signal and transmitted through the antenna 30. For n-bit input RF data, the digital power amplifier 10 contains 2 n -1 identical amplifier unit, RF data b of the i-th bit i Control 2 i amplifier units, corresponding to the i-th RF data b i weights, thereby realizing the analog-to-digital conversion function, where 0≤i≤n-1.

[0034] like Figure 5 FIG. 1 shows a circuit structure of a current-mode differential digital power amplifier according to an embodiment of the present invention. The digital power amplifier includes a transformer, a current mirror, 2 n - 1 identical amplifier unit, each amplifier unit includes a first MOS tube M i1 , the second MOS tube M i2 , the third MOS tube M i3 , the fourth MOS tube M i4 And the fifth MOS tube M i0 , the current mirror consists of a sixth MOS tube M src and the fifth MOS tube M of each amplifier unit i0 (0≤i≤n-1) to set the bias current i bias The mirror image is copied to each amplifier unit. Among them, the 2 iThe gates of the corresponding MOS transistors in each amplifier unit are connected to each other (that is, the 2 gates controlled by the i-th RF data are connected to each other). i The first MOS tube M in the amplifier unit i1 The gates of the second MOS tube M are connected to each other. i2 The gates of the third MOS tube M are connected to each other. i3 The gates of the fourth MOS tube M are connected to each other. i4 The gates of the fifth MOS tube M are connected to each other. i0 The gates of the fifth MOS tube are connected to the gate of the sixth MOS tube, the source and drain of the sixth MOS tube are respectively connected to the ground and the gates and bias current of the fifth and sixth MOS tubes, and the fifth MOS tube M i0 One end of the source and drain is connected to the ground, and the other end is connected to the first MOS tube M i1 And the second MOS tube M i2 ; First MOS tube M i1 The gate connection RF data b i , the first MOS tube M i1 The source and drain of the fifth MOS tube M are respectively connected i0 And the third MOS tube M i3 ; Second MOS tube M i2 Gate connection RF data The second MOS tube M i2 The source and drain of the fifth MOS tube M are respectively connected i0 And the fourth MOS tube M i4 ; The third MOS tube M i3 And the fourth MOS tube M i4 The gate connection voltage V B (In this embodiment, the voltage V B The default value is a fixed value, and the current is adjusted by the current mirror). The third MOS tube M i3 The source and drain of the first MOS tube M are connected i1 and the positive output V OP , the fourth MOS tube M i4 The source and drain of the second MOS tube M are connected i2 and the negative output V ON ; Positive output V OP and the negative output V ON Connect the positive and negative terminals of the transformer's primary terminal respectively. The power supply voltage of the transformer's primary terminal is V CC .

[0035] The digital power amplifier circuit can adjust the bias current i bias To control the current of each amplifier unit, thereby changing the power of the output signal.i1 And the second MOS tube M i2 Used as a switch tube, RF data b i and Connect the gates of the two MOS tubes respectively to control the fifth MOS tube M in the unit i0 The bias current flows to the positive output of the differential power amplifier V OP Or negative output V ON The outputs of all amplifier units are connected together to generate RF data b n-1 ...the analog current signal represented by b0 drives the primary end of the transformer, and the induced voltage and current generated at the secondary end of the transformer drives the antenna to transmit b n-1 …b0 represents the RF signal.

[0036] Since the RF data b i and The frequency is the RF local oscillator clock frequency, which is relatively high (for example, for UWB applications, the frequency can reach up to 9.48 GHz). Therefore, it limits the size of the capacitive load that can be driven by the RF input data. i1 And the second MOS tube M i2 The thin-oxide low-voltage MOS tube is used to achieve the minimum channel length in the process, which also reduces the channel width to achieve a certain driving capability, thereby effectively reducing the size of the MOS tube and the size of the parasitic capacitance. Therefore, the use of low-voltage tubes can reduce the RF data b i and Specifically, the minimum size of a low-voltage MOS transistor is related to the process. For example, the minimum channel length of a 40nm process is about 40nm, and the minimum channel length of a 22nm process is about 25nm. As the channel length decreases, the area of ​​the MOS transistor decreases, and the corresponding parasitic capacitance also decreases. For example, at 22nm, the minimum channel length of a 0.8V low-voltage transistor is about 25nm, while the minimum channel length of a 3.3V medium-voltage transistor is 550nm, which is dozens of times larger in area and parasitic capacitance.

[0037] The output signal voltage amplitude of the power amplifier determines the output power. The application of large output power requires the power supply voltage of the primary end of the transformer to be V CC Therefore, in this embodiment, the third MOS tube M i3 And the fourth MOS tube M i4 Thick oxide 3.3V medium voltage tube is used to isolate the lower low voltage tube from the upper transformer. The thick oxide 3.3V medium voltage tube limits the voltage between the source and drain of the lower low voltage tube to not exceed its withstand voltage value, thereby protecting the working safety of the lower low voltage tube.

[0038] In this embodiment, the first MOS tube M i1 And the second MOS tube M i2 The thin oxygen low-pressure tube used, the third MOS tube M i3 And the fourth MOS tube M i4 Thick-oxygen medium-voltage transistors are used, with the voltage ranges of low-voltage and medium-voltage transistors varying depending on the process. Those skilled in the art will understand that the low-voltage transistor is a commonly used core device (the device used internally in the chip), and the medium-voltage transistor is a commonly used I / O device (the device used when the chip interacts with external interfaces). For example, in the commonly used TSMC 40nm process, there are 0.9V, 3.3V, and 5V MOS transistors. That is, the typical operating voltage values ​​of MOS transistors are 0.9V, 3.3V, and 5V, respectively. The 0.9V MOS transistor is generally referred to as a low-voltage transistor, and the 3.3V MOS transistor is generally referred to as a medium-voltage transistor. The silicon dioxide between the gate and channel of the 0.9V MOS transistor is typically thinner, while the silicon dioxide between the gate and channel of the 3.3V MOS transistor is thicker, hence the distinction between thin-oxygen low-voltage transistors and thick-oxygen medium-voltage transistors. The specific thickness depends on the process parameters.

[0039] like Figure 6 FIG. 1 shows a circuit structure of a current-mode differential digital power amplifier according to another embodiment of the present invention. In this embodiment, the fifth MOS transistor M in the current mirror i0 With the third MOS tube M i3 , the fourth MOS tube M i4 Merge, through the third MOS tube M i3 , the fourth MOS tube M i4 The gate voltage V B Controls the current flowing through the amplifier unit to achieve direct voltage V B Adjust the bias current and further adjust the voltage V B The size of can change the output power of the digital radio frequency transmitter. That is, in this embodiment, the digital power amplifier does not include a current mirror, and the first MOS tube M i1 , the second MOS tube M i2 One end of the source and drain is directly grounded. Based on this, in some other embodiments, the voltage V B Connect to a fixed power supply voltage, and generate branch bias current by the on-resistance of the MOS tube connected to each branch; adjust the power supply voltage V CC , the size of the branch bias current can be changed, thereby controlling the transmitter output power.

[0040] In an embodiment of the present invention, the digital RF transmitter combines a digital-to-analog converter (DAC) and a power amplifier (PA) into a digital power amplifier (PA), simplifying the RF transmitter structure. The low-pass filter can be implemented in the digital domain using a digital filtering algorithm. The RF transmitter's digital baseband input data is digitally filtered, saving analog filter costs. The RF mixing circuit is also digitally implemented, mixing the transmit baseband digital input data and the RF clock via digital logic gates. These digital logic gates effectively prevent clock leakage to the PA output. Furthermore, the digital implementation of the module further reduces circuit layout area and power consumption.

[0041] The background section of the present invention may contain background information about the problem or environment of the present invention rather than describing prior art by others. Therefore, the inclusion of content in the background section is not an admission by the applicant that the prior art is available.

[0042] The above description further details the present invention in conjunction with specific / preferred embodiments, and the specific implementation of the present invention should not be construed as being limited to these descriptions. Persons skilled in the art will appreciate that, without departing from the spirit of the present invention, they may make various substitutions or modifications to the described embodiments, and these substitutions or modifications should be considered to fall within the scope of protection of the present invention. Throughout this specification, reference to terms such as "one embodiment," "some embodiments," "preferred embodiments," "examples," "specific examples," or "some examples" indicates that the specific features, structures, materials, or characteristics described in conjunction with such embodiment or example are included in at least one embodiment or example of the present invention. In this specification, the schematic representations of these terms do not necessarily refer to the same embodiment or example. Furthermore, the specific features, structures, materials, or characteristics described may be combined in any suitable manner in any one or more embodiments or examples. Furthermore, those skilled in the art may combine and assemble the different embodiments or examples described in this specification, as well as features from different embodiments or examples, without conflicting opinions. Although the embodiments of the present invention and their advantages have been described in detail, it should be understood that various changes, substitutions, and modifications may be made herein without departing from the scope of the appended claims.

Claims

1. A digital radio frequency transmitter, characterized in that: The device comprises a digital logic mixer, a digital power amplifier, and an antenna, wherein the output of the digital logic mixer is connected to the input of the digital power amplifier, and the output of the digital power amplifier is connected to the antenna. The digital logic mixer is used to perform logic mixing on the baseband data input to the digital RF transmitter and the RF local oscillator clock signal to generate RF data. The digital power amplifier is used to convert the RF data into an analog power signal. The antenna is used to transmit the analog power signal. The digital power amplifier includes a transformer and 2 n -1 identical amplifier unit, where n is the number of bits of the radio frequency data, and the i-th radio frequency data controls 2 i an amplifier unit corresponding to the weight of the i-th bit of RF data to realize the analog-to-digital conversion function, where 0≤i≤n-1; Each amplifier unit includes a first MOS transistor and a second MOS transistor. The gates of the first MOS transistor and the second MOS transistor are connected to the radio frequency data respectively. The 2 i The gates of the corresponding MOS tubes in the amplifier units are connected to each other respectively; and the first MOS tube and the second MOS tube are thin-oxygen low-voltage tubes.

2. The digital radio frequency transmitter according to claim 1, wherein The baseband data input to the digital radio frequency transmitter is data that has been digitally filtered using a digital filtering algorithm.

3. The digital radio frequency transmitter according to claim 1, wherein The digital logic mixer includes a first logic AND gate and a first multiplexer, wherein the first input end of the first logic AND gate is the baseband data, the second input end is connected to the output end of the first multiplexer, and the output end outputs the radio frequency data; The first input end of the first multiplexer is connected to the radio frequency local oscillator clock signal, and the second input end is connected to the inverted signal of the radio frequency local oscillator clock signal; The first multiplexer is used to select the radio frequency local oscillator clock signal or the inverted signal of the radio frequency local oscillator clock signal according to the sign bit of the baseband data.

4. The digital radio frequency transmitter according to claim 3, characterized in that The digital logic mixer further includes a second logic AND gate and a second multiplexer, wherein a first input end of the second logic AND gate is the baseband data, a second input end is connected to an output end of the second multiplexer, and an output end outputs the radio frequency data; The first input end of the second multiplexer is connected to the inverted signal of the RF local oscillator clock signal, and the second input end is connected to the RF local oscillator clock signal; The second multiplexer is configured to select the inverted signal of the radio frequency local oscillator clock signal or the radio frequency local oscillator clock signal according to the sign bit of the baseband data.

5. The digital radio frequency transmitter according to claim 1, wherein Each amplifier unit includes a switching tube, a current regulation module and an isolation module. The input end of the switching tube is connected to the RF data. The current regulation module is connected to the switching tube for regulating the current of each amplifier unit. The isolation module is connected between the input end of the transformer and the output end of the switching tube for isolating the switching tube from the transformer.

6. The digital radio frequency transmitter according to claim 1, wherein Each amplifier unit further includes a third MOS tube and a fourth MOS tube, the gates of the third MOS tube and the fourth MOS tube are connected to a voltage V B The source and drain of the first MOS tube are connected to the ground and the third MOS tube respectively, the source and drain of the second MOS tube are connected to the ground and the fourth MOS tube respectively, and the source and drain of the third MOS tube are connected to the first MOS tube and the positive output V OP The source and drain of the fourth MOS tube are connected to the second MOS tube and the negative output V ON , positive output V OP and the negative output V ON Connect the positive and negative terminals of the primary terminal of the transformer respectively.

7. The digital radio frequency transmitter according to claim 6, characterized in that Voltage V B is a fixed power supply voltage terminal or an adjustable power supply voltage terminal, where the voltage V B When the power supply voltage terminal is fixed, the power supply voltage of the transformer is an adjustable power supply voltage terminal.

8. The digital radio frequency transmitter according to claim 6, characterized in that The digital power amplifier further includes a current mirror, and each amplifier unit further includes a fifth MOS transistor. The current mirror is composed of a sixth MOS transistor and the fifth MOS transistor included in each amplifier unit. The source and drain of the fifth MOS transistor are connected between the first MOS transistor, the second MOS transistor and the ground. The gate of the fifth MOS transistor is connected to the gate of the sixth MOS transistor. The source and drain of the sixth MOS transistor are respectively connected to the ground and the gates of the fifth and sixth MOS transistors and the bias current. Wherein, the 2 i The gates of the fifth MOS transistors in the amplifier units are respectively connected.

9. The digital radio frequency transmitter according to any one of claims 6 to 8, characterized in that: The third MOS tube and the fourth MOS tube are respectively thick-oxygen medium-pressure tubes.

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