Test circuit and electronic device

Abstract

The present application provides a test circuit and an electronic device for testing a memory circuit, which includes a controller, a pattern generating circuit, a comparison circuit and a register. The controller is used to generate a plurality of internal test signals and receive a test result. The pattern generating circuit writes a test data into a memory block of the memory circuit according to the internal test signals and reads the memory block to generate a read data. The comparison circuit compares the test data and the read data to generate the test result. The register is used to store the test result. The controller judges whether the memory circuit is normal according to the test result stored in the register.

Description

Technical Field

[0001] This invention relates to a test circuit, and more particularly to a test circuit for testing memory circuits. Background Technology

[0002] With advancements in manufacturing processes, integrated circuits are becoming increasingly smaller. However, during the testing phase, the testing frequency of testing equipment is limited by factors such as ribbon cables, probe cards, and package pin configurations, preventing its increase. Summary of the Invention

[0003] This invention provides a test circuit for testing a storage circuit, comprising a controller, a pattern generation circuit, a comparison circuit, and a temporary register. The controller generates multiple internal test signals and receives a test result. The pattern generation circuit writes test data into a storage block of the storage circuit based on the internal test signals and reads the storage block to generate read data. The comparison circuit compares the test data and the read data to generate a test result. The temporary register stores the test result. The controller determines whether the storage circuit is functioning correctly based on the test result stored in the first temporary register.

[0004] The present invention further provides an electronic device, including a storage circuit and a test circuit. The test circuit is used to test the storage circuit and includes a controller, a pattern generating circuit, a comparison circuit, and a register. The controller generates a plurality of internal test signals. The pattern generating circuit writes test data into a storage block of the storage circuit according to the internal test signals and reads the storage block to generate read data. The comparison circuit compares the test data and the read data to generate a test result. The register temporarily stores the test result. The controller determines whether the storage circuit is functioning correctly based on the test result stored in the first register. Attached Figure Description

[0005] Figure 1 This is a schematic diagram of the testing system of the present invention.

[0006] Figure 2A This is a possible embodiment of the test circuit of the present invention.

[0007] Figure 2B This is a possible embodiment of the test circuit of the present invention.

[0008] Figure 3 This is another possible embodiment of the controller of the present invention.

[0009] Symbol explanation:

[0010] 100: Test System

[0011] 110: Testing equipment

[0012] 120: Device under test

[0013] 130: Connecting cable

[0014] EX T External test signal

[0015] MBE: Mode Selection Signal

[0016] UT T Test Results

[0017] MBT: Test Output Signal

[0018] 121, 200A, 200B: Test Circuits

[0019] 122: Storage circuit

[0020] TST E TST I TST M Test pattern

[0021] DT E DT I Test data

[0022] AD E AD I Access address

[0023] CM E CM I Control commands

[0024] DT R Read data

[0025] 210: Test access circuit

[0026] 220: Pattern Generation Circuit

[0027] 230: Comparator Circuit

[0028] 240, 260: Temporary registers

[0029] 250: Controller

[0030] 221: Data Generator

[0031] 222: Address Generator

[0032] 223: Control Generator

[0033] 224~226: Selection Circuit

[0034] S D Internal data

[0035] S SELSelection signal

[0036] S A Address signal

[0037] S C Control signals

[0038] DF1~DF3, DF 21 ~DF 2N Type D flip-flop

[0039] OPF: Operating Clock

[0040] S TR1 ~S TRN Status code

[0041] 251, 252, 310, 320: Combinational Logic Circuits

[0042] S Q1 ~S Q3 S O S Q21 ~S Q2N Output signal

[0043] S TR Status signal

[0044] S P / F Test Results

[0045] 270: Logic Gates

[0046] SI: Serial Data Detailed Implementation

[0047] To make the objectives, features, and advantages of this invention more apparent and understandable, embodiments are provided below in conjunction with the accompanying drawings for detailed description. This specification provides different embodiments to illustrate the technical features of different implementations of the invention. The configuration of the elements in the embodiments is for illustrative purposes only and is not intended to limit the invention. Furthermore, the repetition of some reference numerals in the embodiments is for simplification and does not imply any correlation between different embodiments.

[0048] Figure 1 This is a schematic diagram of the testing system of the present invention. As shown, the testing system 100 includes a testing platform 110 and a device under test 120. The testing platform 110 is used to provide an external test signal EX. T And receive a test result UT returned by the device under test 120. T In one possible embodiment, the test bench 110 is coupled to the test device 120 via a connection line 130 to provide an external test signal EX. TThe device under test (DUT) is then fed to the device 120. In other embodiments, the test equipment 110 also receives the test result UT from the DUT 120 via the connection line 130. T In some embodiments, the test machine 110 may wirelessly output an external test signal EX. T And receive the test results UT returned by the device under test 120. T This invention does not limit the external test signal EX. T The format. In one possible embodiment, the external test signal EX T It includes test data, an access address, and a control command. In other embodiments, the external test signal EX... T It also includes a mode selection signal, MBE.

[0049] In this embodiment, the device under test 120 is an electronic device that operates in a normal test mode, a self-test mode, or a mixed test mode based on the characteristic parameters of the mode selection signal MBE. For example, when the characteristic parameters of the mode selection signal MBE meet a first preset condition, the device under test 120 enters a normal test mode. In the normal test mode, the device under test 120 operates according to the external test signal EX. T The device under test (DUT) 120 generates a test signal for its internal storage circuit 122. When the characteristic parameters of the mode selection signal MBE meet a second preset condition, the DUT 120 enters a self-test mode. In self-test mode, the DUT 120 generates a test signal for its internal storage circuit 122. In this mode, the DUT 120 ignores the external test signal EX. T When the characteristic parameters of the mode selection signal MBE meet a third preset condition, the device under test 120 enters a mixed test mode. In the mixed test mode, the device under test 120 operates according to the external test signal EX. T The components, along with internally generated test signals, are used to test the storage circuit 122.

[0050] This invention does not limit the type of device under test 120. In one possible embodiment, the device under test 120 is a non-volatile memory or a volatile memory. In other embodiments, the device under test 120 is other types of electronic components. In this embodiment, the device under test 120 includes a test circuit 121 and a storage circuit 122.

[0051] When the characteristic parameters of the mode selection signal MBE meet a first preset condition, the test circuit 121 receives and processes the external test signal EX.T Used to generate test patterns (TST) E In one possible embodiment, the test pattern TST E Including test data DT E Access address AD E and control commands CM E In this example, the storage circuit 122 operates according to the control command CM. E Perform a write operation or a read operation. For example, when the control command CM... E When a write instruction is received, the storage circuit 122 performs a write operation to transfer the test data DT. E Write access address AD E In the corresponding storage block. When the control command CM E When a read instruction is received, the storage circuit 122 performs a read operation to read the access address AD. E The data in the corresponding storage block is used to generate a read data DT. R .

[0052] When the characteristic parameters of the mode selection signal MBE meet a second preset condition, the test circuit 121 automatically generates a test pattern TST. I Storage circuit 122. In one possible embodiment, the test pattern TST I Including test data DT I Access address AD I and control commands CM I The storage circuit 122 operates according to the control command CM. I Perform a write operation or a read operation. For example, when the control command CM... I When a write instruction is received, the storage circuit 122 performs a write operation to transfer the test data DT. I Write access address AD I In the corresponding storage block. When the control command CM I When a read instruction is received, the storage circuit 122 performs a read operation to read the access address AD. I The data in the corresponding storage block is used to generate a read data DT. R .

[0053] When the characteristic parameters of the mode selection signal MBE meet a third preset condition, the test circuit 121 determines the external test signal EX. T And the self-generated test signal, producing a test pattern TST M In one possible embodiment, the test pattern TST M Including test data DT E Access address ADI and control commands CM I The storage circuit 122 operates according to the control command CM. I Perform a write operation or a read operation. For example, when the control command CM... I When a write instruction is received, the storage circuit 122 performs a write operation to transfer the test data DT. E Write access address AD I In the corresponding storage block. When the control command CM I When a read instruction is received, the storage circuit 122 performs a read operation to read the access address AD. I The data in the corresponding storage block is used to generate a read data DT. R .

[0054] The present invention does not limit the type of storage circuit 122. Storage circuit 122 may be a non-volatile storage circuit or a volatile storage circuit. In one possible embodiment, storage circuit 122 is a static random access memory (SRAM).

[0055] Test circuit 121 reads the data DT provided by storage circuit 122. R The test circuit 121 determines whether the storage circuit 122 is operating normally. This invention does not limit how the test circuit 121 determines the operation based on the read data DT. R The test circuit 121 determines whether the storage circuit 122 is operating normally. In one possible embodiment, the test circuit 121 will read the data DT. R Compare with a preset data set. When reading data DT R When the value equals the preset data, it indicates that the access operation of the storage circuit 122 is normal. However, when reading data DT... R When the value is not equal to the preset data, it indicates an abnormal access operation of the storage circuit 122. In one possible embodiment, the test circuit 121 records the number of abnormal access operations of the storage circuit 122. In another possible embodiment, once an abnormality occurs in the storage circuit 122, the test circuit 121 immediately notifies the test machine 110.

[0056] Figure 2A This is a possible embodiment of the test circuit of the present invention. As shown in the figure, the test circuit 200A includes a test access circuit 210, a pattern generation circuit 220, a comparison circuit 230, a register 240, and a controller 250. The test access circuit 210 is used to receive and process the external test signal EX. T DT is used to generate test data. E (or external test data), access address AD E and control commands CM EIn one possible embodiment, the test data DT E Access address AD E and control commands CM E Each has multiple bits. In this embodiment, the test data DT E Access address AD E and control commands CM E Forming the test pattern TST E .

[0057] This invention does not limit the architecture of the test access circuit 210. Any architecture that can be accessed via an external test signal EX... T In the middle, the test data DT is decoded. E Access address AD E and control commands CM E Any of the following circuit architectures can be used as the test access circuit 210. In one possible embodiment, the test access circuit 210 includes a test access port (TAP).

[0058] In other embodiments, the test access circuit 210 further outputs a mode selection signal MBE and a serial data SI to the controller 250. In one possible embodiment, when the characteristic parameters of the mode selection signal MBE meet a first preset condition, the test access circuit 210 receives and processes the external test signal EX. T Used to generate test patterns TST E However, when the characteristic parameters of the mode selection signal MBE meet a second preset condition, the test access circuit 210 does not process the external test signal EX. T When the characteristic parameters of the mode selection signal MBE meet a third preset condition, the test access circuit 210 processes the external test signal EX. T DT is used to generate test data. E .

[0059] Pattern generation circuit 220 is used to provide test pattern TST E TST I Or TST M The storage circuit 122 is used for this purpose. For example, in a normal test mode (such as when the characteristic parameters of the mode selection signal MBE meet a first preset condition), the pattern generation circuit 220 provides the test pattern TST. E Pre-stored circuit 122. In a self-test mode (e.g., the characteristic parameters of the mode selection signal MBE meet a second preset condition), pattern generation circuit 220 processes internal test signals (e.g., internal data S). D Address signal S A and control signal S C ), used to generate the test pattern TSTI And provide test patterns TST I Pre-storage circuit 122. In a mixed test mode (e.g., the characteristic parameters of the mode selection signal MBE meet a third preset condition), the pattern generation circuit 220A generates a pattern based on the external test signal EX. T And the internal test signal generates the test pattern TST M and output the test pattern TST M Pre-storage circuit 122. In this embodiment, the test pattern TST E Including test data DT E Access address AD E Control commands CM E Additionally, the test pattern TST I Including test data DT I Access address AD I Control commands CM I In other embodiments, the test pattern TST M Including test data DT E Access address AD I Control commands CM I .

[0060] The present invention does not limit the architecture of the pattern generation circuit 220. Any circuit capable of generating a test pattern can be used as the pattern generation circuit 220. In this embodiment, the pattern generation circuit 220 includes a data generator 221, an address generator 222, a control generator 223, and selection circuits 224 to 226.

[0061] Data generator 221 based on internal data S D DT generates test data. I (Or internal test data). This invention does not limit how the data generator 221 generates the test data DT. I In one possible embodiment, the data generator 221 uses a specific algorithm to compute the internal data S. D DT is used to generate test data. I For example, internal data S D The value is 01. In this example, data generator 221 converts and processes internal data S. D DT is used to generate test data. I Its value may be 01010101 0101 0101.

[0062] Selection circuit 224 selects a selection signal S. SELOutput test data DT I Or DT E Storage circuit 122. For example, when the selection signal S... SEL When the signal level is a first level (e.g., low level), the selection circuit 224 outputs test data DT. I When the selection signal S SEL When the signal level is a second level (e.g., high level), the selection circuit 224 outputs test data DT. E The present invention does not limit the architecture of the selection circuit 224. In one possible embodiment, the selection circuit 224 is a multiplexer.

[0063] Address generator 222 determines the address signal S A Generate an access address AD I This invention does not limit how the address generator 222 generates the access address AD. I In one possible embodiment, the address generator 222 has a counter. The counter is based on the address signal S. A Adjust a counter value. In this example, address generator 222 generates access address AD based on the count value of an internal counter (not shown). I In one possible embodiment, the counter is an up counter or an down counter.

[0064] The selection circuit 225 selects the signal S according to the selection signal S. SEL Output access address AD I or AD E Storage circuit 122. For example, when the selection signal S... SEL When the first level is reached, the selection circuit 225 outputs the access address AD. I When the selection signal S SEL When the second level is reached, the selection circuit 225 outputs the access address AD. E The present invention does not limit the architecture of the selection circuit 225. In one possible embodiment, the selection circuit 225 is a multiplexer.

[0065] The control generator 223 controls the generator according to the control signal S C Generate a control command CM I In one possible embodiment, when the control signal S C When the control signal S is at a first level, the control generator 223 generates a write command to instruct the storage circuit 122 to perform a write operation. C When the signal level is at the second level, the control generator 223 generates a read instruction to command the storage circuit 122 to perform a read operation.

[0066] Selection circuit 226 selects the selection signal S.SEL Output control command CM I or CM E Storage circuit 122. For example, when the selection signal S... SEL When the first level is reached, the selection circuit 226 outputs the control command CM. I When the selection signal S SEL When the second level is reached, the selection circuit 226 outputs the control command CM. E The present invention does not limit the architecture of the selection circuit 226. In one possible embodiment, the selection circuit 226 is a multiplexer.

[0067] In other embodiments, selection circuits 224-226 are controlled by a first selection signal, a second selection signal, and a third selection signal, respectively. When selection circuits 224-226 are controlled by different selection signals, they can selectively output internal or external test signals to storage circuit 122. For example, when the characteristic parameters of the mode selection signal MBE meet a first preset condition, controller 250 may set each of the first to third selection signals to a second level (e.g., high level). Therefore, selection circuit 224 outputs test data DT. E The selection circuit 225 outputs the address access AD. E Select circuit 226 outputs control command CM E In this example, the test data DT E Access address AD E With control command CM E Forming the test pattern TST E .

[0068] When the characteristic parameters of the mode selection signal MBE meet a second preset condition, the controller 250 may set each of the first to third selection signals to a first level (e.g., low level). Therefore, the selection circuit 224 outputs test data DT. I The selection circuit 225 outputs the address access AD. I Select circuit 226 outputs control command CM I In this example, the test data DT I Access address AD I and control commands CM I Forming the test pattern TST I .

[0069] When the characteristic parameters of the mode selection signal MBE meet a third preset condition, the controller 250 may set the first selection signal to a second level (e.g., high level) and set the second and third selection signals to a first level (e.g., low level). Therefore, the selection circuit 224 outputs test data DT. EThe selection circuit 225 outputs the address access AD. I Select circuit 226 outputs control command CM I In this example, the test data DT E Access address AD I and control commands CM I Forming the test pattern TST M In one possible embodiment, the test data DT E This is set by the user. In this example, the user might provide test data DT through test machine 110. E The test circuit is rated 200A.

[0070] Storage circuit 122 according to test pattern TST E TST I Or TST M And the action. To test the pattern TST I For example, the storage circuit 122, according to the control command CM I Enter either a write mode or a read mode. For example, when the control command CM... I When a preset value is met, the storage circuit 122 enters a write mode to write the test data DT. I Write access address AD I In the corresponding storage block. When the control command CM I If the preset value is not met, the storage circuit 122 enters a read mode. In read mode, the storage circuit 122 reads the access address AD. I The data in the corresponding storage block is used to generate the read data DT. R In this embodiment, data DT is read. R It has multiple bits, such as 16 bits.

[0071] Comparator Circuit 230 Comparison Test Data DT I / DT E With reading data DT R To generate a test result S P / F In normal test mode and mixed test mode, comparator circuit 230 compares test data DT. E With reading data DT R In self-test mode, comparator 230 compares the test data DT. I With reading data DT R In this embodiment, the test data DT I / DT E With reading data DT R It has multiple bits (e.g., 16 bits), and the test result S P / F It has only one digit.

[0072] Scratch test results for register 240 P / F In this embodiment, the temporary register 240 is a D-type flip-flop DF1. The input terminal D of the D-type flip-flop DF1 receives the test result S. P / F Its clock input clk receives an operating clock OPF. In this example, the operating clock OPF is used to trigger the D-type flip-flop DF1. During the first cycle of the operating clock OPF, the D-type flip-flop DF1 receives the test result S. P / F During the second week of operation of the clock OPF, the D-type flip-flop DF1 will test the result S. P / F As an output signal S Q1 Provided to controller 250. In this embodiment, output signal S Q1 It has a single digit.

[0073] Controller 250 is used to generate internal data S D Address signal S A and control signal S C And according to the output signal S Q1 The controller 250 determines whether the storage circuit 122 is operating normally. In one possible embodiment, when the storage circuit 122 performs a write operation, the controller 250 ignores the output signal S. Q1 The system stops detecting whether the storage circuit 122 is functioning correctly. However, when the storage circuit 122 performs a read operation, the controller 250 begins to detect the operation based on the output signal S. Q1 The system detects whether the storage circuit 122 is operating normally and generates a test output signal MBT based on the detection result.

[0074] In one possible embodiment, the controller 250 determines whether to generate internal data S based on the characteristic parameters of the mode selection signal MBE. D Address signal S A and control signal S C For example, when the characteristic parameters of the mode selection signal MBE meet a first preset condition, the controller 250 stops providing internal data S. D Address signal S A and control signal S C Pattern generation circuit 220. At this time, controller 250 uses selection signal S SEL The pattern generation circuit 220 is required to provide test data DT. E Access address AD E and control commands CM E Storage circuit 122. However, when the characteristic parameters of the mode selection signal MBE meet a second preset condition, the controller 250 provides internal data S. D Address signal S Aand control signal S C Therefore, the pattern generating circuit 220 generates the pattern based on the internal data S. D Address signal S A and control signal S C Generate test data DT I Access address AD I and control commands CM I In this example, controller 250 utilizes the selection signal S SEL The pattern generation circuit 220 is required to provide test data DT. I Access address AD I and control commands CM I Pre-stored circuit 122. When the characteristic parameters of the mode selection signal MBE meet a third preset condition, the controller 250 provides the address signal S. A and control signal S C At this time, the pattern generation circuit 220 generates the pattern according to the address signal S. A and control signal S C Generate access address AD I and control commands CM I In this example, controller 250 utilizes the selection signal S SEL The pattern generation circuit 220 is required to provide test data DT from an external test equipment. E Access address AD I and control commands CM I Pre-storage circuit 122.

[0075] This invention does not limit the circuit architecture of the controller 250. In this embodiment, the controller 250 includes combinational logic circuits 251 and 252 and a D-type flip-flop DF2. The combinational logic circuit 251 outputs a signal S. Q1 The system determines whether the storage circuit 122 is operating normally. When the storage circuit 122 malfunctions, the combinational logic circuit 251 decodes the abnormal signal into a corresponding abnormal status code and records the abnormal information in the D-type flip-flop DF2. For example, in self-test mode or mixed test mode, if data DT is read... R Inconsistent with test data DT I Output signal S Q1 It could be a high level. Conversely, if the data is read as DT... R Meets test data DT I Then the output signal S Q1 It could be a low level. Therefore, according to the output signal S Q1 The combinational logic circuit 251 can determine whether the storage circuit 122 is operating normally by checking the level of the signal.

[0076] In one possible embodiment, when the storage circuit 122 malfunctions, the combinational logic circuit 251 may generate a status signal S. TR This signal can be decoded into an anomaly notification signal (such as MBT) by the D-type flip-flop DF2 and combinational logic circuit 252 and sent to an external test instrument. In other embodiments, the D-type flip-flop DF2 records the number of anomalies in the storage circuit 122. In this embodiment, whenever the combinational logic circuit 251 detects a read data DT... R Then, the combinational logic circuit 251 generates a status signal S. TR .

[0077] The D-type flip-flop DF2 is triggered by the operating clock OPF and receives the status signal S. TR In this example, the D-type flip-flop DF2 will convert the status signal S... TR As an output signal S Q2 As shown in the figure, the input terminal D of the D-type flip-flop DF2 receives the status signal S. TR Its output terminal Q provides the output signal S Q2 Its clock terminal clk receives the operation clock OPF. In one possible embodiment, when the D-type flip-flop DF1 provides the output signal S Q1 When the combinational logic circuit 251 is in operation (i.e., the second cycle of the operating clock OPF), the D-type flip-flop DF2 provides the output signal S. Q2 Pre-combinatorial logic circuit 252.

[0078] The combinational logic circuit 252 outputs the signal S. Q2 , generating internal data S D Address signal S A Control signal S C and test output signal MBT. In one possible embodiment, whenever combinational logic circuit 252 receives output signal S Q2 The combinational logic circuit 252 then generates internal data S. D Address signal S A Control signal S C and a test output signal MBT. In some embodiments, the test output signal MBT is used to indicate whether the access of the storage circuit 122 is normal. In this example, the test access circuit 210 processes (e.g., encodes) the test output signal MBT to generate a test result UT. T External testing equipment (such as) Figure 1 (110).

[0079] For ease of explanation, combinational logic circuit 252 is referred to as a first combinational logic circuit, pattern generation circuit 220 as a second combinational logic circuit, comparison circuit 230 as a third combinational logic circuit, and combinational logic circuit 251 as a fourth combinational logic circuit. When the second combinational logic circuit outputs a test pattern (TST)... E TST I Or TST M When ), the storage circuit 122 generates a read data DT. R The third combinational logic circuit then reads the data DT. R Generates and provides test results S P / F The fourth combinational logic circuit is provided. Because there are many components between the storage circuit 122 and the fourth combinational logic circuit, and each component has a fixed delay time, the fourth combinational logic circuit needs to wait a long time before receiving the test result S. P / F .

[0080] However, the test result S is temporarily stored in register 240. P / F This shortens the self-test cycle of the device under test 120, thereby increasing the speed of self-testing. For example, in the first cycle of the operating clock OPF, the first to third combinational logic circuits operate, thus generating the first test result. In the second cycle of the operating clock OPF (lagging behind and adjacent to the first cycle), the D-type flip-flop DF1 stores the first test result and uses the first test result as the output signal S. Q1 and provides output signal S Q1 The fourth combinational logic circuit (i.e., 251) is then activated. At this time, the first to third combinational logic circuits operate, thus generating the second test result. In the third cycle of the operating clock OPF (lagging behind and adjacent to the second cycle), the D-type flip-flop DF1 stores the second test result and uses it as the output signal S. Q1 and provides output signal S Q1 The fourth combinational logic circuit (i.e., 251) is then applied. At this time, due to the operation of the first to third combinational logic circuits, a third test result is generated, and the D-type flip-flop DF1 stores the third test result in the fourth cycle of the operating clock OPF (lagging behind and adjacent to the third cycle).

[0081] In this embodiment, by temporarily storing the previous test result through the D-type flip-flop DF1, the first to third combinational logic circuits can immediately generate new test results without waiting for the fourth combinational logic circuit to complete its operation, thus shortening the work cycle. Furthermore, since the third combinational logic circuit outputs a single-bit test result S... P / F Therefore, only a single temporary register 240 is needed.

[0082] Figure 2BThis is another possible embodiment of the test circuit of the present invention. Figure 2B resemblance Figure 2A The difference is that, Figure 2B An additional temporary register 260 and a logic gate 270 have been added. The temporary register 260 is used to temporarily store the test result S. P / F In one possible embodiment, the temporary register 260 is a D-type flip-flop DF3. The D-type flip-flop DF3 receives the test result S according to the operating clock OPF. P / F and the test results S P / F As an output signal S Q3 In this embodiment, the input terminal D of the D-type flip-flop DF3 receives the test result S. P / F Its clock terminal clk receives the operation clock OPF, and its output terminal Q provides an output signal S. Q3 .

[0083] Logic gate 270 is coupled to the outputs of registers 240 and 260, and is based on the output signal S. Q1 and S Q3 This generates an output signal S. O This invention does not limit the type of logic gate 270. In one possible embodiment, logic gate 270 is an OR gate. When the output signal S... Q1 and S Q3 When it is high (e.g., when reading data DT) R Inconsistent with test data DT I / DT E The logic gate 270 outputs a high-level output signal S. O When the output signal S Q1 and S Q3 When the level is low, it indicates that data DT is being read. R Meets test data DT I / DT E Therefore, logic gate 270 outputs a low-level output signal S. O In this example, controller 250 determines the output signal S based on... O The level of the signal allows us to determine the reading of the data (DT). R Does it meet the test data DT? I / DT E .

[0084] In this embodiment, since both temporary registers 240 and 260 store the test result S P / F Therefore, if one of the registers 240 and 260 fails, the other can still output the test result S. P / F Logic gate 270. For example, when reading data DT R Does not meet test data DT I / DTE At that time, the output signal S Q1 and S Q3 It should be high. However, if register 240 malfunctions and generates a low-level output signal S... Q1 At that time, because the temporary register 240 still generates a high-level output signal S Q3 Therefore, logic gate 270 outputs a high-level output signal S. O .

[0085] Since registers 240 and 260 store the same test results, when one of registers 240 and 260 fails, the other can still normally store the test results. P / F As the output signal S Q1 or S Q3 The logic gate 270 is provided. Therefore, the controller 250 can determine the output signal S generated by the logic gate 270. O To determine whether the access operation of the storage circuit 122 is normal.

[0086] In other embodiments, logic gate 270 is an AND gate. When reading data DT... R Meets test data DT I / DT E At that time, the output signal S Q1 and S Q3 All are at a high level. Therefore, logic gate 270 outputs a high-level output signal S. O However, when reading data DT R Does not meet test data DT I / DT E At that time, the output signal S Q1 and S Q3 All are at low level. Therefore, logic gate 270 outputs a low-level output signal S. O .

[0087] Figure 3 This is another embodiment of the controller 250 of the present invention. As shown in the figure, the controller 300 includes combinational logic circuits 310 and 320 and a D-type flip-flop DF. 21 ~DF 2N The combinational logic circuit 310 outputs the mode selection signal MBE and the output signal S based on these parameters. O A series of data SI is used to determine whether the storage circuit 122 is operating normally. The combinational logic circuit 310 decodes the judgment result into a status code S. TR1 ~S TRN and output status code S TR1 ~S TRN Type D flip-flop DF 21 ~DF 2NDue to the characteristics of the combinational logic circuit 310 and... Figure 2A The characteristics of the combinational logic circuit 251 are similar, so they will not be described in detail here.

[0088] D-type flip-flop DF 21 ~DF 2N Triggered by the operating clock (OPF). Each D-type flip-flop receives a status code and uses it as an output signal. (The last sentence appears to be incomplete and possibly refers to a specific type of flip-flop, "DF.") 21 For example, the D-type flip-flop DF 21 The input terminal D receives the status code S. TR1 Its output terminal Q provides the output signal S Q21 Its clock input clk receives the operation clock OPF. Due to the D-type flip-flop DF... 21 ~DF 2N Characteristics and Figure 2A The characteristics of the D-type flip-flop DF2 are similar, so they will not be described in detail here.

[0089] The combinational logic circuit 320 outputs the signal S. Q21 ~S Q2N , generating internal data S D Address signal S A Control signal S C Test output signal MBT and selection signal S SEL Due to the characteristics of the combinational logic circuit 320 and... Figure 2A The characteristics of the combinational logic circuit 252 are similar, so they will not be described in detail here.

[0090] Unless otherwise defined, all terms herein (including technical and scientific terms) are as commonly understood by one of ordinary skill in the art to which this invention pertains. Furthermore, unless expressly stated otherwise, definitions of terms in general dictionaries should be interpreted as consistent with their meaning in the context of their respective technical fields, and not as idealized or overly formal expressions.

[0091] While the present invention has been disclosed above with reference to preferred embodiments, it is not intended to limit the invention. Those skilled in the art can make modifications and refinements without departing from the spirit and scope of the invention. For example, the systems, apparatus, or methods described in the embodiments of the present invention can be implemented in physical embodiments using hardware, software, or a combination of hardware and software. Therefore, the scope of protection of the present invention is determined by the foregoing claims.

Claims

1. A test circuit for testing a storage circuit, said storage circuit comprising a storage block, characterized in that, Also includes: A test access circuit for receiving a first access address, a first control command, external test data, and a mode selection signal; A controller for generating an address signal, a control signal, and internal data; A pattern generating circuit generates and provides test data to the storage circuit, and includes: A data generator generates internal test data based on the internal data; A first selection circuit, when a selection signal is at a first level, uses the internal test data as the test data, and when the selection signal is at a second level, uses the external test data as the test data; An address generator generates a second access address based on the address signal; A second selection circuit, when the selection signal is at the first level, outputs the second access address to the storage circuit, and when the selection signal is at the second level, outputs the first access address to the storage circuit; A control generator generates a second control command based on the control signal; and A third selection circuit, when the selection signal is at the first level, outputs the second control command to the storage circuit, and when the selection signal is at the second level, outputs the first control command to the storage circuit, wherein the storage circuit writes the test data into the storage block and reads the storage block to generate read data; A comparison circuit compares the test data and the read data to generate a test result; and A first temporary register is used to temporarily store the test results; in: The controller determines whether the storage circuit is functioning correctly based on the test results stored in the first register. When the characteristic parameters of the mode selection signal meet a first preset condition, the test access circuit commands the controller to stop providing the address signal, the control signal, and the internal data. This causes the pattern generation circuit to generate an access address, a control command, and the test data based on the first access address, the first control command, and the external test data, and to provide the access address, the control command, and the test data to the storage circuit. When the characteristic parameters of the mode selection signal meet a second preset condition, the test access circuit commands the controller to provide the address signal, the control signal, and the internal data, so that the pattern generation circuit generates the access address, the control command, and the test data according to the address signal, the control signal, and the internal data, and provides the access address, the control command, and the test data to the storage circuit.

2. The test circuit according to claim 1, characterized in that, The storage circuit is a static random access storage circuit.

3. The test circuit according to claim 1, characterized in that, The first register is a first D-type flip-flop. The first D-type flip-flop receives the test result according to an operating clock and provides the test result as a first output signal to the controller.

4. The test circuit according to claim 3, characterized in that, The controller includes: A first combinational logic circuit receives the first output signal, and when the first output signal indicates that the read data conforms to the test data, the first combinational logic circuit generates a status signal. A second type D flip-flop receives the status signal according to the operating clock, and uses the status signal as a second output signal; and A second combinational logic circuit generates the address signal, the control signal, and the internal data based on the second output signal.

5. The test circuit according to claim 4, characterized in that, When the first D-type flip-flop outputs the first output signal, the second D-type flip-flop outputs the second output signal.

6. The test circuit according to claim 1, characterized in that, Also includes: A second temporary register is used to temporarily store the test results, and A logic gate is coupled to the first register and the second register, and generates an output signal based on the test results stored in the first register and the second register. The controller determines whether the storage circuit is functioning correctly based on the output signal.

7. The test circuit according to claim 6, characterized in that, The logic gate is an OR gate.

8. An electronic device, characterized in that, include: A storage circuit, including a storage block; as well as A test circuit for testing the memory circuit, and includes: A test access circuit for receiving a first access address, a first control command, external test data, and a mode selection signal; A controller for generating an address signal, a control signal, and internal data; A pattern generating circuit generates and provides test data to the storage circuit, and includes: A data generator generates internal test data based on the internal data; A first selection circuit, when a selection signal is at a first level, uses the internal test data as the test data, and when the selection signal is at a second level, uses the external test data as the test data; An address generator generates a second access address based on the address signal; A second selection circuit, when the selection signal is at a first level, outputs the second access address to the storage circuit, and when the selection signal is at the second level, outputs the first access address to the storage circuit; A control generator generates a second control command based on the control signal; and A third selection circuit, when the selection signal is at a first level, outputs the second control command to the storage circuit, and when the selection signal is at the second level, outputs the first control command to the storage circuit, wherein the storage circuit writes the test data into the storage block and reads the storage block to generate read data; A comparison circuit compares the test data and the read data to generate a test result; and A first temporary register is used to temporarily store the test results; in: The controller determines whether the storage circuit is functioning correctly based on the test results stored in the first register. When the characteristic parameters of the mode selection signal meet a first preset condition, the test access circuit commands the controller to stop providing the address signal, the control signal, and the internal data. This causes the pattern generation circuit to generate an access address, a control command, and the test data based on the first access address, the first control command, and the external test data, and to provide the access address, the control command, and the test data to the storage circuit. When the characteristic parameters of the mode selection signal meet a second preset condition, the test access circuit commands the controller to provide the address signal, the control signal, and the internal data, so that the pattern generation circuit generates the access address, the control command, and the test data according to the address signal, the control signal, and the internal data, and provides the access address, the control command, and the test data to the storage circuit.

9. The electronic device according to claim 8, characterized in that, The storage circuit is a static random access storage circuit.

10. The electronic device according to claim 8, characterized in that, The first register is a first D-type flip-flop. The first D-type flip-flop receives the test result according to an operating clock and provides the test result as a first output signal to the controller.

11. The electronic device according to claim 10, characterized in that, The controller includes: A first combinational logic circuit receives the first output signal, and when the first output signal indicates that the read data conforms to the test data, the first combinational logic circuit generates a status signal. A second type D flip-flop receives the status signal according to the operating clock, and uses the status signal as a second output signal; and A second combinational logic circuit generates the address signal, the control signal, and the internal data based on the second output signal.

12. The electronic device according to claim 11, characterized in that, When the first D-type flip-flop outputs the first output signal, the second D-type flip-flop outputs the second output signal.

13. The electronic device according to claim 8, characterized in that, Also includes: A second temporary register is used to temporarily store the test results, and A logic gate is coupled to the first register and the second register, and generates an output signal based on the information stored in the first register and the second register. The controller determines whether the storage circuit is functioning correctly based on the output signal.

14. The electronic device of claim 13, wherein the logic gate is an OR gate.

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