Method for forming semiconductor element and integrated circuit thereof

Abstract

A method for forming a semiconductor device and an integrated circuit thereof, providing a method for forming a line end extension region and a device having a line end extension region. In some embodiments, a method includes forming a patterned photoresist on a first region of a hard mask layer. A line end extension region is formed in the hard mask layer. The line end extension region extends laterally outward from the end of the first region of the hard mask layer. The line end extension region can be formed by changing the physical properties of the hard mask layer in the line end extension region.

Description

Technical Field

[0001] Some embodiments of the present disclosure relate to methods of forming semiconductor devices and integrated circuits thereof. Background Art

[0002] Advances in the manufacturing of semiconductor integrated circuits (ICs) have resulted in increased performance density (i.e., the number of interconnected components per chip area) and reduced geometry (i.e., the smallest component (or line) that can be produced using a manufacturing process). Increasing performance density while reducing geometry generally provides benefits by increasing production efficiency and reducing associated costs. However, advances in the size and density of components or parts are accompanied by increased complexity in the design and manufacture of these IC components.

[0003] For example, reducing the size and spacing of IC features defined and formed on a semiconductor substrate typically involves using a plurality of different photolithography masks and performing a sawing process to obtain the patterned features utilized in the IC. Summary of the invention

[0004] Some embodiments of the present disclosure provide a method of forming a semiconductor device, comprising: forming a patterned photoresist on a first region of a hard mask layer. Forming a line end extension region in the hard mask layer. The line end extension region extends laterally outward from an end of the first region of the hard mask layer. Forming the line end extension region includes changing a physical property of the hard mask layer in the line end extension region.

[0005] Other embodiments of the present disclosure provide methods of forming a semiconductor device, including: forming a hard mask layer on a target layer, the target layer being disposed between a substrate and the hard mask layer; forming a patterned photoresist on a plurality of first regions of the hard mask layer; forming a plurality of line end extension regions extending outwardly from the ends of the first regions by irradiating the hard mask layer with a plurality of ion beams, each of the ion beams having a non-zero ion beam angle relative to a direction orthogonal to the hard mask layer, the patterned photoresist blocking at least a portion of the ion beams from reaching the line end extension regions; removing the patterned photoresist; exposing a portion of the target layer by removing a portion of the hard mask layer outside the first region and the line end extension region; and forming a patterned feature in the target layer by removing the exposed portion of the target layer.

[0006] Still other embodiments of the present disclosure provide an integrated circuit, comprising: a substrate and a plurality of patterned features on the substrate, wherein each of the patterned features is formed of the same material, wherein a distance between an end of a first patterned feature of the patterned features and an end of a second patterned feature of the patterned features is less than 25 nanometers. BRIEF DESCRIPTION OF THE DRAWINGS

[0007] The aspects of the present disclosure can be better understood from the following detailed description when read in conjunction with the accompanying drawings. It should be noted that, in accordance with standard industry practice, various features are not drawn to scale. In fact, the dimensions of various features may be arbitrarily increased or reduced for clarity of discussion.

[0008] Figures 1 to 8 is a schematic diagram of a method for manufacturing an integrated circuit according to some embodiments of the present disclosure;

[0009] Fig. 9 According to some embodiments of the present disclosure, the modified Figures 1 to 8 The described method, schematic diagram of the patterned features formed;

[0010] Fig.10 is a top view of a component according to some embodiments of the present disclosure.

[0011]

Explanation of symbols

[0012] 10:Substrate

[0013] 12: Target layer

[0014] 14: Hard mask layer

[0015] 16: Photoresist

[0016] 20: Ions

[0017] 22: Direction

[0018] 31: First Area

[0019] 32: Second Area

[0020] 33: Non-impact area

[0021] 42: First etching gas

[0022] 52: Second etching gas

[0023] 112: Patterned features

[0024] 201: Part 1

[0025] 202: Part 2

[0026] 212: Patterned Features

[0027] 300: Components

[0028] 312: Patterned features

[0029] 312a: Part

[0030] 312b: Partial

[0031] 332a: Part

[0032] 332b: Partial

[0033] L1: Length

[0034] L2: Length

[0035] h: height

[0036] G1: Clearance

[0037] G2: Gap

[0038] θ: ion beam angle DETAILED DESCRIPTION

[0039] The following disclosure provides many different embodiments or examples for implementing the different features of the provided subject matter. The following describes specific embodiments of components and arrangements to simplify the present disclosure. Of course, these are only embodiments and are not intended to be restrictive. For example, in the following description, a first feature is formed on or on a second feature and may include an embodiment in which the first feature and the second feature are formed as direct contacts, and may also include an embodiment in which an additional feature may be formed between the first feature and the second feature so that the first feature and the second feature may not be in direct contact. In addition, the present disclosure may repeat element symbols and / or letters in various embodiments. This repetition is for simplification and clarity purposes, and does not itself represent the relationship between the various embodiments and / or configurations discussed.

[0040] Additionally, to simplify the description, spatially relative terms such as "below," "beneath," "lower," "above," "upper," and the like may be used herein to describe the relationship of one element or feature to another (additional) element or feature as depicted in the figures. These spatially relative terms are intended to encompass different orientations of the elements in use or operation in addition to the orientation depicted in the figures. The device may be otherwise oriented (rotated 90 degrees or at other orientations) and the spatially relative descriptors used herein should likewise be interpreted accordingly.

[0041] The deposition techniques described in the specification for depositing dielectric layers, metals or any other materials may include chemical vapor deposition (CVD), low-pressure chemical vapor deposition (LPCVD), metal organic chemical vapor deposition (MOCVD), plasma-enhanced chemical vapor deposition (PECVD), plasma vapor deposition (PVD), atomic layer deposition (ALD), molecular beam epitaxy (MBE), electroplating, electroless plating, etc. Specific embodiments are described herein with reference to examples of such processes. However, the present disclosure and the specific deposition techniques referenced are not limited to the described contents.

[0042] The etching techniques described in the specification for selectively removing semiconductor materials, dielectric materials, metals or any other materials may refer to processes including dry etching, wet chemical etching, reactive ion (plasma) etching (RIE; ReactiveIon Etching), washing, wet cleaning, pre-cleaning, spray cleaning, chemical-mechanical planarization (CMP; Chemical-Mechanical Planarization), etc. Specific implementations are described herein with reference to examples of such processes. However, the present disclosure and the specific etching techniques referenced are not limited to the described contents.

[0043] As the size or dimensions of features formed in integrated circuits decrease, the spacing, distance or gap between the ends of adjacent features may be limited by the limitations of the process steps used to form the features. For example, the lithography and sawing processes used to fabricate patterned features of integrated circuits have lower limits on the spacing between features that can be practically achieved. These lower limits may be defined by the dimensions of the photomasks that are physically produced based on the layout of the integrated circuit.

[0044] As described herein, the present disclosure provides methods and devices for forming line-end extension regions of patterned features at the ends of feature lines, thereby facilitating reducing distances or gaps between patterned features of an integrated circuit. In some embodiments, the line-end extension regions can be formed without requiring additional cut layers (and corresponding additional masking processes) that may be relied upon to form the line-end extension regions in other techniques.

[0045] In view of the above, various embodiments of the present disclosure relate to methods and elements for forming line end extension regions in a hard mask layer by directed impact of an ion beam. The ion beam may be at least partially blocked to avoid reaching the line end extension region of the hard mask layer. The line end extension region may be an area extending laterally outward from the end of a patterned photoresist on the hard mask layer, and the patterned photoresist blocks at least some of the ion beam from reaching the line end extension region. For example, the line end extension region may be a shadow region that receives a lower concentration or fewer ions than other areas of the hard mask layer. The ions may change the physical properties of the hard mask layer, such as selectivity to an etchant. Thus, unblocked areas of the hard mask layer may be easily removed by an etchant, while the line end extension region of the hard mask layer (and areas covered by the patterned photoresist) may be retained and used to pattern a target layer. Thus, patterned features may be formed in a self-aligned manner, wherein the patterned features include areas corresponding to the line end extension region of the hard mask layer. This helps to achieve a significant reduction in the gaps between patterned features.

[0046] Figures 1 to 8 1 is a schematic diagram of a method for manufacturing an integrated circuit according to one or more embodiments of the present disclosure. Additional steps may be provided before, during, and after the method, and in other embodiments, some of the steps described in the method may be replaced or eliminated.

[0047] like Figure 1 As shown, a hard mask layer 14 is formed on the target layer 12. The hard mask layer 14 can be any suitable hard mask, including a mask material used to protect the underlying area (e.g., of the target layer 12) during processing. Suitable materials for the hard mask layer 14 can include dielectric materials (e.g., semiconductor oxides, semiconductor nitrides, semiconductor oxynitrides, semiconductor carbides, metal oxides, other metal compounds, etc.), metals, metal alloys, polysilicon, and / or other suitable materials. In some embodiments, the hard mask layer 14 is a silicon nitride film.

[0048] The hard mask layer 14 may be formed by any suitable process, including, for example, deposition, anodization, thermal oxidation, etc. In some embodiments, the hard mask layer 14 is formed by a deposition process. The deposition process may be any suitable deposition process for depositing a hard mask layer, including, for example, chemical vapor deposition (CVD), low pressure chemical vapor deposition (LPCVD), plasma enhanced chemical vapor deposition (PECVD), plasma vapor deposition (PVD), atomic layer deposition (ALD), etc.

[0049] A target layer 12 is formed on a substrate 10. The substrate 10 may be any suitable substrate, such as any suitable semiconductor substrate. In various embodiments, the substrate 10 may be formed of a crystalline semiconductor material, such as single crystal silicon, polycrystalline silicon, or some other type of crystalline semiconductor material. In some embodiments, the substrate 10 is a silicon substrate; however, the embodiments provided herein are not limited thereto. For example, in various embodiments, the substrate 10 may include gallium arsenide (GaAs), gallium nitride (GaN), silicon carbide (SiC), or any other semiconductor material. The substrate 10 may include a variety of doping configurations depending on the design specifications. In some embodiments, the substrate 10 is a p-type substrate having a certain concentration of p-type dopants. In other embodiments, the substrate 10 is an n-type substrate having a certain concentration of n-type dopants.

[0050] In various embodiments, substrate 10 may have a substantially homogeneous composition, or may include multiple layers. Each layer may have a similar or different composition, and in some embodiments, some substrate layers have a non-homogeneous composition to induce device strain, thereby tuning device performance. Examples of layered substrates include silicon-on-insulator (SOI) substrates. In some embodiments, a layer of substrate 10 may include an insulator, such as a semiconductor oxide, a semiconductor nitride, a semiconductor oxynitride, a semiconductor carbide, and / or other suitable insulator materials.

[0051] The target layer 12 can be a layer of any material that is patterned to form one or more features of an integrated circuit. The line end extension region is formed in or by the target layer 12, which will be further discussed below. In some embodiments, the target layer 12 can be a dielectric layer, such as a dielectric layer containing or formed by an oxide, a nitride, a silicon oxide (SiOx), a silicon oxynitride (SiON), a silicon nitride (SiN), etc. In some embodiments, the target layer 12 can be a semiconductor layer, such as silicon (Si), gallium arsenide (GaAs), gallium nitride (GaN), silicon carbide (SiC), or any other semiconductor material. In some embodiments, the target layer 12 can be a conductive layer, such as copper (Cu) or a layer of any other metal or conductive material. The material used for the target layer 12 can be selected as desired, for example, depending on the specific features to be formed by patterning the target layer 12. In various embodiments, the features formed from the target layer 12 may include, for example, semiconductor fins of a Fin Field-Effect Transistor (FinFET) device, gate features, conductive traces or vias, or any other features of an integrated circuit.

[0052] The target layer 12 can be formed by any suitable process including, for example, depositing a dielectric layer, a metal or any other material, including the following processes: chemical vapor deposition (CVD), low pressure chemical vapor deposition (LPCVD), metal organic chemical vapor deposition (MOCVD), plasma enhanced chemical vapor deposition (PECVD), plasma vapor deposition (PVD), atomic layer deposition (ALD), molecular beam epitaxy (MBE), electroplating, electroless plating, etc.

[0053] like Figure 2 As shown, a photoresist 16 is patterned on the hard mask layer 14, for example using photolithographic exposure, wherein selected areas of the photoresist 16 are exposed to radiation using a mask. The exposure causes a chemical reaction to occur in the exposed areas of the photoresist 16. After exposure, a developer is applied to the photoresist 16. The developer dissolves or removes the exposed areas in the positive photoresist development process, or the unexposed areas in the negative photoresist development process. Suitable positive developers include tetramethyl ammonium hydroxide (TMAH), KOH, and NaOH, and suitable negative developers include solvents such as butyl acetate, ethanol, hexane, benzene, and toluene. In various embodiments, the patterned photoresist 16 remaining after the development process has a shape that substantially corresponds to the shape of the feature defined in the target layer 12. However, the ends (e.g., line ends) of the features defined in the target layer 12 will extend laterally beyond the ends of the patterned photoresist 16.

[0054] like Figure 2 As shown, ions 20 are implanted into the hard mask layer 14. Implantation of the ions 20 (e.g., by ion bombardment) causes one or more properties of the hard mask layer 14 to change in the region where the ions 20 are implanted. In some embodiments, the implanted ions 20 change (e.g., increase) the selective etch rate of the hard mask layer 14 when exposed to a suitable etchant. In some embodiments, the ions 20 include an element from the group consisting of nitrogen (N), tellurium (Te), boron (B), gallium (Ga), phosphorus (P), arsenic (As), argon (Ar), krypton (Kr), and xenon (Xe), or are formed from an element from the foregoing group.

[0055] The ions 20 are implanted into the hard mask layer 14 and can be implanted, for example, by directional implantation of an ion beam that radiates at a specific angle relative to the hard mask layer 14. In some embodiments, the ions 20 are directed toward the hard mask layer 14 by an ion beam that is non-orthogonal relative to the hard mask layer 14. For example, in some embodiments, the ions 20 are radiated toward the hard mask layer 14 at an ion beam angle θ relative to a direction 22 that is orthogonal to the hard mask layer 14. Figure 2 In the example shown, it is possible to provide Figure 2 As shown, for example, an ion beam having an ion beam angle θ from right to left and from left to right).

[0056] like Figure 2 As shown, ions 20 are impacted or implanted into the hard mask layer 14 to form a first region 31 that is impacted by all ions and a second region 32 that is impacted by some ions. The second region 32 of the hard mask layer 14 is only partially impacted by the ions 20, so the photoresist 16 blocks at least some of the directed ion beam from reaching the second region 32 of the hard mask layer 14. That is, the second region 32 can be a shadow region or a region of the hard mask layer 14 that is shielded from receiving the entire directed ion beam due to the presence of the photoresist 16. In some embodiments, the first region 31 of the hard mask layer 14 can be completely unprotected, otherwise it would be shielded from receiving the ion beam, so the first region 31 can be said to receive 100% of the impact of the ions 20. The second region 32 can receive any portion of the impact of the ions 20, such as 90% or less, 75% or less, 50% or less, or 25% or less of the impact of the ions 20. The amount or percentage of hits received by the second region 32 from the ions 20 should be less than the amount or percentage of hits received by the first region 31, so that one or more properties of the first region 31 are changed relative to the second region 32, as discussed below, and may include a change in selectivity to the etchant. For example, by receiving less than all hits (e.g., less than 90%, less than 75%, less than 50%, or less than 25%), the second region 32 may be less susceptible to removal by the etchant than the first region 31 receiving 100% of the hits from the ions 20. Other factors that may affect the change in selectivity to the etchant due to a reduction or partial hit of the ions 20 include, for example, the material of the hard mask layer 14, the ion species, the etchant used, etc. In some embodiments, receiving a portion of the impact of ions 20 (e.g., 90% or less, 75% or less, 50% or less, or 25% or less) promotes a significant difference in properties between the second region 32 and the first region 31 (receiving 100% of the impact), so that the first region 31 can be easily removed (e.g., by an etchant) while the second region 32 is at least partially retained.

[0057] In some embodiments, Figure 2 As shown, the second regions 32 may be said to receive 50% of the impacts of the ions 20 because each of the second regions 32 receives only one impact from a particular direction (eg, Figure 2 As shown, for example, ions 20 of ion beams from right to left and from left to right) are blocked by photoresist 16, while ions 20 from other ion beams are blocked. In this article, second regions 32 may be referred to as line end extension regions because these regions will effectively extend the line ends of features formed in target layer 12, as will be discussed further below.

[0058] The line end extension region (second region 32) may have a length L1 (eg, Figure 2In the horizontal direction shown in FIG. 1 ), this length depends on the ion beam angle θ and the height h of the photoresist 16. In some embodiments, the length L1 of the line end extension region (the second region 32) can be provided by the following formula:

[0059] L1=h×tanθ

[0060] Thus, the line end extension region (second region 32) can be formed to have any desired length L1, for example, by selectively forming the height h of the photoresist 16 suitable for forming the length L1 of the desired line end extension region (second region 32), and / or by selectively irradiating the hard mask layer 14 with an ion beam having a specific ion beam angle θ suitable for forming the length L1 of the desired line end extension region (second region 32). The area below the photoresist 16 can have any desired length L2, which can depend on the desired feature length of the patterned features formed by the methods described herein. The total length of the patterned features to be formed is equal to the length L2 plus twice the length L1 of the line end extension region (second region 32).

[0061] In some embodiments, photoresist 16 has a thickness or height h of less than 100 nanometers. In some embodiments, photoresist 16 has a height h of less than 75 nanometers. In some embodiments, photoresist 16 has a height h in a range of about 20 nanometers to about 50 nanometers.

[0062] In some embodiments, the hard mask layer 14 has a thickness of less than 100 nanometers. In some embodiments, the hard mask layer 14 has a thickness of less than 50 nanometers. In some embodiments, the hard mask layer 14 has a thickness in a range of about 10 nanometers to about 20 nanometers.

[0063] In some embodiments, target layer 12 has a thickness of less than 100 nanometers. In some embodiments, target layer 12 has a thickness of less than 50 nanometers. In some embodiments, target layer 12 has a thickness in a range of about 20 nanometers to about 35 nanometers.

[0064] In some embodiments, the ion beam angle θ is less than about 85°. In some embodiments, the ion beam angle θ is less than 80°. In some embodiments, the ion beam angle θ is greater than 30°. In some embodiments, the ion beam angle θ is in the range of about 30° to about 85°. In some embodiments, the ion beam angle θ is in the range of about 50° to about 80°. As discussed above, the length L1 of the line end extension region (the second region 32) depends at least in part on the height h of the photoresist 16 and the ion beam angle θ. By irradiating the ions 20 at an ion beam angle θ in the range of about 30° to about 85°, a line end extension region (the second region 32) having an appropriate length L1 can be formed, and the ions 20 can be effectively implanted into the hard mask layer 14. Outside the range described herein, the ions 20 may not be effectively implanted into the hard mask layer 14, which may result in insufficient changes in one or more properties of the first region 31 of the hard mask layer 14. For example, by irradiating ions 20 at an ion beam angle θ of less than about 30°, the first region 31 may not receive implanted ions 20 suitable for changing the selectivity of the first region 31 to the etchant. On the other hand, by irradiating ions 20 at an ion beam angle θ of greater than about 85°, the length L1 of the line end extension region (second region 32) may be limited because the photoresist 16 will need to have a relatively high height h in order to provide the desired length L1 of the line end extension region (second region 32).

[0065] The ions 20 are implanted into the hard mask layer 14 to change one or more physical properties of the hard mask layer 14. In some embodiments, the ions 20 are implanted into the first region 31 of the hard mask layer 14 to reduce resistance to etching of the first region 31, so that the first region 31 of the hard mask layer 14 can be more easily removed by an etching process than portions of the hard mask layer 14 that are not irradiated with the ions 20 or receive a lower percentage of ion 20 impacts. That is, the first region 31 can be more easily removed by etching than the second region or line end extension region (second region 32).

[0066] In some embodiments, the ions 20 are implanted at an appropriate energy so that the ions 20 pass through at least half of the hard mask layer 14. In some embodiments, the ions 20 are implanted at an energy of 25 keV to 250 keV. In some embodiments, the ions 20 are implanted in the first region 31 at a concentration of about 1012 to 1015 ions / cm2, and the ions 20 are implanted in the line end extension region (second region 32) at a concentration less than the concentration of the ions 20 implanted in the first region 31. In some embodiments, the ions 20 are implanted in the line end extension region (second region 32) at a concentration less than 25% compared to the concentration of the ions 20 implanted in the first region 31. In some embodiments, the ions 20 are implanted in the line end extension region (second region 32) at a concentration less than 50% compared to the concentration of the ions 20 implanted in the first region 31. In some embodiments, the ions 20 are implanted in the line end extension region (second region 32) at a concentration less than 75% compared to the concentration of the ions 20 implanted in the first region 31. The concentration of ions 20 implanted into the first region 31 and into the line end extension region (second region 32) may be selected based on a variety of factors including, for example, a desired change in a property (e.g., etch rate) of the line end extension region (second region 32) of the hard mask layer 14 compared to the first region 31.

[0067] The ratio of the etching rates r1 / r2 for respectively etching the first region 31 and the second region or the line end extension region (second region 32) of the hard mask layer 14 can be selected as desired, for example, depending on design considerations. In some embodiments, the ratio of the etching rates can depend at least in part on a variety of factors, such as the type of ions 20, the duration of the ion impact, the concentration of the ions 20 during the ion impact, the etchant used, or other factors. In some embodiments, the ratio of the etching rates r1 / r2 can be greater than 1.5, greater than 2.0, greater than 3.0, or greater than 5.0.

[0068] like Figure 3 As shown, the photoresist 16 is removed after the ions strike the hard mask layer 14. The photoresist 16 can be removed by any suitable technique. In some embodiments, the photoresist 16 is removed by a wet etching process. In some embodiments, the photoresist 16 can be removed by any photoresist removal technique using any organic removal, inorganic removal, or dry removal chemistry.

[0069] Once the photoresist 16 is removed, the non-hit region 33 of the hard mask layer 14 is exposed. The non-hit region 33 is a region that exists below the photoresist 16, and the photoresist 16 blocks the ions 20 from reaching the non-hit region 33. Therefore, the non-hit region 33 may have greater resistance to etching than the first region 31 of the hard mask layer 14. In some embodiments, the non-hit region 33 may have greater resistance to etching than the line end extension region (second region 32) of the hard mask layer 14.

[0070] like Figure 4 As shown, the first region 31 of the hard mask layer 14 is removed. The first region 31 of the hard mask layer 14 can be removed by any suitable technique, including, for example, by wet etching, dry etching, reactive ion etching (RIE), ashing, or any other suitable etching method. In some embodiments, the first region 31 of the hard mask layer 14 is removed by a first etching gas 42, and the first etching gas 42 has an etching chemistry that is highly selective to the first region 31. For example, an etching gas having a higher etching rate for removing the first region 31 compared to removing the line end extension region (second region 32) and the non-impact region 33 of the hard mask layer 14 can be used. In some embodiments, the first region 31 of the hard mask layer 14 is removed by an etching gas including carbon tetrafluoride (CF4), difluoromethane (CH2F2), trifluoromethane (CHF3), other suitable etchants or combinations thereof.

[0071] like Figure 5 As shown, a portion of the target layer 12 from which the first region 31 of the hard mask layer 14 has been removed is exposed. Remaining on the target layer 12 are portions of the hard mask layer 14 that constitute the line end extension region (second region 32) and the non-impact region 33. After the first region 31 of the hard mask layer 14 is removed, the thickness of the line end extension region (second region 32) is reduced. For example, the etching gas used to remove the first region 31 of the hard mask layer 14 may also remove portions of the line end extension region (second region 32), thereby reducing the thickness or height of the line end extension region (second region 32). However, as discussed previously, the line end extension region (second region 32) is etched at a lower rate than the first region 31 of the hard mask layer 14 because the line end extension region (second region 32) receives a lower percentage or proportion of ions 20 during ion impact (see Figure 2 ). Therefore, the line end extension region (second region 32) is etched at a slower or lower rate than the first region 31. Therefore, the thickness of the line end extension region (second region 32) may be reduced during etching; however, the surface area of ​​the line end extension region (second region 32) may remain substantially the same.

[0072] The non-impact regions 33 may maintain substantially the same size after the hard mask layer 14 is removed as described above. For example, the etching rate of the non-impact regions 33 of the hard mask layer 14 is not reduced because the non-impact regions 33 are protected from the impact of the ions 20. Therefore, the use of an etchant to remove the first regions 31 of the hard mask layer 14 does not substantially affect the non-impact regions 33. However, it should be understood that in various embodiments, the removal of the first regions 31 of the hard mask layer 14 by, for example, an etching gas may result in a reduction in the thickness of the non-impact regions 33.

[0073] like Figure 6 As shown, the target layer 12 is patterned by transferring the pattern of the remaining hard mask layer 14 (e.g., the non-hit region 33 and the line end extension region (second region 32)) to the target layer 12. For example, the target layer 12 is patterned by removing portions of the target layer 12 that are exposed or not covered by the non-hit region 33 or the line end extension region (second region 32) of the hard mask layer 14. The exposed portions of the target layer 12 may be removed by any suitable technique, including, for example, by wet etching, dry etching, RIE, ashing, or any other suitable etching method. In some embodiments, the exposed portions of the target layer 12 are removed by a second etching gas 52, wherein the second etching gas 52 has an etching chemistry that is highly selective to the target layer 12. For example, the second etching gas 52 may be used to remove the exposed portions of the target layer 12 while retaining the line end extension region (second region 32) and the non-hit region 33 of the hard mask layer 14. In some embodiments, the second etching gas 52 is different from the first etching gas 42 used to remove the first region 31 of the hard mask layer 14 (see Figure 4 ). The second etching gas 52 may be selected as desired, for example, due to design considerations. In some embodiments, the second etching gas 52 may be selected based on the composition of the target layer 12. For example, the etching gas used to remove the target layer formed of a dielectric material may be different from the etching gas used to remove the target layer formed of a conductive material.

[0074] like Figure 7 As shown, patterned features 112 are formed by patterning the target layer 12. After removing the exposed portion of the target layer 12, the patterned features 112 remain on the substrate 10, for example, as shown and described in Figure 6 The patterned feature 112 has substantially the same size as the non-impact region 33 and the line end extension region (second region 32). For example, the patterned feature 112 may have substantially the same length and width as the non-impact region 33 and the line end extension region (second region 32).

[0075] like Figure 8As shown, the non-impact area 33 and the line end extension area (second area 32) of the hard mask layer 14 can be removed. The non-impact area 33 and the line end extension area (second area 32) of the hard mask layer 14 can be removed by any suitable technique, including, for example, by wet etching, dry etching, RIE, ashing, or any other suitable etching method. In some embodiments, the non-impact area 33 and the line end extension area (second area 32) of the hard mask layer 14 are removed by a third etching gas, and the third etching gas has an etching chemistry that is highly selective to the hard mask layer 14. In some embodiments, the non-impact area 33 and the line end extension area (second area 32) of the hard mask layer 14 are removed by an etching gas, including carbon tetrafluoride (CF4), difluoromethane (CH2F2), trifluoromethane (CHF3), other suitable etchants or combinations thereof. In some embodiments, the third etching gas is the same as the first etching gas 42.

[0076] The patterned feature 112 may be any feature of an integrated circuit, including any conductive feature or semiconductor feature. In some embodiments, the patterned feature 112 may be a semiconductor fin of a FinFET element, a gate feature (such as a polysilicon or metal gate), a conductive trace or via, or any other feature of an integrated circuit.

[0077] The patterned features 112 can be formed to have any desired shape. For example, it should be readily understood that although the patterned features 112 are shown as having a linear shape with a length along one direction, other shapes can be formed in various embodiments using the methods described herein. For example, by utilizing the photolithography techniques described herein, the photoresist can be patterned to have any desired shape, and the hard mask layer can be ion implanted as described herein to form a line end extension region at the line end of the photoresist having any desired shape.

[0078] In some embodiments, a plurality of patterned features 112 can be formed adjacent to one another. Line end extension regions formed by ion implantation as described herein facilitate reducing gaps between adjacent or facing line ends of integrated circuit features.

[0079] Fig. 9 is a schematic diagram of a patterned feature 212 according to some embodiments of the present disclosure. The patterned feature 212 may be Figures 1 to 8 The method illustrated is substantially the same as that described above but includes some modifications. The patterned features 212 may be formed by performing Figures 1 to 7 As shown, but relative to Figure 8 There is a method of modification.

[0080] Specifically, if Fig. 9 As shown, it can be achieved by Figure 8The etching gas of the third etching gas described above removes the non-impact area 33 and the line end extension area (second area 32) of the hard mask layer 14. Fig. 9 In the illustrated embodiment, the non-impact area 33 and the line end extension area (second area 32) of the hard mask layer 14 can be removed by a fourth etching gas having a low or marginal selectivity between the hard mask layer 14 and the material of the target layer 12, rather than using a third etching gas having an etching chemistry with high selectivity to the hard mask layer 14.

[0081] Since the fourth etching gas has a low or marginal selectivity between the materials of the hard mask layer 14 and the target layer 12, the fourth etching gas can remove the corresponding portions of the hard mask layer 14 and the target layer 12 at similar or substantially the same rates. Therefore, before completely removing the thicker portions of the hard mask layer 14 (e.g., the non-impact regions 33), the thinner portions of the hard mask layer 14 (e.g., the line end extension regions (second regions 32)) can be completely removed by the etching gas. Before completely removing the non-impact regions 33, the line end extension regions (second regions 32) are removed, thereby exposing portions of the target layer 12 in the area of ​​the line end extension regions (second regions 32) that are removed first. Therefore, the resulting shape of the patterned feature 212 can be similar to the shape of the hard mask layer 14, for example Figure 7 For example, the patterned feature 212 may include: a first portion 201; and a second portion 202, wherein the second plurality of portions 202 extend laterally outward from the first portion 201. The first portion 201 of the patterned feature 212 may be referred to as a "natural line end", so the first portion 201 has a shape corresponding to the photoresist 16 (see Figure 2 ) and the dimensions (e.g., length and width) of the non-impact area 33 of the hard mask layer 14. The second portion 202 of the patterned feature 212 can be referred to as an "extended line end" portion because the second portion 202 has dimensions corresponding to the line end extension area (second area 32) of the hard mask layer 14.

[0082] Fig.10 is a plan view illustrating an element 300, which may be referred to herein, for example Figures 1 to 9 The device 300 may be an electronic device, such as an integrated circuit.

[0083] Component 300 includes a plurality of patterned features 312 formed on a substrate. Patterned features 312 may be formed according to methods described herein, for example, Figures 1 to 9 In various embodiments, patterned features 312 may include, for example, semiconductor device features such as heat sinks, gate features, conductive traces or vias of FinFET devices, or any other features of an integrated circuit.

[0084] At least some of the patterned features 312 may include natural line end portions 312a, 312b and line end extension region portions 332a, 332b. The line end extension region portions 332a, 332b may be formed, for example, by ion impact, as described above. The natural line end portions 312a, 312b represent portions of the patterned features 312 that are blocked by ion impact, for example, as described above in relation to the non-impact region 33. By utilizing the processes described herein (such as ion impact), the line end extension region portions 332a, 332b may be formed in a manner that helps reduce the end-to-end gap between the patterned features 312.

[0085] In some embodiments, a plurality of patterned features 312 may be formed based on a layout including a shape layout. The layout may be, for example, a data file stored on a non-transitory computer readable medium and represented in a design standard such as GDSII, OASIS, etc. The layout may be a digital representation of a component 300, wherein the component 300 may be an integrated circuit. The shapes of the layout may correspond to and define physical features of the component 300. More specifically, the shapes of the layout may define physical features, such as portions of the patterned features 312 of the component 300. However, the layout may be subject to the dimensions of a lithography process for manufacturing an integrated circuit based on the layout. For example, the gaps (or line end-to-end distances) between the shapes of the layout may be subject to the dimensions of a mask physically produced based on the layout. More specifically, the natural line end-to-end gaps G1 between the oriented shapes of the layout may be limited by the limitations of the lithography process, such as the dimensions of the mask that may be produced to form the shapes.

[0086] In some embodiments, a mask is formed based on the shape of the layout. As described, for example, relative to Figure 1 and Figure 2 , a hard mask layer is formed on the target layer, and a mask may be used to pattern the photoresist formed on the hard mask layer. The patterned photoresist may correspond to Fig.10 The patterned features 312 and the natural line end portions 312a and 312b shown in FIG. 1 and the minimum distance between the patterned photoresist (e.g., used to form the portions 312a and 312b) may be the natural line end-to-end gap G1. The line end extension region portions 332a and 332b of the patterned feature portions 312a and 312b may not be covered by the photoresist, and the line end extension regions 332a and 332b may be formed as described above, for example, by ion bombardment to form the line end extension regions in the hard mask, and then patterning the target layer to form the patterned features 312 including the line end extension region portions 332a and 332b.

[0087] By utilizing the processes described herein (such as, ion bombardment) to form the line end extension regions, the line end extension region portions 332a, 332b of the patterned features 312 can be formed to have a reduced line end-to-end gap G2 between the patterned features 312 compared to the natural line end-to-end gap G1 that is limited by the limitations of conventional photolithography processes.

[0088] In some embodiments, the line end-to-end gap G2 may be less than 25 nanometers. In some embodiments, the line end-to-end gap G2 may be less than 18 nanometers. In some embodiments, the line end-to-end gap G2 may be less than 14 nanometers. In some embodiments, the line end-to-end gap G2 may be less than 10 nanometers. In some embodiments, the line end-to-end gap G2 may be in the range of about 5 nanometers to about 25 nanometers. By forming the line end-to-end gap G2 within this range, the line ends of the patterned features 312 can be formed to be close to each other, thereby increasing the number of such patterned features 312 that can be formed within a given area, while having sufficient gaps or distances between the patterned features 312 to electrically isolate the patterned features 312 and prevent or reduce improper cross-coupling of the patterned features 312.

[0089] The size of the line end-to-end gap G2 is not limited to any specific size limit of the photolithography or cutting process. Instead, the gap G2 can be formed with a significantly reduced distance, where the significantly reduced distance is limited by the height h of the photoresist and the ion beam angle θ (as described above, for example Figure 2 ), each of the height h and the ion beam angle θ can be selected as needed to provide a desired length of the line end extension region and a desired gap G2 between the patterned features 312.

[0090] As previously described, patterned feature 312 may be any feature of an integrated circuit, including, for example, a semiconductor device feature such as a heat sink of a FinFET device, a gate feature, a conductive trace or via, or any other feature of an integrated circuit.

[0091] Should be easy to understand, Fig.10 The illustrated component 300 may be a portion or region of an integrated circuit, and in some embodiments, the component 300 may include various additional features, including, for example, additional patterned features 312 and any other features of an integrated circuit.

[0092] The present disclosure provides, in various embodiments, methods and devices for forming line-end extension regions of patterned features at the ends of feature lines, thereby facilitating a reduction in the distance or gap that can be achieved between patterned features of an integrated circuit. In some embodiments, the line-end extension regions can be formed without additional cutting layers (and corresponding additional masking processes) that may otherwise be relied upon to form the line-end extension regions in other techniques, providing a significant advantage in increasing the density of features formed in an integrated circuit.

[0093] According to one embodiment, a method includes forming a patterned photoresist on a first region of a hard mask layer. Forming a line end extension region in the hard mask layer. The line end extension region extends laterally outward from a terminal end of the first region of the hard mask layer. The line end extension region may be formed by changing a physical property of the hard mask layer in the line end extension region.

[0094] In one embodiment, the method further comprises: removing the patterned photoresist; and exposing a portion of the target layer by removing a portion of the hard mask layer outside the first region and the line end extension region.

[0095] In one embodiment, the physical property of the hard mask layer includes selectivity to the etching gas, wherein removing the portion of the hard mask layer includes etching the portion of the hard mask layer by the etching gas to remove the portion of the hard mask layer.

[0096] In one embodiment, the method further comprises: removing the exposed portion of the target layer.

[0097] In one embodiment, forming the line end extension region includes: implanting ions of a first ion concentration in the line end extension region of the hard mask layer; and implanting ions of a second ion concentration outside the line end extension region of the hard mask layer, wherein the second ion concentration is greater than the first ion concentration.

[0098] In one embodiment, forming the line end extension region in the hard mask layer includes irradiating the hard mask layer with an ion beam having a non-zero ion beam angle relative to a direction normal to the hard mask layer.

[0099] In one embodiment, the non-zero ion beam angle is less than about 85°.

[0100] In one embodiment, the non-zero ion beam angle is greater than about 30°.

[0101] In one embodiment, the non-zero ion beam angle is in the range of about 50° to about 80°.

[0102] In one embodiment, the ion beam includes ions formed of an element selected from the group consisting of nitrogen (N), tellurium (Te), boron (B), gallium (Ga), phosphorus (P), arsenic (As), argon (Ar), krypton (Kr) and xenon (Xe).

[0103] In one embodiment, the length of the line end extension region is based at least in part on the height of the patterned photoresist.

[0104] In one embodiment, the height of the patterned photoresist is in a range from about 20 nanometers to about 50 nanometers.

[0105] According to another embodiment, a method for forming a semiconductor element is provided, comprising: forming a hard mask layer on a target layer. Disposing the target layer between a substrate and the hard mask layer. Forming a patterned photoresist on a first region of a plurality of hard mask layers. Forming a plurality of line end extension regions extending outward from the ends of the plurality of first regions by irradiating the hard mask layer with a plurality of ion beams. Each of the ion beams has a non-zero ion beam angle relative to a direction orthogonal to the hard mask layer, and the patterned photoresist blocks at least a portion of the plurality of ion beams from reaching the plurality of line end extension regions. Removing the patterned photoresist. Exposing a portion of the target layer by removing a plurality of portions outside the plurality of first regions and the plurality of line end extension regions in the hard mask layer. Forming a patterned feature in the target layer by removing the exposed portion of the target layer.

[0106] In one embodiment, the step of forming the line end extension region includes: changing the selectivity of the hard mask layer to the etching gas in the line end extension region by irradiating the hard mask layer.

[0107] In one embodiment, removing portions of the hard mask layer outside the first region and the line end extension region includes exposing the hard mask layer to an etching gas having a lower selectivity to the line end extension region than to portions of the hard mask layer outside the first region and the line end extension region.

[0108] In one embodiment, forming the line-end extension region includes forming the line-end extension region to have a length substantially equal to h×tanθ, where h is a height of the patterned photoresist and θ is the non-zero ion beam angle.

[0109] According to yet another embodiment, an integrated circuit includes a substrate and a plurality of patterned features on the substrate. Each of the patterned features is formed of the same material. A distance between an end of a first patterned feature in the plurality of patterned features and an end of a second patterned feature in the plurality of patterned features is less than 25 nanometers.

[0110] In one embodiment, a distance between an end of the first patterned feature and an end of the second patterned feature is less than 10 nanometers.

[0111] In one embodiment, the patterned features include at least one of the following: semiconductor device features, polysilicon or metal gates, conductive traces, or conductive vias.

[0112] The foregoing summarizes the features of several embodiments so that those skilled in the art can better understand the aspects of the present disclosure. Those skilled in the art will appreciate that they can easily use the present disclosure as a basis for designing or modifying other processes and structures for achieving the same purposes and / or achieving the same advantages of the embodiments described herein. Those skilled in the art will also recognize that these equivalent constructions do not depart from the spirit and scope of the present disclosure, and that they can make various changes, substitutions, and replacements herein without departing from the spirit and scope of the present disclosure.

[0113] The various embodiments described above may be combined to provide further embodiments. These and other changes may be made to the embodiments in light of the above detailed description. In general, in the claims, the terms used should not be construed to limit the scope of the claims to the specific embodiments disclosed in the specification and claims, but should be construed to include all possible embodiments and the full scope of equivalents, the claims having the right of equivalents. Therefore, the claims are not limited by the present disclosure.

Claims

1. A method for forming a semiconductor device, characterized in that: include: forming a patterned photoresist on a region of a hard mask layer; irradiating the hard mask layer with an ion beam having a non-zero ion beam angle relative to a direction orthogonal to the hard mask layer to form a line end extension region in the hard mask layer, wherein an area of ​​the hard mask layer below the patterned photoresist is a non-impact region, and the patterned photoresist blocks the ion beam from reaching the non-impact region, and the line end extension region extends laterally outward from an end of the patterned photoresist, and the forming of the line end extension region includes changing a physical property of the hard mask layer in the line end extension region; removing the patterned photoresist; removing portions of the hard mask layer outside the non-impact region and the line end extension region to expose portions of a target layer not covered by the non-impact region or the line end extension region, and the non-impact region and the line end extension region remain on the target layer; as well as The patterns of the non-impact area and the line end extension area are transferred to the target layer by removing the exposed portions of the target layer to form a patterned feature in the target layer, wherein the patterned feature includes a first portion and a second portion located below the first portion, and the second portion extends laterally outward from the first portion.

2. The method according to claim 1, characterized in that The line end extension region has a length equal to h×tanθ, where h is a height of the patterned photoresist and θ is the non-zero ion beam angle.

3. The method according to claim 1, characterized in that The physical property of the hard mask layer includes a selectivity to an etching gas, wherein removing the portions of the hard mask layer includes etching the portions of the hard mask layer by the etching gas to remove the portions of the hard mask layer.

4. The method according to claim 1, characterized in that The forming of the line end extension region in the hard mask layer comprises: The patterned photoresist blocks the ion beam from reaching the line end extension area, so that the line end extension area is a shadow area that receives a lower concentration or fewer ions than the unblocked area of ​​the hard mask layer.

5. The method according to claim 4, characterized in that The line end extension area and the unblocked area have different selectivity to an etching gas.

6. The method according to claim 1, characterized in that The forming of the line end extension area comprises: Implanting ions of a first ion concentration in the line end extension region of the hard mask layer; and Ions with a second ion concentration are implanted outside the line end extension region of the hard mask layer, and the second ion concentration is greater than the first ion concentration.

7. The method according to claim 1, characterized in that The non-impact region has greater resistance to etching than the line end extension region.

8. The method according to claim 1, characterized in that The non-zero ion beam angle is less than 85°.

9. The method according to claim 1, characterized in that The non-zero ion beam angle is greater than 30°.

10. The method according to claim 1, characterized in that The non-zero ion beam angle is in a range of 50° to 80°.

11. The method according to claim 1, characterized in that The ion beam includes ions formed of an element selected from the group consisting of nitrogen, tellurium, boron, gallium, phosphorus, arsenic, argon, krypton, and xenon.

12. The method according to claim 1, characterized in that A length of the line end extension region is at least partially based on a height of the patterned photoresist.

13. The method according to claim 12, characterized in that The height of the patterned photoresist is in a range of 20 nanometers to 50 nanometers.

14. A method for forming a semiconductor device, characterized in that: include: forming a hard mask layer on a target layer, the target layer being disposed between a substrate and the hard mask layer; forming a patterned photoresist on a plurality of regions of the hard mask layer; forming a plurality of line end extension regions extending outwardly from a terminal end of the patterned photoresist by irradiating the hard mask layer with a plurality of ion beams, each of the ion beams having a non-zero ion beam angle relative to a direction normal to the hard mask layer, the region of the hard mask layer below the patterned photoresist being a non-impact region, and the patterned photoresist blocking at least a portion of the ion beams from reaching the line end extension regions; removing the patterned photoresist; Exposing portions of the target layer that are not covered by the non-impact area or the line-end extension areas by removing portions of the hard mask layer outside the non-impact area and the line-end extension areas, the non-impact area and the line-end extension areas remaining on the target layer; as well as The patterns of the non-impact area and the line end extension areas are transferred to the target layer by removing the exposed portions of the target layer to form a patterned feature in the target layer, wherein the patterned feature includes a first portion and a second portion located below the first portion, and the second portion extends laterally outward from the first portion.

15. The method according to claim 14, characterized in that The step of forming the line end extension regions includes: changing a selectivity of an etching gas in the line end extension regions of the hard mask layer by irradiating the hard mask layer.

16. The method according to claim 15, characterized in that The removing of the portions of the hard mask layer outside the non-impact region and the line end extension regions includes exposing the hard mask layer to an etching gas having a lower selectivity for the line end extension regions than for portions of the hard mask layer outside the non-impact region and the line end extension regions.

17. The method according to claim 15, characterized in that The forming of the line end extension regions includes forming the line end extension regions to have a length equal to h×tanθ, where h is a height of the patterned photoresist and θ is the non-zero ion beam angle.

18. An integrated circuit, characterized in that: include: a substrate; as well as A plurality of patterned features on the substrate, each of the patterned features being formed of a same material, each of the patterned features comprising a first portion and a second portion located below the first portion, and the second portion extending laterally outward from the first portion, A distance between an end of a first patterned feature among the patterned features and an end of a second patterned feature among the patterned features is less than 25 nanometers.

19. The integrated circuit of claim 18, wherein: The distance between the end of the first patterned feature and the end of the second patterned feature is less than 10 nanometers.

20. The integrated circuit of claim 18, wherein: The patterned features include at least one of: a semiconductor device feature, a polysilicon or metal gate, a conductive trace, or a conductive via.

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