Semiconductor packaging structure and manufacturing method thereof

Abstract

The present invention provides a semiconductor package structure. The semiconductor package structure includes a substrate, a first electronic component, and a support component. The first electronic component is disposed on the substrate. The first electronic component has a back surface facing a first surface of the substrate. The support component is disposed between the back surface of the first electronic component and the first surface of the substrate. The back surface of the first electronic component has a first portion connected to the support component and a second portion exposed from the support component.

Description

Technical Field

[0001] The present invention relates to a semiconductor packaging structure, in particular to a semiconductor packaging structure with an oscillator chip. Background Art

[0002] A crystal oscillator consists of a crystal unit composed of a quartz crystal blank hermetically encapsulated in a container, and an oscillation circuit using the crystal unit. Crystal oscillators are used as frequency and time reference sources in various electronic devices. One such crystal oscillator is an oven-controlled crystal oscillator (OCXO), which maintains a constant operating temperature for the crystal unit. Because the operating temperature of the crystal unit remains constant regardless of ambient temperature, OCXOs offer exceptionally high frequency stability and exhibit minimal frequency deviation. For example, such OCXOs are used in communications equipment such as base stations. Summary of the Invention

[0003] In some embodiments, a semiconductor package structure includes a substrate, a first electronic component, and a support component. The first electronic component is disposed on the substrate. The first electronic component has a back surface facing a first surface of the substrate. The support component is disposed between the back surface of the first electronic component and the first surface of the substrate. The back surface of the first electronic component has a first portion connected to the support component and a second portion exposed from the support component.

[0004] In some embodiments, a semiconductor package structure includes a substrate, a first electronic component, a first insulator, and a second insulator. The first electronic component is disposed on the substrate. The first electronic component has a back surface facing a first surface of the substrate. The first insulator and the second insulator are disposed between the back surface of the first electronic component and the first surface of the substrate. The equivalent thermal resistance of the first insulator and the second insulator is greater than the thermal resistance of the substrate.

[0005] In some embodiments, a method of manufacturing a semiconductor package structure includes (a) providing a ceramic substrate having a cavity; (b) disposing an insulator on a bottom surface of the cavity; and (c) disposing a first electronic component on the insulator, the back surface of the first electronic component having a first portion connected to the insulator and a second portion exposed from the insulator. BRIEF DESCRIPTION OF THE DRAWINGS

[0006] When read in conjunction with the accompanying drawings, aspects of the present invention will be readily understood from the following detailed description. It should be noted that the various features may not be drawn to scale. In fact, the dimensions of the various features may be arbitrarily increased or decreased for clarity of discussion.

[0007] Figure 1 A cross-sectional view of a semiconductor package structure according to some embodiments of the present invention is shown.

[0008] Figure 2A A cross-sectional view of a semiconductor package structure according to some embodiments of the present invention is shown.

[0009] Figure 2B A cross-sectional view of a semiconductor package structure according to some embodiments of the present invention is shown.

[0010] Figure 3 A cross-sectional view of a semiconductor package structure according to some embodiments of the present invention is shown.

[0011] Figure 4A 、 Figure 4B 、 Figure 4C 、 Figure 4C '、 Figure 4D and Figure 4E A method of manufacturing a semiconductor package structure according to some embodiments of the present invention is shown.

[0012] Figure 5A and Figure 5B A method of manufacturing a semiconductor package structure according to some embodiments of the present invention is shown. DETAILED DESCRIPTION

[0013] Throughout the drawings and detailed description, common reference numerals are used to indicate the same or similar components. Embodiments of the present invention will be more readily understood from the following detailed description taken in conjunction with the accompanying drawings.

[0014] Spatial descriptors such as "above," "below," "upward," "left," "right," "downward," "top," "bottom," "vertical," "horizontal," "side," "higher," "lower," "upper," "above," "below," and the like are directed to a component or group of components, or to a plane of a component or group of components, the orientation of which is as shown in the associated Figures. It should be understood that the spatial descriptors used herein are for illustrative purposes only, and that actual embodiments of the structures described herein may be spatially arranged in any orientation or manner, provided that the advantages of the embodiments of the present invention are not deviated from such arrangements.

[0015] In order to maintain the crystal unit in the OCXO at a constant temperature, a thermostat is usually used. As communication facilities become increasingly miniaturized, OCXOs also need to become smaller. OCXOs with microelectromechanical systems (MEMS) oscillators use complex stacked structures or high-cost materials to enhance temperature control capabilities. For example, the MEMS oscillator and oscillation circuit can be packaged on a ceramic cavity substrate and hermetically sealed by a lid on the ceramic cavity substrate. Because the thermal conductivity of ceramics is considered to be very high, for example, greater than 15W·m -1 ·K -1 (aluminum oxide), or greater than 150W·m -1 ·K -1(aluminum nitride), so the insertion has a lower thermal conductivity (e.g. about 1 W·m -1 ·K -1 An insulating layer of glass is used to separate the MEMS oscillator and the oscillation circuit from the ceramic cavity substrate in order to keep the crystal unit in the OCXO at a constant temperature. However, the implementation of the ceramic cavity substrate and the additional insulating layer increases the manufacturing cost.

[0016] Furthermore, the thermal conductivity of the insulating layer (eg, glass) is still insufficient to prevent heat loss from the crystal oscillator and the oscillation circuit, so that more power needs to be provided to maintain the crystal oscillator and the oscillation circuit at a constant temperature.

[0017] The present invention uses an air cavity or a vacuum cavity as a heat conduction blocking area to prevent heat loss in the crystal oscillator and the oscillation circuit. -1 ·K -1 The thermal conductivity of the organic substrate is substantially lower than that of insulating materials such as glass, so the heat loss of the crystal oscillator and the oscillation circuit can be effectively reduced. The thermal conductivity of a vacuum is even lower than that of air. In another aspect of the present invention, the present invention provides an organic substrate for packaging a crystal oscillator and an oscillation circuit. The polymer component of the organic substrate has a thermal conductivity lower than that of the ceramic substrate (<1 W·m -1 ·K -1 ) and is more economical than a ceramic cavity substrate and an additional insulating layer such as glass. For example, a substrate based on molding material has a power of about 0.8 to 1 W·m -1 ·K -1 The thermal conductivity of the polyimide substrate is about 0.1 to 0.2 W·m -1 ·K -1 The thermal conductivity of FR-4 substrate is about 0.3W·m -1 ·K -1 The thermal conductivity of the liquid crystal polymer (LCP) substrate is about 0.3 to 0.5 W·m -1 ·K -1 The thermal conductivity of the solder resist layer on the organic substrate is about 0.2 to 0.3 W·m -1 ·K -1 The combination of an organic substrate and an air cavity not only reduces manufacturing costs but also reduces the power consumption required to maintain a constant temperature for the crystal oscillator and oscillation circuit.

[0018] Figure 1 FIG. 1 is a cross-sectional view of a semiconductor package structure 1 according to some embodiments of the present invention. The semiconductor package structure 1 includes a substrate 10 , an insulator 11 , electronic components 12 , 13 , and a lid 14 .

[0019] The substrate 10 may be an organic substrate, including but not limited to a substrate based on a molding material, a polyimide substrate, an FR-4 substrate, a liquid crystal polymer (LCP) substrate, a cored substrate, a coreless substrate, or other substrates composed of organic small molecules or polymers. In some embodiments, the polymer component of the organic substrate has a power density of less than about 1 W·m -1 ·K -1 In some embodiments, substrate 10 defines a cavity 10c that accommodates thermal insulator 11 and electronic components 12 and 13. In some embodiments, substrate 10 has a stepped structure encircled by a dotted circle 10s. For example, substrate 10 has a top surface 101 and a top surface 102 that is not coplanar with top surface 101. For example, top surface 102 is recessed from top surface 101.

[0020] An insulator (also referred to as a thermal insulator or support member) 11 is disposed above the surface 103 of the substrate 10. The insulator 11 is disposed within a cavity 10c defined by the substrate 10. In some embodiments, the insulator 11 is connected to the surface 103 of the substrate 10 via an adhesive layer 11a (e.g., a die attach film (DAF)). In some embodiments, the thermal conductivity of the insulator 11 is equal to or lower than approximately 1.2 W·m -1 ·K -1 In some embodiments, the thermal conductivity of the insulator 11 is about 0.2 W·m -1 ·K -1 For example, the insulator 11 may include a glass material or any other suitable material.

[0021] The electronic component 12 is disposed above the insulator 11. In some embodiments, the electronic component 12 may be or include an active component, such as a bare die or chip. The electronic component 12 has a back surface facing the insulator 11 and an active surface opposite the insulator 11. In some embodiments, the back surface of the electronic component 12 is connected to the insulator via an adhesive layer 12a. In other embodiments, the back surface of the electronic component 12 directly contacts the insulator 11. In order to effectively provide thermal insulation for the electronic component 12, the width (or area) of the back surface of the electronic component 12 is equal to or less than the width (or area) of the insulator 11. For example, the back surface of the electronic component 12 is completely covered by the insulator 11 or the adhesive layer 12a.

[0022] Electronic component 12 may include control circuitry configured to control electronic component 13 and / or process signals received from electronic component 13. In some embodiments, electronic component 12 further includes a heat source region 12h proximate the active surface of electronic component 12. Heat source region 12h may include a resistor pattern exposed from the active surface and configured to conduct heat to an object in physical contact with it under the action of appropriate electrical power. In some embodiments, electronic component 12 may be electrically connected to substrate 10 via conductive wires 12w.

[0023] The electronic component 13 is placed above the electronic component 12. In some embodiments, the electronic component 13 is placed above the heat source area 12h of the electronic component 12. The electronic component 13 is electrically connected to the electronic component 12 via a conductive wire 13w. Of course, other electrical connections such as vias, conductive posts, or solder joints can also be used to electrically connect the electronic component 12, the electronic component 13, and the substrate 10. The electronic component 13 has an active surface facing away from the electronic component 12 and a back surface opposite to the active surface. In some embodiments, the back surface of the electronic component 13 is connected to or bonded to the active surface of the electronic component 12 via a bonding layer 13a (e.g., DAF). The bonding layer 13a may be thin enough to allow effective heat conduction between the heat source area 12h and the electronic component 13. The bonding layer 13a may also have a high thermal conductivity material.

[0024] In some embodiments, the electronic component 13 may be or include an oscillator, such as a crystal oscillator or a micro-electromechanical system (MEMS) oscillator chip that can be controlled by an underlying control chip (e.g., the electronic component 12). In some embodiments, the electronic component 12 is configured to maintain a constant temperature of the electronic component 13 by the heat source region 12h.

[0025] Lid 14 is disposed on top surface 101 of substrate 10, covering insulator 11, electronic components 12 and 13, and cavity 10c. In some embodiments, the space defined by lid 14 and cavity 10c is hermetically sealed. For example, the space is insulated from the exterior of semiconductor package structure 1, which can enhance thermal insulation of the space.

[0026] Figure 2A FIG. 2 shows a cross-sectional view of a semiconductor package structure 2A according to some embodiments of the present invention. The semiconductor package structure 2A is similar to Figure 1 The semiconductor package structure 1 is shown in FIG. 1 , and some differences therebetween are described below.

[0027] Figure 2A The substrate 10 in the embodiment may be or include a ceramic substrate. For example, the substrate 10 may be formed of Al2O3. In some embodiments, the thermal conductivity of the ceramic substrate is about 15 W·m -1 ·K -1 . Compared with organic substrates, ceramic substrates have higher stability. Organic substrates may have gas leakage problems. For example, at operating temperature, some organic gas may volatilize from the organic substrate, which will change the composition of the air in the space defined by the cover 14 and the substrate 10 and may adversely affect the performance of the electronic component 13 (for example, oscillation frequency accuracy). In addition, the volatilized organic gas may damage the components in the space defined by the cover 14 and the substrate 10 (for example, the electronic components 12 and 13) and reduce the service life of the semiconductor package structure. According to Figure 2AIn the embodiment shown in FIG, because the ceramic substrate is relatively stable at the operating temperature within the space defined by the lid 14 and the substrate 10, gases (e.g., organic gases) are not volatilized. Consequently, the electronic component 13 can have better performance (e.g., precise oscillation frequency). In addition, the service life of the semiconductor package structure 2A can be increased.

[0028] refer to Figure 2A , one or more insulators 21 are disposed between the electronic component 12 (e.g., the back surface of the electronic component 12) and the substrate 10. The insulator 21 may serve as a support structure for supporting the electronic component 12. The insulator 21 is connected to the surface 103 of the substrate 10 via an adhesive layer 11a. In some embodiments, the insulator 21 is connected to the back surface of the electronic component 12 via an adhesive layer 12a. In other embodiments, the adhesive layer 12a may be omitted, and the insulator 21 is in direct contact with the back surface of the electronic component 12. For example, the insulator 21 may be or include a patterned photoresist disposed on the back surface of the electronic component 12. In some embodiments, the thermal conductivity of the insulator 21 is equal to or less than about 1.2 W·m -1 ·K -1 In some embodiments, the thermal conductivity of the insulator 11 is about 0.2 W·m -1 ·K -1 For example, the insulator 21 may include a glass material or any other suitable material. In some embodiments, the insulators 21 may include or be formed of the same material. Alternatively, the insulators 21 may include or be formed of different materials. For example, some insulators 21 may include one material, and other insulators 21 may include another material.

[0029] In some embodiments, each insulator 21 may be a pillar (or support column) or any other supporting structure. Figure 2A As shown in FIG, the insulator 21 may be disposed at or near the edge of the back surface of the electronic component 12. In some embodiments, the insulator 21 may completely surround the back surface of the electronic component 12. For example, the back surface of the electronic component 12, the surface 103 of the substrate 10, and the insulator 21 may form a sealed space. In some embodiments, the insulators 21 may be separated from each other. For example, there may be a gap between two adjacent insulators 21. In some embodiments, as shown in FIG. Figure 2B , insulator 21 may be disposed at or near the center of electronic component 12. In some embodiments, the geometric center of all insulators 21 is substantially aligned with the geometric center of electronic component 12. In some embodiments, the height of each of insulators 21 (or the distance between the back surface of electronic component 12 and surface 103 of substrate 10) is in a range of about 15 microns to about 500 microns.

[0030] Insulator 21 is connected to a portion of the back surface of electronic component 12. For example, a portion of the back surface of electronic component 12 is connected to insulator 21, while the rest of the back surface of electronic component 12 is exposed from insulator 21 (or exposed to the space defined by cover 14 and substrate 10). For example, the total area of ​​the top surfaces of all insulators 21 is less than the area of ​​the back surface of electronic component 12. In some embodiments, the total area of ​​the top surfaces of all insulators is approximately 3% to approximately 50% (e.g., approximately 6%, 10%, 15%, 20%, 25%, 30%, 40%, etc.) of the area of ​​the back surface of electronic component 12. Heat conduction between the back surface of electronic component 12 and substrate 10 can be achieved through two paths: one path includes insulator 21 (or insulator 21 and adhesive layers 11a, 12a), and the other path includes the space (e.g., air, gas, or vacuum) between the portion of the back surface of electronic component 12 not connected to insulator 21 and surface 103 of substrate 10.

[0031] In some embodiments, the equivalent thermal resistance between the back surface of the electronic component 12 and the surface 103 of the substrate 10 (for example, the equivalent thermal resistance of the insulator 21 and the cavity / space between a portion of the back surface of the electronic component 12 that is not connected to the insulator 21 and the surface 103 of the substrate 10) is less than the thermal resistance of the substrate 10.

[0032] like Figure 1 As shown in FIG, since the insulator 11 is connected to the entire back surface of the electronic component 12, heat conduction between the back surface of the electronic component 12 and the substrate 10 can be achieved by only one path (for example, the insulator 11). Therefore, the equivalent thermal conductivity (or equivalent thermal resistance) between the back surface of the electronic component 12 and the substrate 10 is substantially equal to the thermal conductivity (or equivalent thermal resistance) of the insulator 11. Figure 2A and Figure 2B In the embodiment shown in FIG, heat conduction between the back surface of the electronic component 12 and the substrate 10 can be achieved by the insulator 21 and air (or vacuum). Because the thermal conductivity of air is about 0.026 W·m -1 ·K -1 , so the equivalent thermal conductivity between the back surface of the electronic component 12 and the substrate 10 is less than the thermal conductivity of the insulator 21, or the equivalent thermal resistance between the back surface of the electronic component 12 and the substrate 10 is greater than the thermal resistance of the insulator 21. Figure 1 Compared to the semiconductor package structure 1 shown in FIG, the thermal insulation within the space defined by the lid 14 and substrate 10 of the semiconductor package structure 2A or 2B can be improved, which improves the performance (e.g., accurate oscillation frequency) of the electronic component 13. In addition, the semiconductor package structure 2A or 2B has better thermal insulation, and the power consumption of the electronic component 12 to heat the electronic component 13 at the operating temperature can be reduced.

[0033] In some embodiments, when the thickness of insulator 11 and the height of each insulator 21 are approximately 500 microns, the thermal resistance between the back surface of electronic component 12 and substrate surface 103 of semiconductor package structure 2A (the total area of ​​the insulator is approximately 6% of the area of ​​the back surface of electronic component 12) is approximately 186% higher than that of semiconductor package structure 1, and the thermal resistance between the back surface of electronic component 12 and substrate surface 103 of semiconductor package structure 2B (the total area of ​​the insulator is approximately 3% of the area of ​​the back surface of electronic component 12) is approximately 357% higher than that of semiconductor package structure 1. Furthermore, the power consumption of electronic component 12 of semiconductor package structure 2A is approximately 65% ​​lower than that of semiconductor package structure 1, and the power consumption of electronic component 12 of semiconductor package structure 2B is approximately 78% lower than that of semiconductor package structure 1.

[0034] In some embodiments, when the thickness of insulator 11 and the height of each insulator 21 are approximately 200 microns, the thermal resistance between the back surface of electronic component 12 and substrate surface 103 of semiconductor package structure 2A (the total area of ​​the insulator is approximately 6% of the area of ​​the back surface of electronic component 12) is approximately 302% higher than that of semiconductor package structure 1, and the thermal resistance between the back surface of electronic component 12 and substrate surface 103 of semiconductor package structure 2B (the total area of ​​the insulator is approximately 3% of the area of ​​the back surface of electronic component 12) is approximately 525% higher than that of semiconductor package structure 1. Furthermore, the power consumption of electronic component 12 of semiconductor package structure 2A is approximately 75% lower than that of semiconductor package structure 1, and the power consumption of electronic component 12 of semiconductor package structure 2B is approximately 84% lower than that of semiconductor package structure 1.

[0035] Figure 3 A cross-sectional view of a semiconductor package structure according to some embodiments of the present invention is shown. Figure 3 The semiconductor package structure shown is similar to Figure 2A The semiconductor package structure 2A is shown in FIG. 1 , and some differences therebetween are described below.

[0036] like Figure 3 As shown in FIG, the substrate 10 does not include Figure 2A For example, the substrate 10 includes only one top surface 102. The cover 34 has a first portion substantially parallel to the surface 103 of the substrate 10 and a second portion connected to the first portion and substantially perpendicular to the first portion. The second portion of the cover 34 is disposed on the top surface 102 of the substrate 10. Figure 2A In FIG, the electronic component 13 does not overlap the cover 14 in a direction substantially parallel to the surface 103 of the substrate 10. Figure 3In the embodiment of the present invention, the electronic component 13 may overlap the cover 34 (eg, the second portion of the cover 34 ) in a direction substantially parallel to the surface 103 of the substrate 10 .

[0037] Figure 4A 、 Figure 4B 、 Figure 4C 、 Figure 4C '、 Figure 4D and Figure 4E Shows the manufacturing of some embodiments according to the present invention Figure 2A The method of the semiconductor package structure 2A shown in FIG.

[0038] refer to Figure 4A , providing a plurality of electronic components including electronic components 12. In some embodiments, the electronic components may be in strip form or wafer form. An insulator 21' is provided, having a first portion substantially parallel to the back surface of the electronic component 12 (e.g., the surface facing away from the heat source region 12h) and a second portion connected to the first portion and substantially perpendicular to the first portion. The second portion of the insulator 21' is connected to the back surface of the electronic component including the electronic component 12 via, for example, an adhesive layer 12a.

[0039] refer to Figure 4B , the first portion of the insulator 21' is removed, leaving the second portion of the insulator 21' to form a plurality of insulators 21. In some embodiments, the first portion of the insulator 21' is removed, for example, by etching or any other suitable process.

[0040] In other embodiments, the insulator 21 may be formed by patterning a photoresist on the back surface of the electronic component including the electronic component 12 , and the adhesive layer 12 a may be omitted.

[0041] refer to Figure 4C Singulation may be performed to separate the individual electronic components comprising electronic component 12. Singulation may be performed, for example, using a saw, a laser, or other suitable cutting technique.

[0042] As shown Figure 4C The bottom view of the electronic assembly 12 is shown in FIG. Figure 4C ', the insulator 21 may be disposed at or near a corner of the back surface of the electronic component 12. In other embodiments, the insulator 21 may be disposed at or near the center of the back surface of the electronic component 12. The number of insulators 21 may vary depending on different design specifications.

[0043] refer to Figure 4D , providing a substrate 10 having a cavity 10c. Figure 4CThe structure shown in FIG is disposed within cavity 10c. Insulator 21 is connected to surface 103 of substrate 10 via adhesive layer 11a. Electronic component 13 is then disposed on the active surface of electronic component 12 (e.g., on heat source region 12h). Electronic component 13 is electrically connected to electronic component 12 via conductive wire 13w. Electronic component 12 is electrically connected to substrate 10 via conductive wire 12w.

[0044] refer to Figure 4E , the cover 14 is placed on the top surface 101 of the substrate. The cover 14 is connected to the top surface 101 of the substrate 10 to form a hermetically sealed space.

[0045] Figure 5A and Figure 5B Shows the manufacturing of some embodiments according to the present invention Figure 3 In some embodiments, Figure 5A The operations in Figure 4C Execute after the operation in . Figure 5A and Figure 5B The operation in is similar to Figure 4D and Figure 4E , and some differences between them are described below.

[0046] like Figure 5A As shown in FIG, the substrate 10 does not include Figure 4D For example, the substrate 10 only includes a top surface 102. Figure 5B As shown in FIG, the cover 34 has a first portion substantially parallel to the surface 103 of the substrate 10 and a second portion connected to the first portion and substantially perpendicular to the first portion. The second portion of the cover 34 is disposed on the top surface 102 of the substrate 10 to form a hermetically sealed space.

[0047] As used herein and not otherwise defined, the terms "substantially," "generally," "approximately," and "about" are used to describe and account for small variations. When used in conjunction with an event or circumstance, the terms can encompass situations where the event or circumstance occurs exactly as well as situations where the event or circumstance closely approximates to occurring. For example, when used in conjunction with a numerical value, the terms can encompass a range of variation of less than or equal to ±10% of the numerical value, such as less than or equal to ±5%, less than or equal to ±4%, less than or equal to ±3%, less than or equal to ±2%, less than or equal to ±1%, less than or equal to ±0.5%, less than or equal to ±0.1%, or less than or equal to ±0.05%. The term "substantially coplanar" can refer to two surfaces that are within microns along the same plane, such as within 40 μm, within 30 μm, within 20 μm, within 10 μm, or within 1 μm along the same plane.

[0048] Unless the context clearly dictates otherwise, as used herein, the singular terms "a," "an," and "the" may include plural referents. In the description of some embodiments, reference to a component being "on" or "over" another component may encompass both the case where the former component is directly on (e.g., in physical contact with) the latter component and the case where one or more intervening components are located between the former and latter components.

[0049] Although the present invention has been described and illustrated with reference to its specific embodiments, these descriptions and illustrations are not restrictive. Those skilled in the art will understand that various changes may be made and equivalents may be substituted without departing from the true spirit and scope of the present invention as defined by the appended claims. The illustrations may not necessarily be drawn to scale. Due to manufacturing processes and tolerances, there may be differences between the process reproduction in the present invention and the actual equipment. There may be other embodiments of the present invention that are not specifically described. This specification and drawings should be regarded as illustrative rather than restrictive. Modifications may be made to adapt specific circumstances, materials, material compositions, methods or processes to the objectives, spirit and scope of the present invention. All such modifications are intended to be within the scope of the claims appended hereto. Although the methods disclosed herein have been described with reference to specific operations performed in a specific order, it should be understood that these operations may be combined, subdivided or reordered to form equivalent methods without departing from the teachings of the present invention. Therefore, unless specifically indicated herein, the order and grouping of operations are not limitations.

Claims

1. A semiconductor package structure, comprising: substrate; a first electronic component disposed on the substrate, the first electronic component having a back surface facing the first surface of the substrate and an active surface opposite to the back surface, wherein the first electronic component includes a heat source region exposed from the active surface; a second electronic component disposed on the first electronic component, wherein the heat source region is configured to maintain a constant temperature of the second electronic component; a bonding layer configured to allow efficient heat conduction between the heat source region and a back surface of the second electronic component; and A support component is disposed between the back surface of the first electronic component and the first surface of the substrate. 2 . The semiconductor package structure according to claim 1 , wherein the support member comprises a glass material.

3. The semiconductor packaging structure according to claim 1 , wherein the back surface of the first electronic component has a first portion connected to the support component and a second portion exposed from the support component, and an area of ​​the first portion of the back surface of the first electronic component is approximately 3% to approximately 50% of an area of ​​the back surface of the first electronic component.

4. The semiconductor package structure according to claim 1 , wherein the thermal conductivity of the support member is equal to or less than about 1.2 W·m -1 ·K -1 .

5. The semiconductor packaging structure according to claim 4 further comprises a cover, which is disposed on the substrate to form a hermetic sealed space, wherein the support component, the first electronic component and the substrate define a cavity, and the thermal conductivity of the cavity is less than the thermal conductivity of the hermetic sealed space. 6 . The semiconductor package structure according to claim 1 , wherein thermal conductivity of the support member is smaller than thermal conductivity of the substrate, and the support member overlaps with the heat source region in a direction perpendicular to the first surface of the substrate. 7 . The semiconductor package structure according to claim 1 , wherein the heat source region comprises a resistor pattern exposed from the active surface. 8 . The semiconductor package structure according to claim 1 , further comprising an adhesive layer connecting the support element to the first surface of the substrate, and the support element is partially buried in the adhesive layer. 9 . The semiconductor package structure according to claim 1 , wherein a width of the bonding layer is smaller than a width of the heat source region, and the bonding layer is partially exposed from the heat source region.

10. A semiconductor package structure, comprising: substrate; a first electronic component disposed on the substrate, the first electronic component having a back surface facing the first surface of the substrate and an active surface opposite to the back surface, wherein the first electronic component includes a heat source region exposed from the active surface; a second electronic component disposed on the heat source region of the first electronic component; a first conductive line electrically connecting the active surface of the first electronic component to the active surface of the second electronic component; and a first insulator and a second insulator disposed between the back surface of the first electronic component and the first surface of the substrate, The equivalent thermal resistance of the first insulator and the second insulator is greater than the thermal resistance of the substrate. 11 . The semiconductor package structure according to claim 10 , wherein the heat source region comprises a resistor pattern exposed from the active surface, which is configured to maintain a constant temperature of the second electronic component. 12 . The semiconductor package structure according to claim 11 , further comprising a bonding layer contacting the heat source region and a back surface of the second electronic component and configured to allow efficient heat conduction between the heat source region and the back surface of the second electronic component. The semiconductor package structure according to claim 10 , wherein the first insulator is gas or vacuum.

14. The semiconductor package structure according to claim 10, further comprising a second conductive line electrically connecting the active surface of the first electronic component to the top surface of the substrate, wherein the elevation of the active surface of the first electronic component is located between the elevation of the top surface of the substrate and the elevation of the active surface of the second electronic component. 15 . The semiconductor package structure according to claim 10 , wherein the second insulator is glass, and a width of the second insulator is smaller than a width of the heat source region. 16 . The semiconductor package structure according to claim 10 , further comprising a cover disposed on the substrate to form a hermetically sealed space, wherein a thermal resistance of the hermetically sealed space is greater than a thermal resistance of the second insulator.

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