Thermal management materials for semiconductor devices and associated systems and methods

Abstract

This application relates to thermal management materials for semiconductor devices and associated systems and methods. In some embodiments, a semiconductor package includes a first semiconductor die coupled to a second semiconductor die by a plurality of interconnect structures. A thermal material may be positioned between the first semiconductor die and the second semiconductor die. The thermal material may include an array of heat transfer elements embedded in a support matrix material. The array of heat transfer elements may include at least one void region aligned with at least one of the interconnect structures.

Description

Technical Field

[0001] The present technology generally relates to semiconductor devices, and more particularly, to materials for thermal management in semiconductor devices. Background Art

[0002] Encapsulated semiconductor dies (including memory chips, microprocessor chips, and imager chips) typically include a semiconductor die mounted on a substrate and encapsulated in a protective layer. The semiconductor die may include functional features such as memory cells, processor circuits, and imager devices, as well as bond pads electrically connected to the functional features. The bond pads may be electrically connected to terminals outside the protective layer to allow the semiconductor die to be connected to a higher-level circuit system.

[0003] Market pressures constantly drive semiconductor manufacturers to reduce the size of die packages to fit the space constraints of electronic devices, while also driving semiconductor manufacturers to increase the functional capacity of each package to meet operating parameters. One method for increasing the processing power of a semiconductor package without significantly increasing the surface area covered by the package (the "footprint" of the package) is to vertically stack multiple semiconductor dies on top of each other in a single package. The dies in such vertically stacked packages can be interconnected by electrically coupling the bond pads of individual dies to the bond pads of adjacent dies using through-silicon vias (TSVs).

[0004] A challenge associated with vertically stacked die packages is that the heat generated by each die is additive, and it may be difficult to dissipate the aggregated heat generated by the stacked dies. This additional heat increases the operating temperature of the individual dies, the junctions between the dies, and the entire package, which may cause the stacked dies to reach temperatures above their maximum operating temperature (T max ) above. As the die density in the package increases, this problem may be exacerbated. In addition, when the device has different types of dies in the die stack, the maximum operating temperature of the device may be limited to the die with the lowest maximum operating temperature. Summary of the Invention

[0005] In one aspect, the present application provides a semiconductor package, the semiconductor package including: a first semiconductor die; a second semiconductor die; a plurality of interconnect structures coupling the first semiconductor die and the second semiconductor die; and a thermal material located between the first semiconductor die and the second semiconductor die and surrounding the interconnect structures, wherein the thermal material includes a support matrix material and an array of heat transfer elements, the heat transfer elements being at least partially embedded in the support matrix material, and wherein the array of heat transfer elements has at least one void region aligned with at least one of the interconnect structures.

[0006] On the other hand, the present application provides a method of manufacturing a semiconductor package, the method comprising: forming an array of heat transfer elements comprising a plurality of void regions; embedding at least a portion of the array of heat transfer elements in a support matrix material; and positioning the array of heat transfer elements between a first semiconductor die and a second semiconductor die, wherein the first semiconductor die and the second semiconductor die are coupled to each other by a plurality of interconnect structures, and wherein the plurality of interconnect structures are aligned with the plurality of void regions. BRIEF DESCRIPTION OF THE DRAWINGS

[0007] Many aspects of the present technology can be better understood with reference to the following drawings. The components in the drawings are not necessarily to scale. Instead, the emphasis is on clearly showing the principles of the present technology.

[0008] Figure 1 is a side cross-sectional view of a semiconductor package configured in accordance with an embodiment of the present technology.

[0009] Figures 2A - 2C is a side cross-sectional view of a thermal material at various stages of manufacture in accordance with an embodiment of the present technology.

[0010] Figure 3 is a block diagram showing a method of manufacturing a semiconductor package in accordance with an embodiment of the present technology.

[0011] Figure 4 is an illustration showing an enhancement of the thermal conductivity of a thermal material configured in accordance with an embodiment of the present technology.

[0012] Figure 5 is an illustration showing that Figure 4 the junction temperature decreases as the thermal conductivity of the thermal material increases.

[0013] Figure 6 is a schematic diagram of a system including a semiconductor device or package configured in accordance with an embodiment of the present technology. DETAILED DESCRIPTION

[0014] Specific details of several embodiments of semiconductor devices and associated systems and methods are described below. Those skilled in the relevant art will recognize that suitable stages of the methods described herein may be performed at the wafer level or die level. Thus, depending on the context in which it is used, the term "substrate" may refer to a wafer-level substrate or a singulated die-level substrate. Additionally, unless the context indicates otherwise, conventional semiconductor manufacturing techniques may be used to form the structures disclosed herein. Materials may be deposited, for example, using chemical vapor deposition, physical vapor deposition, atomic layer deposition, electroplating, electroless plating, spin coating, and / or other suitable techniques. Similarly, materials may be removed, for example, using plasma etching, wet etching, chemical mechanical planarization, or other suitable techniques. Those skilled in the relevant art will also understand that the present technology may have additional embodiments and that the present technology may be practiced without some of the details of the embodiments described below Figures 1 - 6 and practice the present technology without several of the details of the embodiments described below.

[0015] In several of the embodiments described below, a semiconductor package includes a first semiconductor die coupled to a second semiconductor die through a plurality of interconnect structures (e.g., as part of a semiconductor die stack). A thermal material may be positioned between the first semiconductor die and the second semiconductor die. The thermal material may include an array of heat transfer elements (e.g., carbon nanotubes) embedded in a support matrix material (e.g., non-conductive film, underfill material, etc.). The array of heat transfer elements may be patterned to form at least one void region aligned with at least one of the interconnect structures. The thermal material may exhibit a higher thermal conductivity compared to the support matrix material alone. Thus, the thermal material may be used to increase heat transfer between the semiconductor dies (e.g., out of the die stack), which is expected to reduce the overall operating temperature of the semiconductor package and improve thermal performance.

[0016] Numerous specific details are disclosed herein to provide a thorough and practicable description of embodiments of the present technology. However, those skilled in the art should understand that the present technology may have additional embodiments and that the present technology may be practiced without some of the details of the embodiments described below Figures 1 - 6 and practice the present technology without several of the details of the embodiments described below. For example, some details of semiconductor devices and / or packages known in the art have been omitted to avoid obscuring the present technology. Generally, it should be understood that various other devices and systems may also be within the scope of the present technology, in addition to the specific embodiments disclosed herein.

[0017] As used herein, the terms "vertical," "lateral," "upper," "lower," "above," and "below" may refer to the relative direction or orientation of features in a semiconductor device as viewed from the orientation shown in the figures. For example, "upper" or "uppermost" may refer to a feature positioned closer to the top of the page than another feature. However, these terms should be construed broadly to encompass semiconductor devices having other orientations, such as reverse or tilted orientations, where top / bottom, above / below, over / under, up / down, and left / right may be interchanged depending on the orientation.

[0018] Although certain embodiments herein are described with respect to thermal materials for high heat transfer rates between two semiconductor dies, it should be understood that the techniques are equally applicable to thermal materials for increasing heat transfer between other semiconductor device components, such as between a semiconductor die and a package substrate.

[0019] Figure 1 is a side cross-sectional view of a semiconductor package 100 ("package 100") configured in accordance with an embodiment of the present technique. Package 100 may include a first semiconductor die 102 ("first die 102") and a plurality of second semiconductor dies 104 ("one or more second dies 104") mounted on first die 102. The second semiconductor dies 104 may be vertically arranged to form a die stack 106. In the illustrated embodiment, die stack 106 includes three second semiconductor dies 104. In other embodiments, die stack 106 may include fewer or more second semiconductor dies 104 (e.g., two, four, five, six, seven, eight, nine, ten, or more dies).

[0020] The first die 102 and / or the second die 104 may each include a semiconductor substrate (e.g., a silicon substrate, a gallium arsenide substrate, an organic laminate substrate, etc.). In some embodiments, one or more of the first die 102 and / or the second die 104 include various types of semiconductor components and functional features, such as memory circuits (e.g., dynamic random access memory (DRAM), static random access memory (SRAM), flash memory, or other types of memory circuits), controller circuits (e.g., DRAM controller circuits), logic circuits, processing circuits, circuit elements (e.g., wires, traces, interconnects, transistors, etc.), imaging components, and / or other semiconductor features. For example, the package 100 may be a Hybrid Memory Cube (HMC), where the stacked second die 104 is a DRAM die or other memory die providing data storage, and the first die 102 is a high-speed logic die providing memory control (e.g., DRAM control) within the HMC. Alternatively or in combination, one or more of the first die 102 and / or the second die 104 may be a "blank" substrate that does not include integrated circuit components and is formed of, for example, crystalline, semi-crystalline, and ceramic substrate materials such as silicon, polysilicon, aluminum oxide (Al 2 O 3 ), sapphire, and / or other suitable materials). Optionally, the first die 102 and / or the second die 104 may include an insulating material, such as a suitable dielectric material (e.g., a passivation material, a polyimide material, and / or other materials for covering the surface of a semiconductor device).

[0021] The first die 102 and / or the second die 104 may be coupled to each other (e.g., mechanically, thermally, and / or electrically) via a plurality of interconnect structures 108 (e.g., bumps, micro-bumps, pillars, studs, etc.). Each interconnect structure 108 may be formed of any suitable conductive material (such as copper, nickel, gold, silicon, tungsten, solder (e.g., SnAg-based solder), conductive epoxy resin, combinations thereof, etc.) and may be formed by electroplating, electroless plating, or other suitable processes. In some embodiments, the interconnect structure 108 may also include a barrier material (e.g., nickel, nickel-based intermetallic compounds, and / or gold) formed over an end portion of the interconnect structure 108. The barrier material may facilitate bonding and / or prevent or at least inhibit electromigration of copper or other metals used to form the interconnect structure 108.

[0022] In some embodiments, at least some of the interconnect structures 108 in the interconnect structure are electrically coupled to the first die 102 and / or the second die 104 (e.g., coupled to the TSV 109 located within the first die 102 and / or the second die 104). Alternatively or in combination, at least some of the interconnect structures 108 in the interconnect structure may be “dummy” structures that are not electrically coupled to the first die 102 and / or the second die 104. Optionally, at least some of the interconnect structures may be thermal bumps that thermally couple the first die 102 and / or the second die 104 to reduce the thermal resistance between the dies. Although Figure 1 nine interconnect structures 108 are shown in, the package 100 may include fewer or more interconnect structures 108. For example, the package 100 may include dozens, hundreds, thousands, or more interconnect structures 108 arranged between the first die 102 and / or the second die 104.

[0023] The package 100 further includes a thermal material 110 for thermally managing the package 100, for example, by increasing heat transfer between the dies and / or reducing the thermal resistance between the dies. In the illustrated embodiment, the thermal material 110 is located between the first die 102 and the bottommost second die 104 and between each of the second dies 104. The thermal material 110 may be configured to surround the interconnect structures 108. In some embodiments, the thermal material 110 includes a plurality of holes formed therein to receive the interconnect structures 108. Optionally, the thermal material 110 may be omitted from certain portions of the package 100. Additionally, although Figure 1 the outer edge of the thermal material 110 is depicted as protruding beyond the outer edge of the die stack 106, in other embodiments, the outer edge of the thermal material 110 may be aligned with the outer edge of the die stack 106 or be entirely located within the die stack 106.

[0024] In some embodiments, the thermal material 110 is a composite material that includes different types of materials. For example, the composite material may include a plurality of heat transfer elements 112 embedded in a support matrix material 114. Various types of heat transfer elements 112 are suitable for use with the embodiments disclosed herein. For example, the heat transfer elements 112 may be made of any suitable material having a relatively high thermal conductivity, such as a metal (e.g., copper) or a carbon-based material (e.g., graphite, graphene, carbon nanotubes). The heat transfer elements 112 may be structured in many different ways, such as particles, fibers, wires, tubes, meshes, or combinations thereof. In some embodiments, the heat transfer elements 112 are nano-scale or nanostructured elements, such as nanoparticles, nanofibers, nanotubes, nanowires, etc.

[0025] The heat transfer element 112 can be configured as needed. For example, the heat transfer element 112 can be arranged in an organized configuration, such as an array. The heat transfer elements 112 can be aligned with each other within the array (e.g., vertically aligned). In other embodiments, the heat transfer elements 112 can be randomly dispersed in a region of the support matrix material 114 without any particular organization and / or alignment within a given region. Optionally, the heat transfer element 112 can be patterned or otherwise formed with at least one void area such that some regions of the thermal material 110 have the heat transfer element 112 while other regions of the thermal material 110 do not have the heat transfer element 112. One or more void areas can be sized and shaped to accommodate components of the package 100 (e.g., the interconnect structure 108), as described in more detail below. For example, the heat transfer element 112 can be configured as a sheet or layer of material that is patterned to have a plurality of void areas at discrete locations. As another example, the heat transfer element 112 can be configured as one or more discrete material sections (e.g., strips, segments, patches, etc.) that are spaced apart from each other or otherwise separated to form at least one void area.

[0026] In some embodiments, the heat transfer element 112 is an array of carbon nanotubes. The carbon nanotubes can be single-walled nanotubes or multi-walled nanotubes (e.g., double-walled, triple-walled, etc.). Each carbon nanotube can have an elongated shape extending along a longitudinal axis, e.g., having an aspect ratio greater than or equal to 10:1, 100:1, 1000:1, 10000:1, 10 5 :1, 10 6 :1 or greater. The carbon nanotubes can be vertically aligned with each other along their longitudinal axes. Thus, it is expected that the array of carbon nanotubes generally exhibits high thermal conductivity in the vertical direction to reduce the thermal resistance between die and enhance heat transfer between die.

[0027] The support matrix material 114 can be any material suitable for filling the space between the heat transfer elements 112, such as a film, underfill, resin, paste, etc. The support matrix material 114 can also mechanically support the heat transfer elements 112 and / or hold the heat transfer elements together. The support matrix material 114 can be made of a material (such as a polymeric material) having a relatively low thermal conductivity compared to the heat transfer elements 112. For example, the support matrix material 114 can be a non-conductive film or a die attach film. In some embodiments, the support matrix material 114 is an underfill material, such as a non-conductive epoxy paste (e.g., XS8448-171 manufactured by Namics Corporation of Niigata, Japan), capillary underfill, and / or other suitable electrical insulating materials. Alternatively, the underfill material 110 can be a dielectric underfill, such as FP4585 manufactured by Henkel of Düsseldorf, Germany. Optionally, as described in more detail below, the support matrix material 114 can be patterned, for example, to have a plurality of holes to accommodate components of the package 100 (e.g., the interconnect structure 108).

[0028] The composition of the thermal material 110 (e.g., the relative amounts of the heat transfer elements 112 and the support matrix material 114) can be selected to improve the thermal properties of the thermal material 110. In some embodiments, the heat transfer elements 112 constitute at least 10 wt%, 20 wt%, 30 wt%, 40 wt%, 50 wt%, 60 wt%, 70 wt%, 80 wt% or 90 wt% of the thermal material 110. In some embodiments, the support matrix material 114 constitutes at least 10 wt%, 20 wt%, 30 wt%, 40 wt%, 50 wt%, 60 wt%, 70 wt%, 80 wt% or 90 wt% of the thermal material 110. In some embodiments, the thermal conductivity of the thermal material 110 is high enough such that the maximum operating temperature (e.g., the junction temperature) of the package 100 is less than or equal to 110°C, 105°C, 100°C, 95°C or lower. For example, the thermal conductivity of the thermal material 110 can be greater than or equal to 5 W / mK, 10 W / mK, 15 W / mK, 20 W / mK, 25 W / mK or greater.

[0029] The package 100 may include other components commonly found in semiconductor devices and known to those skilled in the art. For example, the first die 102 may be mounted on a package substrate (not shown), such as a redistribution layer, an interposer, a printed circuit board, a dielectric spacer, another semiconductor die (e.g., a logic die), or another suitable substrate. The package substrate may include semiconductor components (e.g., doped silicon wafers or gallium arsenide wafers), non-conductive components (e.g., various ceramic substrates such as alumina (Al2O3), etc.), aluminum nitride, and / or conductive portions (e.g., interconnect circuitry, TSVs, etc.). The package substrate may further include electrical connectors (e.g., solder balls, conductive bumps, conductive pillars, conductive epoxy, and / or other suitable conductive elements) that are electrically coupled to the package substrate and configured to electrically couple the package 100 to an external device or circuitry (not shown). In some embodiments, the package 100 includes other components, such as an external heat sink, a housing (e.g., a thermally conductive housing), an electromagnetic interference (EMI) shielding component, etc.

[0030] Figures 2A - 2C is a side cross-sectional view of the thermal material 110 at various stages of manufacture in accordance with an embodiment of the present technology. Figure 2A Shows a plurality of heat transfer elements 112 (e.g., an array of carbon nanotubes) formed on a substrate 201. The heat transfer elements 112 may be patterned or otherwise formed with a plurality of void regions 202 (e.g., holes, apertures, spaces, grooves, channels, gaps, etc.) to accommodate various components of the semiconductor package. For example, the void regions 202 may be configured to accommodate interconnect structures (e.g., the interconnect structure 108 described with respect to Figure 1 ). In some embodiments, each void region 202 is configured to receive a single interconnect structure. In other embodiments, each void region 202 may be configured to receive a plurality of interconnect structures (e.g., two, three, four, five, 10, 20, 50, 100, or more interconnect structures). Additionally, the size (e.g., length, width, diameter, area) and / or spacing (e.g., pitch) of the void regions 202 may be designed to reduce or avoid electrical interference with the interconnect structure 108. In some embodiments, the cross-sectional shape of the void region 202 may be the same as or similar to the cross-sectional shape of the interconnect structure 108 (e.g., circular, oval, square, rectangular, polygonal, linear, or curvilinear or a combination thereof). The cross-sectional size (e.g., cross-sectional area, diameter, width, etc.) of the void region 202 may be the same as or similar to the cross-sectional size of the interconnect structure 108. In other embodiments, the cross-sectional size of the void region 202 may be larger than the cross-sectional size of the interconnect structure 108 (e.g., at least 10%, 20%, 30%, 40%, 50%, 60%, 70%, 80%, 90%, 100%, or more larger).

[0031] Figure 2B Shows a heat transfer element 112 embedded in a support matrix material 114 to form a thermal material 110. The process of embedding the heat transfer element 112 in the support matrix material 114 can be performed while the heat transfer element 112 is still attached to the substrate 201. In other embodiments, the heat transfer element 112 can be removed from the substrate 201 before being embedded in the support matrix material 114. The support matrix material 114 can fill the interstitial space between the heat transfer element 112 and / or the void regions 202. In some embodiments, the heat transfer element 112 is fully embedded in the support matrix material 114. In other embodiments, only a portion of the heat transfer element 112 is embedded in the support matrix material 114. For example, in embodiments where the heat transfer element 112 is vertically aligned, the upper end portion and / or the lower end portion of the heat transfer element 112 can protrude from the upper surface and / or the lower surface of the support matrix material 114, respectively.

[0032] Optionally, the support matrix material 114 can be patterned to have a plurality of holes 203 shown in dashed lines, in which various components (e.g., the interconnect structure 108) of the semiconductor package can be received. The holes 203 can have the same size and / or shape as the void regions 202 formed in the array of heat transfer elements 112, or the holes 203 can have a cross-sectional size smaller than the cross-sectional size of the void regions 202. In some embodiments, the cross-sectional shape of the holes 203 can be the same as or similar to the cross-sectional shape of the interconnect structure 108 (e.g., circular, oval, square, rectangular, polygonal, linear or curvilinear or a combination thereof). The cross-sectional size (e.g., cross-sectional area, diameter, width, etc.) of the holes 203 can be the same as or similar to the cross-sectional size of the interconnect structure 108. In other embodiments, the cross-sectional size of the holes 203 can be larger than the cross-sectional size of the interconnect structure 108 (e.g., at least 10%, 20%, 30%, 40%, 50%, 60%, 70%, 80%, 90%, 100% or more larger). In other embodiments, the support matrix material 114 is formed without any holes or other patterning.

[0033] Figure 2CShows a process stage after the thermal material 110 has been removed from the substrate 201 and positioned between the first semiconductor die 104a and the second semiconductor die 104b. In the illustrated embodiment, the interconnect structure 108 between the first semiconductor die 104a and the second semiconductor die 104b is aligned with and passes through the empty regions 202 formed in the array of heat transfer elements 112. The interconnect structure 108 also passes through the support matrix material 114. In embodiments where the support matrix material 114 is patterned to have holes 203, each interconnect structure 108 can pass through the corresponding hole 203 in the support matrix material 114. In other embodiments, the support matrix material 114 can be initially formed without any holes, and the holes can then be formed in the support matrix material 114 during the process of coupling the first semiconductor die 104a, the second semiconductor die 104b, the interconnect structure 108, and / or the thermal material 110 to each other, as described in detail below.

[0034] Figure 3 is a block diagram showing a method 300 for manufacturing a semiconductor package according to an embodiment of the present technology. The method 300 can be used to manufacture any embodiment of the devices and systems described herein (e.g., the semiconductor package 100 described with respect to Figure 1 or its components (e.g., the thermal material 110 described with respect to Figures 1 - 2C ).

[0035] The method 300 includes forming a plurality of heat transfer elements (block 310). As previously described, the heat transfer elements can be an array of heat transfer elements, such as an array of nanoscale thermal conductive elements. In embodiments where the heat transfer elements are an array of carbon nanotubes, the carbon nanotubes can be formed according to processes known to those skilled in the art. For example, vertically aligned carbon nanotubes can be grown on a substrate (e.g., silicon) using techniques such as chemical vapor deposition (CVD) (e.g., thermal CVD, plasma-enhanced CVD) or electrophoretic deposition.

[0036] For example, as with respect to Figure 2AAs described, the heat transfer element can be patterned or otherwise formed with at least one void area. As is known to those skilled in the art, patterning can be performed in a variety of different ways. For example, in some embodiments, the heat transfer element is initially formed as a uniform, unpatterned material without one or more void areas (e.g., an array of continuous heat transfer elements without void areas). Subsequently, one or more portions of the uniform material can be removed (e.g., by etching, transfer, etc.) to create one or more void areas within the array and / or to separate portions of the array from each other. Alternatively or in combination, the heat transfer element can be formed at selected locations (e.g., by growing on a patterned substrate or by a catalyst) to create one or more void areas. For example, in an embodiment where the heat transfer element is an array of carbon nanotubes, the array can be patterned into having one or more void areas by growing a uniform array on a first substrate. Subsequently, one or more portions of the array can be selectively transferred to a patterned second substrate. One or more void areas can correspond to locations where the carbon nanotubes are not transferred to the second substrate.

[0037] Method 300 further includes embedding the heat transfer element in a support matrix material (block 320). For example, as previously described with respect to Figure 2B As described, the heat transfer element can be at least partially or fully embedded in the support matrix material. The embedding process can be performed using techniques known to those skilled in the art. For example, in some embodiments, the support matrix material can be caused to flow, inject, pour, etc. into the heat transfer element to surround and encapsulate each heat transfer element. In such embodiments, the support matrix material can be a capillary underflow material that is adapted to penetrate into the interstitial spaces between each heat transfer element by capillary action. Alternatively or in combination, the heat transfer element can be embedded by pressing it into the support matrix material. Once the support matrix material is in place, it can be cured to bond the support matrix material to the heat transfer element.

[0038] The method further includes positioning the heat transfer element in a semiconductor device (block 330). As previously described with respect to Figure 2C As described, the heat transfer element can be positioned between a first semiconductor die and a second semiconductor die. In some embodiments, the first semiconductor die and the second semiconductor die are configured to be coupled to each other by a plurality of interconnect structures such that the positioning process includes aligning one or more void areas formed in the heat transfer element with the interconnect structures so that the interconnect structures pass through the one or more void areas. Each interconnect structure can pass through a corresponding void area, or a plurality of interconnect structures can pass through a single void area. The heat transfer element can then be coupled to the first die and the second die (e.g., by thermocompression bonding (TCB)).

[0039] The support matrix material can be positioned in the semiconductor device together with the heat transfer element (e.g., between the first die and the second die). In some embodiments, the support matrix material is provided as a film (e.g., a non-conductive film), and the interconnect structure is pressed through the support matrix material or otherwise displaced to contact another semiconductor die. Optionally, the film can be patterned to have holes aligned with the interconnect structures such that each interconnect structure passes through a corresponding hole in the film during the positioning process. Subsequently, the first semiconductor die, the second semiconductor die, the interconnect structure, the heat transfer element, and the support matrix material can be coupled to each other, for example, by a TCB operation.

[0040] Method 300 can be performed in a variety of different ways, and the steps of method 300 can be performed in any suitable order. For example, the heat transfer element can be positioned in the semiconductor device before being embedded in the support matrix material. In such embodiments, after positioning the heat transfer element, the support matrix material can be flowed between the first die and the second die to fill the gap space between the heat transfer element and / or the interconnect structure. As another example, the heat transfer element can be formed on one of the semiconductor dies (e.g., the first die or the second die) in the semiconductor die and then coupled to the other semiconductor die. In such embodiments, the support matrix material can be introduced before, simultaneously with, or after coupling to the other semiconductor die.

[0041] Figure 4 is a diagram showing an enhancement of the thermal conductivity of a thermal material configured according to an embodiment of the present technology. In the illustrated embodiment, the thermal material is a non-conductive film having a vertically aligned embedded array of carbon nanotubes. As seen in Figure 4 the overall thermal conductivity of the material increases with the increasing weight fraction of the carbon nanotubes. For example, a 10% weight fraction of carbon nanotubes corresponds to a thermal conductivity of approximately 20 W / mK.

[0042] Figure 5 is a diagram showing that the junction temperature decreases with Figure 4 the increasing thermal conductivity of the thermal material. Referring together to Figure 4 and 5 , the thermal conductivity of the non-conductive film without any carbon nanotubes is approximately 2.7 W / mK, which corresponds to a junction temperature of approximately 107.1 °C. In contrast, the thermal conductivity of the non-conductive film with a 10% weight fraction of carbon nanotubes is approximately 20 W / mK, which corresponds to a junction temperature of approximately 100.2 °C. As seen in Figure 5 incorporating carbon nanotubes can significantly reduce the junction temperature of the semiconductor package and improve the thermal performance.

[0043] has the above reference Figures 1 - 5Any semiconductor device and / or package of the described features can be incorporated into any of a large number of larger and / or more complex systems, representative examples of which are Figure 6 the system 600 schematically shown in FIG. The system 600 can include a processor 602, a memory 604 (e.g., SRAM, DRAM, flash memory, and / or other memory devices), an input / output device 606, and / or other subsystems or components 608. The semiconductor die and / or package described above with reference to Figures 1 - 5 can be included in any of the elements Figure 6 shown. The resulting system 600 can be configured to perform any of a variety of suitable computing functions, processing functions, storage functions, sensing functions, imaging functions, and / or other functions. Thus, representative examples of the system 600 include, but are not limited to, computers and / or other data processors, such as desktop computers, laptop computers, Internet appliances, handheld devices (e.g., palmtop computers, wearable computers, cellular phones or mobile phones, personal digital assistants, music players, etc.), tablet computers, multiprocessor systems, processor-based consumer electronic devices or programmable consumer electronic devices, network computers, and minicomputers. Additional representative examples of the system 600 include lights, cameras, vehicles, etc. With respect to these examples and others, the system 600 can be housed in a single unit or distributed, for example, over multiple interconnected units via a communication network. The components of the system 600 can thus include local memory storage devices and / or remote memory storage devices and any of a variety of suitable computer-readable media.

[0044] In view of the foregoing, it should be understood that specific embodiments of the present technology have been described herein for purposes of illustration, but various modifications can be made without departing from the disclosure. Thus, the invention is not limited except as by the appended claims. Additionally, certain aspects of the new technology described in the context of a particular embodiment can also be combined in other embodiments or omitted. Moreover, although advantages associated with certain embodiments of the new technology have been described in the context of those embodiments, other embodiments can also exhibit such advantages and not all embodiments need to exhibit such advantages to fall within the scope of the present technology. Thus, the disclosure and the associated technology can cover other embodiments not expressly shown or described herein.

Claims

1. A semiconductor package, which comprises: a first semiconductor die; a second semiconductor die; a plurality of interconnect structures that couple the first semiconductor die and the second semiconductor die; and a thermal material that is located between the first semiconductor die and the second semiconductor die and surrounds the plurality of interconnect structures, wherein the thermal material comprises: a support matrix material, and an array of heat transfer elements that are at least partially embedded in the support matrix material, wherein the array of heat transfer elements has a plurality of void regions that are aligned with the plurality of interconnect structures, and wherein each of the plurality of void regions contains a portion of the support matrix material that contacts a corresponding interconnect structure.

2. The semiconductor package according to claim 1, wherein the array of heat transfer elements comprises nanoscale elements.

3. The semiconductor package according to claim 2, wherein the nanoscale elements are aligned with each other.

4. The semiconductor package according to claim 2, wherein the array of heat transfer elements comprises carbon nanotubes.

5. The semiconductor package according to claim 4, wherein the carbon nanotubes are vertically aligned to facilitate heat transfer between the first semiconductor die and the second semiconductor die.

6. The semiconductor package according to claim 1, wherein the support matrix material comprises a non-conductive film or an underfill material.

7. The semiconductor package according to claim 1, wherein the support matrix material fills the interstitial spaces between individual heat transfer elements of the array of heat transfer elements.

8. The semiconductor package according to claim 1, wherein the support matrix material is patterned to form a plurality of holes that are aligned with the plurality of interconnect structures.

9. The semiconductor package according to claim 1, wherein the thermal conductivity of the array of heat transfer elements is higher than the thermal conductivity of the support matrix material.

10. The semiconductor package according to claim 1, wherein the thermal conductivity of the thermal material is at least 20 W / mK.

11. The semiconductor package according to claim 1, wherein the array of heat transfer elements accounts for at least 10 wt% of the thermal material.

12. The semiconductor package according to claim 1, wherein the outer edge of the thermal material extends beyond the outer edge of the second semiconductor die.

13. A method of manufacturing a semiconductor package, the method comprises: forming an array of heat transfer elements; embedding at least a portion of the array of heat transfer elements in a support matrix material; and positioning the array of heat transfer elements between a first semiconductor die and a second semiconductor die, wherein the first semiconductor die and the second semiconductor die are coupled to each other by a plurality of interconnect structures, wherein the array of heat transfer elements has a plurality of void regions that are aligned with the plurality of interconnect structures, and wherein each of the plurality of void regions contains a portion of the support matrix material that contacts a corresponding interconnect structure.

14. The method according to claim 13, wherein the array of heat transfer elements comprises carbon nanotubes.

15. The method according to claim 13, wherein forming the array of the heat transfer elements comprises: forming a uniform array of the heat transfer elements; and removing one or more portions of the uniform array of the heat transfer elements to create the plurality of void regions.

16. The method according to claim 13, wherein forming the array of the heat transfer elements comprises forming the heat transfer elements at selected locations so as to create the plurality of void regions.

17. The method according to claim 13, wherein the array of the heat transfer elements is formed on a surface of the first semiconductor die or the second semiconductor die.

18. The method according to claim 13, wherein the array of the heat transfer elements is coupled to the first semiconductor die and the second semiconductor die after being formed.

19. The method according to claim 13, wherein embedding at least a portion of the array of the heat transfer elements in the support matrix material comprises flowing the support matrix material into interstitial spaces between individual heat transfer elements of the array of the heat transfer elements.

20. The method according to claim 13, wherein embedding at least a portion of the array of the heat transfer elements in the support matrix material is performed before positioning the array of the heat transfer elements between the first semiconductor die and the second semiconductor die.

21. The method according to claim 13, wherein embedding at least a portion of the array of the heat transfer elements in the support matrix material is performed after positioning the array of the heat transfer elements between the first semiconductor die and the second semiconductor die.

Images