A signal detection circuit with polymorphic output

Abstract

The present invention discloses a signal detection circuit with polymorphic output, comprising an input module; an input terminal Vin1 of the input module is used to receive a detection input signal 1; an input terminal Vin2 of the input module receives a detection input signal 2; a first output terminal and a second output terminal of the input module are respectively connected to an input terminal A1 and an input terminal A2 of the output module; the input terminal A1 of the output module is connected to the first output terminal of the input module for receiving a control signal A1; the input terminal A2 of the output module is connected to the second output terminal of the input module for receiving a control signal A2; a power input terminal of the output module is connected to an output terminal of a second power module; an output terminal Vo of the output module 20 is connected to a detection chip. The present invention can characterize the states of two input signals through four signal states of one output port, realizing parallel signal detection, saving the number of input and output ports of a signal processing chip, and reducing detection errors.

Description

Technical Field

[0001] The present invention relates to the technical field of electronic circuits, and particularly to a signal detection circuit with multi-state output. Background Art

[0002] Currently, electronic circuits often detect multiple input signals simultaneously, then convert them into multiple output signals and send them to a signal processing chip (such as a single-chip microcomputer) serving as a detection chip. This will occupy a large number of input and output ports of the detection chip, resulting in a shortage of port resources of the detection chip.

[0003] In existing technical solutions, a multi-channel signal detection integrated chip is generally used to detect multi-channel signals. However, the multi-channel signal detection integrated chip (such as a single-chip microcomputer) needs to sequentially select corresponding signal channels through an addressing method to serially receive multi-channel signals. If the number of signals to be detected is large, then the multi-channel signal detection integrated chip (such as a single-chip microcomputer) will cause asynchronous signal detection due to detection delay, increasing the detection error. Summary of the Invention

[0004] The object of the present invention is to provide a signal detection circuit with multi-state output for the technical defects existing in the prior art.

[0005] To this end, the present invention provides a signal detection circuit with multi-state output, including an input module, an output module, and a second power supply module;

[0006] Among them, the input end Vin1 of the input module is used to receive the detection input signal 1;

[0007] The input end Vin2 of the input module receives the detection input signal 2;

[0008] The first output end of the input module is connected to the input end A1 of the output module to provide a control signal A1 for the output module;

[0009] The second output end of the input module is connected to the input end A2 of the output module to provide a control signal A2 for the output module;

[0010] Among them, the input end A1 of the output module is connected to the first output end of the input module to receive the control signal A1 output by the input module;

[0011] The input end A2 of the output module is connected to the second output end of the input module to receive the control signal A2 output by the input module;

[0012] The power input end of the output module is connected to the output end VDD2 of the second power supply module to receive the DC power supply VDD2;

[0013] The output terminal Vo of the output module is connected to the detection chip, and is used to provide a detection output signal Vo for the detection chip;

[0014] The detection output signal includes four states: 0V, low level, high level 2, and high level 1, where the voltage of high level 1 is greater than the voltage of high level 2.

[0015] Preferably, when the detection input signal 1 and the detection input signal 2 are not common ground signals, a first power supply module is further included;

[0016] Among them, the power input terminal of the input module is connected to the output terminal VDD1 of the first power supply module, and is used to receive the DC power supply VDD1.

[0017] Preferably, the input module includes: resistors R1 to R4, switching transistors Q1 to Q2, and optocouplers Q56 to Q57;

[0018] Among them, the first pin of resistor R1 serves as the input terminal Vin1 of the input module and is used to receive the detection input signal 1;

[0019] The second pin of resistor R1 is connected to the base B of switching transistor Q1;

[0020] The emitter E of switching transistor Q1 is connected to the ground terminal GND1;

[0021] The collector C of switching transistor Q1 is connected to the second pin of optocoupler Q6;

[0022] The first pin of optocoupler Q6 is connected to the second pin of resistor R3;

[0023] The third pin of optocoupler Q6 serves as the first output terminal of the input module and is connected to the input terminal A1 of the output module, and is used to output a control signal A1 for the output module;

[0024] The fourth pin of optocoupler Q6 is connected to the ground terminal GND2;

[0025] Among them, the first pin of resistor R2 serves as the input terminal Vin2 of the input module and is used to receive the detection input signal 2;

[0026] The second pin of resistor R2 is connected to the base B of switching transistor Q2;

[0027] The emitter E of switching transistor Q2 is connected to the ground terminal GND1;

[0028] The collector C of switching transistor Q2 is connected to the second pin of optocoupler Q7;

[0029] The first pin of optocoupler Q7 is connected to the second pin of resistor R4;

[0030] The 3rd pin of optocoupler Q7, as the second output terminal of the input module, is connected to the input terminal A2 of the output module, and is used to output the control signal A2 to the output module;

[0031] The 4th pin of optocoupler Q7 is connected to the ground terminal GND2;

[0032] The 1st pins of resistor R3 and resistor R4, after the busbars intersect, serve as the power input terminal of the input module and are connected to the output terminal VDD1 of the first power module, for receiving the DC power supply VDD1.

[0033] Preferably, the output module includes: resistors R5 to R11, switching transistors Q3 to Q5, and diode D1, where:

[0034] The 1st pins of resistor R5 and resistor R6, as the power input terminal of the output module, are connected to the output terminal VDD2 of the power module, for receiving the DC power supply VDD2, such as 5V;

[0035] The 1st pin of resistor R5 is also respectively connected to the 1st pin of resistor R7, the 1st pin of resistor R11, and the 1st pin of resistor R9;

[0036] The 2nd pin of resistor R5, as the input terminal A1 of the output module, is connected to the first output terminal of the input module, for receiving the control signal A1;

[0037] The 2nd pin of resistor R6, as the input terminal A2 of the output module, is connected to the second output terminal of the input module, for receiving the control signal A2;

[0038] The 2nd pin of resistor R5 is also connected to the gate G of switching transistor Q4;

[0039] The source S of switching transistor Q4 is connected to the 2nd pin of resistor R7;

[0040] The drain D of switching transistor Q4, as the output terminal Vo of the output module, is used to output the detection output signal Vo to the detection chip;

[0041] The drain D of switching transistor Q4 is also respectively connected to the anode of diode D1, the 1st pin of resistor R10, and the drain D of switching transistor Q5;

[0042] The cathode of diode D1 is connected to the 1st pin of resistor R8;

[0043] The source S of switching transistor Q3 is respectively connected to the 2nd pin of resistor R8, the 2nd pin of resistor R11, and the gate G of switching transistor Q5;

[0044] The drain D of switching transistor Q3 is connected to the ground terminal GND2;

[0045] The gate G of the switching transistor Q3, which serves as the input terminal A2 of the output module, is connected to the second output terminal of the input module for receiving the control signal A2.

[0046] The gate G of the switching transistor Q3 is also connected to the second pin of the resistor R6.

[0047] Among them, the source S of the switching transistor Q5 is connected to the second pin of the resistor R9.

[0048] The second pin of the resistor R10 is connected to the ground terminal GND2.

[0049] Preferably, when it is detected that the input signals Vin1 and Vin2 are common-ground signals, the input module includes a resistor R1 and a resistor R2:

[0050] Among them, the first pin of the resistor R1 serves as the input terminal Vin1 of the input module for receiving the detection input signal 1.

[0051] The second pin of the resistor R1 is connected to the base B of the switching transistor Q1.

[0052] The emitter E of the switching transistor Q1 is connected to the ground terminal GND1.

[0053] The collector C of the switching transistor Q1 is connected to the input terminal A2 of the output module to output the control signal A2 for the output module.

[0054] Among them, the first pin of the resistor R2 serves as the input terminal Vin2 of the input module for receiving the detection input signal 2.

[0055] The second pin of the resistor R2 is connected to the base B of the switching transistor Q2.

[0056] The emitter E of the switching transistor Q2 is connected to the ground terminal GND1.

[0057] The collector C of the switching transistor Q2 is connected to the input terminal A1 of the output module to output the control signal A1 for the output module.

[0058] Preferably, it includes the following working modes:

[0059] First, when the detection output signal Vo provided by the output module is 0V, the detection chip determines that both the input terminals Vin1 and Vin2 of the input module are at low level, that is, it determines that both the detection input signal 1 and the detection input signal 2 are at low level.

[0060] Second, when the detection output signal Vo provided by the output module is high level 2, therefore, the detection chip determines that both the input terminals Vin1 and Vin2 of the input module are at high level, that is, it determines that both the detection input signal 1 and the detection input signal 2 are at high level.

[0061] III. When the detection output signal Vo provided by the output module is at a high level of 1, the detection chip determines that the input terminal Vin1 of the input module is at a high level and Vin2 is at a low level. That is to say, it is determined that the detection input signal 1 is at a high level while the detection input signal 2 is at a low level;

[0062] IV. When the detection output signal Vo provided by the output module is at a low level, the detection chip determines that the input terminal Vin1 of the input module is at a low level and Vin2 is at a high level. That is to say, it is determined that the detection input signal 1 is at a low level while the detection input signal 2 is at a high level.

[0063] As can be seen from the technical solution provided by the present invention above, compared with the prior art, the present invention provides a signal detection circuit with polymorphic output. Its design is scientific, and it can characterize the states of two input signals through four signal states of one output port, realizing parallel signal detection. It not only saves the number of input and output ports of signal processing chips (such as single-chip microcontrollers), but also reduces the detection error caused by detection delay, and has great practical significance in production practice.

[0064] For the technical solution of the present invention, the hardware circuit design is scientific, and the electronic components are commonly used models, which are easy to select and have low component prices. Therefore, the technical solution of the present invention has strong practical value and market promotion value. BRIEF DESCRIPTION OF THE DRAWINGS

[0065] Figure 1 It is a block diagram of the structure of the first embodiment of a signal detection circuit with polymorphic output provided by the present invention;

[0066] Figure 2 It is a specific schematic diagram of the first embodiment of the input module and the output module in a signal detection circuit with polymorphic output provided by the present invention;

[0067] Figure 3 It is a block diagram of the structure of the second embodiment of a signal detection circuit with polymorphic output provided by the present invention;

[0068] Figure 4 It is a specific schematic diagram of the second embodiment of the input module and the output module in a signal detection circuit with polymorphic output provided by the present invention. DETAILED DESCRIPTION OF THE EMBODIMENTS

[0069] To make the technical means implemented by the present invention easier to understand, the following further details the present application with reference to the drawings and embodiments. It can be understood that the specific embodiments described herein are only for explaining the relevant application and not for limiting the application. Additionally, it should be noted that for the sake of convenience of description, only parts related to the present application are shown in the drawings.

[0070] It should be noted that, without conflict, the embodiments in this application and the features in the embodiments can be combined with each other. The following will describe this application in detail with reference to the accompanying drawings and in combination with the embodiments.

[0071] For those skilled in the art, the specific meanings of the above terms in this application can be understood according to specific circumstances.

[0072] See Figures 1 to 4 , the present invention provides a signal detection circuit with polymorphic output, including an input module 10, an output module 20, and a second power module 40;

[0073] Among them, the input terminal Vin1 of the input module 10 is used to receive the detection input signal 1;

[0074] The input terminal Vin2 of the input module 10 receives the detection input signal 2;

[0075] It should be noted that for the present invention, the detection input signal Vin1 and the detection input signal Vin2 should have two states of high level and low level, and at the same time, they also need to have a driving ability of at least 1 mA. Specifically, in implementation, it can be any existing circuit or functional module that can provide two signals with two states of high level and low level to provide the detection input signal Vin1 and the detection input signal Vin2.

[0076] The first output terminal of the input module 10 is connected to the input terminal A1 of the output module 20, and is used to provide the control signal A1 for the output module 20;

[0077] The second output terminal of the input module 10 is connected to the input terminal A2 of the output module 20, and is used to provide the control signal A2 for the output module 20;

[0078] Among them, the input terminal A1 of the output module 20 is connected to the first output terminal of the input module 10, and is used to receive the control signal A1 output by the input module 10;

[0079] The input terminal A2 of the output module 20 is connected to the second output terminal of the input module 10, and is used to receive the control signal A2 output by the input module 10;

[0080] The power input terminal of the output module 20 is connected to the output terminal VDD2 of the second power module 40, and is used to receive the DC power supply VDD2;

[0081] The output terminal Vo of the output module 20 is connected to the detection chip 50 (such as a single-chip microcomputer) for providing a detection output signal Vo to the detection chip. The detection output signal includes four states: 0V, low level, high level 2, and high level 1. Among them, the voltage of high level 1 is greater than that of high level 2, and their respective voltage values are determined according to the DC power supply VDD2.

[0082] It should be noted that the detection chip 50 is used to pre-store and set the correspondence between the detection output signal Vo in four different states and the two detection input signals in different states, and determine the states of the two detection input signals correspondingly according to the state of the currently received detection output signal Vo. Among them, the two detection input signals include the detection input signal 1 and the detection input signal 2.

[0083] It should be noted that the detection chip 50 can select a commonly used single-chip microcomputer, such as the 8051 single-chip microcomputer (the 8051 single-chip microcomputer is an 8-bit single-chip microcontroller), etc.

[0084] In the present invention, specifically, a signal detection circuit with multi-state output provided by the present invention further includes a first power module 30 when the detection input signal 1 and the detection input signal 2 are not common-ground signals.

[0085] Among them, the power input terminal of the input module 10 is connected to the output terminal VDD1 of the first power module 30 for receiving the DC power supply VDD1.

[0086] In the present invention, see Figure 1 , the working principle of the present invention is as follows:

[0087] 1. When the input terminals Vin1 and Vin2 of the input module 10 are both at low level, the input terminals A1 and A2 of the output module 20 are both at high level, then the output terminal Vo of the output module 20 is 0V.

[0088] Since the detection output signal Vo provided by the output module 20 is 0V, the detection chip determines that the input terminals Vin1 and Vin2 of the input module 10 are both at low level, that is, it determines that the detection input signal 1 and the detection input signal 2 are both at low level.

[0089] 2. When the input terminals Vin1 and Vin2 of the input module 10 are both at high level, the input terminals A1 and A2 of the output module 20 are both at low level, then the output terminal Vo of the output module 20 is high level 2 (the voltage of the level is less than high level 1).

[0090] Since the detection output signal Vo provided by the output module 20 is at a high level 2, the detection chip determines that both the input terminals Vin1 and Vin2 of the input module 10 are at a high level. That is to say, it is determined that both the detection input signal 1 and the detection input signal 2 are at a high level.

[0091] Third, when the input terminal Vin1 of the input module 10 is at a high level and Vin2 is at a low level, the input terminal A1 of the output module 20 is made at a low level and A2 is at a high level, then the output terminal Vo of the output module 20 is at a high level 1 (the level voltage is greater than the high level 2);

[0092] Since the detection output signal Vo provided by the output module 20 is at a high level 1, the detection chip determines that the input terminal Vin1 of the input module 10 is at a high level and Vin2 is at a low level. That is to say, the detection input signal 1 is at a high level, while the detection input signal 2 is at a low level.

[0093] Fourth, when the input terminal Vin1 of the input module 10 is at a low level and Vin2 is at a high level, the input terminal A1 of the output module 20 is made at a high level and A2 is at a low level, then the output terminal Vo of the output module 20 is at a low level (the level voltage is greater than 0V and less than the high level 2);

[0094] Since the detection output signal Vo provided by the output module 20 is at a low level, the detection chip determines that the input terminal Vin1 of the input module 10 is at a low level and Vin2 is at a high level. That is to say, the detection input signal 1 is at a low level, while the detection input signal 2 is at a high level.

[0095] In summary, the present invention can simultaneously detect the states of two detection input signals through the signal state of one output port (i.e., the state of the detection output signal Vo), realizing the signal parallel detection function, reducing the signal detection error caused by time delay, and improving the correctness of signal detection.

[0096] Therefore, by applying the signal detection circuit with polymorphic output provided by the present invention, it is possible to realize the parallel detection of two input signals.

[0097] Embodiment 1, see Figure 1 、 Figure 2 , at this time, the detection input signal 1 and the detection input signal 2 are not common ground signals.

[0098] In the present invention, in terms of specific implementation, see Figure 2 , the input module 10 includes: resistors R1 to R4, switching transistors Q1 to Q2, and optocouplers Q56 to Q57;

[0099] Among them, the first pin of the resistor R1 serves as the input terminal Vin1 of the input module 10 for receiving the detection input signal 1;

[0100] The second pin of resistor R1 is connected to the base B of switching transistor Q1;

[0101] The emitter E of switching transistor Q1 is connected to ground terminal GND1;

[0102] The collector C of switching transistor Q1 is connected to the second pin of optocoupler Q6;

[0103] The first pin of optocoupler Q6 is connected to the second pin of resistor R3;

[0104] The third pin of optocoupler Q6 serves as the first output terminal of input module 10 and is connected to the input terminal A1 of output module 20 (specifically, the gate G of switching transistor Q4 in output module 20), for outputting control signal A1 to output module 20;

[0105] The fourth pin of optocoupler Q6 is connected to ground terminal GND2;

[0106] Among them, the first pin of resistor R2 serves as the input terminal Vin2 of input module 10, for receiving detection input signal 2;

[0107] The second pin of resistor R2 is connected to the base B of switching transistor Q2;

[0108] The emitter E of switching transistor Q2 is connected to ground terminal GND1;

[0109] The collector C of switching transistor Q2 is connected to the second pin of optocoupler Q7;

[0110] The first pin of optocoupler Q7 is connected to the second pin of resistor R4;

[0111] The third pin of optocoupler Q7 serves as the second output terminal of input module 10 and is connected to the input terminal A2 of output module 20 (specifically, the gate G of switching transistor Q3 in output module 20), for outputting control signal A2 to output module 20;

[0112] The fourth pin of optocoupler Q7 is connected to ground terminal GND2;

[0113] The first pins of resistor R3 and resistor R4, after converging and intersecting, serve as the power input terminal of input module 10 and are connected to the output terminal VDD1 of first power module 30, for receiving DC power supply VDD1.

[0114] In the present invention, in terms of specific implementation, for Embodiment 1, refer to Figure 2 , output module 20 includes: resistors R5 to R11, switching transistors Q3 to Q5, and diode D1, where:

[0115] The first pins of resistor R5 and resistor R6, as the power input terminals of the output module 20, are connected to the output terminal VDD2 of the power module 40 to receive the DC power supply VDD2, such as 5V.

[0116] The first pin of resistor R5 is also respectively connected to the first pin of resistor R7, the first pin of resistor R11, and the first pin of resistor R9.

[0117] The second pin of resistor R5, as the input terminal A1 of the output module 20, is connected to the first output terminal of the input module 10 (specifically, the third pin of optocoupler Q6 in the input module 10) to receive the control signal A1.

[0118] The second pin of resistor R6, as the input terminal A2 of the output module 20, is connected to the second output terminal of the input module 10 (specifically, the third pin of optocoupler Q7 in the input module 10) to receive the control signal A2.

[0119] The second pin of resistor R5 is also connected to the gate G of switch Q4.

[0120] The source S of switch Q4 is connected to the second pin of resistor R7.

[0121] The drain D of switch Q4, as the output terminal Vo of the output module 20, is used to output the detection output signal Vo to the detection chip 50. The detection output signal Vo has four states: 0V, low level, high level 2, and high level 1. Among them, the voltage of high level 1 is greater than the voltage of high level 2.

[0122] The drain D of switch Q4 is also respectively connected to the anode of diode D1, the first pin of resistor R10, and the drain D of switch Q5.

[0123] The cathode of diode D1 is connected to the first pin of resistor R8.

[0124] The source S of switch Q3 is respectively connected to the second pin of resistor R8, the second pin of resistor R11, and the gate G of switch Q5.

[0125] The drain D of switch Q3 is connected to the ground terminal GND2.

[0126] The gate G of switch Q3, as the input terminal A2 of the output module 20, is connected to the second output terminal of the input module 10 to receive the control signal A2.

[0127] The gate G of switch Q3 is also connected to the second pin of resistor R6.

[0128] Among them, the source S of switch Q5 is connected to the second pin of resistor R9.

[0129] The second pin of resistor R10 is connected to the ground terminal GND2.

[0130] In the present invention, specifically, the logic level state of the output terminal Vo of the output module 20 is as follows:

[0131] I. When both the detection input signal 1 and the detection input signal 2 (i.e., the signals at the input terminals Vin1 and Vin2) are 0, the output signal Vo is 0V;

[0132] II. When the detection input signal 1 is 1 and the detection input signal 2 is 0, the detected output signal Vo is at a high level 1;

[0133] III. When the detection input signal 1 is 0 and the detection input signal 2 is 1, the output signal Vo is at a low level;

[0134] IV. When both the detection input signals Vin1 and Vin2 are 1, the detected output signal Vo is at a high level 2;

[0135] It should be noted that in the above logic level states, for the detection input signal 1 and the detection input signal 2, a low level represents no signal input; 1 represents a high level, representing a signal input; the voltage of the high level 1 is greater than the voltage of the high level 2, and the voltage of the low level is greater than 0V;

[0136] In the present invention, specifically, referring to Figure 2 , the working principle of the signal detection circuit of the present invention is as follows:

[0137] I. When both the input terminals Vin1 and Vin2 of the input module 10 are at a low level, the switching transistors Q1 - Q2 and the optocouplers Q6 - Q7 in the input module 10 are all cut off, respectively making their output terminals A1 and A2 at a high level. Among them, the output terminals A1 and A2 are respectively pulled up by the resistors R5 and R6 in the output module 20 to be equal to the power supply voltage of the power supply VDD1, thereby respectively making the switching transistors Q3 and Q4 in the output module 20 all cut off. Since the switching transistor Q3 is cut off, the switching transistor Q5 is also cut off. Then, the output terminal Vo of the output module 20 is pulled down by the resistor R10 to the ground terminal voltage and becomes 0V;

[0138] Since the detected output signal Vo of the output terminal Vo of the output module 20 is 0V, the detection chip (such as a single - chip microcomputer) can determine that both the input terminals Vin1 and Vin2 of the input module 10 are at a low level.

[0139] Second, when the input terminal Vin1 of the input module 10 is at a high level while Vin2 is at a low level, the low-level Vin2 causes both the switching transistor Q2 and the optocoupler Q7 in the input module 10 to be cut off, making the A2 terminal at a high level. As a result, both the switching transistors Q3 and Q5 in the output module 20 are cut off. And the high-level Vin1 causes the switching transistor Q1 and the optocoupler Q6 to conduct, making the A1 terminal at a low level. Then, the switching transistor Q4 in the output module 20 conducts, making its output terminal Vo at a high level 1. The amplitude of its level voltage is equal to: the voltage obtained by dividing the power supply VDD2 by the resistors R7 and R10 in series. This voltage value is greater than the voltage of the high level 2;

[0140] Since the output signal Vo of the output terminal Vo is at a high level 1, the detection chip (such as a single-chip microcomputer) can determine that the input terminal Vin1 of the input module 10 is at a high level while Vin2 is at a low level.

[0141] Third, when the input terminal Vin1 of the input module 10 is at a low level while Vin2 is at a high level, the low-level Vin1 causes both the switching transistor Q1 and the optocoupler Q6 in the input module 10 to be cut off, making the A1 terminal at a high level. As a result, the switching transistor Q4 in the output module 20 is cut off. And both the switching transistor Q2 and the optocoupler Q7 conduct, making the A2 terminal at a low level. Then, the switching transistor Q3 in the output module 20 conducts, and thus the switching transistor Q5 conducts. At this time, the output terminal Vo of the output module 20 is at a low level. The amplitude of its level voltage is equal to: the voltage obtained by dividing the power supply VDD2 by the parallel resistance of the resistors R8 and R10 and the resistor R9 in series. This voltage value is greater than 0V and less than the voltage of the high level 2;

[0142] Since the output signal Vo of the output terminal Vo is at a low level, the detection chip (such as a single-chip microcomputer) can determine that the input terminal Vin1 of the input module 10 is at a low level while Vin2 is at a high level.

[0143] Fourth, when the input terminals Vin1 and Vin2 of the input module 10 are both at a high level, both the switching transistors Q1 - Q2 and the optocouplers Q6 - Q7 in the input module 10 conduct. As a result, both the switching transistors Q3 - Q5 in the output module 20 conduct. Then, the output terminal Vo of the output module 20 is at a high level 2. The amplitude of its level voltage is equal to: the voltage obtained by dividing the power supply VDD2 by the parallel resistance of the resistors R7 and R9 and the parallel resistance of the resistors R8 and R10 in series. This voltage value is greater than the low level and less than the voltage of the high level 1;

[0144] Since the output signal Vo of the output terminal Vo is at a high level 2, the detection chip (such as a single-chip microcomputer) can determine that both the input terminals Vin1 and Vin2 of the input module 10 are at a high level.

[0145] It should be noted that the value of the resistor R11 should be much larger than that of the resistors R7 and R9. For example, if the values of the resistors R7 and R9 are 1 kΩ, then the value of R11 should be 1 MΩ.

[0146] It should be noted that the corresponding relationship between the detected output signal Vo and the detected input signals Vin1 and Vin2 should be pre-stored in a detection chip (such as a single-chip microcomputer).

[0147] In the present invention, specifically, it should be noted that the first power supply module 30 and the second power supply module 40 are two independent power supplies and are not grounded together.

[0148] In the present invention, specifically, it should be noted that the first power supply module 30 and the second power supply module 40 can adopt existing power supply modules. For example, a power supply circuit commonly used in existing BMS technical solutions can be adopted. Technical personnel can easily obtain and apply it without innovation, and its technical solutions do not belong to the technical solutions of the present invention, so no specific explanation is given here.

[0149] Embodiment 2, see Figure 3 、 Figure 4 , at this time, the detected input signal 1 and the detected input signal 2 are grounded signals.

[0150] In the present invention, specifically, as Figure 3 、 Figure 4 shown, when the detected input signals Vin1 and Vin2 are grounded signals, then, at this time, the input module 10 includes a resistor R1 and a resistor R2:

[0151] Among them, the first pin of the resistor R1 serves as the input terminal Vin1 of the input module 10 and is used to receive the detected input signal 1;

[0152] The second pin of the resistor R1 is connected to the base B of the switching transistor Q1;

[0153] The emitter E of the switching transistor Q1 is connected to the ground terminal GND1;

[0154] The collector C of the switching transistor Q1 is connected to the input terminal A2 of the output module 20 (specifically, the gate G of the switching transistor Q3 in the output module 20) and is used to output a control signal A2 for the output module 20;

[0155] Among them, the first pin of the resistor R2 serves as the input terminal Vin2 of the input module 10 and is used to receive the detected input signal 2;

[0156] The second pin of the resistor R2 is connected to the base B of the switching transistor Q2;

[0157] The emitter E of the switching transistor Q2 is connected to the ground terminal GND1;

[0158] The collector C of the switching transistor Q2 is connected to the input terminal A1 of the output module 20 (specifically, the gate G of the switching transistor Q4 in the output module 20), and is used to output a control signal A1 to the output module 20.

[0159] It should be noted that Figure 4 The structural design and working principle of the output module 20 in Figure 2 are the same as those of the output module 20 in

[0160] and will not be elaborated here. Figure 3 、 Figure 4 If the input signals Vin1 and Vin2 are common-ground signals for the present invention, then, as shown in Figure 2 the resistors R3 - R4 and the optocouplers Q6 - Q7 in the input module 10 can be deleted, the collector C of the switching transistor Q2 can be connected to the A1 terminal, the collector C of the switching transistor Q2 can be connected to the A2 terminal, and at the same time, the power input terminal of the input module 10 can be removed. There is no need to configure the first power module 30, and only the second power module 40 needs to be configured for the output module 20 and the output terminal VDD2 of the second power module can be connected.

[0161] It should be noted that for the present invention, the state of two input signals can be characterized by the signal state of one input-output port, enabling parallel detection of multiple signals, ensuring the synchronization of signal detection, and saving the I / O (input-output port) resources of the single-chip microcomputer.

[0162] In summary, compared with the prior art, a signal detection circuit with multi-state output provided by the present invention has a scientific design. The states of two input signals can be characterized by four signal states of one output port, realizing parallel signal detection. This not only saves the number of input-output ports of the signal processing chip (such as a single-chip microcomputer), but also reduces the detection error caused by detection delay, and has great significance in production practice.

[0163] For the technical solution of the present invention, the hardware circuit design is scientific, the electronic components are commonly used models, easy to select, and the component prices are low. Therefore, the technical solution of the present invention has strong practical value and market promotion value.

[0164] The above are only the preferred embodiments of the present invention. It should be pointed out that for those of ordinary skill in the art, without departing from the principle of the present invention, several improvements and refinements can be made, and these improvements and refinements should also be regarded as the protection scope of the present invention.

Claims

1. A signal detection circuit with polymorphic output, characterized in that, It includes an input module (10), an output module (20) and a second power supply module (40); among them, the input terminal Vin1 of the input module (10) is used to receive the detection input signal 1; the input terminal Vin2 of the input module (10) receives the detection input signal 2; the first output terminal of the input module (10) is connected to the input terminal A1 of the output module (20) to provide the control signal A1 for the output module (20); the second output terminal of the input module (10) is connected to the input terminal A2 of the output module (20) to provide the control signal A2 for the output module (20); among them, the input terminal A1 of the output module (20) is connected to the first output terminal of the input module (10) to receive the control signal A1 output by the input module (10); the input terminal A2 of the output module (20) is connected to the second output terminal of the input module (10) to receive the control signal A2 output by the input module (10); the power input terminal of the output module (20) is connected to the output terminal VDD2 of the second power supply module (40) to receive the DC power supply VDD2; the output terminal Vo of the output module (20) is connected to the detection chip (50) to provide the detection output signal Vo for the detection chip; the detection output signal includes four states: 0V, low level, high level 2 and high level 1, where the voltage of high level 1 is greater than the voltage of high level 2; The output module (20) includes: resistors R5 to R11, switching transistors Q3 to Q5, and diode D1, where: the first pins of resistor R5 and resistor R6 serve as the power input terminal of the output module (20) and are connected to the output terminal VDD2 of the power module (40) for receiving a DC power supply VDD2, such as 5V; the first pin of resistor R5 is also respectively connected to the first pin of resistor R7, the first pin of resistor R11, and the first pin of resistor R9; the second pin of resistor R5 serves as the input terminal A1 of the output module (20) and is connected to the first output terminal of the input module (10) for receiving a control signal A1; the second pin of resistor R6 serves as the input terminal A2 of the output module (20) and is connected to the second output terminal of the input module (10) for receiving a control signal A2; the second pin of resistor R5 is also connected to the gate G of switching transistor Q4; the source S of switching transistor Q4 is connected to the second pin of resistor R7; the drain D of switching transistor Q4 serves as the output terminal Vo of the output module (20) for outputting a detection output signal Vo to the detection chip (50); the drain D of switching transistor Q4 is also respectively connected to the anode of diode D1, the first pin of resistor R10, and the drain D of switching transistor Q5; the cathode of diode D1 is connected to the first pin of resistor R8; the source S of switching transistor Q3 is respectively connected to the second pin of resistor R8, the second pin of resistor R11, and the gate G of switching transistor Q5; the drain D of switching transistor Q3 is connected to the ground terminal GND2; the gate G of switching transistor Q3 serves as the input terminal A2 of the output module (20) and is connected to the second output terminal of the input module (10) for receiving a control signal A2; the gate G of switching transistor Q3 is also connected to the second pin of resistor R6; where, the source S of switching transistor Q5 is connected to the second pin of resistor R9; the second pin of resistor R10 is connected to the ground terminal GND2; It includes the following working modes: First, when the detection output signal Vo provided by the output module (20) is 0V, the detection chip determines that both input terminals Vin1 and Vin2 of the input module (10) are at low level, that is, it determines that both the detection input signal 1 and the detection input signal 2 are at low level; Second, when the detection output signal Vo provided by the output module (20) is high level 2, the detection chip determines that both input terminals Vin1 and Vin2 of the input module (10) are at high level, that is, it determines that both the detection input signal 1 and the detection input signal 2 are at high level; Third, when the detection output signal Vo provided by the output module (20) is high level 1, the detection chip determines that the input terminal Vin1 of the input module (10) is at high level and Vin2 is at low level, that is, it determines that the detection input signal 1 is at high level while the detection input signal 2 is at low level; Fourth, when the detection output signal Vo provided by the output module (20) is at low level, the detection chip determines that the input terminal Vin1 of the input module (10) is at low level and Vin2 is at high level, that is, it determines that the detection input signal 1 is at low level while the detection input signal 2 is at high level.

2. The signal detection circuit with polymorphic output according to claim 1, characterized in that, When the detection input signal 1 and the detection input signal 2 are not common-ground signals, it further includes a first power supply module (30); wherein, the power input terminal of the input module (10) is connected to the output terminal VDD1 of the first power supply module (30) for receiving the DC power supply VDD1.

3. The signal detection circuit with polymorphic output according to claim 2, characterized in that, The input module (10) includes resistors R1 to R4, switching transistors Q1 to Q2, and optocouplers Q6 to Q7; wherein, the first pin of resistor R1 serves as the input terminal Vin1 of the input module (10) for receiving the detection input signal 1; the second pin of resistor R1 is connected to the base B of switching transistor Q1; the emitter E of switching transistor Q1 is connected to the ground terminal GND1; the collector C of switching transistor Q1 is connected to the second pin of optocoupler Q6; the first pin of optocoupler Q6 is connected to the second pin of resistor R3; the third pin of optocoupler Q6 serves as the first output terminal of the input module (10) and is connected to the input terminal A1 of the output module (20) for outputting a control signal A1 to the output module (20); the fourth pin of optocoupler Q6 is connected to the ground terminal GND2; wherein, the first pin of resistor R2 serves as the input terminal Vin2 of the input module (10) for receiving the detection input signal 2; the second pin of resistor R2 is connected to the base B of switching transistor Q2; the emitter E of switching transistor Q2 is connected to the ground terminal GND1; the collector C of switching transistor Q2 is connected to the second pin of optocoupler Q7; the first pin of optocoupler Q7 is connected to the second pin of resistor R4; the third pin of optocoupler Q7 serves as the second output terminal of the input module (10) and is connected to the input terminal A2 of the output module (20) for outputting a control signal A2 to the output module (20); the fourth pin of optocoupler Q7 is connected to the ground terminal GND2; the first pins of resistors R3 and R4 are connected together after converging and then serve as the power input terminal of the input module (10), which is connected to the output terminal VDD1 of the first power supply module (30) for receiving the DC power supply VDD1.

4. The signal detection circuit with polymorphic output according to claim 1, characterized in that, When the detection input signals Vin1 and Vin2 are common-ground signals, the input module (10) includes resistors R1 and R2: wherein, the first pin of resistor R1 serves as the input terminal Vin2 of the input module (10) for receiving the detection input signal 1; the second pin of resistor R1 is connected to the base B of switching transistor Q1; the emitter E of switching transistor Q1 is connected to the ground terminal GND1; the collector C of switching transistor Q1 is connected to the input terminal A2 of the output module (20) for outputting a control signal A2 to the output module (20); wherein, the first pin of resistor R2 serves as the input terminal Vin1 of the input module (10) for receiving the detection input signal 2; the second pin of resistor R2 is connected to the base B of switching transistor Q2; the emitter E of switching transistor Q2 is connected to the ground terminal GND1; the collector C of switching transistor Q2 is connected to the input terminal A1 of the output module (20) for outputting a control signal A1 to the output module (20).

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