Pixel circuit, driving method and display device

Abstract

The present invention provides a pixel circuit, a driving method and a display device. The pixel circuit includes a light-emitting element, a first reset circuit, a driving circuit and a light-emitting control circuit; the first reset circuit is electrically connected to a reset control line, a first reset voltage line and a first pole of the light-emitting element respectively, and is used for a reset time period included in multiple stop-light-emitting stages in a frame time. Under the control of a reset control signal provided by the reset control line, a first reset voltage signal provided by the first reset voltage line is repeatedly written into the first pole of the light-emitting element to control the light-emitting element not to emit light. The present invention can timely control the light-emitting element not to emit light in the stop-light-emitting stage, thereby avoiding the phenomenon of light leakage from the back of the display panel (the display panel includes the pixel circuit).

Description

Technical Field

[0001] The present invention relates to the field of display technology, and in particular to a pixel circuit, a driving method and a display device. Background Art

[0002] In the related art, when an OLED (organic light emitting diode) display screen is used under low ambient light, a PWM (pulse width modulation) technology is usually used to control the brightness of the OLED display screen, that is, the duty cycle of the light emitting control signal is adjusted to adjust the duration of the OLED lighting in a cycle. The greater the duty cycle of the light emitting control signal, the longer the OLED lighting duration in a cycle, and the greater the brightness of the OLED display screen. Under normal circumstances, within a cycle, the OLED in the OLED display screen can be turned off and on multiple times by controlling the light emitting control signal. In a specific implementation, an ambient light sensor is placed on the back of the OLED display screen. If the back of the OLED display screen emits bright light, it will affect the sensing accuracy of the ambient light sensor. When the OLED display screen is working, due to the device itself, the carriers cannot stop migrating immediately at the moment when the potential of the light emitting control signal is switched to an invalid voltage, and the OLED display screen cannot be turned off immediately. There is a process from the OLED turning on to the off. The bright light generated by the OLED shines directly on the back of the OLED display screen through the gaps in the panel wiring, affecting the operation of the ambient light sensor. Summary of the invention

[0003] The main purpose of the present invention is to provide a pixel circuit, a driving method and a display device to solve the problem of light leakage from the back of the display panel caused by the failure of the light emitting element to stop emitting light in time during the stop emitting stage when the existing display device is working.

[0004] An embodiment of the present invention provides a pixel circuit, including a light-emitting element, a first reset circuit, a driving circuit and a light-emitting control circuit;

[0005] The first reset circuit is electrically connected to the reset control line, the first reset voltage line and the first electrode of the light emitting element respectively, and is used to write the first reset voltage signal provided by the first reset voltage line into the first electrode of the light emitting element multiple times under the control of the reset control signal provided by the reset control line during the reset time period included in the multiple light stopping stages in one frame time, so as to control the light emitting element not to emit light;

[0006] The second electrode of the light emitting element is electrically connected to the first voltage line;

[0007] The driving circuit is used to generate a driving current under the control of the potential of its control terminal;

[0008] The light-emitting control circuit is electrically connected to the light-emitting control line, the second voltage line, the first end of the drive circuit, the second end of the drive circuit and the first pole of the light-emitting element, respectively, and is used to control the second voltage line to be disconnected from the first end of the drive circuit, and to control the second end of the drive circuit to be disconnected from the first pole of the light-emitting element under the control of the light-emitting control signal provided by the light-emitting control line during the light-emitting stop stage.

[0009] Optionally, the reset time period includes the start time of the stop lighting phase.

[0010] Optionally, the first reset circuit includes a first transistor;

[0011] A gate of the first transistor is electrically connected to the reset control line, a first electrode of the first transistor is electrically connected to the first reset voltage line, and a second electrode of the first transistor is electrically connected to a first electrode of the light emitting element.

[0012] Optionally, the pixel circuit described in the embodiment of the present invention further includes a data writing circuit, a compensation control circuit, a second reset circuit and an energy storage circuit;

[0013] The data writing circuit is electrically connected to the gate line, the data line and the first end of the driving circuit respectively, and is used to write the data voltage on the data line into the first end of the driving circuit under the control of the gate driving signal provided by the gate line;

[0014] The compensation control circuit is electrically connected to the gate line, the control end of the drive circuit and the second end of the drive circuit respectively, and is used to control the connection or disconnection between the control end of the drive circuit and the second end of the drive circuit under the control of the gate drive signal;

[0015] The second reset circuit is electrically connected to the reset control line, the second reset voltage line and the control end of the drive circuit, and is used to write the second reset voltage provided by the second reset voltage line into the control end of the drive circuit under the control of the reset control signal provided by the reset control line;

[0016] The energy storage circuit is electrically connected to the control end of the drive circuit and is used to maintain the potential of the control end of the drive circuit.

[0017] Optionally, the driving circuit includes a driving transistor; the light emitting control circuit includes a second transistor and a third transistor;

[0018] The gate of the second transistor is electrically connected to the light emitting control line, the first electrode of the second transistor is electrically connected to the second voltage line, and the second electrode of the second transistor is electrically connected to the first electrode of the driving transistor;

[0019] The gate of the third transistor is electrically connected to the light emitting control line, the first electrode of the third transistor is electrically connected to the second electrode of the driving transistor, and the second electrode of the third transistor is electrically connected to the first electrode of the light emitting element;

[0020] The gate of the driving transistor is electrically connected to the control terminal of the driving circuit;

[0021] The data writing circuit includes a fourth transistor, the compensation control circuit includes a fifth transistor, the second reset circuit includes a sixth transistor, and the energy storage circuit includes a storage capacitor;

[0022] The gate of the fourth transistor is electrically connected to the gate line, the first electrode of the fourth transistor is electrically connected to the data line, and the second electrode of the fourth transistor is electrically connected to the first electrode of the driving transistor;

[0023] The gate of the fifth transistor is electrically connected to the gate line, the first electrode of the fifth transistor is electrically connected to the gate of the driving transistor, and the second electrode of the fifth transistor is electrically connected to the second electrode of the driving transistor;

[0024] The gate of the sixth transistor is electrically connected to the reset control line, the first electrode of the sixth transistor is electrically connected to the second reset voltage line, and the second electrode of the sixth transistor is electrically connected to the gate of the driving transistor;

[0025] The first plate of the storage capacitor is electrically connected to the gate of the driving transistor, and the second plate of the storage capacitor is electrically connected to the second voltage line.

[0026] An embodiment of the present invention further provides a driving method, which is applied to the above-mentioned pixel circuit, wherein one frame time includes a plurality of light-stopping stages, and the plurality of light-stopping stages respectively include a reset time period; the driving method includes:

[0027] In the stop light emission stage, the light emission control circuit controls the second voltage line to be disconnected from the first end of the driving circuit and controls the second end of the driving circuit to be disconnected from the first electrode of the light emitting element under the control of the light emission control signal;

[0028] In the reset time period, the first reset circuit writes a first reset voltage signal into the first electrode of the light emitting element under the control of the reset control signal, so that the light emitting element does not emit light.

[0029] Optionally, the reset time period includes the start time of the stop lighting phase.

[0030] An embodiment of the present invention further provides a display device, comprising a display substrate, wherein the display substrate comprises a base, and a plurality of rows and columns of the above-mentioned pixel circuits arranged in a display area of ​​the base, and a reset control signal generating module arranged in a peripheral area of ​​the base;

[0031] The reset control signal generating module includes a multi-stage reset control signal generating circuit, and the reset control signal generating circuit is used to generate a reset control signal.

[0032] Optionally, the reset control signal generating circuit is electrically connected to the pixel circuits in two adjacent rows, and is used to provide corresponding reset control signals for the pixel circuits in the two adjacent rows.

[0033] Optionally, the reset control signal generating circuit includes a first node control circuit, a second node control circuit and an output circuit;

[0034] The first node control circuit is electrically connected to the first clock signal line, the third voltage line, the first node and the second node respectively, and is used to control the connection or disconnection between the first node and the third voltage line under the control of the first clock signal provided by the first clock signal line, and to control the connection or disconnection between the first node and the first clock signal line under the control of the potential of the second node;

[0035] The second node control circuit is electrically connected to the first clock signal line, the input terminal, the second node, the first node, the fourth voltage line and the second clock signal line respectively, and is used to control the connection or disconnection between the second node and the input terminal under the control of the first clock signal, and control the connection or disconnection between the second node and the fourth voltage line under the control of the potential of the first node and the second clock signal provided by the second clock signal line;

[0036] The output circuit is electrically connected to the first node, the third node, the fourth voltage line, the second clock signal line and the reset control signal output terminal respectively, and is used to maintain the potential of the first node, control the potential of the second node according to the potential of the reset control signal output terminal, and control the connection or disconnection between the reset control signal output terminal and the fourth voltage line under the control of the potential of the first node, and control the connection or disconnection between the reset control signal output terminal and the second clock signal line under the control of the potential of the third node;

[0037] The second node and the third node are the same node; or, the reset control signal generating circuit also includes an on-off control circuit, which is electrically connected to the third voltage line, the second node and the third node, respectively, and is used to control the connection or disconnection between the second node and the third node under the control of a third voltage signal provided by the third voltage line.

[0038] Optionally, the first node control circuit includes a first control transistor and a second control transistor;

[0039] The gate of the first control transistor is electrically connected to the first clock signal line, the first electrode of the first control transistor is electrically connected to the third voltage line, and the second electrode of the first control transistor is electrically connected to the first node;

[0040] The gate of the second control transistor is electrically connected to the second node, the first electrode of the second control transistor is electrically connected to the first clock signal line, and the second electrode of the second control transistor is electrically connected to the first node;

[0041] The second node control circuit includes a third control transistor, a fourth control transistor and a fifth control transistor;

[0042] The gate of the third control transistor is electrically connected to the first clock signal line, the first electrode of the third control transistor is electrically connected to the input terminal, and the second electrode of the third control transistor is electrically connected to the second node;

[0043] The gate of the fourth control transistor is electrically connected to the first node, and the first electrode of the fourth control transistor is electrically connected to the fourth voltage line;

[0044] The gate of the fifth control transistor is electrically connected to the second clock signal line, the first electrode of the fifth control transistor is electrically connected to the second electrode of the fourth control transistor, and the second electrode of the fifth control transistor is electrically connected to the second node;

[0045] The output circuit includes a first capacitor, a second capacitor, a first output transistor and a second output transistor;

[0046] The gate of the first output transistor is electrically connected to the first node, the first electrode of the first output transistor is electrically connected to the fourth voltage line, and the second electrode of the first output transistor is electrically connected to the reset control signal output terminal;

[0047] The gate of the second output transistor is electrically connected to the third node, the first electrode of the second output transistor is electrically connected to the reset control signal output terminal, and the second electrode of the second output transistor is electrically connected to the second clock signal line;

[0048] The first plate of the second capacitor is electrically connected to the reset control signal output terminal, and the second plate of the second capacitor is electrically connected to the third node;

[0049] The first plate of the first capacitor is electrically connected to the first node, and the second plate of the first capacitor is electrically connected to the fourth voltage line;

[0050] The reset control signal generating circuit further comprises an on-off control circuit, and the on-off control circuit comprises an on-off control transistor;

[0051] A gate of the on-off control transistor is electrically connected to the third voltage line, a first electrode of the on-off control transistor is electrically connected to the second node, and a second electrode of the on-off control transistor is electrically connected to the third node.

[0052] Optionally, the display device described in the embodiment of the present invention further includes a gate driving module disposed in the peripheral area of ​​the substrate, the gate driving module includes a multi-stage gate driving circuit, and the gate driving circuit is used to provide a corresponding gate driving signal for the corresponding row pixel circuit;

[0053] The reset control signal generating circuit is located at a side of the gate driving circuit away from the display area.

[0054] Optionally, the display substrate comprises a first third voltage line, a second third voltage line and a fourth voltage line; the first third voltage line, the second third voltage line and the fourth voltage line all extend along the first direction;

[0055] In the reset control signal generating circuit, the first output transistor, the second output transistor and the on-off control transistor are arranged between the first capacitor and the second capacitor, the first output transistor and the second output transistor are arranged along a first direction, and the second capacitor, the first output transistor, the on-off control transistor and the first capacitor are arranged in sequence along a direction away from the display area;

[0056] The orthographic projection of the first plate of the second capacitor on the substrate and the orthographic projection of the second plate of the second capacitor on the substrate at least partially overlap, and the orthographic projection of the first plate of the first capacitor on the substrate and the orthographic projection of the second plate of the first capacitor on the substrate at least partially overlap; the orthographic projection of the first plate of the second capacitor on the substrate partially overlaps with the orthographic projection of the first third voltage line on the substrate, and the orthographic projection of the first plate of the first capacitor on the substrate partially overlaps with the orthographic projection of the fourth voltage line on the substrate.

[0057] Optionally, the active layer of the first output transistor includes at least one first output channel portion extending along the second direction, and the active layer of the second output transistor includes at least one second output channel portion extending along the second direction;

[0058] The at least one first output channel portion and the at least one second output channel portion are arranged along a first direction;

[0059] A length of the first output channel portion along the second direction and a length of the second output channel portion along the second direction are both less than a first predetermined length.

[0060] Optionally, the area of ​​the first plate of the first capacitor and the area of ​​the second plate of the first capacitor are both less than or equal to a first predetermined area, and the area of ​​the first plate of the second capacitor and the area of ​​the second plate of the second capacitor are both less than or equal to a second predetermined area.

[0061] Optionally, in the reset control signal generating circuit, the first control transistor, the second control transistor, the third control transistor, the fourth control transistor and the fifth control transistor are arranged on a side of the first capacitor away from the display area, and the fourth control transistor and the fifth control transistor are arranged along a first direction.

[0062] Optionally, the display substrate includes a first clock signal line and a second clock signal line, the first clock signal line and the second clock signal line both extend along a first direction, and the first clock signal line, the second clock signal line and the second third voltage line are arranged on a side of the first control transistor away from the display area.

[0063] Optionally, the display substrate further comprises a light emitting control signal generating module and a reset control signal generating module disposed in the peripheral area of ​​the substrate; the light emitting control signal generating module comprises a multi-stage light emitting control signal generating circuit, and the light emitting control signal generating circuit is used to generate a light emitting control signal; the reset control signal generating module comprises a multi-stage reset control signal generating circuit, and the reset control signal generating circuit is used to generate a reset control signal;

[0064] The light emission control signal generating circuit is located at a side of the gate driving circuit away from the display area, and the reset control signal generating circuit is located at a side of the gate driving circuit away from the display area.

[0065] The pixel circuit, driving method and display device described in the embodiments of the present invention write a first reset voltage signal to the first electrode of the light-emitting element through a first reset circuit when the light-emitting element needs to stop emitting light, so that the light-emitting element does not emit light; in this way, the light-emitting element can be controlled in time not to emit light during the light-stopping stage, thereby avoiding light leakage from the back of the display panel (the display panel includes the pixel circuit). BRIEF DESCRIPTION OF THE DRAWINGS

[0066] Figure 1 is a structural diagram of a pixel circuit according to an embodiment of the present invention;

[0067] Figure 2 is a structural diagram of a pixel circuit according to an embodiment of the present invention;

[0068] Figure 3 is a circuit diagram of a pixel circuit according to an embodiment of the present invention;

[0069] Figure 4A The present invention is Figure 3 A first working timing diagram of the embodiment of the pixel circuit shown;

[0070] Figure 4B The present invention is Figure 3 A second working timing diagram of the embodiment of the pixel circuit shown;

[0071] Figure 5 yes Figure 3 A layout diagram of an embodiment of a pixel circuit shown in FIG.

[0072] Fig. 6A yes Figure 5 Schematic diagram of the active layer in;

[0073] Figure 6B yes Figure 5 A schematic diagram of the first gate metal layer in FIG.

[0074] Figure 6C for Figure 5 A schematic diagram of a second gate metal layer in FIG.

[0075] Fig.6D yes Figure 5 Schematic diagram of the source and drain metal layers in FIG.

[0076] Figure 7is a structural diagram of an embodiment of a reset control signal generating circuit in a display device according to the present invention;

[0077] Figure 8 is a circuit diagram of an embodiment of the reset control signal generating circuit;

[0078] Fig. 9 yes Figure 8 The working timing diagram of the embodiment of the reset control signal generating circuit shown;

[0079] Fig.10 yes Figure 8 The layout diagram of the embodiment of the reset control signal generating circuit shown in FIG.

[0080] Fig.11 yes Fig.10 The structure diagram of the active layer in ;

[0081] Fig.12 yes Fig.10 A structural diagram of the first gate metal layer in FIG.

[0082] Fig.13 yes Fig.10 A structural diagram of the second gate metal layer in FIG.

[0083] Fig.14 yes Fig.10 Structural diagram of source and drain metal layers in FIG.

[0084] Fig.15 It is a schematic diagram of the structure of the display device according to an embodiment of the present invention. DETAILED DESCRIPTION

[0085] The following will be combined with the drawings in the embodiments of the present invention to clearly and completely describe the technical solutions in the embodiments of the present invention. Obviously, the described embodiments are only part of the embodiments of the present invention, not all of the embodiments. Based on the embodiments of the present invention, all other embodiments obtained by ordinary technicians in this field without creative work are within the scope of protection of the present invention.

[0086] The transistors used in all embodiments of the present invention may be thin film transistors or field effect transistors or other devices with the same characteristics. In the embodiments of the present invention, to distinguish the two electrodes of the transistor except the gate, one electrode is called the first electrode and the other electrode is called the second electrode.

[0087] In actual operation, when the transistor is a thin film transistor or a field effect transistor, the first electrode may be a drain electrode, and the second electrode may be a source electrode; or, the first electrode may be a source electrode, and the second electrode may be a drain electrode.

[0088] like Figure 1 As shown, the pixel circuit described in the embodiment of the present invention includes a light-emitting element 10 and a first reset circuit 11; the first reset circuit 11 is electrically connected to the reset control line AR, the first reset voltage line Vi1 and the first electrode of the light-emitting element 10 respectively, and is used to write the first reset voltage signal provided by the first reset voltage line Vi1 into the first electrode of the light-emitting element 10 under the control of the reset control signal provided by the reset control line AR, so as to control the light-emitting element 10 not to emit light;

[0089] The second electrode of the light emitting element 10 is electrically connected to the first voltage line V1 .

[0090] In at least one embodiment of the present invention, the first voltage line V1 may be a first low voltage line.

[0091] When the pixel circuit of the embodiment of the present invention is working, the first reset circuit 11 can write a first reset voltage signal to the first electrode of the light emitting element 10 when the light emitting element 10 needs to stop emitting light, so that the light emitting element 10 does not emit light. In this way, the light emitting element 10 can be controlled not to emit light in time during the stop-emitting stage, thereby avoiding the phenomenon of light leakage from the back of the display panel (the display panel includes the pixel circuit).

[0092] In at least one embodiment of the present invention, the light-emitting element may be an organic light-emitting diode, and the difference between the voltage value of the first reset voltage signal provided by the first reset voltage line Vi1 and the voltage value of the first voltage signal provided by the first voltage line V1 may be smaller than the turn-on voltage of the organic light-emitting diode.

[0093] Optionally, the first reset circuit includes a first transistor;

[0094] A gate of the first transistor is electrically connected to the reset control line, a first electrode of the first transistor is electrically connected to the first reset voltage line, and a second electrode of the first transistor is electrically connected to a first electrode of the light emitting element.

[0095] like Figure 1 As shown, the pixel circuit described in the embodiment of the present invention may further include a driving circuit 21 and a light emitting control circuit 22;

[0096] The light emitting control circuit 22 is electrically connected to the light emitting control line EM, the second voltage line V2, the first end of the driving circuit 21, the second end of the driving circuit 21 and the first pole of the light emitting element 10 respectively, and is used to control the connection or disconnection between the second voltage line V2 and the first end of the driving circuit 21, and control the connection or disconnection between the second end of the driving circuit 21 and the first pole of the light emitting element 10 under the control of the light emitting control signal provided by the light emitting control line EM;

[0097] The driving circuit 21 is used to generate a driving current under the control of the potential of its control terminal.

[0098] exist Figure 1 In the illustrated embodiment, the first reset circuit 11 is used for the reset time period included in multiple stop light emission stages in a frame time, and under the control of a reset control signal, writes the first reset voltage signal to the first pole of the light emitting element 10 multiple times so that the light emitting element 10 does not emit light; the light emission control circuit 21 is used for controlling the disconnection between the drive circuit 21 and the second voltage line V2, and controlling the disconnection between the second end of the drive circuit 21 and the first pole of the light emitting element 10 under the control of a light emission control signal during the stop light emission stage.

[0099] When the pixel circuit described in the embodiment of the present invention is working, one frame time may include multiple stop-lighting stages, and the multiple stop-lighting stages may respectively include a reset time period. During the reset time period, the first reset circuit 11 writes the first reset voltage signal into the first pole of the light-emitting element 10.

[0100] In the embodiment of the present invention, the first reset circuit 11 writes the first reset voltage signal multiple times into the first pole of the light-emitting element 10 during the reset time periods included in the multiple light-emitting stop phases in one frame time, which may refer to: writing the first reset voltage signal into the first pole of the light-emitting element 10 during the reset time period, and writing the first reset voltage signal multiple times into the first pole of the light-emitting element 10 during multiple reset time periods. That is, the first reset voltage signal may be written into the first pole of the light-emitting element 10 once during one reset time period, and thus the first reset voltage signal may be written into the first pole of the light-emitting element 10 multiple times during multiple reset time periods.

[0101] For example, one frame time includes a first stop light emission stage, a second stop light emission stage, a third stop light emission stage and a fourth stop light emission stage, the first stop light emission stage includes a first reset time period, the second stop light emission stage includes a second reset time period, the third stop light emission stage includes a third reset time period, and the fourth stop light emission stage includes a fourth reset time period. In the first reset time period, the first reset voltage signal is written to the first pole of the light emitting element 10, in the second reset time period, the first reset voltage signal is written to the first pole of the light emitting element 10, in the third reset time period, the first reset voltage signal is written to the first pole of the light emitting element 10, in the third reset time period, the first reset voltage signal is written to the first pole of the light emitting element 10, and in four reset time periods, the first reset voltage signal is written to the first pole of the light emitting element 10 four times. When the pixel circuit described in the embodiment of the present invention is working, when the light emitting control circuit 21 controls the second voltage line V2 to be disconnected from the first end of the driving circuit 21, and controls the second end of the driving circuit 21 to be disconnected from the first pole of the light emitting element 10, the light emitting element 10 can be controlled not to emit light through the first reset circuit 11, so as to avoid the phenomenon of light leakage from the back of the display panel, and will not affect the operation of the ambient light sensor arranged on the back of the display panel.

[0102] In the embodiment of the present invention, the light-stopping stage including the reset time period may mean that: the reset time period is a part of the light-stopping stage, or the reset time period and the light-stopping stage are the same time period.

[0103] In a preferred case, the reset time period may include the start time of the stop light-emitting stage, so that when the light-emitting control circuit 21 starts to control the disconnection between the second voltage line V2 and the first end of the driving circuit 21, and controls the disconnection between the second end of the driving circuit 21 and the first pole of the light-emitting element 10, the light-emitting element 10 can be controlled not to emit light through the first reset circuit 11.

[0104] In at least one embodiment of the present invention, Figure 2 As shown, in Figure 1 Based on the embodiment of the pixel circuit shown, the pixel circuit may further include a data writing circuit 31, a compensation control circuit 32, a second reset circuit 33 and an energy storage circuit 34;

[0105] The data writing circuit 31 is electrically connected to the gate line Gate, the data line Data and the first end of the driving circuit 21 respectively, and is used to write the data voltage on the data line Data into the first end of the driving circuit 21 under the control of the gate driving signal provided by the gate line Gate;

[0106] The compensation control circuit 32 is electrically connected to the gate line Gate, the control end of the drive circuit 21 and the second end of the drive circuit 21 respectively, and is used to control the connection or disconnection between the control end of the drive circuit 21 and the second end of the drive circuit 21 under the control of the gate drive signal;

[0107] The second reset circuit 33 is electrically connected to the reset control line Reset, the second reset voltage line Vi2 and the control end of the drive circuit 21, and is used to write the second reset voltage provided by the second reset voltage line Vi2 into the control end of the drive circuit 21 under the control of the reset control signal provided by the reset control line Reset;

[0108] The energy storage circuit 34 is electrically connected to the control end of the driving circuit 21 and is used to maintain the potential of the control end of the driving circuit 21 .

[0109] In the present invention, Figure 2 In at least one embodiment of the pixel circuit shown, the data writing circuit 31 controls the writing of the data voltage into the first end of the driving circuit 21, and the compensation control circuit, under the control of the gate driving signal, controls the connection or disconnection between the control end of the driving circuit 21 and the second end of the driving circuit 21, and the second reset circuit 33 controls the resetting of the potential of the control end of the driving circuit 21.

[0110] Optionally, the driving circuit includes a driving transistor; the light emitting control circuit includes a second transistor and a third transistor;

[0111] The gate of the second transistor is electrically connected to the light emitting control line, the first electrode of the second transistor is electrically connected to the second voltage line, and the second electrode of the second transistor is electrically connected to the first electrode of the driving transistor;

[0112] The gate of the third transistor is electrically connected to the light emitting control line, the first electrode of the third transistor is electrically connected to the second electrode of the driving transistor, and the second electrode of the third transistor is electrically connected to the first electrode of the light emitting element;

[0113] The gate of the driving transistor is electrically connected to the control terminal of the driving circuit;

[0114] The data writing circuit includes a fourth transistor, the compensation control circuit includes a fifth transistor, the second reset circuit includes a sixth transistor, and the energy storage circuit includes a storage capacitor;

[0115] The gate of the fourth transistor is electrically connected to the gate line, the first electrode of the fourth transistor is electrically connected to the data line, and the second electrode of the fourth transistor is electrically connected to the first electrode of the driving transistor;

[0116] The gate of the fifth transistor is electrically connected to the gate line, the first electrode of the fifth transistor is electrically connected to the gate of the driving transistor, and the second electrode of the fifth transistor is electrically connected to the second electrode of the driving transistor;

[0117] The gate of the sixth transistor is electrically connected to the reset control line, the first electrode of the sixth transistor is electrically connected to the second reset voltage line, and the second electrode of the sixth transistor is electrically connected to the gate of the driving transistor;

[0118] The first plate of the storage capacitor is electrically connected to the gate of the driving transistor, and the second plate of the storage capacitor is electrically connected to the second voltage line.

[0119] In a specific implementation, the first reset voltage line and the second reset voltage line may be the same reset voltage line, but the present invention is not limited thereto. In actual operation, the first reset voltage line and the second reset voltage line may also be different.

[0120] like Figure 3 As shown, in Figure 2 Based on the embodiment of the pixel circuit shown, the light emitting element is an organic light emitting diode O1;

[0121] The first reset circuit 11 includes a first transistor T1;

[0122] The gate of the first transistor T1 is electrically connected to the reset control line AR, the first electrode of the first transistor T1 is electrically connected to the reset voltage line Vi, and the second electrode of the first transistor T1 is electrically connected to the anode of O1;

[0123] The driving circuit 21 includes a driving transistor T0; the light emitting control circuit includes a second transistor T2 and a third transistor T3;

[0124] The gate of the second transistor T2 is electrically connected to the light emitting control line EM, the first electrode of the second transistor T2 is electrically connected to the first high voltage line VDD, and the second electrode of the second transistor T2 is electrically connected to the first electrode of the driving transistor T0;

[0125] The gate of the third transistor T3 is electrically connected to the light emitting control line EM, the first electrode of the third transistor T3 is electrically connected to the second electrode of the driving transistor T0, and the second electrode of the third transistor T3 is electrically connected to the anode of O1;

[0126] The data writing circuit 31 includes a fourth transistor T4, the compensation control circuit 32 includes a fifth transistor T5, the second reset circuit 33 includes a sixth transistor T6, and the energy storage circuit 34 includes a storage capacitor C0;

[0127] A gate of the fourth transistor T4 is electrically connected to the gate line Gate, a first electrode of the fourth transistor T4 is electrically connected to the data line Data, and a second electrode of the fourth transistor T4 is electrically connected to the first electrode of the driving transistor T0;

[0128] The gate of the fifth transistor T5 is electrically connected to the gate line Gate, the first electrode of the fifth transistor T5 is electrically connected to the gate of the driving transistor T0, and the second electrode of the fifth transistor T5 is electrically connected to the second electrode of the driving transistor T0;

[0129] The gate of the sixth transistor T6 is electrically connected to the reset control line Reset, the first electrode of the sixth transistor T6 is electrically connected to the reset voltage line Vi, and the second electrode of the sixth transistor T6 is electrically connected to the gate of the driving transistor T0;

[0130] The first plate of the storage capacitor C0 is electrically connected to the gate of the driving transistor T0, and the second plate of the storage capacitor C0 is electrically connected to the first high voltage line VDD;

[0131] The cathode of O1 is electrically connected to the first low voltage line VSS.

[0132] In the embodiment of the present invention, the first voltage line may be a first low voltage line, and the second voltage line may be a first high voltage line.

[0133] exist Figure 3 In the illustrated embodiment, all transistors are p-type thin film transistors, but the present invention is not limited thereto.

[0134] exist Figure 3 In the illustrated embodiment, both the first reset voltage line and the second reset voltage line are the reset voltage line Vi, but the present invention is not limited thereto.

[0135] like Figure 4A As shown, the present invention is Figure 3 When the embodiment of the pixel circuit shown is in operation, a display cycle may include a first stop light emission stage t11, a first light emission stage t01, a second stop light emission stage t12, a second light emission stage t02, a third stop light emission stage t13 and a third light emission stage t03;

[0136] The first stop light emission phase t11 includes a first reset time period t21 and a data writing time period t3;

[0137] The second stop light emission stage t12 includes a second reset time period t22, and the third stop light emission stage t13 includes a third reset time period t23;

[0138] In the first stop light emission stage t11, the second stop light emission stage t12 and the third stop light emission stage t13, EM provides a high voltage signal to turn off T2 and T3;

[0139] In the first reset time period t21, the second reset time period t22 and the third reset time period t23, AR provides a low voltage signal to turn on T1, write the reset voltage on Vi to the anode of O1, so that O1 does not emit light;

[0140] In the first reset time period t21, Reset provides a low voltage signal, T6 is turned on to write the reset voltage on Vi to the gate of T0, so that T0 can be turned on when the data writing time period t3 starts;

[0141] In the data writing time period t3, Gate provides a low voltage signal, T4 and T5 are turned on, so as to write the data voltage Vdata on Data into the first electrode of T0, and control the connection between the gate of T0 and the second electrode of T0; at the beginning of the data writing time period t3, T0 is turned on, and Vdata charges C0 through T4, T0 and T5 to increase the potential of the gate of T0 until T0 is turned off, at which time the potential of the gate of T0 becomes Vdata+Vth, where Vth is the threshold voltage of T0;

[0142] In the first light-emitting stage t01, the second light-emitting stage t02 and the third light-emitting stage t03, EM provides a low voltage signal, T2 and T3 are both turned on, T0 drives O1 to emit light, and AR provides a high voltage signal to turn off T1.

[0143] like Figure 4B As shown, the present invention is Figure 3 When the embodiment of the pixel circuit shown is in operation, the display cycle may include a first stop light emission stage t11, a first light emission stage t01, a second stop light emission stage t12, a second light emission stage t02, a third stop light emission stage t13 and a third light emission stage t03; the first stop light emission stage t11 includes a reset time period t6 and a data writing time period t3;

[0144] In the first stop light emission stage t11, the second stop light emission stage t12 and the third stop light emission stage t13, EM provides a high voltage signal to turn off T2 and T3, AR provides a low voltage signal to turn on T1, and writes the reset voltage on Vi to the anode of O1, so that O1 does not emit light;

[0145] In the reset time period t6, Reset provides a low voltage signal, T6 is turned on to write the reset voltage on Vi to the gate of T0, so that T0 can be turned on when the data writing time period t3 starts;

[0146] In the data writing time period t3, Gate provides a low voltage signal, T4 and T5 are turned on, so as to write the data voltage Vdata on Data into the first electrode of T0, and control the connection between the gate of T0 and the second electrode of T0; at the beginning of the data writing time period t3, T0 is turned on, and Vdata charges C0 through T4, T0 and T5 to increase the potential of the gate of T0 until T0 is turned off, at which time the potential of the gate of T0 becomes Vdata+Vth, where Vth is the threshold voltage of T0;

[0147] In the first light-emitting stage t01, the second light-emitting stage t02 and the third light-emitting stage t03, EM provides a low voltage signal, T2 and T3 are both turned on, T0 drives O1 to emit light, AR provides a high voltage signal, and T1 is turned off.

[0148] The driving method described in the embodiment of the present invention is applied to the above-mentioned pixel circuit, and the driving method may include:

[0149] In the stop light emission stage, the light emission control circuit controls the second voltage line to be disconnected from the first end of the driving circuit and controls the second end of the driving circuit to be disconnected from the first electrode of the light emitting element under the control of the light emission control signal;

[0150] In the start time period, the first reset circuit writes a first reset voltage signal into the first electrode of the light emitting element under the control of the reset control signal, so that the light emitting element does not emit light.

[0151] In the driving method described in the embodiment of the present invention, when the light-emitting element needs to stop emitting light, the first reset voltage signal can be written to the first electrode of the light-emitting element through the first reset circuit, so that the light-emitting element does not emit light. In this way, the light-emitting element can be controlled not to emit light in time during the stop-emitting stage, thereby avoiding light leakage from the back of the display panel (the display panel includes the pixel circuit).

[0152] When the light-emitting control circuit controls the second voltage line to be disconnected from the first end of the driving circuit, and controls the second end of the driving circuit to be disconnected from the first pole of the light-emitting element, the light-emitting element can be controlled not to emit light through the first reset circuit, thereby avoiding light leakage from the back of the display panel and not affecting the operation of the ambient light sensor arranged on the back of the display panel.

[0153] In a specific implementation, the start time period preferably includes the start time of the stop light-emitting stage, so that when the light-emitting control circuit starts to control the disconnection between the second voltage line and the first end of the driving circuit, and controls the disconnection between the second end of the driving circuit and the first pole of the light-emitting element, the light-emitting element can be controlled not to emit light through the first reset circuit.

[0154] The display device described in the embodiment of the present invention includes a display substrate, wherein the display substrate includes a base, and a plurality of rows and columns of the above-mentioned pixel circuits arranged in a display area of ​​the base, and a reset control signal generating module arranged in a peripheral area of ​​the base;

[0155] The reset control signal generating module includes a multi-stage reset control signal generating circuit, and the reset control signal generating circuit is used to generate a reset control signal.

[0156] In a specific implementation, the reset control signal generating circuit may be electrically connected to the pixel circuits in two adjacent rows, so as to provide corresponding reset control signals for the pixel circuits in the two adjacent rows.

[0157] In an embodiment of the present invention, a plurality of rows and columns of pixel circuits are arranged in a display area of ​​a substrate, and a gate driving module and a reset control signal generating module are arranged in a peripheral area of ​​the substrate. The reset control signal generating module includes a reset control signal generating circuit which can be used to provide a reset control signal for two adjacent rows of pixel circuits, and the gate driving module includes a gate driving circuit which can provide a gate driving signal for a corresponding row of pixel circuits.

[0158] Figure 5 yes Figure 3 A layout diagram of an embodiment of a pixel circuit is shown.

[0159] exist Figure 5 In the figure, the black rectangles indicate vias.

[0160] Fig. 6A yes Figure 5 Schematic diagram of the active layer in Figure 6B yes Figure 5 Schematic diagram of the first gate metal layer in FIG. Figure 6C for Figure 5 Schematic diagram of the second gate metal layer in FIG. Fig.6D yes Figure 5 Schematic diagram of the source and drain metal layers in .

[0161] exist Figure 6BIn the figure, G0 is the gate of T0, and G0 is reused as the first plate of C0; G1 is the gate of T1, G2 is the gate of T2, G3 is the gate of T3, G4 is the gate of T4, G5 is the gate of T5, T6 is the gate of G6, Reset is the reset control line, Gate is the gate line, EM is the light-emitting control line, and AR is the reset control line.

[0162] exist Figure 6C Among them, the one labeled Vi is the reset voltage line, and the one labeled C0b is the second electrode plate of C0.

[0163] exist Fig.6D In the figure, the line labeled Data is the data line.

[0164] Optionally, the reset control signal generating circuit may include a first node control circuit, a second node control circuit and an output circuit;

[0165] The first node control circuit is electrically connected to the first clock signal line, the third voltage line, the first node and the second node respectively, and is used to control the connection or disconnection between the first node and the third voltage line under the control of the first clock signal provided by the first clock signal line, and to control the connection or disconnection between the first node and the first clock signal line under the control of the potential of the second node;

[0166] The second node control circuit is electrically connected to the first clock signal line, the input terminal, the second node, the first node, the fourth voltage line and the second clock signal line respectively, and is used to control the connection or disconnection between the second node and the input terminal under the control of the first clock signal, and control the connection or disconnection between the second node and the fourth voltage line under the control of the potential of the first node and the second clock signal provided by the second clock signal line;

[0167] The output circuit is electrically connected to the first node, the third node, the fourth voltage line, the second clock signal line and the reset control signal output terminal, respectively, and is used to maintain the potential of the first node, control the potential of the second node according to the potential of the reset control signal output terminal, and control the connection or disconnection between the reset control signal output terminal and the fourth voltage line under the control of the potential of the first node, and control the connection or disconnection between the reset control signal output terminal and the second clock signal line under the control of the potential of the third node.

[0168] In a specific implementation, when the reset signal generating circuit is working, the first node control circuit controls the potential of the first node, the second node control circuit controls the potential of the second node, and the output circuit controls the reset control signal output terminal to output the reset control signal under the control of the potential of the first node and the potential of the third node.

[0169] In at least one embodiment of the present invention, the second node and the third node are the same node; or,

[0170] The reset control signal generating circuit also includes an on-off control circuit, which is electrically connected to the third voltage line, the second node and the third node, respectively, and is used to control the connection or disconnection between the second node and the third node under the control of a third voltage signal provided by the third voltage line.

[0171] In a specific implementation, the second node and the third node may be the same node, or the second node and the third node may be electrically connected via an on-off control circuit. The purpose of adding the on-off control circuit is to stabilize the potential of the second node.

[0172] like Figure 7 As shown, an embodiment of the reset control signal generating circuit may include a first node control circuit 61, a second node control circuit 62, an on-off control circuit 60 and an output circuit 63;

[0173] The first node control circuit 61 is electrically connected to the first clock signal line CK, the third voltage line V3, the first node N1 and the second node N2 respectively, and is used to control the connection or disconnection between the first node N1 and the third voltage line V3 under the control of the first clock signal provided by the first clock signal line CK, and control the connection or disconnection between the first node N1 and the first clock signal line CK under the control of the potential of the second node N2;

[0174] The second node control circuit 62 is electrically connected to the first clock signal line CK, the input terminal STV, the second node N2, the first node N1, the fourth voltage line V4 and the second clock signal line CB, respectively, and is used to control the connection or disconnection between the second node N2 and the input terminal STV under the control of the first clock signal, and control the connection or disconnection between the second node N2 and the fourth voltage line V4 under the control of the potential of the first node N1 and the second clock signal provided by the second clock signal line CB;

[0175] The on-off control circuit 60 is electrically connected to the third voltage line V3, the second node N2 and the third node N3 respectively, and is used to control the connection or disconnection between the second node N2 and the third node N3 under the control of the third voltage signal provided by the third voltage line V3;

[0176] The output circuit 63 is electrically connected to the first node N1, the third node N3, the fourth voltage line V4, the second clock signal line CB and the reset control signal output terminal OUT, respectively, and is used to maintain the potential of the first node N1, control the potential of the second node N2 according to the potential of the reset control signal output terminal OUT, and control the connection or disconnection between the reset control signal output terminal OUT and the fourth voltage line V4 under the control of the potential of the first node N1, and control the connection or disconnection between the reset control signal output terminal OUT and the second clock signal line CB under the control of the potential of the third node N3.

[0177] In at least one embodiment of the present invention, the third voltage line may be a second low voltage line, and the fourth voltage line may be a second high voltage line, but the present invention is not limited thereto.

[0178] Optionally, the first node control circuit includes a first control transistor and a second control transistor;

[0179] The gate of the first control transistor is electrically connected to the first clock signal line, the first electrode of the first control transistor is electrically connected to the third voltage line, and the second electrode of the first control transistor is electrically connected to the first node;

[0180] The gate of the second control transistor is electrically connected to the second node, the first electrode of the second control transistor is electrically connected to the first clock signal line, and the second electrode of the second control transistor is electrically connected to the first node;

[0181] The second node control circuit includes a third control transistor, a fourth control transistor and a fifth control transistor;

[0182] The gate of the third control transistor is electrically connected to the first clock signal line, the first electrode of the third control transistor is electrically connected to the input terminal, and the second electrode of the third control transistor is electrically connected to the second node;

[0183] The gate of the fourth control transistor is electrically connected to the first node, and the first electrode of the fourth control transistor is electrically connected to the fourth voltage line;

[0184] The gate of the fifth control transistor is electrically connected to the second clock signal line, the first electrode of the fifth control transistor is electrically connected to the second electrode of the fourth control transistor, and the second electrode of the fifth control transistor is electrically connected to the second node;

[0185] The output circuit includes a first capacitor, a second capacitor, a first output transistor and a second output transistor;

[0186] The gate of the first output transistor is electrically connected to the first node, the first electrode of the first output transistor is electrically connected to the fourth voltage line, and the second electrode of the first output transistor is electrically connected to the reset control signal output terminal;

[0187] The gate of the second output transistor is electrically connected to the third node, the first electrode of the second output transistor is electrically connected to the reset control signal output terminal, and the second electrode of the second output transistor is electrically connected to the second clock signal line;

[0188] The first plate of the second capacitor is electrically connected to the reset control signal output terminal, and the second plate of the second capacitor is electrically connected to the third node;

[0189] The first plate of the first capacitor is electrically connected to the first node, and the second plate of the first capacitor is electrically connected to the fourth voltage line.

[0190] In a specific implementation, the reset control signal generating circuit may further include an on-off control circuit, and the on-off control circuit may include an on-off control transistor;

[0191] A gate of the on-off control transistor is electrically connected to the third voltage line, a first electrode of the on-off control transistor is electrically connected to the second node, and a second electrode of the on-off control transistor is electrically connected to the third node.

[0192] like Figure 8 As shown, in Figure 7 Based on the embodiment of the reset control signal generating circuit shown,

[0193] The first node control circuit 61 includes a first control transistor M1 and a second control transistor M2;

[0194] The gate of the first control transistor M1 is electrically connected to the first clock signal line CK, the first electrode of the first control transistor M1 is electrically connected to the second low voltage line VGL, and the second electrode of the first control transistor M1 is electrically connected to the first node N1;

[0195] The gate of the second control transistor M2 is electrically connected to the second node N2, the first electrode of the second control transistor M2 is electrically connected to the first clock signal line CK, and the second electrode of the second control transistor M2 is electrically connected to the first node N1;

[0196] The second node control circuit 62 includes a third control transistor M3, a fourth control transistor M4 and a fifth control transistor M5;

[0197] The gate of the third control transistor M3 is electrically connected to the first clock signal line CK, the first electrode of the third control transistor M3 is electrically connected to the input terminal STV, and the second electrode of the third control transistor M3 is electrically connected to the second node N2;

[0198] The gate of the fourth control transistor M4 is electrically connected to the first node N1, and the first electrode of the fourth control transistor M4 is electrically connected to the second high voltage line VGH;

[0199] The gate of the fifth control transistor M5 is electrically connected to the second clock signal line CK, the first electrode of the fifth control transistor M5 is electrically connected to the second electrode of the fourth control transistor M4, and the second electrode of the fifth control transistor M5 is electrically connected to the second node N2;

[0200] The output circuit 63 includes a first capacitor C1, a second capacitor C2, a first output transistor M6 and a second output transistor M7;

[0201] The gate of the first output transistor M6 is electrically connected to the first node N1, the first electrode of the first output transistor M6 is electrically connected to the second high voltage line VGH, and the second electrode of the first output transistor M6 is electrically connected to the reset control signal output terminal OUT;

[0202] The gate of the second output transistor M7 is electrically connected to the third node N3, the first electrode of the second output transistor M7 is electrically connected to the reset control signal output terminal OUT, and the second electrode of the second output transistor M7 is electrically connected to the second clock signal line CB;

[0203] The first plate of the second capacitor C2 is electrically connected to the reset control signal output terminal OUT, and the second plate of the second capacitor C2 is electrically connected to the third node N3;

[0204] The first plate of the first capacitor C1 is electrically connected to the first node N1, and the second plate of the first capacitor C1 is electrically connected to the second high voltage line VGH;

[0205] The on-off control circuit 60 includes an on-off control transistor M8;

[0206] A gate of the on-off control transistor M8 is electrically connected to the second low voltage line VGL, a first electrode of the on-off control transistor M8 is electrically connected to the second node N2, and a second electrode of the on-off control transistor M8 is electrically connected to the third node N3.

[0207] exist Figure 8 In the illustrated embodiment, M3 is a dual-gate transistor, which can reduce leakage.

[0208] exist Figure 8 In the illustrated embodiment, all transistors are p-type thin film transistors, but the present invention is not limited thereto.

[0209] when Figure 8 When the reset control signal generating circuit shown in the embodiment is a first-stage reset control signal generating circuit included in the reset control signal generating module, the input terminal STV is connected to the start signal; Figure 8 When the reset control signal generating circuit shown in the embodiment is not a first-stage reset control signal generating circuit included in the reset control signal generating module, the input terminal STV is electrically connected to the reset control signal output terminal of the reset control signal generating circuit of the adjacent previous stage.

[0210] like Fig. 9 As shown, the present invention is Figure 8 When the reset control signal generating circuit shown in the embodiment is working,

[0211] In the first stage t1, STV provides a low voltage signal, CK provides a low voltage signal, CB provides a high voltage signal, M1 and M3 are both turned on, the potential of N1 and the potential of N2 are both low voltage, M6 and M7 are both turned on, and OUT outputs a high voltage signal;

[0212] In the second stage t2, STV provides a high voltage signal, CK provides a high voltage signal, CB provides a low voltage signal, M1 is turned off, M3 is turned off, and M2 is turned on, so that the potential of N1 is a high voltage, the potential of N2 is a low voltage, M6 is turned off, M7 is turned on, and OUT provides a low voltage signal;

[0213] In the third stage t3, STV provides a high voltage signal, CK provides a low voltage signal, CB provides a high voltage signal, M1 and M3 are both turned on, the potential of N1 and the potential of N2 are both low voltage, M6 and M7 are both turned on, and OUT outputs a high voltage signal;

[0214] In the fourth stage t4, STV provides a high voltage signal, CK provides a high voltage signal, CB provides a low voltage signal, M1 is turned off, M3 is turned off, and M2 is turned on, so that the potential of N1 is a high voltage, the potential of N2 is a low voltage, M6 is turned off, M7 is turned on, and OUT provides a low voltage signal.

[0215] The display device according to the embodiment of the present invention may further include a gate driving module disposed in the peripheral area of ​​the substrate, the gate driving module including a multi-stage gate driving circuit, the gate driving circuit being used to provide corresponding gate driving signals for corresponding row pixel circuits;

[0216] The reset control signal generating circuit is located at a side of the gate driving circuit away from the display area.

[0217] In a specific implementation, a gate driving module and a reset control signal generating circuit may be disposed in the peripheral area of ​​the substrate, and the gate driving circuit and the reset control signal generating circuit may be arranged in a direction away from the display area.

[0218] Optionally, the display substrate may include a first third voltage line, a second third voltage line and a fourth voltage line; the first third voltage line, the second third voltage line and the fourth voltage line all extend along the first direction;

[0219] In the reset control signal generating circuit, the first output transistor, the second output transistor and the on-off control transistor are arranged between the first capacitor and the second capacitor, the first output transistor and the second output transistor are arranged along a first direction, and the second capacitor, the first output transistor, the on-off control transistor and the first capacitor are arranged in sequence along a direction away from the display area;

[0220] The orthographic projection of the first plate of the second capacitor on the substrate and the orthographic projection of the second plate of the second capacitor on the substrate at least partially overlap, and the orthographic projection of the first plate of the first capacitor on the substrate and the orthographic projection of the second plate of the first capacitor on the substrate at least partially overlap; the orthographic projection of the first plate of the second capacitor on the substrate partially overlaps with the orthographic projection of the first third voltage line on the substrate, and the orthographic projection of the first plate of the first capacitor on the substrate partially overlaps with the orthographic projection of the fourth voltage line on the substrate.

[0221] In at least one embodiment of the present invention, the on-off control transistor is arranged by utilizing the space between the first capacitor and the second output transistor, and the layout can be reasonably optimized by adjusting the position of the on-off control transistor.

[0222] In at least one embodiment of the present invention, the first output transistor and the second output transistor are arranged along the first direction to shorten the length of the reset control signal generating circuit in the second direction (the first direction and the second direction intersect each other), which is conducive to achieving a narrow frame. In addition, the orthographic projection of the electrode plate of the second capacitor on the substrate partially overlaps with the orthographic projection of the first third voltage line on the substrate, and the orthographic projection of the first electrode plate of the first capacitor on the substrate partially overlaps with the orthographic projection of the fourth voltage line on the substrate, so as to save space.

[0223] In a specific implementation, multiple rows of gate lines and multiple columns of data lines may be arranged in the display area, the first direction may be substantially the same as the extension direction of the data lines, and the second direction may be substantially the same as the extension direction of the gate lines, but not limited thereto.

[0224] Optionally, the active layer of the first output transistor may include at least one first output channel portion extending along the second direction, and the active layer of the second output transistor may include at least one second output channel portion extending along the second direction;

[0225] The at least one first output channel portion and the at least one second output channel portion are arranged along a first direction;

[0226] The length of the first output channel portion along the second direction and the length of the second output channel portion along the second direction are both less than the first predetermined length, so as to narrow the length occupied by the reset control signal generating circuit in the second direction (the intersection of the first direction and the second direction), thereby facilitating the realization of a narrow frame.

[0227] In a specific implementation, the length of the first output channel portion along the second direction and the length of the second output channel portion along the second direction are set to be relatively small. In order to make the width-to-length ratio of the first output transistor and the width-to-length ratio of the second output transistor be a preset width-to-length ratio, it is necessary to set the length of the first output channel portion along the first direction and the length of the second output channel portion along the first direction to be correspondingly smaller. Such a setting can also reduce the length of the reset control signal generating circuit in the first direction, and set the area occupied by the reset control signal generating circuit to be relatively small.

[0228] In at least one embodiment of the present invention, the first predetermined length may be, for example, 24 um, for example, the first predetermined length may be 18 um, but is not limited thereto.

[0229] Optionally, the area of ​​the first plate of the first capacitor and the area of ​​the second plate of the first capacitor are both less than or equal to a first predetermined area, and the area of ​​the first plate of the second capacitor and the area of ​​the second plate of the second capacitor are both less than or equal to a second predetermined area, so as to compress the area occupied by the reset control signal generating circuit.

[0230] For example, the first predetermined area may be 150 um2, and the second predetermined area may be 200 um2, but the present invention is not limited thereto.

[0231] In at least one embodiment of the present invention, in the reset control signal generating circuit, the first control transistor, the second control transistor, the third control transistor, the fourth control transistor and the fifth control transistor are arranged on a side of the first capacitor away from the display area;

[0232] The fourth control transistor and the fifth control transistor are arranged along a first direction to shorten the length of the reset control signal generating circuit in a second direction (where the first direction and the second direction intersect), thereby facilitating the realization of a narrow frame.

[0233] In a specific implementation, the display substrate may include a first clock signal line and a second clock signal line, both of which extend along a first direction, and the first clock signal line, the second clock signal line and the second third voltage line are arranged on a side of the first control transistor away from the display area.

[0234] In at least one embodiment of the present invention, the length of the channel of the transistor in the reset control signal generating circuit and the width of the channel of the transistor can be set to be relatively small to reduce the space occupied by the reset control signal generating circuit without changing the width-to-length ratio of the transistor.

[0235] Fig.10 yes Figure 8 The layout diagram of the embodiment of the reset control signal generating circuit shown in FIG.

[0236] Fig.11 yes Fig.10 The structure diagram of the active layer in Fig.12 yes Fig.10 The structure diagram of the first gate metal layer in Fig.13 yes Fig.10 The structure diagram of the second gate metal layer in Fig.14 yes Fig.10 Structural diagram of the source and drain metal layers.

[0237] exist Figure 10-Figure 14In the illustrated embodiment, the first direction may be a vertical direction, and the second direction may be a horizontal direction.

[0238] like Figure 10-Figure 14 As shown, the display substrate includes a first second low voltage line VGL-1, a second second low voltage line VGL-2 and a second high voltage line VGH; VGL-1, VGL-2 and VGH all extend vertically;

[0239] In the reset control signal generating circuit, M6, M7 and M8 may all be arranged between C1 and C2, M6 and M7 are arranged vertically, and C2, M6, M8 and C1 are arranged in sequence in a direction away from the display area;

[0240] The orthographic projection of the first electrode plate C2a of C2 on the substrate and the orthographic projection of the second electrode plate C2b of C2 on the substrate at least partially overlap, the orthographic projection of the first electrode plate C1a of C1 on the substrate and the orthographic projection of the second electrode plate C1b of the first capacitor C1 on the substrate at least partially overlap; the orthographic projection of the first electrode plate C2a of the second capacitor C2 on the substrate partially overlaps with the orthographic projection of the first second low voltage line VGL-1 on the substrate, and the orthographic projection of the first electrode plate C1a of the first capacitor C1 on the substrate partially overlaps with the orthographic projection of the second high voltage line VGH on the substrate.

[0241] like Fig.11 As shown, the active layer of M6 and the active layer of M7 are formed by a continuous semiconductor layer 120;

[0242] The active layer of M6 includes a first output channel portion 126 extending in the horizontal direction, and the active layer of M7 includes a second output channel portion 127 extending in the horizontal direction; the first output channel portion 126 and the second output channel portion 127 are arranged in the vertical direction;

[0243] The horizontal length of the first output channel portion 126 and the horizontal length of the second output channel portion 127 may both be 18 um, and the vertical length of the first output channel portion 126 and the vertical length of the second output channel portion may both be 3.3 um.

[0244] like Fig.10 , Fig.12 and Fig.13 As shown, the overlapping area between the orthographic projection of C1a on the substrate and the orthographic projection of C1b on the substrate can be, for example, 117 μm. 2 The overlapping area between the orthographic projection of C2a on the substrate and the orthographic projection of C2b on the substrate can be, for example, 162 μm. 2 .

[0245] like Figure 10-Figure 14 As shown, the second second low voltage line VGL-2, the first clock signal line CK and the second clock signal line CB may extend vertically, and VGL-2, CK and CB may be arranged on a side of VGH away from the display area;

[0246] M4 and M5 may be arranged in a vertical direction; M4, M3, M2, and M5 may be disposed between VGL-2 and VGH.

[0247] exist Fig.10 and Fig.14 , the line labeled VGL-1 is the first second low voltage line, the line labeled VGL-2 is the second second low voltage line, the line labeled VGH is the second high voltage line, the line labeled CK is the first clock signal line, and the line labeled CB is the second clock signal line.

[0248] exist Fig.12 , G1 is the gate of M1, G2 is the gate of M2, G3 is the gate of M3, G4 is the gate of M4, G5 is the gate of M5, G6 is the gate of M6, G7 is the gate of M7, G8 is the gate of M8, C1a is the first electrode plate of C1, and C2a is the first electrode plate of C2.

[0249] exist Fig.13 , the one labeled C1b is the second electrode plate of C1, and the one labeled C2b is the second electrode plate of C2.

[0250] exist Fig.14 In the figure, the one labeled 61 is the first electrode of M6, the one labeled 62 is the second electrode of M6, the one labeled 72 is the second electrode of M7, and the second electrode 62 of M6 is reused as the first electrode of M7.

[0251] exist Fig.11 In the figure, numeral 120 is the first semiconductor layer, numeral 121 is the channel of M1, numeral 122 is the channel of M2, numeral 123 is the channel of M3, numeral 124 is the channel of M4, numeral 125 is the channel of M5, and numeral 128 is the channel of M8.

[0252] like Fig.11 As shown, the channel of M2 may include two channel portions, and the channel of M3 may include two channel portions.

[0253] In at least one embodiment of the present invention, the area occupied by the reset control signal generating circuit can be reduced by reducing the length and width of the channels of M1-M8, and reducing the area of ​​the plate of C1 and the area of ​​the plate of C2.

[0254] exist Figure 10-Figure 14 In at least one embodiment of the display substrate shown, the width of the channel of M1 may be 3um, the length of the channel of M1 may be 5um, the width of the channel of M2 may be 3um, the length of the channel of M2 may be 8um, the width of the channel of M3 may be 4.5um, the length of the channel of M3 may be 8um, the width of the channel of M4 may be 4um, the length of the channel of M4 may be 4um, the width of the channel of M5 may be 4um, the length of the channel of M5 may be 4um, the width of the channel of M8 may be 5um, the length of the channel of M8 may be 4um, but not limited thereto.

[0255] exist Fig.10 In the figure, the black rectangle indicates the via.

[0256] When manufacturing the display substrate in the display device described in at least one embodiment of the present invention, firstly, a semiconductor material layer is arranged on the substrate, and the semiconductor material layer is patterned to form the active layer of each transistor; a first gate insulating layer is made on the side of the active layer facing away from the substrate; a first gate metal layer is made on the side of the first gate insulating layer facing away from the active layer, and the first gate metal layer is patterned to form the gate of each transistor in the driving circuit and the first electrode of each capacitor. Using the gate of each transistor as a mask, the portion of the active layer not covered by the gate is doped, so that the portion of the active layer not covered by the gate is formed into a conductive portion, and the portion of the active layer covered by the gate is formed into a channel; the conductive portion is used as a source or a drain; or the conductive portion is coupled to the source or the drain. A second gate insulating layer is formed on the side of the first gate metal layer facing away from the active layer, and a second gate metal layer is arranged on the side of the second gate insulating layer facing away from the first gate metal layer; the second gate metal layer is patterned to form the second electrode plate of each capacitor in the driving circuit; an interlayer dielectric layer is arranged on the side of the second gate metal layer facing away from the second gate insulating layer. A plurality of vias are arranged on the substrate on which the active layer, the first gate insulating layer, the first gate metal layer, the second gate insulating layer, the second gate metal layer and the interlayer dielectric layer are arranged. A source-drain metal layer is arranged on the side of the interlayer dielectric layer facing away from the second gate metal layer. The source-drain metal layer is patterned to form each clock signal line, each voltage line, the first electrode of M6, the second electrode of M6 and the second electrode of M7.

[0257] In the display device described in the embodiment of the present invention, the display substrate may further include a light emitting control signal generating module and a reset control signal generating module disposed in the peripheral area of ​​the substrate; the light emitting control signal generating module includes a multi-stage light emitting control signal generating circuit, and the light emitting control signal generating circuit is used to generate a light emitting control signal; the reset control signal generating module includes a multi-stage reset control signal generating circuit, and the reset control signal generating circuit is used to generate a reset control signal;

[0258] The light emission control signal generating circuit is located at a side of the gate driving circuit away from the display area, and the reset control signal generating circuit is located at a side of the gate driving circuit away from the display area.

[0259] In a specific implementation, the first-level reset control signal generating circuit can provide a reset control signal for two adjacent rows of pixel circuits arranged in the display area, and the first-level light emitting control signal generating circuit can provide a reset control signal for two adjacent rows of pixel circuits arranged in the display area, but is not limited to this.

[0260] Optionally, the light emitting control signal generating circuit, the reset control signal generating circuit and the reset control signal generating circuit may be arranged in sequence along the first direction, but is not limited thereto.

[0261] like Fig.15 As shown, En is the n-th level light emitting control signal generating circuit, An is the n-th level reset control signal generating circuit, Rn is the n-th level reset control signal generating circuit, G2n-1 is the 2n-1-th level gate driving circuit, G2n is the 2n-th level gate driving circuit, G2n+1 is the 2n+1-th level gate driving circuit, G2n+2 is the 2n+2-th level gate driving circuit, and n is a positive integer;

[0262] The area labeled B1 is the peripheral area, and the area labeled A0 is the display area;

[0263] In the display area A0, a pixel circuit P2n-1 in the 2n-1th row, a pixel circuit P2n in the 2nth row, a pixel circuit P2n in the 2n+1th row, and a pixel circuit P2n+2 in the 2n+2th row are provided;

[0264] G2n-1 provides a corresponding gate drive signal for P2n-1, G2n provides a corresponding gate drive signal for P2n, G2n+1 provides a corresponding gate drive signal for P2n+1, and G2n+2 provides a corresponding gate drive signal for P2n+2;

[0265] En provides corresponding light-emitting control signals for P2n-1 and P2n, An provides corresponding reset control signals for P2n-1 and P2n, and Rn provides corresponding reset control signals for P2n-1 and P2n;

[0266] En+1 provides a corresponding light-emitting control signal for P2n+1 and P2n+2, An+1 provides a corresponding reset control signal for P2n+1 and P2n+2, and Rn+1 provides a corresponding reset control signal for P2n+1 and P2n+2;

[0267] En, An, Rn, En+1, An+1 and Rn+1 are arranged along the vertical direction;

[0268] En, An, Rn, En+1, An+1 and Rn+1 are arranged on a side of each level of the gate driving circuit away from the display area A0.

[0269] The display device provided in the embodiment of the present invention can be any product or component with a display function, such as a mobile phone, a tablet computer, a television, a monitor, a notebook computer, a digital photo frame, a navigator, etc.

[0270] The above is a preferred embodiment of the present invention. It should be pointed out that for ordinary technicians in this technical field, several improvements and modifications can be made without departing from the principles of the present invention. These improvements and modifications should also be regarded as the scope of protection of the present invention.

Claims

1. A pixel circuit, characterized in that: It includes a light-emitting element, a first reset circuit, a driving circuit and a light-emitting control circuit; The first reset circuit is electrically connected to the reset control line, the first reset voltage line and the first electrode of the light emitting element respectively, and is used to write the first reset voltage signal provided by the first reset voltage line into the first electrode of the light emitting element multiple times under the control of the reset control signal provided by the reset control line during the reset time period included in the multiple light stopping stages in one frame time, so as to control the light emitting element not to emit light; The second electrode of the light emitting element is electrically connected to the first voltage line; The driving circuit is used to generate a driving current under the control of the potential of its control terminal; The light-emitting control circuit is electrically connected to the light-emitting control line, the second voltage line, the first end of the drive circuit, the second end of the drive circuit and the first pole of the light-emitting element respectively, and is used to control the second voltage line to be disconnected from the first end of the drive circuit and the second end of the drive circuit to be disconnected from the first pole of the light-emitting element under the control of the light-emitting control signal provided by the light-emitting control line in the light-emitting stop stage; The reset time period includes the start time of the light-emitting stop phase.

2. The pixel circuit according to claim 1, wherein: The first reset circuit includes a first transistor; A gate of the first transistor is electrically connected to the reset control line, a first electrode of the first transistor is electrically connected to the first reset voltage line, and a second electrode of the first transistor is electrically connected to a first electrode of the light emitting element.

3. The pixel circuit according to claim 1, wherein: It also includes a data writing circuit, a compensation control circuit, a second reset circuit and an energy storage circuit; The data writing circuit is electrically connected to the gate line, the data line and the first end of the driving circuit respectively, and is used to write the data voltage on the data line into the first end of the driving circuit under the control of the gate driving signal provided by the gate line; The compensation control circuit is electrically connected to the gate line, the control end of the drive circuit and the second end of the drive circuit respectively, and is used to control the connection or disconnection between the control end of the drive circuit and the second end of the drive circuit under the control of the gate drive signal; The second reset circuit is electrically connected to the reset control line, the second reset voltage line and the control end of the drive circuit, and is used to write the second reset voltage provided by the second reset voltage line into the control end of the drive circuit under the control of the reset control signal provided by the reset control line; The energy storage circuit is electrically connected to the control end of the drive circuit and is used to maintain the potential of the control end of the drive circuit.

4. The pixel circuit according to claim 3, characterized in that: The driving circuit includes a driving transistor; the light emitting control circuit includes a second transistor and a third transistor; The gate of the second transistor is electrically connected to the light emitting control line, the first electrode of the second transistor is electrically connected to the second voltage line, and the second electrode of the second transistor is electrically connected to the first electrode of the driving transistor; The gate of the third transistor is electrically connected to the light emitting control line, the first electrode of the third transistor is electrically connected to the second electrode of the driving transistor, and the second electrode of the third transistor is electrically connected to the first electrode of the light emitting element; The gate of the driving transistor is electrically connected to the control terminal of the driving circuit; The data writing circuit includes a fourth transistor, the compensation control circuit includes a fifth transistor, the second reset circuit includes a sixth transistor, and the energy storage circuit includes a storage capacitor; The gate of the fourth transistor is electrically connected to the gate line, the first electrode of the fourth transistor is electrically connected to the data line, and the second electrode of the fourth transistor is electrically connected to the first electrode of the driving transistor; The gate of the fifth transistor is electrically connected to the gate line, the first electrode of the fifth transistor is electrically connected to the gate of the driving transistor, and the second electrode of the fifth transistor is electrically connected to the second electrode of the driving transistor; The gate of the sixth transistor is electrically connected to the reset control line, the first electrode of the sixth transistor is electrically connected to the second reset voltage line, and the second electrode of the sixth transistor is electrically connected to the gate of the driving transistor; The first plate of the storage capacitor is electrically connected to the gate of the driving transistor, and the second plate of the storage capacitor is electrically connected to the second voltage line.

5. A driving method, applied to the pixel circuit according to any one of claims 1 to 4, characterized in that: One frame time includes a plurality of stop-lighting stages, and the plurality of stop-lighting stages respectively include a reset time period; the driving method includes: In the stop light emission stage, the light emission control circuit controls the second voltage line to be disconnected from the first end of the driving circuit and controls the second end of the driving circuit to be disconnected from the first electrode of the light emitting element under the control of the light emission control signal; In the reset time period, the first reset circuit writes a first reset voltage signal into the first electrode of the light-emitting element under the control of the reset control signal, so that the light-emitting element does not emit light; The reset time period includes the start time of the light-emitting stop phase.

6. A display device, characterized in that: A display substrate comprising a base, and a plurality of rows and columns of pixel circuits according to any one of claims 1 to 4 arranged in a display area of ​​the base, and a reset control signal generating module arranged in a peripheral area of ​​the base; The reset control signal generating module includes a multi-stage reset control signal generating circuit, and the reset control signal generating circuit is used to generate a reset control signal.

7. The display device according to claim 6, characterized in that The reset control signal generating circuit is electrically connected to the pixel circuits in two adjacent rows, and is used to provide corresponding reset control signals for the pixel circuits in two adjacent rows.

8. The display device according to claim 6, wherein: The reset control signal generating circuit includes a first node control circuit, a second node control circuit and an output circuit; The first node control circuit is electrically connected to the first clock signal line, the third voltage line, the first node and the second node respectively, and is used to control the connection or disconnection between the first node and the third voltage line under the control of the first clock signal provided by the first clock signal line, and to control the connection or disconnection between the first node and the first clock signal line under the control of the potential of the second node; The second node control circuit is electrically connected to the first clock signal line, the input terminal, the second node, the first node, the fourth voltage line and the second clock signal line respectively, and is used to control the connection or disconnection between the second node and the input terminal under the control of the first clock signal, and control the connection or disconnection between the second node and the fourth voltage line under the control of the potential of the first node and the second clock signal provided by the second clock signal line; The output circuit is electrically connected to the first node, the third node, the fourth voltage line, the second clock signal line and the reset control signal output terminal respectively, and is used to maintain the potential of the first node, control the potential of the second node according to the potential of the reset control signal output terminal, and control the connection or disconnection between the reset control signal output terminal and the fourth voltage line under the control of the potential of the first node, and control the connection or disconnection between the reset control signal output terminal and the second clock signal line under the control of the potential of the third node; The second node and the third node are the same node; or, the reset control signal generating circuit also includes an on-off control circuit, which is electrically connected to the third voltage line, the second node and the third node, respectively, and is used to control the connection or disconnection between the second node and the third node under the control of a third voltage signal provided by the third voltage line.

9. The display device according to claim 8, wherein: The first node control circuit includes a first control transistor and a second control transistor; The gate of the first control transistor is electrically connected to the first clock signal line, the first electrode of the first control transistor is electrically connected to the third voltage line, and the second electrode of the first control transistor is electrically connected to the first node; The gate of the second control transistor is electrically connected to the second node, the first electrode of the second control transistor is electrically connected to the first clock signal line, and the second electrode of the second control transistor is electrically connected to the first node; The second node control circuit includes a third control transistor, a fourth control transistor and a fifth control transistor; The gate of the third control transistor is electrically connected to the first clock signal line, the first electrode of the third control transistor is electrically connected to the input terminal, and the second electrode of the third control transistor is electrically connected to the second node; The gate of the fourth control transistor is electrically connected to the first node, and the first electrode of the fourth control transistor is electrically connected to the fourth voltage line; The gate of the fifth control transistor is electrically connected to the second clock signal line, the first electrode of the fifth control transistor is electrically connected to the second electrode of the fourth control transistor, and the second electrode of the fifth control transistor is electrically connected to the second node; The output circuit includes a first capacitor, a second capacitor, a first output transistor and a second output transistor; The gate of the first output transistor is electrically connected to the first node, the first electrode of the first output transistor is electrically connected to the fourth voltage line, and the second electrode of the first output transistor is electrically connected to the reset control signal output terminal; The gate of the second output transistor is electrically connected to the third node, the first electrode of the second output transistor is electrically connected to the reset control signal output terminal, and the second electrode of the second output transistor is electrically connected to the second clock signal line; The first plate of the second capacitor is electrically connected to the reset control signal output terminal, and the second plate of the second capacitor is electrically connected to the third node; The first plate of the first capacitor is electrically connected to the first node, and the second plate of the first capacitor is electrically connected to the fourth voltage line; The reset control signal generating circuit further comprises an on-off control circuit, and the on-off control circuit comprises an on-off control transistor; A gate of the on-off control transistor is electrically connected to the third voltage line, a first electrode of the on-off control transistor is electrically connected to the second node, and a second electrode of the on-off control transistor is electrically connected to the third node.

10. The display device according to any one of claims 6 to 9, characterized in that: Also included is a gate driving module disposed in the peripheral area of ​​the substrate, the gate driving module includes a multi-stage gate driving circuit, and the gate driving circuit is used to provide a corresponding gate driving signal for a corresponding row of pixel circuits; The reset control signal generating circuit is located at a side of the gate driving circuit away from the display area.

11. The display device according to claim 9, wherein: The display substrate comprises a first third voltage line, a second third voltage line and a fourth voltage line; the first third voltage line, the second third voltage line and the fourth voltage line all extend along a first direction; In the reset control signal generating circuit, the first output transistor, the second output transistor and the on-off control transistor are arranged between the first capacitor and the second capacitor, the first output transistor and the second output transistor are arranged along a first direction, and the second capacitor, the first output transistor, the on-off control transistor and the first capacitor are arranged in sequence along a direction away from the display area; The orthographic projection of the first electrode plate of the second capacitor on the substrate at least partially overlaps with the orthographic projection of the second electrode plate of the second capacitor on the substrate, and the orthographic projection of the first electrode plate of the first capacitor on the substrate at least partially overlaps with the orthographic projection of the second electrode plate of the first capacitor on the substrate; The orthographic projection of the first plate of the second capacitor on the substrate partially overlaps with the orthographic projection of the first third voltage line on the substrate, and the orthographic projection of the first plate of the first capacitor on the substrate partially overlaps with the orthographic projection of the fourth voltage line on the substrate.

12. The display device according to claim 11, wherein: The active layer of the first output transistor includes at least one first output channel portion extending along the second direction, and the active layer of the second output transistor includes at least one second output channel portion extending along the second direction; The at least one first output channel portion and the at least one second output channel portion are arranged along a first direction; A length of the first output channel portion along the second direction and a length of the second output channel portion along the second direction are both less than a first predetermined length.

13. The display device according to claim 11, wherein: The area of ​​the first plate of the first capacitor and the area of ​​the second plate of the first capacitor are both less than or equal to the first predetermined area, and the area of ​​the first plate of the second capacitor and the area of ​​the second plate of the second capacitor are both less than or equal to the second predetermined area.

14. The display device according to claim 11, wherein: In the reset control signal generating circuit, the first control transistor, the second control transistor, the third control transistor, the fourth control transistor and the fifth control transistor are arranged on a side of the first capacitor away from the display area, and the fourth control transistor and the fifth control transistor are arranged along a first direction.

15. The display device according to claim 14, wherein: The display substrate includes a first clock signal line and a second clock signal line, both of which extend along a first direction, and the first clock signal line, the second clock signal line and the second third voltage line are arranged on a side of the first control transistor away from the display area.

16. The display device according to claim 10, wherein: The display substrate further comprises a light emitting control signal generating module and a reset control signal generating module arranged in the peripheral area of ​​the substrate; the light emitting control signal generating module comprises a multi-stage light emitting control signal generating circuit, and the light emitting control signal generating circuit is used to generate a light emitting control signal; the reset control signal generating module comprises a multi-stage reset control signal generating circuit, and the reset control signal generating circuit is used to generate a reset control signal; The light emission control signal generating circuit is located at a side of the gate driving circuit away from the display area, and the reset control signal generating circuit is located at a side of the gate driving circuit away from the display area.

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