Memory device, source line voltage adjuster and source line voltage adjusting method thereof

Abstract

A memory device, a source line voltage regulator and a source line voltage regulating method thereof are disclosed. The source line voltage regulator includes an operational amplifier, a current sink and a current generator. The operational amplifier has a first input coupled to a common source line and a second input to receive a reference voltage. The operational amplifier generates a bias voltage. The current sink sinks a sink current from the common source line in accordance with the bias voltage. The current generator provides an output current to the common source line. The current generator generates a first current in accordance with the bias voltage and a second current in accordance with a reference current. The current generator generates the output current in accordance with a difference between the second current and the first current.

Description

TECHNICAL FIELD

[0001] The present application relates to a memory device, a source line voltage regulator and a source line voltage regulating method thereof, and more particularly to a memory device, a source line voltage regulator and a source line voltage regulating method thereof capable of reducing power consumption. BACKGROUND

[0002] In known NAND flash memory, a plurality of strings of memory cells share a common source line, and thus, when a read operation is performed on the memory cells, the data stored in the selected memory cells in each string of memory cells is transferred to the common source line as different currents.

[0003] In another aspect, the known technique further draws the current of the common source line through a pull-down transistor and provides a current source to provide a current to flow to the common source line. The voltage of the common source line is maintained by the interaction of the pull-down transistor and the current source. In the known technique, the current generated by the current source is fixed and results in a certain degree of power consumption, causing unnecessary power waste. SUMMARY

[0004] The present application provides a memory device, a source line voltage regulator and a source line voltage regulating method thereof capable of effectively saving power consumption.

[0005] The source line voltage regulator of the present application is coupled to a common source line. The source line voltage regulator includes an operational amplifier, a current sink and a current generator. The operational amplifier has a first input coupled to the common source line and a second input to receive a reference voltage, and generates a bias voltage. The current sink is coupled between the common source line and a reference ground, and draws a sink current from the common source line according to the bias voltage. The current generator is coupled to the common source line and the operational amplifier, and provides an output current to the common source line. The current generator generates a first current according to the bias voltage and a second current according to a reference current. The current generator generates the output current according to the difference between the second current and the first current.

[0006] The memory device of the present application includes the source line voltage regulator as described above and a plurality of strings of memory cells. The strings of memory cells are coupled to the common source line.

[0007] The source line voltage adjustment method of the present application is applicable to a memory device. The source line voltage adjustment method comprises: providing an operational amplifier to generate a bias voltage according to a reference voltage and a voltage of a common source line; providing a current sink to sink a sink current from the common source line according to the bias voltage; and providing a current generator to generate a first current according to the bias voltage, to generate a second current according to a reference current, and to generate an output current according to a difference between the second current and the first current, and to provide the output current to the common source line.

[0008] Based on the above, in the source line voltage adjuster of the present application, the output current is provided to the common source line by the current generator. The current generator adjusts the size of the output current according to the bias voltage generated by the operational amplifier to provide a suitable current value of the output current to maintain the voltage of the common source line, thereby effectively reducing unnecessary power consumption.

[0009] In order to make the above features and advantages of the present application more apparent, specific embodiments are described below in detail with reference to the accompanying drawings. BRIEF DESCRIPTION OF DRAWINGS

[0010] Figure 1 A schematic diagram of a source line voltage adjuster according to an embodiment of the present application is shown.

[0011] Figure 2 A schematic diagram of a source line voltage adjuster according to another embodiment of the present application is shown.

[0012] Figure 3 A schematic diagram of an implementation of a current generator of a source line voltage adjuster according to an embodiment of the present application is shown.

[0013] Figure 4 A schematic diagram of a source line voltage adjuster according to another embodiment of the present application is shown.

[0014] Figure 5 A schematic diagram of a memory device according to an embodiment of the present application is shown.

[0015] Figure 6 A flowchart of a source line voltage adjustment method according to an embodiment of the present application is shown.

[0016] LIST OF SYMBOLS

[0017] 100, 200, 400, 510: source line voltage adjuster

[0018] 110, 210, 410, 511: current sink

[0019] 120, 220, 300, 420, 512: current generator

[0020] 310: current source

[0021] 320, 330, 340: current mirror

[0022] 350: reference current source

[0023] 411: comparison and decoder

[0024] 500: memory device

[0025] 520: memory cell array

[0026] CSL: common source line

[0027] OP1: operational amplifier

[0028] CSL: common source line

[0029] CSL_REF: reference voltage

[0030] CSLREG: bias voltage

[0031] GND: reference ground terminal

[0032] IO: output current

[0033] VCC: power supply voltage

[0034] ID: draw current

[0035] MPD, MMIR, M1-M6, MPD0-MPDN, MSW1-MSWN: transistor

[0036] I1-I3: current

[0037] VCC: power supply voltage

[0038] MS0-MSN: memory cell string

[0039] BL0-BL n : bit line

[0040] SSL: source line selection signal

[0041] GSL: ground selection signal

[0042] WL N -WL M : word line signal

[0043] VRD: read voltage

[0044] S610-S630: adjustment steps of source line voltage DETAILED DESCRIPTION

[0045] For the purpose of making the object, technical solutions and advantages of the present application clearer, the present application will be further described in details below with reference to specific embodiments and the accompanying drawings.

[0046] Please refer to Figure 1 , Figure 1 A schematic diagram of a source line voltage regulator according to an embodiment of the present application is shown. The source line voltage regulator 100 is coupled to a common source line CSL. The source line voltage regulator 100 includes an operational amplifier OP1, a current sink 110, and a current generator 120. The operational amplifier OP1 has a first input (e.g., a positive input) coupled to the common source line CSL. The operational amplifier OP1 also has a second input (e.g., a negative input) to receive a reference voltage CSL_REF. The output of the operational amplifier OP1 generates a bias voltage CSLREG.

[0047] In addition, in the present embodiment, the current sink 110 is coupled between the common source line CSL and a reference ground GND. The current sink 110 is also coupled to the output of the operational amplifier OP1 and receives the bias voltage CSLREG generated by the operational amplifier OP1. The current sink 110 is configured to sink a sink current ID from the common source line CSL in response to the bias voltage CSLREG. In the present embodiment, the magnitude of the sink current ID generated by the current sink 110 can be positively related to the bias voltage CSLREG. Specifically, the sink current ID generated by the current sink 110 can be directly proportional to the bias voltage CSLREG when the bias voltage CSLREG is within a certain range. The current generator 120 is coupled between a supply voltage VCC and the common source line CSL. In the present embodiment, the current generator 120 is configured to provide an output current IO to the common source line CSL. When the output current IO is greater than the sink current ID, the voltage on the common source line CSL can be pulled up. When the output current IO is less than the sink current ID, the voltage on the common source line CSL can be pulled down. When the output current IO is equal to the sink current ID, the voltage on the common source line CSL can be maintained.

[0048] It is worth mentioning that, in the present embodiment, the current generator 120 generates the output current IO in response to the magnitude of the bias voltage CSLREG. Specifically, the output current IO generated by the current generator 120 can be negatively related to the bias voltage CSLREG. That is, when the bias voltage CSLREG rises, the output current IO generated by the current generator 120 will be lowered. Conversely, when the bias voltage CSLREG falls, the output current IO generated by the current generator 120 will be increased.

[0049] In terms of overall operation, when the common source line CSL receives a relatively high current (e.g., source current from a plurality of memory strings of the memory device), the voltage on the common source line CSL can be pulled up in a short time. Based on the voltage on the common source line CSL being pulled up, the operational amplifier OP1 can increase the voltage of the generated bias voltage CSLREG, and cause the sink current ID generated by the current sink 110 to increase. Correspondingly, the current generator 120 can decrease the current value of the generated output current IO according to the voltage value of the pulled-up bias voltage CSLREG. In this way, the phenomenon of the voltage on the common source line CSL being pulled up can be suppressed and maintained at a default voltage value.

[0050] On the contrary, when the common source line CSL receives a relatively low current (e.g., source current from a plurality of memory strings of the memory device), the voltage on the common source line CSL can be pulled down in a short time. Based on the voltage on the common source line CSL being pulled down, the operational amplifier OP1 can decrease the voltage of the generated bias voltage CSLREG, and cause the sink current ID generated by the current sink 110 to decrease. Correspondingly, the current generator 120 can increase the current value of the generated output current IO according to the voltage value of the pulled-down bias voltage CSLREG. In this way, the phenomenon of the voltage on the common source line CSL being pulled down can be suppressed and maintained at a default voltage value.

[0051] From the above description, it can be known that the output current IO in the present application is not a fixed current value, but can be dynamically adjusted according to the variation of the voltage bias voltage CSLREG. Therefore, the source line voltage regulator 100 of the embodiment of the present application can save power consumption and reduce unnecessary power waste.

[0052] Please refer to Figure 2 , Figure 2 A schematic diagram of a source line voltage regulator of another embodiment of the present application is shown. The source line voltage regulator 200 includes an operational amplifier OP1, a current sink 210, and a current generator 220. The operational amplifier OP1 has a first input end (e.g., a positive input end) coupled to a common source line CSL. The operational amplifier OP1 also has a second input end (e.g., a negative input end) to receive a reference voltage CSL_REF. The output end of the operational amplifier OP1 generates a bias voltage CSLREG.

[0053] In the present embodiment, the current sink 210 is constructed by a transistor MPD. The first end of the transistor MPD is coupled to the common source line CSL, the second end of the transistor MPD is coupled to a reference ground end GND, and the control end of the transistor MPD is coupled to the output end of the operational amplifier OP1, thereby receiving the bias voltage CSLREG.

[0054] The transistor MPD is a pull-down transistor that generates a draw current ID based on the bias voltage CSLREG. In this embodiment, the transistor MPD is N-type, and the magnitude of the generated draw current ID is positively correlated with the bias voltage CSLREG.

[0055] Please refer to the following: Figure 3 , Figure 3 A schematic diagram illustrating an embodiment of the current generator of the source line voltage regulator according to an embodiment of the present invention is shown. The current generator 300 includes a current source 310, current mirrors 320, 330, and 340, and a reference current source 350. The current source 310 is constructed from a transistor MMIR. The first terminal of the transistor MMIR is coupled to the current mirror 320, and the second terminal of the transistor MMIR is coupled to the reference ground terminal GND. The control terminal of the transistor MMIR receives a bias voltage CSLREG and generates a current I3 according to the bias voltage CSLREG. Figure 1 Current generator 120 and Figure 2 The current generator 220 in the embodiment can be implemented using the current generator 300 of this embodiment.

[0056] Additionally, the current mirror 320 receives current I3 and generates current I1 by mirroring current I3. The current mirror 320 includes transistors M1 and M2, wherein the first terminals of transistors M1 and M2 share a common power supply voltage VCC, and the second terminal of transistor M1 is coupled to its control terminal and also coupled to the control terminal of transistor M2. The second terminal of transistor M1 further receives current I3, while the second terminal of transistor M2 generates current I1.

[0057] On the other hand, a current mirror 330 is coupled to a reference current source 350. The current mirror 330 receives a reference current IR generated by the reference current source 350 and generates a current I2 by mirroring the reference current IR. The current mirror 330 includes transistors M3 and M4. The second terminals of transistors M3 and M4 are commonly coupled to a reference ground terminal GND. The first terminal of transistor M3 receives the reference current IR and is coupled to the control terminals of both transistors M3 and M4. Furthermore, the first terminal of transistor M4 is coupled to the second terminal of transistor M2, and draws current I2 from the first terminal of transistor M4.

[0058] Note that at the coupling point between the second terminal of transistor M2 and the first terminal of transistor M4, a subtraction effect between current I2 and current I1 can occur. In this embodiment, the absolute value of current I2 can be greater than the absolute value of current I1, and the difference between current I2 and current I1 can be provided to current mirror 340.

[0059] Current mirror 340 is coupled to current mirrors 320 and 330. Current mirror 340 mirrors the difference between current I2 and current I1, thereby generating an output current IO. Current mirror 340 includes transistors M5 and M6. The first terminals of transistors M5 and M6 share the power supply voltage VCC. The second terminal of transistor M5 receives the difference between current I2 and current I1 and is coupled to the control terminals of transistors M5 and M6. The second terminal of transistor M6 generates the output current IO.

[0060] It is worth noting that in this embodiment, the transistor MMIR can be with Figure 2 In this embodiment, the transistors MPD used to construct the current extractor 210 have the same polarity (e.g., both are N-type transistors). In other embodiments, the transistor MMIR can have the same electrical characteristics as the transistor MPD, for example, the transistor MMIR and the transistor MPD can have the same channel width-to-length (W / L) ratio. This allows the current generator 300 to have better characteristic matching with the current extractor 210. Furthermore, in this embodiment, transistors M1, M2, M5, and M6 can have the same polarity, transistors M3 and M4 can have the same polarity, while transistors M1 and M3 can have different polarities. To further illustrate, transistors M1, M2, M5, and M6 can be P-type transistors, while transistors M3 and M4 can be N-type transistors.

[0061] Furthermore, the current mirror ratios provided by current mirrors 320, 330, and 340 do not necessarily have to be 1:1. Designers can design different or the same current mirror ratios for current mirrors 320, 330, and 340 according to actual needs, without any certain restrictions.

[0062] Please refer to the following: Figure 4 , Figure 4 A schematic diagram illustrating a source line voltage regulator according to another embodiment of the present invention is shown. The source line voltage regulator 400 includes an operational amplifier OP1, a current extractor 410, and a current generator 420. The operational amplifier OP1 has a first input (e.g., a positive input) coupled to a common source line CSL. The operational amplifier OP1 also has a second input (e.g., a negative input) to receive a reference voltage CSL_REF. The output of the operational amplifier OP1 generates a bias voltage CSLREG.

[0063] In this embodiment, the current sink 410 includes transistors MPD0~MPDN, transistors MSW1~MSWN, and a comparator and decoder 411. The transistors MPD0~MPDN are used as a plurality of current sources to generate sink currents, and the transistors MSW1~MSWN are used as a plurality of switches, respectively. The first terminals of the transistors MPD0~MPDN are commonly coupled to a common source line CSL, and the transistors MSW1~MSWN are connected in series with the transistors MPD0~MPDN between the common source line CSL and a reference ground terminal, respectively. The control terminals of the transistors MPD0~MPDN commonly receive a bias voltage CSLREG generated by an operational amplifier OP1, and the control terminals of the transistors MSW1~MSWN receive a plurality of enable signals EN0~ENN, respectively.

[0064] In another aspect, the comparator and decoder 411 is coupled to the operational amplifier OP1. The comparator and decoder 411 compares a reference voltage CSL_REF with the bias voltage CSLREG to generate a comparison result, and decodes the comparison result to generate the enable signals ENN~EN0.

[0065] In an operation aspect, the comparator and decoder 411 compares the reference voltage CSL_REF with the bias voltage CSLREG, and decodes a magnitude of a difference between the reference voltage CSL_REF and the bias voltage CSLREG to generate the enable signals ENN~EN0. Through the enable signals ENN~EN0, the number of the transistors MSW0~MSWN turned on can be controlled, and the transistors MSW0~MSWN turned on can provide sink currents to the corresponding transistors MPD0~MPDN, respectively, and thereby pull down a voltage level on the common source line CSL.

[0066] In an embodiment of the present application, the comparator and decoder 411 can be provided with a voltage dividing circuit to divide the reference voltage CSL_REF to generate a plurality of sub-reference voltages, and a plurality of comparator circuits to compare the bias voltage CSLREG with the plurality of sub-reference voltages to generate the comparison result. The comparator and decoder 411 can also be provided with a digital circuit to decode the comparison result to generate the enable signals ENN~EN0.

[0067] In another embodiment of the present application, the comparator and decoder 411 can also perform an analog voltage subtraction operation on the bias voltage CSLREG and the reference voltage CSL_REF to generate the comparison result. The comparator and decoder 411 can further perform an analog-to-digital conversion on the comparison result to generate the enable signals ENN~EN0.

[0068] In this embodiment, the current drawn by the current sink 410 is adjusted in multiple stages. Thus, each of the pull-down transistors (each of the transistors MPD ~ MPDN) in the current sink 410 can operate in the saturation region, and the stability of the adjustment of the common source line CSL can be improved.

[0069] Please refer to Figure 5 , Figure 5 A schematic diagram of a memory device according to an embodiment of the present application is shown. The memory device 500 includes a source line voltage adjuster 510 and a memory cell array 520 composed of a plurality of memory cell strings MS0 ~ MSN. The plurality of memory cell strings MS0 ~ MSN are respectively coupled to bit lines BL0 ~ BL n , and are commonly coupled to a common source line CSL, and receive a source line selection signal SSL, a ground selection signal GSL, and a plurality of word line signals WL N ~ WL M The source line voltage adjuster 510 is coupled to the common source line CSL. The source line voltage adjuster 510 includes a current sink 511, a current generator 512, and an operational amplifier OP1. The implementation details of the source line voltage adjuster 510 are described in detail in the foregoing embodiments, and thus will not be described again.

[0070] When the memory cell strings MS0 ~ MSN perform a read operation, the memory cell strings MS0 ~ MSN can provide a plurality of source currents to the common source line CSL according to the data stored in the selected memory cells according to the word line signals WL M set as a read voltage VRD. The source line voltage adjuster 510 can dynamically adjust the current values of the sink current and the output current generated by the current sink 511 and the current generator 512 according to the voltage variation state of the common source line CSL, and thus reduce unnecessary power consumption.

[0071] Please refer to Figure 6 , Figure 6 A flowchart of a method for adjusting a source line voltage according to an embodiment of the present application is shown. In step S610, an operational amplifier is provided to generate a bias voltage according to a reference voltage and a voltage of a common source line. In step S620, a current sink is provided to draw a sink current from the common source line according to the bias voltage, and in step S630, a current generator is provided to generate a first current according to the bias voltage, generate a second current according to a reference current, generate an output current according to a difference between the second current and the first current, and provide the output current to the common source line.

[0072] The implementation details of the steps in this embodiment are described in detail in the foregoing embodiments, and thus will not be described again.

[0073] In summary, the present application compares the common source line voltage with the default reference voltage to generate a bias voltage, and causes the current generator to adjust the magnitude of the output current provided to the common source line in accordance with the bias voltage. By avoiding providing a constant output current to the common source line, unnecessary power consumption is effectively reduced, achieving the purpose of saving power consumption.

[0074] The above-described embodiments of the present application are further explained in connection with the accompanying drawings that show, by way of example only and not by limitation, specific embodiments of the present application.

Claims

1. A source line voltage regulator coupled to a common source line, comprising: an operational amplifier having a first input coupled to the common source line and having a second input to receive a reference voltage, the operational amplifier generating a bias voltage; a current sink coupled between the common source line and a reference ground, the current sink sinking a sink current from the common source line in accordance with the bias voltage; and a current generator coupled to the common source line, the current generator providing an output current to the common source line, the current generator generating a first current in accordance with the bias voltage and generating a second current in accordance with a reference current, the current generator generating the output current in accordance with a difference between the second current and the first current; wherein the current generator comprises: a first current source generating a third current in accordance with the bias voltage; a first current mirror coupled to the first current source, the first current mirror mirroring the third current to generate the first current; a second current mirror mirroring the reference current to generate the second current; and a third current mirror mirroring the difference between the first current and the second current to generate the output current. The current sink is a first transistor, wherein a control terminal of the first transistor receives the bias voltage, a first terminal of the first transistor is coupled to the common source line, and a second terminal of the first transistor is coupled to the reference ground. The first current source is a second transistor, a first terminal of the second transistor is coupled to the first current mirror and provides the third current, a second terminal of the second transistor is coupled to the reference ground, and a control terminal of the second transistor receives the bias voltage. The first transistor and the second transistor have the same polarity.

5. The source line voltage regulator of claim 1, wherein the current generator further comprises: a reference current source coupled to the second current mirror to provide the reference current.

6. The source line voltage regulator of claim 1, wherein the first current mirror comprises: a first transistor having a first terminal to receive a supply voltage, a second terminal of the first transistor receiving the third current, and a control terminal of the first transistor coupled to the second terminal of the first transistor; and a second transistor having a first terminal to receive the supply voltage, a control terminal of the second transistor coupled to the control terminal of the first transistor, and a second terminal of the second transistor generating the first current.

7. The source line voltage regulator of claim 6, wherein the second current mirror comprises: a third transistor having a first terminal to receive the reference current, a first terminal of the third transistor coupled to a control terminal of the third transistor, and a second terminal of the third transistor coupled to the reference ground; and a fourth transistor having a first terminal coupled to the second terminal of the second transistor, a second terminal of the fourth transistor coupled to the reference ground, and a control terminal of the fourth transistor coupled to the control terminal of the third transistor.

8. The source line voltage regulator of claim 7, wherein the third current mirror comprises: ​ ​ 2. The source line voltage adjuster of claim 1, wherein, ​ 3. The source line voltage adjuster of claim 2, wherein, ​ 4. The source line voltage adjuster of claim 3, wherein, ​ ​ ​ ​ ​ ​ ​ ​ ​ ​ ​ ​ a fifth transistor having a first terminal receiving the supply voltage, a second terminal coupled to a second terminal of the second transistor and a first terminal of the fourth transistor, and a control terminal coupled to the second terminal of the fifth transistor; and a sixth transistor having a first terminal receiving the supply voltage, a second terminal generating the output current, and a control terminal coupled to the control terminal of the fifth transistor, wherein a current on the second terminal of the fifth transistor is equal to a difference between the second current and the first current.

9. The source line voltage regulator of claim 8, wherein polarities of the first transistor, the second transistor, the fifth transistor, and the sixth transistor are the same, polarities of the third transistor and the fourth transistor are the same, and a polarity of the first transistor is different from a polarity of the third transistor.

10. The source line voltage regulator of claim 1, wherein the current sink comprises: a plurality of transistors coupled in parallel between the common source line and the reference ground terminal, control terminals of the transistors commonly receiving a bias voltage, and configured to sink the sink current from the common source line; a plurality of switches respectively coupled in series between the transistors and the common source line, and respectively controlled by a plurality of enable signals; and a comparator and decoder configured to compare the reference voltage and the bias voltage to generate a comparison result, and decode the comparison result to generate the enable signals.

11. A memory device, comprising: the source line voltage regulator of claim 1; and a plurality of memory cell strings coupled to the common source line.

12. The memory device of claim 11, wherein the memory cell strings are respectively coupled to a plurality of bit lines, commonly receive a source line select signal, a ground select signal, and a plurality of word line signals.

13. The memory device of claim 11, wherein in a read operation, the memory cell strings provide a plurality of source currents to the common source line in accordance with data in a plurality of selected memory cells.

14. A method for adjusting a source line voltage, adapted for a memory device, comprising: providing an operational amplifier to generate a bias voltage in accordance with a reference voltage and a voltage on a common source line; providing a current sink to sink a sink current from the common source line in accordance with the bias voltage; and providing a current generator to generate a first current in accordance with the bias voltage, to generate a second current in accordance with a reference current, to generate an output current in accordance with a difference between the second current and the first current, and to provide the output current to the common source line; wherein the step of providing a current generator to generate a first current in accordance with the bias voltage, to generate a second current in accordance with a reference current, to generate an output current in accordance with a difference between the second current and the first current comprises: generating a third current in accordance with the bias voltage; mirroring the third current to generate the first current; mirroring the reference current to generate the second current; and mirroring a difference between the second current and the first current to generate the output current. ​

Images