Method of manufacturing sic electronic devices with reduced processing steps and sic electronic devices

Abstract

Embodiments of the present disclosure relate to methods of manufacturing SIC electronic devices with reduced processing steps and SIC electronic devices. A method for manufacturing a SiC-based electronic device includes forming a structural layer of SiC at a front side of a substrate. The substrate has a back side opposite the front side along a direction. An active region of the electronic device is formed in the structural layer, and the active region is configured to generate or conduct electrical current during use of the electronic device. A first electrical terminal is formed on the structural layer and an intermediate layer is formed at the back side of the substrate. The intermediate layer is heated by a laser beam to generate localized heating to facilitate formation of an ohmic contact of a titanium compound. A second electrical terminal of the electronic device is formed on the intermediate layer.

Description

Technical Field

[0001] This disclosure relates to a method for manufacturing SiC electronic devices, and the SiC electronic devices thus manufactured. In particular, this disclosure relates to an enhanced method for forming ohmic contacts on the back side of an electronic device, which requires a reduction in the number of device processing (“flipping”) steps. Background Technology

[0002] Semiconductor materials are known to be ideal for manufacturing electronic components (e.g., diodes or transistors), particularly for power applications, due to their wide bandgap, especially a bandgap energy value (Eg) greater than 1.1 eV, low on-resistance (RON), high thermal conductivity, high operating frequency, and high charge carrier saturation velocity. Silicon carbide (SiC) is a material possessing these properties and designed for use in manufacturing electronic components. Specifically, in terms of the previously listed properties, silicon carbide in its various polymorphs (e.g., 3C-SiC, 4H-SiC, 6H-SiC) is preferred over silicon.

[0003] Compared to similar devices provided on silicon substrates, electronics provided on silicon-carbon substrates offer numerous advantages, such as lower output impedance during conduction, lower leakage current, higher operating temperature, and higher operating frequency. In particular, SiC Schottky diodes exhibit superior switching performance, making SiC electronics especially advantageous for high-frequency applications. Current applications place demands on electrical characteristics and long-term device reliability.

[0004] Resistance value R ON It depends on several factors. For example, in a SiC Schottky diode (e.g., 4H-SiC) configured to operate at 650V and having a SiC substrate with a thickness of several hundred micrometers (e.g., 350μm), approximately [a certain percentage] of the resistance R [is affected]. ON 70% of the total value is contributed by the SiC substrate. Thus, reducing the thickness of the SiC substrate to close to one hundred micrometers (e.g., 110 μm) makes the substrate's resistance R... ON The contribution to the total value is significantly reduced (down to approximately 44%). Therefore, for medium-voltage applications (600-1200V), a polishing process on the back side of the SiC substrate is considered suitable, even if it is not required.

[0005] However, such processing steps cause serious problems in handling and processing wafers, which may become very thin and therefore prone to cracking, warping, or generally becoming damaged.

[0006] Figure 1 A known type of merged PN Schottky (MPS) device 1 in a Cartesian (triaxial) reference system of X, Y, and Z axes is shown in a side sectional view.

[0007] MPS device 1 includes: an N-type SiC substrate 3 having a first doping concentration, having a surface 3a opposite to surface 3b, and a thickness of approximately 350 μm; an N-type SiC drift layer (epitaxy growth) 2 having a second doping concentration lower than the first doping concentration, extending on surface 3a of substrate 3, with a thickness in the range of 5-10 μm; an ohmic contact region 6 (e.g., an ohmic contact region of nickel silicide) extending on surface 3b of substrate 3; a cathode metallization layer 16 extending on ohmic contact region 6; an anode metallization layer 8 extending on upper surface 2a of drift layer 2; a plurality of junction-barrier (JB) elements 9 in drift layer 2, facing upper surface 2a of drift layer 2, and each junction-barrier (JB) element 9 including an independent P-type implantation region 9' and an ohmic contact 9" of metallic material; and an edge termination region or guard ring 10 (optional), particularly the P-type implantation region, completely surrounding the junction-barrier (JB) element 9.

[0008] A Schottky diode 12 is formed at the interface between the drift layer 2 and the anode metallization layer 8. Specifically, the Schottky (semiconductor-metal) junction is formed through portions of the drift layer 2 and the anode metallization layer 8 that are in direct electrical contact.

[0009] The region of the MPS device 1, including the JB element 9 and the Schottky diode 12 (i.e., the region contained within the guard ring 10), is the active region 4 of the MPS device 1.

[0010] Figures 2 to 5 The steps of processing semiconductor material into wafer 20 are shown in a side cross-sectional view to obtain Figure 1 MPS device 1.

[0011] refer to Figure 2 The wafer 20 includes a SiC substrate 3 having a first conductivity type (N). On the front side 3a of the substrate 3, a SiC drift layer 2 is formed, for example by epitaxial growth, having the first conductivity type (N) and having a doping concentration lower than that of the substrate 3, for example, at 1.10. 14 -5·10 16 atoms / cm 3 Within the range. Drift layer 2 is specifically made of 4H-SiC, but other polymorphs can be used, such as 2H, 6H, 3C and / or 15R.

[0012] Then, on the upper side 2a of the drift layer 2, a hard mask 22 is formed, for example, by deposition of photoresist, TEOS, or another material. The thickness of the hard mask 22 is sufficient to block the following reference. Figure 2 The injection process is described. The hard mask 22 thus formed extends in the region of the wafer 20, wherein, in successive steps, the active region 4 of the MPS device 1 will be formed.

[0013] In the top view, on the XY plane, the hard mask 22 covers the area on the upper side 2a of the drift layer 2 where the Schottky diode 12 will be formed, and exposes the area on the upper side 2a of the drift layer 2 where the injection region 9' will be formed.

[0014] The next step, implanting a dopant having a second conductivity type (P) (e.g., boron or aluminum), is performed using a hard mask 22 (implantation is indicated by arrow 24 in the figure). During this implantation step, a dopant layer is also formed on... Figure 3 The protective ring 10 is not shown.

[0015] refer to Figure 3 Mask 22 is removed, and a thermal annealing step is performed for the diffusion and activation of the implanted dopant. The thermal annealing is performed, for example, at temperatures above 1600°C (e.g., in the range of 1700-1900°C and in some cases even higher). After thermal annealing, the implanted region 9' has a density of approximately 1.10... 17 atoms / cm 3 -1·10 20 atoms / cm 3 The concentration of dopant within the specified range.

[0016] Nickel deposition is proprietaryly performed at the implantation region 9', specifically using a silicon oxide mask (not shown) to cover the surface area of ​​wafer 20 other than the implantation region 9'. Ohmic contacts 9' of nickel silicide are formed by a chemical reaction between the deposited nickel and the silicon of the drift layer 2, followed by continuous thermal annealing at high temperatures (at intervals of 1 to 120 minutes at around 1000°C). In effect, the deposited nickel reacts with the surface material of the drift layer 2 to form Ni2Si (i.e., an ohmic contact), while the nickel in contact with the oxide of the mask does not react. Next, the unreacted metal and the mask are removed.

[0017] Next, Figure 4 The step of forming a cathode contact is performed, which includes forming Figure 1 The ohmic contact 6 and metallization layer 16 are shown. This may include a step in which the wafer 20 is rotated so that the back side of the same wafer 20 can be processed.

[0018] Since the front side of the wafer 20 does not have an anode metallization layer, forming a cathode contact in this process step is more preferable, thus preventing undesirable interface reactions between the metal and the semiconductor, as well as the electro-degradation of the Schottky diode 12.

[0019] An interface layer 26 of a metallic material (such as nickel) is deposited on the surface 3b of the substrate 3. The interface layer 26 is deposited, for example, by sputtering, and has a thickness in the range of approximately 10 nm to 500 nm. Then, thermal annealing at a high temperature (within time intervals of 1 minute to 120 minutes in the range of 900 to 1000 °C) can form an ohmic contact 6, which facilitates the formation of nickel silicide (Ni2Si) through a chemical reaction between the deposited nickel and the silicon of the substrate 3.

[0020] Then, Figure 5 The wafer 20 is rotated again, and an anode metallization layer 8 is deposited and shaped using photolithography and etching steps (in known methods, this step may include the use of one or more deposition masks and processing steps of the wafer 20 at high temperatures). Processing of the front side of the wafer 20 continues to complete the formation of the MPS device 1. Therefore, multiple Schottky-type semiconductor-metal junctions are formed between the region of the drift layer 2 having a first conductivity type (N) and the anode metallization layer 8. The anode metallization layer 8 is also formed as an anode contact. The passivation layer of the anode metallization layer can also be formed using known methods (not shown in the figure).

[0021] Next, the wafer is rotated again for back-side processing. Further deposition of a metal (e.g., Al or Cu, or an alloy or compound such as Ti / NiV / Ag or Ti / NiV / Au) on the ohmic contact 6 forms the cathode metallization layer 16.

[0022] Multiple MPS devices 1 can be formed on the same wafer 20 (typically). The final step of wafer dicing is performed to isolate one MPS device 1 from another MPS device 1.

[0023] refer to Figures 2 to 5 As can be seen from the description, the following may cause damage to the wafer 20 and / or the structures formed on its sides: various processing steps of the wafer 20 that involve flipping the wafer 20 several times to alternately process the front and back sides of the wafer 20. The smaller the thickness of the wafer 20, the greater the damage.

[0024] In fact, as mentioned earlier, substrate 3 is relatively thin in order to reduce its resistance R to MPS device 1. ON Due to the contribution of high-temperature processing, photolithography and fabrication operations, the wafer 20 may crack or warp.

[0025] The applicant has confirmed that it can be done through [the following]. Figure 3 After the steps and Figure 4The grinding step performed prior to this step is used to thin the wafer 20. In this case, a portion of the substrate 3 on surface 3b is physically removed to obtain the desired final thickness (e.g., 100 to 110 μm). Clearly, by thinning the wafer 20, this step involves a series of consecutive steps: flipping the wafer (in...) Figure 4 After the steps, in Figure 5 (before the steps) and the front side of the processed wafer 20 ( Figure 5 The steps involved are even more complex. The wafer 20 will have a total thickness of approximately 110 μm, making further processing practically impossible or requiring excessive attention and care.

[0026] It is evident that, for ease of discussion and better understanding, although the aforementioned issues have been discussed using a detailed reference to MPS devices, they can be extended to any SiC-based device, where the substrate thickness plays a role in determining the on-resistance (Ron) of the device during use. ON The role of ) . In such devices, reducing the substrate thickness leads to R ON However, the aforementioned processing and handling issues remain similar and limit operational freedom. Summary of the Invention

[0027] In various embodiments, this disclosure provides a method for manufacturing SiC electronic devices and SiC electronic devices to overcome the deficiencies of the prior art.

[0028] According to this disclosure, a method for manufacturing SiC electronic devices, SiC electronic devices, and a system for manufacturing SiC electronic devices are provided. Attached Figure Description

[0029] To better understand this disclosure, preferred embodiments of the present disclosure are now described by way of non-limiting example only, with reference to the accompanying drawings, wherein:

[0030] Figure 1 A cross-sectional view of an MPS device according to a known embodiment is shown;

[0031] Figures 2 to 5 Manufacturing process is shown Figure 1 The steps of the device;

[0032] Figure 6 A cross-sectional view of an MPS device according to an embodiment of the present disclosure is shown; and

[0033] Figures 7 to 13 Manufacture according to embodiments of the present disclosure is shown. Figure 6 The steps of the device. Detailed Implementation

[0034] This disclosure will be described with particular reference to integrated PN Schottky (MPS) devices. However, it will be apparent from the following description that this disclosure is generally applicable to any SiC-based electronic device.

[0035] According to one aspect of this disclosure, Figure 6 A side-section view shows a merged PN Schottky (MPS) device 50 in a Cartesian (triaxial) reference system along the X, Y, and Z axes.

[0036] The MPS device 50 includes: an N-type SiC substrate 53 having a first doping concentration, a surface 53a opposite to a surface 53b, and a thickness in the range of 70 μm to 180 μm, particularly in the range of 100 μm to 120 μm, for example, equal to 110 μm; an N-type SiC drift layer (in the form of epitaxial growth) 52 having a second doping concentration lower than the first doping concentration, extending on the surface 53a of the substrate 53, and having a thickness in the range of 5 to 10 μm; and an ohmic contact region or layer 56 (using Ti). x C y Ti x Si y and Ti x Si y C z A cathode metallization layer 57, such as Ti / NiV / Ag or Ti / NiV / Au, extends on the ohmic contact region 56; an anode metallization layer 58, such as Ti / AlSiCu or Ni / AlSiCu, extends on the upper surface 52a of the drift layer 52; a passivation layer 69 on the anode metallization layer 58 protects the anode metallization layer 58; a plurality of junction-barrier (JB) elements 59 in the drift layer 52 face the upper surface 52a of the drift layer 52, and each includes an independent P-type implantation region 59′ and an ohmic contact 59″ of metallic material; an edge termination region or guard ring 60 (optional), particularly a P-type implantation region, completely surrounds the junction-barrier (JB) elements 59.

[0037] One or more Schottky diodes 62 are formed on the side of the implantation region 59' at the interface between the drift layer 52 and the anode metallization layer 58. In particular, the Schottky (semiconductor-metal) junction is formed through portions of the drift layer 52 that are in direct electrical contact with individual portions of the anode metallization layer 58.

[0038] The region in MPS device 50 that includes JB element 59 and Schottky diode 62 (i.e., the region contained within guard ring 60) is the active region 54 of MPS device 50.

[0039] According to one aspect of this disclosure, as previously stated, the ohmic contact region 56 comprises titanium silicide (utilizing Ti... x C y Ti x Si y and Ti x Si y C z The ohmic contact region 56 is formed by depositing titanium on the surface 53b of the substrate 53 and generating a thermal chemical reaction between the deposited titanium and the material of the substrate 53. The chemical reaction, occurring in the temperature range of 1400-2600 °C, is favorable for Ti. x C y Ti x Si y and Ti x Si y C z The formation of the titanium compound makes the ohmic contact region 56 particularly stable. The following will detail the steps involved in manufacturing the MPS device 50. Figures 7 to 13 The steps for forming the ohmic contact region 56 are described below.

[0040] refer to Figure 7 A wafer 100 is provided, which includes a SiC substrate 53 (particularly 4H-SiC, however other polymorphs such as, but not limited to, 2H-SiC, 3C-SiC and 6H-SiC may be used).

[0041] Substrate 53 has a first conductivity type (N-type dopant in this embodiment) and provides a front surface 53a and a back surface 53b opposite to each other along the Z-axis. Substrate 53 has a conductivity of 1.10 19 -1·10 22 atoms / cm 3 Doping concentration within the range.

[0042] The front side of wafer 100 corresponds to the front surface 53a, and the back side of wafer 100 corresponds to the back surface 53b. The resistivity of substrate 30 is, for example, in the range of 5 mΩ·cm to 40 mΩ·cm.

[0043] On the positive surface 53a of the substrate 53, a silicon carbide drift layer 52 is formed, for example, by epitaxial growth. The drift layer 52 has a first conductivity type (N) and a doping concentration lower than that of the substrate 53, for example, 1.10. 14 -5·10 16 Within the range. For example, 10¹⁶ atoms / cm² can be formed through epitaxial growth. 3The drift layer 52 is made of SiC, particularly 4H-SiC, although other SiC polymorphs such as 2H, 6H, 3C or 15R can be used.

[0044] The drift layer 52 has a thickness defined between the upper side 52a and the lower side 52b (the lower side 52b is in direct contact with the positive surface 53a of the substrate 53).

[0045] Then, Figure 8 On the upper side 52a of the drift layer 52, the hard mask 70 can be formed, for example, by depositing a photoresist or TEOS, or another material suitable for this purpose. The hard mask 70 has a thickness in the range of 0.5 μm to 2 μm, or in any case, can be used to block the following reference. Figure 8 The described injection thickness. The hard mask 70 extends in the region where the wafer 100 is located, and in successive steps, forms the active region 54 of the MPS device 50.

[0046] In the top view, on the XY plane, the hard mask 70 covers the region on the upper side 52a of the drift layer 52 where the Schottky cell (diode 62) will be formed, and exposes the region on the upper side 52a of the drift layer 52 where the injection region 59' will be formed, as referenced. Figure 6 To conduct the identification.

[0047] The next step, implanting a dopant with a second conductivity type (here, P) (e.g., boron or aluminum), is performed using a hard mask 70 (implantation is indicated by arrow 72 in the diagram). Figure 8 If present, a protective ring 60 can also be formed during the process.

[0048] Optionally, Figure 8 The implantation step includes implanting one or more dopants having a second conductivity type to form a doping concentration higher than 1.10. 18 atoms / cm 3 The injection region 59′ utilizes an injection energy in the range of 30 keV to 400 keV and an injection energy of 1.10 keV. 12 atoms / cm 2 Up to 1.10 15 atoms / cm 2 Dosage within the range.

[0049] Next, Figure 9 Mask 70 is removed, and a heat treatment (or hot annealing) step is performed to facilitate the application of the mask. Figure 8 The diffusion and activation of the injected dopant in this step. Annealing is performed, for example, at temperatures above 1600°C (e.g., in the range of 1700°C–1900°C, and in some cases even higher). The dopant concentration is approximately 1.10.17 atoms / cm 3 Up to 1.10 20 atoms / cm 3 The injection zone 59′ within the range can therefore be formed.

[0050] Simultaneously, Schottky units are also formed, which are portions extending from the side of the drift layer 52 (along the X direction) to the injection region 59'. In other words, the Schottky units are portions extending to the drift layer 52... Figure 8 The part that is masked during the injection process.

[0051] See Figure 10 Ohmic contacts 59″ (here, for example, nickel silicide ohmic contacts 59″) are formed at each implanted region 59′, thereby facilitating the formation of the corresponding JB element 59. In a non-limiting embodiment, the implanted regions 59′ visible in a cross-sectional view are fully connected to each other (i.e., they form a grid). Therefore, the ohmic contacts 59″ are also fully connected to each other and electrically connected to the implanted regions 59′.

[0052] Ohmic contact 59 may also be formed at guard ring 60 (if present) and electrically connected to ohmic contact 59″.

[0053] The formation of the ohmic contact 59″ includes: forming a hard mask of thin oxide (e.g., in the range of 100 nm to 500 nm); next, photolithography and chemical etching steps are performed to chemically etch the area where the ohmic contact 59″ is to be formed; next, deposition of a metal material (e.g., nickel) is performed, and continuous thermal annealing (e.g., at a temperature in the range of 900 °C to 1100 °C for a time interval of 1 minute to 120 minutes) is performed. The deposited metal reacts with the surface SiC material to form an ohmic compound (e.g., nickel silicide), while the metal in contact with the hard mask oxide does not react. Next, the unreacted metal and the hard mask are removed.

[0054] Next, Figure 11 The step of forming the anode terminal is performed.

[0055] For this purpose, an interface layer 67 of a metallic material (such as titanium, nickel, or molybdenum) is deposited on the drift layer 52. The interface layer 67 is deposited by sputtering and has a thickness in the range of approximately 10 nm to 500 nm. The interface layer 67 extends to contact the implantation region 59′ through the ohmic contact 59″ and to contact the exposed region (i.e., Schottky cell) of the drift layer 52. In particular, the interface layer 67 facilitates the formation of a Schottky contact / Schottky barrier with the exposed region of the drift layer 52 and facilitates the formation of a junction-barrier (JB) element with the implantation region 59′ through the ohmic contact 59″.

[0056] Next, another metal layer 68 is formed on top of the interface layer 67 and is in direct contact with the interface layer 67. The metal layer 68 is, for example, an aluminum or copper metal layer and has a thickness of a few micrometers, for example, in the range of 1 to 10 μm.

[0057] The assembly consisting of interface layer 67 and metal layer 68 has been formed according to reference. Figure 6 The anodic metallization layer 58 is described.

[0058] like Figure 11 As shown, a plurality of Schottky semiconductor-metal junctions (Schottky diodes 12) are similarly formed between the regions of the anode metallization layer 58 and the drift layer 52 having a first conductivity type (N).

[0059] In an alternative embodiment (not shown), the interface layer 67 is omitted, allowing the metal layer 58 to extend into direct contact with the drift layer 52.

[0060] refer to Figure 12 A passivation layer 69 (e.g., a passivation layer of polyimide) is also formed on the anodic metallization layer 58 and is shaped to open one or more areas of the electrical contact 70 to contact the anodic metallization layer 58.

[0061] Then, Figure 13 The cathode contact terminal is formed on the back side of the wafer 100, that is, on the back surface 53b of the substrate 53.

[0062] The cathode is formed by forming a metallization layer on the back surface 53b of the substrate 53 and an ohmic contact region or layer between the metallization layer and the back surface 53b. The ohmic contact layer facilitates electrical contact between the metallization layer and the substrate 53.

[0063] In detail, the formation of the ohmic contact includes, for example, depositing an intermediate layer 72 (particularly titanium) on the back surface 53b of the substrate 53 by sputtering. The intermediate layer 72 has a thickness, for example, in the range of 10 nm to 200 nm, particularly equal to 100 nm.

[0064] The formation of ohmic contacts can be accomplished by reacting the titanium of the intermediate layer 72 with the carbon and silicon of the substrate 53. This is to create Ti at the intermediate layer 72. x C y Ti x Si y and Ti x Si y C z The required thermal budget, without thermally affecting the structure present on the front side of the wafer 100, is achieved by using a laser source 80 for generating a laser beam 82 to locally heat the intermediate layer 72 to a temperature in the range of 1400 to 2600°C, for example, a temperature equal to 2000°C.

[0065] The intermediate layer 72 reaches a substantially uniform temperature across its entire thickness (along the Z-axis) at the surface portion where the laser beam 82 strikes the intermediate layer 72, thus benefiting Ti. x C y Ti x Si y and Ti x Si y C z The formation of type 72 titanium compounds will convert the intermediate layer 72 into a new type of titanium compound. Figure 6 The ohmic contact area 56 is marked in the middle. From Ti to Ti x C y Ti x Si y and Ti x Si y C z The conversion of the Ti-type titanium compound is achieved by heating the entire usable surface of the intermediate layer 72, particularly at or above the melting temperature of the material of the intermediate layer 72, to completely or partially melt the intermediate layer 72. Here, "usable surface" is used to refer to the surface portion of the intermediate layer 72 that is intended to be used as an ohmic contact (e.g., defined by design); the usable surface may not correspond to the entire surface of the intermediate layer 72 (e.g., when using the MPS device 50, possible portions of the intermediate layer 72 that sideways to the active region 54 are not relevant because these possible portions do not participate in charge conduction).

[0066] Therefore, the intermediate layer 72 becomes the ohmic contact region or layer 56 mentioned above, that is, it has ohmic and non-Schottky characteristics.

[0067] Then, the formation of the cathode metallization layer 57 on the intermediate layer 72 / ohmic contact 56 is performed, for example, by sputtering deposition of Ti / NiV / Ag or Ti / NiV / Au.

[0068] Figure 6 The MPS device 50 was thus obtained.

[0069] Laser 80 is, for example, an excimer UV laser. Other types of lasers are available, including lasers with wavelengths in the visible light region.

[0070] The configuration and operating parameters of the laser 80 optimized to achieve the purpose of the titanium intermediate layer 72 in this disclosure (to generate titanium-based ohmic contacts) are as follows:

[0071] Wavelengths in the range of 290 to 370 nm, especially 310 nm;

[0072] Pulse duration in the range of 100ns to 300ns, especially 160ns;

[0073] The number of pulses in the range of 1 to 10, especially 4;

[0074] Between 1 and 4 J / cm 2 Energy density in the range, especially 3 J / cm 2 .

[0075] The temperature reached in the intermediate layer is in the range of 1400 to 2600°C, particularly 2000°C; more specifically, the operating parameters of the laser 80 are set such that the temperature reached at the intermediate layer 72 is equal to or higher than the melting temperature of the intermediate layer 72. Due to the use of the laser 80, all of the above temperatures can be achieved, regardless of the thickness of the intermediate layer 72.

[0076] To improve the on-resistance (R) of MPS device 50 ON ) characteristics (i.e., reducing R) ON (Value), the wafer 100 can be thinned by a polishing step on the back surface 53 of the substrate 53. This polishing step is in Figure 12 After the steps and in Figure 13 The step is performed before (i.e. before forming the ohmic contact 56). The substrate 53 is thinned to the thickness required to achieve the latter, for example, in the range of 70 μm to 180 μm.

[0077] Multiple MPS devices 50 can be formed on the same wafer 100. In this case, a final die dicing step is performed to physically separate one MPS device 50 from another.

[0078] According to further embodiments of this disclosure, the ohmic contact region 56 may be an ohmic contact region of a material other than titanium compounds (TixCy, TixSiy, and TixSiyCz).

[0079] For example, the formation of the ohmic contact region 56 can be performed by depositing (or forming by another technique) an intermediate layer 72 of a metallic material other than titanium on the back surface 53b of the substrate 53 and heating (particularly at or above the melting temperature of the material of layer 72, for example, at a temperature in the range of 1400 to 2600°C), similar to what has been previously described, the intermediate layer 72 by means of a laser beam 82 to facilitate the formation of an ohmic compound or alloy between the material of the intermediate layer 72 and the material of the substrate 53.

[0080] For example, considering the SiC substrate 53:

[0081] Intermediate layer 72 is a Mo intermediate layer 72, and thermal annealing by laser is beneficial to the formation of MoxCy, MoxSiy, and MoxSiyCz; or

[0082] Intermediate layer 72 is an intermediate layer of Ta, and thermal annealing by laser facilitates the formation of TaxCy, TaxSiy, and TaxSiyCz; or

[0083] Intermediate layer 72 is a W intermediate layer 72, and thermal annealing by laser is beneficial to the formation of WxCy and WxSiy; or

[0084] Intermediate layer 72 is a Co intermediate layer 72, and thermal annealing by laser is beneficial to the formation of CoxSiy; or

[0085] The intermediate layer 72 is a Ni intermediate layer 72, and the thermal annealing performed by laser is conducive to the formation of NixSiy.

[0086] Its advantages are obvious when tested according to the features of this disclosure provided in this specification.

[0087] In particular, the proposed solution allows for the formation of ohmic contacts on the back side of power devices on very thin (≤180 mm) SiC wafers. According to this solution, after the anolyte metallization and passivation layers are deposited and defined on the front side of the wafer, the substrate is thinned to the desired thickness without being limited by prior art processes (e.g., thicknesses greater than 180 μm). Next, a titanium layer is deposited on the back side of the wafer, and the formation of the ohmic contacts is operated via an annealing laser process, thus preserving the structure previously formed on the front side of the wafer. The following benefits can be obtained by using this solution:

[0088] Simplification of the process flow (in fact, in our solution, wafer thinning is performed after the processing of the front side of the device is completed);

[0089] The quality of ohmic contacts is better (only one process step after ohmic contact formation);

[0090] The risk of wafer breakage is reduced (the wafer rotates only once, and there are only three process steps after wafer thinning);

[0091] There are no photolithography limitations after the wafer thinning step;

[0092] The impedance contribution of the substrate to the total Ron of the device is significantly reduced.

[0093] Furthermore, compared to the use of nickel according to existing technologies, the use of titanium as a starting material for the continuous formation of titanium-based ohmic contacts has several advantages. For example, the continuity and uniformity of the reaction layer due to the presence of TixCy, TixSiy, and TixSiyCz type compounds, the absence of C agglomerates within the reaction layer, and the mechanical strength of the reaction layer.

[0094] Finally, it is clear that modifications and variations may be made to the content described and shown herein without departing from the scope of protection of this disclosure as defined by the appended claims.

[0095] In particular, as previously observed, this disclosure is not limited to the formation of ohmic contacts on the back side of MPS devices, but extends to the formation of back ohmic contacts in conventional vertical conduction electronic devices, such as Schottky diodes, JBS diodes, MOSFETs, IGBTs, JFETs, DMOS, etc.

[0096] The various embodiments described above can be combined to provide other embodiments. These and other changes can be made to the embodiments based on the specific description above. Generally, the terminology used in the following claims should not be construed as limiting the claims to the specific embodiments disclosed in this specification and claims, but should be interpreted to include all possible embodiments and the full scope of equivalents to which the claims are given. Therefore, the claims are not limited by this disclosure.

Claims

1. A method for manufacturing SiC-based electronic devices, comprising: A SiC structural layer with first conductivity is formed on the front side of a silicon carbide (SiC) substrate, the substrate having a back side opposite to the front side in one direction; The active region of the electronic device is formed in the structural layer; Multiple doped regions are formed in the active region, and the multiple doped regions have a second conductivity that is opposite to the first conductivity. Multiple metal ohmic contacts are formed in the plurality of doped regions; A first electrical terminal is formed on the structural layer; An intermediate layer of first metal is formed on the back side of the substrate after the first electrical terminal is formed; The compound that forms the first metal layer by locally heating a selected portion of the intermediate layer with a laser beam in a temperature range of 1400°C to 2600°C, wherein the wavelength of the laser beam is substantially equal to 310 nm; and After heating a selected portion of the intermediate layer, a second electrical terminal of the electronic device is formed on the intermediate layer.

2. The method of claim 1, wherein the first metal is titanium and the compound of the first metal comprises Ti. x C y Ti x Si y and Ti x Si y C z .

3. The method of claim 2, wherein the laser beam is generated using the following parameters: Pulse duration in the range of 100 to 300 ns; The number of pulses in the range of 1 to 10; and Between 1 and 4 J / cm 2 Energy density within a certain range.

4. The method of claim 3, wherein the laser beam is generated using the following parameters: This is essentially equal to a pulse duration of 160 ns; The number of pulses that are essentially equal to 4; and Essentially equal to 3J / cm 2 Energy density.

5. The method of claim 1, wherein the first metal comprises at least one of titanium, molybdenum, tantalum, tungsten, cobalt, or nickel, and the formation of the compound of the first metal occurs along the entire thickness of the intermediate layer in the direction thereof.

6. The method according to claim 1, further comprising: Before forming the intermediate layer, the substrate is thinned at the back side to a final thickness equal to or less than 180 μm.

7. The method according to claim 1, wherein the substrate is one of the following: 4H-SiC, 6H-SiC, 3C-SiC, 15R-SiC.

8. The method of claim 1, wherein the electronic device is one of the following: a combined PN Schottky diode, a Schottky diode, a JBS diode, a MOSFET, an IGBT, a JFET, or a DMOS.

9. The method of claim 8, wherein the electronic device is a combined PN Schottky MPS diode, and wherein: The structural layer is the drift layer of the MPS diode; The first electrical terminal is an anode metal terminal, electrically contacting the doped region and directly electrically contacting the drift layer on the side of the doped region, to form a junction-barrier (JB) diode with the doped region and a Schottky diode with the drift layer; and The second electrical terminal is a cathode terminal. The JB diode and Schottky diode define the active region of the MPS diode.

10. The method of claim 9, further comprising: A second metal is deposited at the doped region; and Thermal annealing is performed to enable the formation of silicides of the second metal, thereby forming an ohmic contact at the doped region.

11. A system for manufacturing electronic devices, comprising: A first reaction chamber is used for forming a silicon carbide (SiC) structural layer on the positive side of a SiC substrate, the SiC structural layer having a first conductivity. A second reaction chamber is used for the formation of an active region in the structural layer, the active region comprising: The structural layer contains a plurality of doped regions, each having a second conductivity opposite to the first conductivity; and Multiple metal ohmic contacts in the plurality of doped regions; A third reaction chamber is used for the formation of a first electrical terminal on the structural layer and for the formation of an intermediate metal layer on the back side of the substrate; and A laser device is configured to generate a laser beam in a temperature range of 1400°C to 2600°C to form a compound of a metal layer by locally heating selected portions of the metal layer, the laser beam comprising a wavelength substantially equal to 310 nm.

12. The system of claim 11, wherein the laser device is configured to generate a laser beam using the following parameters: Pulse duration in the range of 100ns to 300ns; The number of pulses in the range of 1 to 10; and Between 1 and 4 J / cm 2 Energy density within a certain range.

13. The system of claim 12, wherein the laser device is configured to at least partially melt the intermediate layer.

14. The system of claim 12, wherein the substrate is one of the following: 4H-SiC, 6H-SiC, 3C-SiC, 15R-SiC.

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