Semiconductor Structure and Method of Forming the Same

Abstract

The method includes providing a structure having: two fins extending from a substrate; an isolation structure isolating the bottoms of the fins; source / drain (S / D) components located above each fin; a dielectric fin longitudinally oriented parallel to the fins and disposed between the two fins and above the isolation structure; a dummy gate stack located above the isolation structure, the fins, and the dielectric fin; and one or more dielectric layers located above the sidewalls of the dummy gate stack. The method further includes: removing the dummy gate stack to create a gate trench within the one or more dielectric layers, wherein the dielectric fin is exposed within the gate trench; trimming the dielectric fin to reduce the width of the dielectric fin; and after trimming, forming a high-k metal gate within the gate trench. Embodiments of the present invention also relate to semiconductor structures and methods of forming the same.

Description

Technical Field

[0001] Embodiments of the present invention relate to semiconductor structures and methods of forming the same. Background Art

[0002] The electronics industry has an ever - increasing need for smaller and faster electronic devices that can simultaneously support a greater number of increasingly complex and sophisticated functions. To meet these needs, there is a continuing trend in the integrated circuit (IC) industry to fabricate low - cost, high - performance, and low - power ICs. To date, these goals have been largely achieved by reducing the IC size (e.g., the smallest IC component size), thereby increasing production efficiency and reducing associated costs. However, such scaling has also increased the complexity of the IC manufacturing process. One area of interest is how to isolate adjacent metal gate electrodes and adjacent source / drain electrodes in highly integrated ICs. Summary of the Invention

[0003] Embodiments of the present invention provide a method of forming a semiconductor structure, comprising: providing a structure having: two fins extending from a substrate; an isolation structure isolating the bottoms of the fins; source / drain (S / D) components located above each of the fins; a dielectric fin longitudinally oriented parallel to the fins and disposed between the two fins and above the isolation structure; a pseudo - gate stack located above the isolation structure, the fins, and the dielectric fin; and one or more dielectric layers located above the sidewalls of the pseudo - gate stack; removing the pseudo - gate stack to create a gate trench in the one or more dielectric layers, wherein the dielectric fin is exposed in the gate trench; trimming the dielectric fin to reduce the width of the dielectric fin; and after the trimming, forming a high - k metal gate in the gate trench.

[0004] Another embodiment of the present invention provides a method of forming a semiconductor structure, comprising: providing a structure having: fins extending from a substrate; an isolation structure isolating the bottoms of the fins; source / drain (S / D) components located above the fins; dielectric fins longitudinally oriented parallel to the fins, disposed between adjacent fins and above the isolation structure and isolating the source / drain components; a dummy gate stack located above the isolation structure, the fins, and the dielectric fins; and one or more dielectric layers located above the sidewalls of the dummy gate stack; partially recessing the dummy gate stack to expose a portion of the dielectric fins; forming an etch mask that covers a first dielectric fin of the dielectric fins and exposes a second dielectric fin of the dielectric fins; partially etching the second dielectric fin through the etch mask such that a top surface of the second dielectric fin is below a top surface of the first dielectric fin; removing the etch mask; removing the dummy gate stack to create a gate trench in the one or more dielectric layers, wherein at least the first dielectric fin is exposed in the gate trench; trimming the first dielectric fin to reduce a width of the first dielectric fin; and after the trimming, forming a high-k metal gate in the gate trench.

[0005] Yet another embodiment of the present invention provides a semiconductor structure, comprising: a substrate; an isolation structure located above the substrate; two source / drain (S / D) components located above the isolation structure; one or more channel semiconductor layers laterally connecting the two source / drain components; a high-k metal gate located between the two source / drain components and engaging the one or more channel semiconductor layers; and a dielectric fin located above the isolation structure and adjacent to the two source / drain components and the high-k metal gate, wherein a top surface of the dielectric fin is above a top surface of the high-k metal gate, and a first portion of the dielectric fin adjacent to the high-k metal gate is narrower than a second portion of the dielectric fin adjacent to the two source / drain components. BRIEF DESCRIPTION OF THE DRAWINGS

[0006] The present invention is best understood from the following detailed description when read in conjunction with the accompanying drawings. It should be emphasized that, according to standard practice in the industry, the various components are not drawn to scale and are for illustrative purposes only. In fact, for clarity of discussion, the dimensions of the various components may be arbitrarily increased or decreased.

[0007] Figure 1A 、 Figure 1B and Figure 1C illustrate flowcharts of methods of forming semiconductor devices having hybrid dielectric fins in accordance with various aspects of the present invention.

[0008] Figure 2 、 Figure 3 、Figure 4 , Figure 5 , Figure 6 , Figure 7 , Figure 8 , Figure 9 , Figure 10 , Figure 11 , Figure 12 , Figure 13 , Figure 14 , Figure 15 , Figure 16 , Figure 17 , Figure 18 , Figure 19 , Figure 20 , Figure 21 , Figure 22 , Figure 23 , Figure 29 and Figure 31 illustrate a perspective view of a portion of a semiconductor device in an intermediate step of manufacturing according to an embodiment of a method in accordance with Figures 1A to 1C . A cross-sectional view of a portion of a semiconductor device according to some embodiments is shown in

[0009] Figure 24 , Figure 25 , Figure 26 , Figure 27B , Figure 27C , Figure 27D , Figure 28 , Figure 30B , Figure 30C , Figure 30D , Figure 32B and Figure 32C illustrate a cross-sectional view of a portion of a semiconductor device according to some embodiments. A top view of a portion of a semiconductor device according to some embodiments is shown in

[0010] Figure 27A , Figure 27E , Figure 30A , Figure 32A and Figure 32D illustrate a top view of a portion of a semiconductor device according to some embodiments. DETAILED DESCRIPTION

[0011] Numerous different embodiments or examples are provided below to implement the different features of the provided subject matter. Specific examples of components and arrangements are described below to simplify the present invention. Of course, these are merely examples and are not intended to be limiting. For example, in the following description, forming the first component above or on the second component may include embodiments where the first component and the second component are in direct contact, and may also include embodiments where additional components may be formed between the first component and the second component such that the first component and the second component may not be in direct contact. For purposes of simplicity and clarity, the various components may be drawn arbitrarily in different proportions. Additionally, the present invention may repeat reference numerals and / or letters in the various examples. This repetition is for purposes of simplicity and clarity and does not in itself indicate a relationship between the various embodiments and / or configurations discussed.

[0012] Furthermore, for ease of description, spatial relative terms such as "below", "beneath", "lower", "above", "upper", etc. may be used herein to describe the relationship of one element or component to another as shown in the figures. In addition to the orientation shown in the figures, the spatial relative terms are intended to encompass different orientations of the device in use or operation. The device may be otherwise oriented (rotated 90 degrees or in other orientations), and the spatial relative descriptors used herein may be interpreted accordingly. Additionally, unless otherwise stated, according to the specific technologies disclosed herein and the knowledge of those skilled in the art, when a numerical value or numerical range is described using terms such as "about", "approximate", etc., the term encompasses values within certain variations (such as + / - 10% or other variations) of the described numerical value. For example, the term "about 5 nm" may encompass size ranges from 4.5 nm to 5.5 nm, 4.0 nm to 5.0 nm, etc.

[0013] This application generally relates to semiconductor structures and manufacturing processes, and more particularly to using dielectric fins to isolate metal gates and epitaxial source / drain (S / D) components. For example, dielectric fins are disposed between two metal gates and between the S / D components of two transistors. The dielectric fins are trimmed to be narrower between the two metal gates than between the S / D components. This isolation scheme provides more space for the formation of metal gates, enabling the formation of metal gates with higher quality more uniformly. When continuing to scale down transistors, this overcomes the common problem of metal gate filling. At the same time, the disclosed isolation scheme provides a greater distance between adjacent S / D components to avoid accidental merging of the S / D components. When continuing to scale down transistors, this overcomes the common problem in S / D engineering. Observed from a top view, the dielectric fins are in a stitched shape - having two wider portions connected by a narrower portion. In some embodiments, the corners of the wider and narrower portions can be rounded. The dielectric fins can include multiple layers, such as a hybrid layer of a low-k layer and a high-k layer, to achieve etching selectivity during manufacturing and provide low coupling capacitance between adjacent metal gates and between adjacent source / drain components. Details of the structure and manufacturing method of the present invention are described below in conjunction with the accompanying drawings, which illustrate the process of manufacturing a GAA device according to some embodiments. A GAA device refers to a device having vertically stacked horizontally oriented multi-channel transistors, such as nanowire transistors and nanosheet transistors. Due to the better gate control ability, lower leakage current, and full FinFET device layout compatibility of GAA devices, they are promising candidates to push CMOS to the next stage of the roadmap. The present invention can also be used to manufacture FinFET devices with the disclosed dielectric fins. For simplicity, the present invention uses a GAA device as an example and points out certain differences in the processes between GAA and FinFET embodiments. Those of ordinary skill in the art should understand that they can easily use the present invention as a basis for designing or modifying other processes and structures to achieve the same purpose and / or achieve the same advantages as the embodiments described herein.

[0014] Figure 1A , Figure 1B and Figure 1C are flowcharts of a method 100 for manufacturing a semiconductor device according to various aspects of the present invention. The present invention anticipates additional processing. Additional operations can be provided before, during, and after method 100, and for additional embodiments of method 100, some of the operations described can be moved, replaced, or eliminated.

[0015] The method 100 is described below in conjunction with Figures 2 to 32D and Figures 2 to 32DShows various perspective views, top views, and cross-sectional views of a semiconductor device (or semiconductor structure) 200 at various manufacturing steps according to Method 100 in accordance with some embodiments. In some embodiments, device 200 is part of an IC chip, a system-on-chip (SoC), or a portion thereof, including various passive and active microelectronic devices such as resistors, capacitors, inductors, diodes, p-type field effect transistors (PFETs), n-type field effect transistors (NFETs), FinFETs, nanosheet FETs, nanowire FETs, other types of multi-gate FETs, metal oxide semiconductor field effect transistors (MOSFETs), complementary metal oxide semiconductor (CMOS) transistors, bipolar junction transistors (BJTs), laterally diffused MOS (LDMOS) transistors, high-voltage transistors, high-frequency transistors, memory devices, other suitable components, or combinations thereof. For clarity, Figures 2 to 32D has been simplified to better understand the inventive concept of the present invention. Additional components may be added to device 200, and some of the components described below may be replaced, modified, or eliminated in other embodiments of device 200.

[0016] At operation 102, Method 100 ( Figure 1A ) forms fins 218 over substrate 201. According to an embodiment, the resulting structure is shown in Figure 2 . In the illustrated embodiment, each fin 218 includes a semiconductor layer 204, a stack 205 of semiconductor layers 210 and 215 over semiconductor layer 204, and a fin top hard mask 206 over stack 205. In an embodiment, substrate 201 is a semiconductor-on-insulator substrate such as a silicon-on-insulator (SOI) substrate, a silicon-germanium-on-insulator (SGOI) substrate, or a germanium-on-insulator (GOI) substrate. A semiconductor-on-insulator substrate may be fabricated using separation by implanted oxygen (SIMOX), wafer bonding, and / or other suitable methods. In an alternative embodiment, substrate 201 is a bulk silicon substrate (i.e., including bulk single-crystalline silicon). In various embodiments, substrate 201 may include other semiconductor materials such as germanium, silicon carbide, gallium arsenide, gallium phosphide, indium phosphide, indium arsenide, indium antimonide, SiGe, GaAsP, AlInAs, AlGaAs, GaInAs, GaInP, GaInAsP, or combinations thereof.

[0017] In an embodiment, the semiconductor layer 204 may be silicon, silicon germanium, germanium, or other suitable semiconductors, and may be undoped or unintentionally doped with a very low dose of dopants. A semiconductor layer stack 205 is formed over the semiconductor layer 204 and includes semiconductor layers 210 and semiconductor layers 215 stacked vertically (e.g., along the z-direction) from the surface of the semiconductor layer 204 in a staggered or alternating configuration. In some embodiments, the semiconductor layers 210 and semiconductor layers 215 are epitaxially grown in the shown staggered and alternating configuration. For example, a first semiconductor layer 210 is epitaxially grown on the semiconductor layer 204, a first semiconductor layer 215 is epitaxially grown on the first semiconductor layer 210, a second semiconductor layer 210 is epitaxially grown on the first semiconductor layer 215, and so on until the semiconductor layer stack 205 has the desired number of semiconductor layers 210 and semiconductor layers 215. In some embodiments, the epitaxial growth of the semiconductor layers 210 and semiconductor layers 215 is achieved by a molecular beam epitaxy (MBE) process, a chemical vapor deposition (CVD) process (e.g., vapor phase epitaxy (VPE) or ultra-high vacuum (UHV) CVD), a metalorganic chemical vapor deposition (MOCVD) process, other suitable epitaxial growth processes, or a combination thereof.

[0018] The composition of semiconductor layer 210 is different from that of semiconductor layer 215 to achieve etch selectivity and / or different oxidation rates during subsequent processing. In some embodiments, semiconductor layer 210 has a first etch rate with respect to an etchant, and semiconductor layer 215 has a second etch rate with respect to the etchant, where the second etch rate is less than the first etch rate. In some embodiments, semiconductor layer 210 has a first oxidation rate, and semiconductor layer 215 has a second oxidation rate, where the second oxidation rate is less than the first oxidation rate. In the illustrated embodiment, semiconductor layer 210 and semiconductor layer 215 include different materials, atomic percentages of components, weight percentages of components, thicknesses, and / or properties to achieve a desired etch selectivity during an etching process (such as an etching process implemented to form a suspended channel layer in the channel region of device 200). For example, in the case where semiconductor layer 210 includes silicon germanium and semiconductor layer 215 includes silicon, the silicon etch rate of semiconductor layer 215 is less than the silicon germanium etch rate of semiconductor layer 210. In some embodiments, semiconductor layer 210 and semiconductor layer 215 may include the same material but have different atomic percentages of components to achieve etch selectivity and / or different oxidation rates. For example, semiconductor layer 210 and semiconductor layer 215 may include silicon germanium, where semiconductor layer 210 has a first silicon atomic percentage and / or a first germanium atomic percentage, and semiconductor layer 215 has a different second silicon atomic percentage and / or a different second germanium atomic percentage. The present invention contemplates any combination of semiconductor materials (e.g., materials that maximize current) that can provide the desired etch selectivity, desired oxidation rate difference, and / or desired performance characteristics for semiconductor layer 210 and semiconductor layer 215, including any materials of the semiconductor materials disclosed herein.

[0019] As further described below, semiconductor layer 215 or a portion thereof forms the channel region of device 200. In the illustrated embodiment, semiconductor layer stack 205 includes three semiconductor layers 210 and three semiconductor layers 215. After undergoing subsequent processing, this configuration will result in a device 200 having three channels. However, depending on, for example, the number of channels required for device 200 (e.g., a GAA transistor) and / or the design requirements of device 200, the present invention contemplates embodiments where semiconductor layer stack 205 includes more or fewer semiconductor layers. For example, semiconductor layer stack 205 may include two to ten semiconductor layers 210 and two to ten semiconductor layers 215. In an alternative embodiment where device 200 is a FinFET device, stack 205 is only one layer of semiconductor material, such as one layer of silicon.

[0020] The fins 218 may be patterned by any suitable method. For example, the fins 218 may be patterned using one or more photolithography processes, including double patterning or multiple patterning processes. Typically, the double patterning or multiple patterning process combines photolithography and self-alignment processes, allowing for the creation of patterns having, for example, a pitch that is smaller than that obtainable using a single direct photolithography process. For example, in one embodiment, a sacrificial layer is formed over the stack 205, and the sacrificial layer is patterned using a photolithography process. Spacers are formed next to the patterned sacrificial layer using a self-alignment process. The sacrificial layer is then removed, and the remaining spacers or mandrels may then be used as mask elements for patterning the fins 218. For example, a mask element (such as a hard mask 206) is used to etch recesses in the stack 205 and the substrate 201, leaving the fins 218 on the substrate 201. The etching process may include dry etching, wet etching, reactive ion etching (RIE), and / or other suitable processes. For example, the dry etching process may employ an oxygen-containing gas, a fluorine-containing gas (e.g., CF 4 , SF 6 , CH 2 F 2 , CHF 3 and / or C 2 F 6 ), chlorine-containing gases (e.g., Cl 2 , CHCl 3 , CCl 4 and / or BCl 3 ), bromine-containing gases (such as HBr and / or CHBr 3 ), iodine-containing gases, other suitable gases and / or plasmas, and / or combinations thereof. For example, the wet etching process may include etching in the following solutions: dilute hydrofluoric acid (DHF); potassium hydroxide (KOH) solution; ammonia; a solution containing hydrofluoric acid (HF), nitric acid (HNO 3 ) and / or acetic acid (CH 3 or other suitable wet etchants. Many other embodiments of methods of forming fins 218 may be suitable.

[0021] At operation 104, method 100 ( Figure 1A ) Various liner layers are formed over the substrate 201 and the fins 218, embodiments of which are described in Figure 3is shown. In the illustrated embodiment, the liner layer includes a dielectric liner layer 202 and a semiconductor liner layer 203. The liner layers 202 and 203 are formed along the surfaces of the substrate 201 and the fins 218 and do not completely fill the space between adjacent fins 218. In an embodiment, each of the liner layers 202 and 203 is formed to have a substantially uniform thickness. In some embodiments, for example, the thickness of the dielectric liner layer 202 can be in the range of about 1.5 nm to about 4.5 nm, and the thickness of the semiconductor liner layer 203 can be in the range of about 1.5 nm to about 4.5 nm. In the present embodiment, the dielectric liner layer 202 helps to protect the surfaces of the fins 218 and helps to improve the adhesion between the liner layer 203 and the respective surfaces of 201 and 218, and the semiconductor liner layer 203 serves as a seed layer when forming a cladding layer in subsequent manufacturing steps. In an embodiment, the dielectric liner layer 202 includes silicon dioxide, and the semiconductor liner layer 203 includes silicon, such as crystalline silicon or amorphous silicon. In an alternative embodiment, the dielectric liner layer 202 includes other dielectric materials, such as silicon oxynitride. In various embodiments, the dielectric liner layer 202 can be formed by thermal oxidation, chemical oxidation, CVD, atomic layer deposition (ALD), or other methods. In various embodiments, the semiconductor liner layer 203 can be formed by CVD, ALD, or other methods.

[0022] At operation 106, method 100 ( Figure 1A ) forms an isolation structure (or isolation component) 230 over the substrate 201 to isolate various regions of the device 200, such as Figure 4 and Figure 5 shown. For example, the isolation component 230 surrounds the bottoms of the fins 218 to separate and isolate the fins 218 from each other. The isolation component 230 includes silicon oxide, silicon nitride, silicon oxynitride, other suitable isolation materials (e.g., including silicon, oxygen, nitrogen, carbon, or other suitable isolation components), or combinations thereof. The isolation component 230 can include different structures, such as a shallow trench isolation (STI) structure and / or a deep trench isolation (DTI) structure. In some embodiments, the isolation component 230 includes a multi-layer structure, such as a silicon nitride layer disposed over a thermal oxide liner layer. The isolation component 230 can be formed in multiple steps. For example, an insulator material can be deposited to fill the trenches between the fins 218 by, for example, a CVD process or a spin-on glass process. Then, a chemical mechanical polishing (CMP) process is performed to remove excess insulator material and / or planarize the top surface of the insulator material. This is shown in Figure 4 and is shown in Figure 5As shown, the etch-back of the insulator material uses an etch process that is tuned to be selective to the insulator material and have no (or minimal) etch on the semiconductor underlayer 203. In the illustrated embodiment, the insulator material is etch-backed such that the top surface of the isolation member 230 is below or flush with the top surface of the semiconductor layer 204. In an alternative embodiment, the insulator material is etch-backed such that the top surface of the isolation member 230 is below the top surface of the bottommost layer 210 in the stack 205 and above the top surface of the semiconductor layer 204.

[0023] At operation 108, method 100 ( Figure 1A ) forms a cladding 231 over the top surface and sidewall surfaces of the fins 218 and over the isolation member 230. According to an embodiment, the resulting structure is shown in Figure 6 . As Figure 6 shown, the cladding 231 does not completely fill the space between adjacent fins 218. In some embodiments, the cladding 231 may be formed to have a thickness in the range of, for example, about 4 nm to about 12 nm. In an embodiment, the cladding 231 includes silicon germanium (SiGe). For example, SiGe can be epitaxially grown from the semiconductor underlayer 203 including silicon. The semiconductor underlayer 203 can be incorporated into the cladding 231 during the epitaxial growth process. In various embodiments, any suitable epitaxial process can be used to deposit the cladding 231, such as VPE and / or UHV CVD, molecular beam epitaxy, other suitable epitaxial growth processes, or combinations thereof. In some embodiments, after depositing the cladding 231, operation 108 performs an etch process to remove portions of the cladding 231 from over the isolation member 230, for example, using a plasma dry etch process. In such embodiments, portions of the cladding 231 on top of the fins 218 can also be partially or completely removed.

[0024] At operation 110, method 100 ( Figure 1A ) forms a dielectric liner 232 over the cladding 231 and over the top surface of the isolation member 230. According to an embodiment, the resulting structure is shown in Figure 7 . As Figure 7 shown, in this embodiment, the dielectric liner 232 does not completely fill the space between adjacent fins 218. In an alternative embodiment, the dielectric liner 232 completely fills the space between adjacent fins 218, as Figure 29 shown, which will be discussed later. In the present embodiment, the dielectric liner 232 can be formed to have a thickness w3 in the range of about 1 nm to about 6 nm. This thickness is designed considering the impact on the source / drain members to be formed nearby, which will be discussed in more detail later with reference to Figure 27B . In the present embodiment, the dielectric liner 232 includes a high-k dielectric material, such as HfO 2 、HfSiOx (e.g., HfSiO 4 ), HfSiON, HfLaO, HfTaO, HfTiO, HfZrO, HfAlOx, ZrO 2 , ZrSiO 2 , AlSiO, Al 2 O 3 , TiO 2 , LaO, LaSiO, Ta 2 O 3 , Ta 2 O 5 , Y 2 O 3 , SrTiO 3 , BaZrO, BaTiO 3 (BTO), (Ba, Sr)TiO 3 (BST), Si 3 N 4 , hafnium oxide - aluminum (HfO 2 -Al 2 O 3 ) alloy, other suitable high - k dielectric materials, or combinations thereof. In the present invention, high - k dielectric materials generally refer to dielectric materials having a high dielectric constant (e.g., greater than 7). Dielectric liner 232 can be deposited using CVD, PVD, ALD, HDPCVD, MOCVD, RPCVD, PECVD, LPCVD, ALCVD, APCVD, other suitable methods, or combinations thereof. As will be discussed, in some embodiments, dielectric liner 232 will be part of a dielectric fin. For simplicity, liner layers 202 and 203 are not shown in Figure 7 (but they still exist adjacent to isolation component 230).

[0025] At operation 112, method 100( Figure 1A ) deposits a dielectric fill layer 233 over dielectric liner 232 and fills the gaps between fins 218. Subsequently, operation 112 can perform a CMP process to planarize the top surface of device 200 and expose cladding 231, as Figure 8 shown. In this embodiment, dielectric fill layer 233 includes a low - k dielectric material, such as a dielectric material including Si, O, N, and C (e.g., silicon oxide (SiO 2) Silicon nitride, silicon oxynitride, silicon carbonitride, silicon carbon oxynitride. In an embodiment, the dielectric fill layer 233 includes an oxide formed from tetraethyl orthosilicate (TEOS), undoped silicate glass, or doped silicon oxide, such as borophosphosilicate glass (BPSG), fluoride-doped silicate glass (FSG), phosphosilicate glass (PSG), boron-doped silicon glass (BSG), other low-k dielectric materials, or combinations thereof. Some example low-k dielectric materials include xerogel, aerogel, amorphous fluorocarbon, parylene, BCB, polyimide, or combinations thereof. In the present invention, a low-k dielectric material generally refers to a dielectric material having a low dielectric constant (e.g., less than 7). A flowable CVD (FCVD) process can be used to deposit the dielectric fill layer 233, which process includes, for example, depositing a flowable material (such as a liquid compound) over the device 200 and converting the flowable material into a solid material by suitable techniques (such as thermal annealing and / or ultraviolet radiation treatment). Other types of methods can be used to deposit the dielectric fill layer 233.

[0026] At operation 114, method 100 ( Figure 1A ) forms a dielectric cap 234 over the dielectric fill layer 233 and between dielectric liners 232 on opposite sidewalls of the cladding 231, such as Figure 9 and Figure 10 shown. In an embodiment, the dielectric cap 234 includes a high-k dielectric material, such as HfO 2 , HfSiO x (e.g., HfSiO 4 ), HfSiON, HfLaO, HfTaO, HfTiO, HfZrO, HfAlOx, ZrO 2 , ZrSiO 2 , AlSiO, Al 2 O 3 , TiO 2 , LaO, LaSiO, Ta 2 O 3 , Ta 2 O 5 , Y 2 O 3 , SrTiO 3 , BaZrO, BaTiO 3 (BTO), (Ba,Sr)TiO 3 (BST), Si 3 N 4 , hafnium oxide-aluminum oxide (HfO 2 -Al 2 O 3) An alloy, other suitable high-k dielectric materials, or a combination thereof. In an embodiment, operation 114 includes recessing the dielectric fill layer 233 using a selective etching process that etches the dielectric fill layer 233 without (or minimally) etching the dielectric liner 232 and the cladding 231. According to an embodiment, in Figure 9 the resulting structure is shown. In various embodiments, the dielectric fill layer 233 is recessed such that the top surface of the dielectric fill layer 233 is approximately flush with the top surface of the topmost layer 215 in the fin 218, e.g., the two top surfaces are within + / - 5 nm of each other. Maintaining the height of the dielectric fill layer 233 at this level helps with the etch load in subsequent manufacturing steps (e.g., referring to operation 132 where the high-k dielectric layer above the dielectric fill layer 233 is recessed). For example, the top surface of the dielectric fill layer 233 can be 5 nm higher or 5 nm lower than the top surface of the topmost layer 215. Then, operation 114 deposits one or more high-k dielectric materials in the grooves using, for example, ALD, CVD, PVD, oxidation-based deposition processes, other suitable processes, or a combination thereof. Subsequently, operation 114 performs a CMP process on the one or more high-k dielectric materials and the cladding 231 to expose the fin top hard mask 206. The remaining portion of the one or more high-k dielectric materials becomes the dielectric cap 234. As Figure 10 shown, the high-k dielectric liner 232, the low-k dielectric fill layer 233, and the high-k dielectric cap 234 together form the dielectric fin 229. The low-k dielectric fill layer 233 is surrounded by the high-k dielectric liner 232 and the high-k dielectric cap 234. The dielectric fin 229 is oriented longitudinally parallel to the fin 218. The dielectric fin 229 and the cladding 231 together completely fill the space between adjacent fins 218.

[0027] At operation 116, method 100 ( Figure 1A ) partially recesses the fins 218 and the cladding 231 disposed between the dielectric fins 229. In particular, operation 116 removes the hard mask layer 206 and recesses the fins 218 until the topmost semiconductor layer 215 is exposed. According to an embodiment, in Figure 11 the resulting structure is shown. Operation 116 can apply one or more etching processes that are selective to the hard mask layer 206 and the cladding 231, while not etching (or minimally etching) the dielectric cap 234 and the dielectric liner 232. The selective etching process can be dry etching, wet etching, reactive ion etching, or other suitable etching methods.

[0028] At operation 118, method 100 ( Figure 1B ) forms the pseudo-gate stack 240 and the gate spacer 247. Referring to Figure 12, each pseudo-gate stack 240 includes a pseudo-gate dielectric layer 235 located above the surfaces of the fin 218 and the dielectric fin 229, a pseudo-gate electrode layer 245 located above the gate dielectric layer 235, and one or more hard mask layers 246 located above the pseudo-gate electrode layer 245. In an embodiment, the pseudo-gate dielectric layer 235 includes a dielectric material such as silicon oxide, a high-k dielectric material, other suitable dielectric materials, or a combination thereof. In some embodiments, the pseudo-gate electrode layer 245 includes polysilicon or other suitable materials, and the one or more hard mask layers 246 include silicon oxide, silicon nitride, or other suitable materials. The pseudo-gate dielectric layer 235, the pseudo-gate electrode layer 245, and the hard mask layer 246 can be deposited using CVD, PVD, ALD, PECVD, LPCVD, ALCVD, APCVD, other suitable methods, or a combination thereof. As Figure 12 shown, a lithography patterning and etching process is then performed to pattern the one or more hard mask layers 246, the pseudo-gate electrode layer 245, and the pseudo-gate dielectric layer 235 to form the pseudo-gate stack 240. The lithography patterning process includes photoresist coating (e.g., spin coating), soft baking, mask alignment, exposure, post-exposure baking, developing the photoresist, rinsing, drying (e.g., hard baking), other suitable lithography processes, or a combination thereof. The etching process includes a dry etching process, a wet etching process, other etching methods, or a combination thereof.

[0029] Operation 118 also forms a gate spacer 247 (such as Figure 13 shown) on the sidewalls of the pseudo-gate stack 240. The gate spacer 247 is formed by any suitable process and includes a dielectric material. The dielectric material can include silicon, oxygen, carbon, nitrogen, other suitable materials, or a combination thereof (e.g., silicon oxide, silicon nitride, silicon oxynitride (SiON), silicon carbide, silicon carbonitride (SiCN), silicon oxycarbide (SiOC), silicon oxynitride (SiOCN)). For example, a dielectric layer including silicon and nitrogen (such as a silicon nitride layer) can be deposited above the pseudo-gate stack 240 and then etched (e.g., anisotropically etched) to form the gate spacer 247. In some embodiments, the gate spacer 247 includes a multi-layer structure, such as a first dielectric layer including silicon nitride and a second dielectric layer including silicon oxide. In some embodiments, more than one set of spacers (such as seal spacers, bias spacers, sacrificial spacers, pseudo-spacers, and / or main spacers) are formed adjacent to the pseudo-gate stack 240. In such an embodiment, each set of spacers can include materials having different etching rates. For example, a first dielectric layer including silicon and oxygen (e.g., silicon oxide) can be deposited and etched to form a first set of spacers adjacent to the pseudo-gate stack 240, and a second dielectric layer including silicon and nitrogen (e.g., silicon nitride) can be deposited and etched to form a second set of spacers adjacent to the first set of spacers.

[0030] At operation 120, method 100( Figure 1B ) forms source / drain (S / D) trenches 250 by etching fins 218 adjacent to gate spacers 247. According to an embodiment, in Figure 13 The resulting structure is shown. In the illustrated embodiment, the etching process completely removes the semiconductor layer stack 205 in the source / drain regions of the fins 218, thereby exposing the semiconductor layer 204 of the fins 218 in the source / drain regions. Thus, the source / drain trenches 250 have sidewalls defined by the remaining portions of the semiconductor layer stack 205 and a bottom defined by the semiconductor layer 204, the remaining portions being disposed in the channel region under the gate stack 240. In some embodiments, the etching process removes some but not all of the semiconductor layer stack 205 such that the source / drain trenches 250 have a bottom defined by the semiconductor layer 210 or the semiconductor layer 215 in the source / drain regions. In some embodiments, the etching process also removes some but not all of the semiconductor layer 204 such that the source / drain trenches 250 extend below the topmost surface of the semiconductor layer 204 and below the topmost surface of the isolation member 230. In the illustrated embodiment, the dielectric cap 234 is partially recessed in the source / drain region. In some alternative embodiments, the dielectric cap 234 is completely removed in the source / drain region and the dielectric fill layer 233 is exposed. The etching process may include a dry etching process, a wet etching process, other suitable etching processes, or a combination thereof. In some embodiments, the etching process is a multi-step etching process. For example, the etching process may alternately use etchants to separately and alternately remove the semiconductor layer 210 and the semiconductor layer 215. In some embodiments, the parameters of the etching process are configured to selectively etch the semiconductor layer stack while minimally (or not at all) etching the dummy gate stack 240 and / or the isolation member 230. In some embodiments, a lithography process (such as the lithography process described herein) is performed to form a patterned mask layer covering the dummy gate stack 240 and / or the isolation member 230, and the etching process uses the patterned mask layer as an etch mask.

[0031] At operation 122, method 100( Figure 1B ) forms inner spacers 255 along the surface of the semiconductor layer 210 within the S / D trenches 250 (see Figure 15 ). This may involve multiple etching and deposition processes. As Figure 14As shown, a first etching process is performed that selectively etches the semiconductor layer 210 and the cladding layer 231 exposed by the source / drain trench 250, while minimally (or not) etching the semiconductor layer 215, such that gaps are formed between the semiconductor layers 215 and between the semiconductor layers 215 and 204 under the gate spacers 247. Accordingly, portions (edges) of the semiconductor layer 215 are suspended in the channel region under the gate spacers 247. In some embodiments, the gaps extend partially under the dummy gate stack 240. The first etching process is configured to etch the semiconductor layer 210 and the cladding layer 231 laterally (e.g., along the "x" direction), thereby reducing the length of the semiconductor layer 210 and the cladding layer 231 along the "x" direction. The first etching process is a dry etching process, a wet etching process, other suitable etching processes, or a combination thereof. Then, a deposition process forms a spacer layer over the gate structure 240 and over the components (e.g., semiconductor layers 215, 204, and 210) defining the source / drain trench 250, such as CVD, PVD, ALD, HDPCVD, MOCVD, RPCVD, PECVD, LPCVD, ALCVD, APCVD, other suitable methods, or a combination thereof. The spacer layer partially (and in some embodiments, completely) fills the source / drain trench 250. The deposition process is configured to ensure that the spacer layer fills the gaps between the semiconductor layers 215 and between the semiconductor layers 215 and the semiconductor layer 204 under the gate spacers 247. Then, a second etching process is performed that selectively etches the spacer layer to form the inner spacers 255, as Figure 15 shown, while minimally (or not) etching the semiconductor layers 215 and 204, the dummy gate stack 240, and the gate spacers 247. In some embodiments, the spacer pieces are removed from the sidewalls of the gate spacers 247, the sidewalls of the semiconductor layers 215, the dummy gate stack 240, and the semiconductor layer 204. The spacer layer (and thus the inner spacers 255) includes a material different from the materials of the semiconductor layers 215 and 204 and the material of the gate spacers 247 to achieve a desired etch selectivity during the second etching process. In some embodiments, the spacer layer 255 includes a dielectric material that includes silicon, oxygen, carbon, nitrogen, other suitable materials, or a combination thereof (e.g., silicon oxide, silicon nitride, silicon oxynitride, silicon carbide, or silicon carbon oxynitride). In some embodiments, the inner spacer layer 255 includes a low-k dielectric material, such as those described herein. In embodiments where the device 200 is a FinFET, the inner spacers 255 are omitted and operation 122 is skipped.

[0032] At operation 124, method 100( Figure 1B ) epitaxially grows semiconductor S / D components 260 (including S / D components 260-1 and 260-2) in the S / D trenches 250. According to an embodiment, inFigure 16 The resulting structure is shown. In an embodiment, an epitaxial S / D component 260 is grown from the semiconductor layer 204 at the bottom of the S / D trench 250 and from the semiconductor layer 215 at the sidewalls of the S / D trench 250. The epitaxial process may use CVD deposition techniques (such as VPE and / or UHV CVD), molecular beam epitaxy, other suitable epitaxial growth processes, or combinations thereof. The epitaxial process may use gaseous and / or liquid precursors that interact with the composition of the semiconductor layers 204 and 215 (especially the semiconductor layer 215). The epitaxial S / D component 260 is doped with an n-type dopant or a p-type dopant for an n-type transistor or a p-type transistor, respectively. In some embodiments, for an n-type transistor, the epitaxial S / D component 260 comprises silicon and may be doped with carbon, phosphorus, arsenic, other n-type dopants, or combinations thereof (e.g., to form a Si:C epitaxial source / drain component, a Si:P epitaxial source / drain component, or a Si:C:P epitaxial source / drain component). In some embodiments, for a p-type transistor, the epitaxial S / D component 260 comprises silicon germanium or germanium and may be doped with boron, other p-type dopants, or combinations thereof (e.g., to form a Si:Ge:B epitaxial source / drain component). In some embodiments, the epitaxial S / D component 260 comprises more than one epitaxial semiconductor layer, where the epitaxial semiconductor layers may comprise the same or different materials and / or dopant concentrations. In some embodiments, the epitaxial S / D component 260 comprises materials and / or dopants that achieve a desired tensile and / or compressive stress in the corresponding channel region. In some embodiments, the epitaxial S / D component 260 is doped by adding impurities to the source material of the epitaxial process (i.e., in-situ) during deposition. In some embodiments, after the deposition process, the epitaxial S / D component 260 is doped by an ion implantation process. In some embodiments, an annealing process (e.g., rapid thermal annealing (RTA) and / or laser annealing) is performed to activate the dopants in the epitaxial S / D component 260. In some embodiments, some of the epitaxial S / D components 260 are p-type while others are n-type. For example, the S / D component 260-1 is p-type while the S / D component 260-2 is n-type. In such an embodiment, the p-type and n-type S / D components 260 are formed in separate processing sequences, including, for example, masking the p-type GAA transistor region when forming the epitaxial S / D component 260 in the n-type GAA transistor region and masking the n-type GAA transistor region when forming the epitaxial S / D component 260 in the p-type GAA transistor region. In various embodiments, the S / D components 260-1 and 260-2 may both be p-type, both be n-type, or one be p-type and the other be n-type. Additionally, as Figure 16As shown, the size of the S / D component 260 is limited by the dielectric fin 229. In particular, the dielectric fin 229 is taller than the S / D component 260 to ensure that adjacent S / D components 260 do not accidentally merge. This improves the yield of the device 200. In some embodiments, an air gap (or void) is formed, which is surrounded by the S / D component 260, the isolation component 230, and the dielectric fin 229.

[0033] At operation 126, method 100 ( Figure 1B ) forms a contact etch stop layer (CESL) 269 over the S / D component 260, and forms an interlayer dielectric (ILD) layer 270 over the CESL 269, and fills the space between the opposing gate spacers 247. According to an embodiment, the resulting structure is shown in Figure 17 . The CESL 269 includes a material different from the ILD layer 270. The CESL 269 may include La 2 O 3 , Al 2 O 3 , SiOCN, SiOC, SiCN, SiO 2 , SiC, ZnO, ZrN, Zr 2 Al 3 O 9 , TiO 2 , TaO 2 , ZrO 2 , HfO 2 , Si 3 N 4 , Y 2 O 3, AlON, TaCN, ZrSi, or other suitable materials; and can be formed by CVD, PVD, ALD, or other suitable methods. The ILD layer 270 can include oxides formed from tetraethyl orthosilicate (TEOS), undoped silicate glass, or doped silicon oxide, such as borophosphosilicate glass (BPSG), fluoride-doped silicate glass (FSG), phosphosilicate glass (PSG), boron-doped silicon glass (BSG), low-k dielectric materials, other suitable dielectric materials, or combinations thereof. The ILD 270 can be formed by PECVD (plasma-enhanced CVD), FCVD (flowable CVD), or other suitable methods. After depositing the CESL 269 and the ILD layer 270, operation 126 performs a CMP process and / or other planarization processes on the CESL 269, the ILD layer 270, and the hard mask layer 246 until the top (or top surface) of the pseudo-gate electrode layer 245 is exposed. In this embodiment, as discussed later, the ILD layer 270 is recessed to a level below the top surface of the pseudo-gate electrode layer 245, and the ILD protection layer 271 is deposited over the ILD layer 270 to protect the ILD layer 270 from subsequent etching processes performed on the pseudo-gate stack 240 and the dielectric fin 229. As Figure 17 shown, the ILD layer 270 is surrounded by the CESL 269 and the ILD protection layer 271. In an embodiment, the ILD protection layer 271 includes the same or similar material as the CESL 269. The ILD protection layer 271 includes dielectric materials such as Si 3 N 4 , SiCN, SiOCN, SiOC, metal oxides such as HrO 2 , ZrO 2 , hafnium aluminum oxide, and hafnium silicate, or other suitable materials, and can be formed by CVD, PVD, ALD, or other suitable methods.

[0034] At operation 128, the method 100 ( Figure 1B ) partially recesses the pseudo-gate electrode 245 such that the top surface of the pseudo-gate electrode 245 is below the top surface of the dielectric fin 229. According to an embodiment, the resulting structure is shown in Figure 18 . Looking across the line A-A in Figure 17 at the front of Figure 18 . Operation 128 can use a dry etching process, a wet etching process, other suitable etching processes, or combinations thereof. Additionally, the etching process is configured to selectively etch the pseudo-gate electrode 245 while minimally (or not) etching other components of the device 200 (such as the CESL 269, the ILD protection layer 271, and the pseudo-gate dielectric layer 235). In Figure 18In the illustrated embodiment, the gate spacer 247 is also partially recessed. In an alternative embodiment, the gate spacer 247 is not recessed or is only minimally recessed.

[0035] At operation 130, method 100 ( Figure 1B ) forms an etch mask 241 that covers the dielectric fins 229, which dielectric fins 229 will be separated (or cut) to form metal gates in subsequent manufacturing steps. These dielectric fins 229 are labeled 229-1. Other dielectric fins 229 that are not covered by the etch mask 241 are labeled 229-2. According to an embodiment, the resulting structure is shown in Figure 19 . The etch mask 241 includes a material different from the materials of the dummy gate dielectric layer 235 and the dielectric fins 229 (including layers 234, 233, and 232) to achieve etch selectivity. In an embodiment, the etch mask 241 includes a patterned photoresist located above a patterned hard mask (such as a patterned mask having silicon nitride). In some embodiments, the etch mask 241 also includes an anti-reflection coating (ARC) or other layer located between the patterned photoresist and the patterned hard mask. Other materials for the etch mask 241 are contemplated by the present invention, provided that etch selectivity is achieved during the etching of the dielectric fins 229-2 and the dummy gate dielectric layer 235. In some embodiments, after depositing a hard mask layer (e.g., a silicon nitride layer), operation 130 performs a lithography process, including forming a photoresist layer (e.g., by spin coating) above the hard mask layer, performing a pre-exposure bake process, performing an exposure process using a mask, performing a post-exposure bake process, and performing a development process. During the exposure process, the photoresist layer is exposed to radiant energy (e.g., UV light, DUV light, or EUV light), where, depending on the mask pattern and / or mask type of the mask (e.g., binary mask, phase-shift mask, or EUV mask), the mask blocks, transmits, and / or reflects radiation to the photoresist layer such that an image is projected onto the photoresist layer corresponding to the mask pattern. Since the photoresist layer is sensitive to radiant energy, depending on the characteristics of the photoresist layer and the characteristics of the developer used in the development process, the exposed portions of the photoresist layer undergo chemical changes, and the exposed (or unexposed) portions of the photoresist layer dissolve during the development process. After development, the photoresist layer is patterned into a photoresist pattern corresponding to the mask. Optionally, the exposure process may be implemented or replaced by other methods, such as maskless lithography, electron beam writing, ion beam writing, or combinations thereof. The hard mask layer is then etched through the patterned photoresist to produce a patterned hard mask.

[0036] At operation 132, method 100 ( Figure 1C ) etches the dummy gate dielectric layer 235 and the dielectric fins 229-2 through the etch mask 241. According to an embodiment, the resulting structure is shown in Figure 20The resulting structure is shown. In particular, the dielectric fins 229-2 are etched until the top surface of the low-k dielectric fill layer 233 is exposed. In the illustrated embodiment, the dummy gate electrode 245 is partially removed by operation 132. In an alternative embodiment, the dummy gate electrode 245 is completely removed by operation 132 in the regions not covered by the etch mask 241. Subsequently, the etch mask 241 is removed, for example, by stripping, ashing, and / or other methods.

[0037] At operation 134, method 100 ( Figure 1C ) completely removes the dummy gate stack 240 (i.e., any remaining portions of the dummy gate electrode 245 and the dummy gate dielectric layer 235) to form a gate trench 242 ( Figure 21 and Figure 22 ). In an embodiment, operation 134 applies a first etch process (such as wet etching) to remove any remaining portions of the dummy gate electrode 245. According to an embodiment, the resulting structure is shown in Figure 21 . Then, operation 134 applies a second etch process (such as wet etching or dry etching) to remove any remaining portions of the dummy gate dielectric layer 235, resulting in a gate trench 242, such as Figure 22 shown. In some embodiments, the etch processes in operation 134 are configured to selectively etch the dummy gate stack 240 while minimally (or not) etching other components of the device 200 (e.g., CESL 269, ILD protection layer 271, gate spacers 247, isolation components 230, and dielectric fins 229-1 and 229-2.

[0038] At operation 136, method 100 ( Figure 1C ) removes the cladding 231 and the semiconductor layer 210 exposed in the gate trench 242, leaving a semiconductor layer 215 suspended above the semiconductor layer 204 and connected to the S / D components 260, such as Figure 22 shown. This process is also referred to as a channel release process, and the semiconductor layer 215 is also referred to as a channel layer. The etch process selectively etches the cladding 231 and the semiconductor layer 210 while minimally (or not) etching the semiconductor layer 215, and in some embodiments, minimally (or not) etching the gate spacers 247 and / or the inner spacers 255. In an embodiment where the device 200 is a FinFET, since there is only one channel layer 215 and there is no semiconductor layer 210 in the channel region, the channel release process is omitted.

[0039] At operation 138, method 100 ( Figure 1C ) trims the portions of the dielectric fins 229-1 and 229-2 exposed in the gate trench 242, such as Figure 23As shown. In an embodiment, operation 138 includes two etching processes, which are designed to target the materials of the high-k dielectric liner 232 and the low-k dielectric fill layer 233, respectively. For example, operation 138 applies a first etching process (such as wet etching or plasma etching) to remove the high-k dielectric liner 232 from the sidewalls of the low-k dielectric fill layer 233 and from the sidewalls of the high-k dielectric cap 234. Then, operation 138 applies a second etching process (such as another wet etching or another plasma etching) to laterally etch the low-k dielectric fill layer 233 along the "y" direction. In some embodiments, due to the second etching process, the low-k dielectric fill layer 233 becomes narrower than the high-k dielectric cap 234. The first etching process and the second etching process are designed to laterally etch the layers 232 and 233 along the "y" direction, for example, by isotropic plasma etching or chemical etching. The etching process can also reduce the width (along the "y" direction) and height (along the "z" direction) of the high-k dielectric cap 234. It is noted that a portion of the high-k dielectric liner 232 remains under the low-k dielectric fill layer 233. In various embodiments, operation 138 can use one etching process to etch the high-k dielectric liner 232 and the low-k dielectric fill layer 233, or use more than two etching processes to achieve the same or similar results as described above. Additionally, in various embodiments, the etching process in operation 138 is configured to selectively etch the dielectric fins 229 while minimally (or not) etching other components of the device 200 (such as the CESL 269, the ILD protection layer 271, the gate spacer 247, the isolation component 230, the internal spacer 255, and the semiconductor layers 215 and 204).

[0040] Due to operation 138, the portions of the dielectric fins 229-1 and 229-2 exposed in the gate trench 242 become narrower than their original width (along the "y" direction). The other portions of the dielectric fins 229-1 and 229-2 (covered by the ILD layer 270 and the gate spacer 247) are not trimmed and remain the same width as their original width. The gate trench 242 expands laterally (i.e., along the "y" direction), and the space between the semiconductor layer 215 and the dielectric fins 229 also expands laterally. As the device continues to scale down, having an expanded gate trench 242 facilitates the deposition of the high-k metal gate therein. In some methods of not trimming the dielectric fins 229, the gate trench is narrower, and the deposition of the high-k metal gate may be difficult. In some cases, after the deposition of the high-k metal gate, voids may remain in the gate trench, which will lead to long-term reliability issues and non-uniform transistor performance. In the present embodiment, trimming the dielectric fins 229 within the gate trench 242 eliminates or alleviates those problems.

[0041] In some embodiments, operation 138 may use a timer or other device to control the amount of trimming of the dielectric fins 229. In various embodiments, portions of the dielectric fins 229-1 and 229-2 that are exposed in the gate trenches 242 are trimmed such that their widths are reduced to about 0.35 to about 0.8 of their original widths. In some embodiments, portions of the dielectric fins 229-1 and 229-2 that are exposed in the gate trenches 242 are trimmed such that their widths are reduced by about 2 nm to about 12 nm from their original widths. If the reduction in their widths is too small (e.g., the reduction is less than 2 nm or their widths are still greater than 80% of their original widths), the gate trenches 242 may not expand enough to have a meaningful improvement and the metal gates therein may still have voids. If the reduction in their widths is too large (e.g., the reduction is greater than 12 nm or their widths are less than 35% of their original widths), the thickness of the dielectric fins 229 may not be sufficient to isolate adjacent metal gates, reducing long-term reliability.

[0042] At operation 140, method 100 ( Figure 1C ) forms a high-k metal gate 243 in the gate trenches 242. According to an embodiment, the resulting structure is shown in Figure 24 . The high-k metal gate 243 includes a gate dielectric layer 349 that wraps around each semiconductor layer 215 and a gate electrode 350 that is located above the gate dielectric layer 349.

[0043] The gate dielectric layer 349 may include a high-k dielectric material such as HfO 2 , HfSiO, HfSiO 4 , HfSiON, HfLaO, HfTaO, HfTiO, HfZrO, HfAlO x , ZrO, ZrO 2 , ZrSiO 2 , AlO, AlSiO, Al 2 O 3 , TiO, TiO 2 , LaO, LaSiO, Ta 2 O 3 , Ta 2 O 5 , Y 2 O 3 , SrTiO 3 , BaZrO, BaTiO 3 (BTO), (Ba,Sr)TiO 3 (BST), Si 3 N 4 , hafnium oxide-aluminum oxide (HfO 2 -Al 2 O3 ) an alloy, other suitable high-k dielectric materials, or combinations thereof. The gate dielectric layer 349 can be formed by chemical oxidation, thermal oxidation, atomic layer deposition (ALD), chemical vapor deposition (CVD), and / or other suitable methods. In particular, the gate dielectric layer 349 is also deposited over the top surface and sidewalls of the dielectric fins 229 (including dielectric fins 229-1 and 229-2). As Figure 24 shown, the low-k dielectric fill layer 233 is again surrounded by high-k dielectric layers. At this manufacturing stage, the low-k dielectric fill layer 233 in the portion of the dielectric fin 229-1 below the gate electrode 350 is surrounded by the high-k dielectric layer 232 at its bottom, the high-k gate dielectric layer 349 at its sidewalls, and the high-k dielectric cap 234 at its top surface; and the low-k dielectric fill layer 233 in the portion of the dielectric fin 229-2 below the gate electrode 350 is surrounded by the high-k dielectric layer 232 at its bottom and the high-k gate dielectric layer 349 at its sidewalls and top surface. In some embodiments, the high-k metal gate 243 further includes an interfacial layer 280 located between the gate dielectric layer 349 and the channel layer 215. The interfacial layer 280 can include silicon dioxide, silicon oxynitride, or other suitable materials. In some embodiments, the gate electrode layer 350 includes an n-type or p-type work function layer and a metal fill layer. For example, the n-type work function layer can include a metal having a sufficiently low effective work function, such as titanium, aluminum, tantalum carbide, tantalum carbonitride, tantalum silicon nitride, or combinations thereof. For example, the p-type work function layer can include a metal having a sufficiently large effective work function, such as titanium nitride, tantalum nitride, ruthenium, molybdenum, tungsten, platinum, or combinations thereof. For example, the metal fill layer can include aluminum, tungsten, cobalt, copper, and / or other suitable materials. The gate electrode layer 350 can be formed by CVD, PVD, plating, and / or other suitable processes. As previously discussed, due to the enlarged space in the gate trench 242, the deposition of the interfacial layer 280, the high-k gate dielectric layer 349, and the gate electrode layer 350 becomes easier, and the gate trench 242 can be completely filled by these layers without leaving voids. This improves the uniformity and long-term reliability of the transistor.

[0044] At operation 142, method 100 ( Figure 1C ) recesses the gate electrode layer 350 such that its top surface is below the top surface of the dielectric fin 229-1 but above the top surface of the dielectric fin 229-2. According to an embodiment, the resulting structure is shown in Figure 25 . As Figure 25As shown, operation 142 effectively cuts or separates the gate electrode layer 350 into two segments, creating two separated high-k metal gates (or two high-k metal gate segments) 243a and 243b. The dielectric fin 229-1 isolates the two gates 243a and 243b. This process is sometimes referred to as a self-aligned cut metal gate process (or self-aligned metal gate cut process) because in this step it can cut the metal gate without using a lithography process, and the cutting position is pre-determined by the position of the dielectric fin 229-1. The self-aligned cut metal gate process is more advantageous than the lithography cut metal gate process because the former is less affected by the lithography overlay window or offset. This further enhances the device scaling. It should be noted that the gate electrode layer 350 is not cut at the position of the dielectric fin 229-2. In other words, the gate electrode layer 350 on the left and right sides of the dielectric fin 229-2 remains connected as a continuous gate electrode layer and serves as one gate. Operation 142 can implement a wet etching or dry etching process that selectively etches the gate electrode layer 350 while minimally (or not) etching the high-k dielectric cap 234. In some embodiments, the etching process also minimally (or not) etches the high-k gate dielectric layer 349 such that the high-k gate dielectric layer 349 remains substantially above the top surface and sidewalls of the high-k dielectric cap 234. In some embodiments, the high-k gate dielectric layer 349 can also be etched by operation 142. In some embodiments, the gate spacer 247 can also be partially recessed by operation 142.

[0045] At operation 144, method 100 ( Figure 1C ) forms a dielectric overlay layer 352 over the gate electrode layer 350 and over the dielectric fin 229-1. According to an embodiment, the resulting structure is shown in Figure 26 . In some embodiments, the dielectric overlay layer 352 includes La 2 O 3 , Al 2 O 3 , SiOCN, SiOC, SiCN, SiO 2 , SiC, ZnO, ZrN, Zr 2 Al 3 O 9 , TiO 2 , TaO 2 , ZrO 2 , HfO 2 , Si 3 N 4 , Y 2 O 3, AlON, TaCN, ZrSi, or other suitable materials. The dielectric capping layer 352 protects the metal gates 243 (including metal gates 243a and 243b) from the etching and CMP processes used to etch the S / D contact holes. The dielectric capping layer 352 can be formed by depositing one or more dielectric materials over the recessed metal gates 243 and optionally over the recessed gate spacers 247 and performing a CMP process on the one or more dielectric materials.

[0046] At operation 146, method 100 ( Figure 1C ) performs further fabrication, such as forming S / D contacts, forming S / D contact vias, forming gate vias, and forming interconnect layers. In this regard, Figure 27A shows a top view of a portion of the device 200 after some further fabrication, and Figure 27B , Figure 27C and Figure 27D respectively show cross-sectional views of portions of the device 200 along the Figure 27A B-B line, C-C line, and D-D line in

[0047] Referring to Figure 27B , operation 146 is in the S / D component 260 (such as Figure 27BA silicide component 273 is formed above the S / D component 260 as shown, and an S / D contact (or via) 275 is formed above the silicide component 273. This may involve etching the ILD layer 270 and the CESL 269 to form an S / D contact hole exposing the S / D component 260, forming the silicide component 273 on the exposed surface of the S / D component 260, and forming the S / D contact (or via) 275 above the silicide component 273. The silicide component 273 may be formed by depositing one or more metals into the S / D contact hole, performing an annealing process on the device 200 to cause a reaction between the one or more metals and the S / D component 260 to produce the silicide component 273, and removing the unreacted portions of the one or more metals, leaving the silicide component 273 in the hole. The silicide component 273 may include titanium silicide (TiSi), nickel silicide (NiSi), tungsten silicide (WSi), nickel platinum silicide (NiPtSi), nickel platinum germanium silicide (NiPtGeSi), nickel germanium silicide (NiGeSi), ytterbium silicide (YbSi), platinum silicide (PtSi), iridium silicide (IrSi), erbium silicide (ErSi), cobalt silicide (CoSi), or other suitable compounds. The S / D contact 275 may include a conduction barrier layer and a metal fill layer located above the conduction barrier layer. The conduction barrier layer may include titanium (Ti), tantalum (Ta), tungsten (W), cobalt (Co), ruthenium (Ru), or a conductive nitride, such as titanium nitride (TiN), titanium aluminum nitride (TiAlN), tungsten nitride (WN), tantalum nitride (TaN), or a combination thereof, and may be formed by CVD, PVD, ALD, and / or other suitable processes. The metal fill layer may include tungsten (W), cobalt (Co), molybdenum (Mo), ruthenium (Ru), or other metals, and may be formed by CVD, PVD, ALD, plating, or other suitable processes. In some embodiments, the conduction barrier layer is omitted in the S / D contact 275.

[0048] Reference Figure 27C , operation 146 forms a gate via 359 that is electrically connected to the gate electrode 350. In an embodiment, each of the gate vias 359 may include a conduction barrier layer and a metal fill layer located above the conduction barrier layer. The conduction barrier layer may include titanium (Ti), tantalum (Ta), tungsten (W), cobalt (Co), ruthenium (Ru), or a conductive nitride, such as titanium nitride (TiN), titanium aluminum nitride (TiAlN), tungsten nitride (WN), tantalum nitride (TaN), or a combination thereof, and may be formed by CVD, PVD, ALD, and / or other suitable processes. The metal fill layer may include tungsten (W), cobalt (Co), molybdenum (Mo), ruthenium (Ru), nickel (Ni), copper (Cu), or other metals, and may be formed by CVD, PVD, ALD, plating, or other suitable processes. In some embodiments, the conduction barrier layer is omitted in the gate via 359.

[0049] Reference Figure 27A, when viewed from the top view, the dielectric fin 229-1 has three parts 229-1a, 229-1b, and 229-1c. Parts 229-1a and 229-1c have a width w1. Part 229-1b has a width w2. Due to the trimming process in operation 138 discussed above, the width w2 is less than the width w1. In some embodiments, the width w1 is in the range of about 10 nm to about 20 nm, and the width w2 is in the range of about 5 nm to about 15 nm. In various embodiments, the width w2 is about 0.35 to about 0.8 of the width w1. In some embodiments, the width w2 is about 2 nm to about 12 nm smaller than the width w1. The importance of these differences between w1 and w2 was discussed above with respect to operation 138. Additionally, having the width w1 within the disclosed range (such as from about 10 nm to about 20 nm) helps ensure that the dielectric fin parts 229-1a and 229-1c completely separate the S / D components 260-1 and 260-2 and prevent the accidental merging of the S / D components 260-1 and 260-2 during epitaxial growth, while still leaving enough space to form large S / D components 260 to improve circuit performance. If the dielectric fin parts 229-1a and 229-1c are too wide (such as greater than 20 nm), there may not be enough space to grow the S / D components 260, reducing circuit performance. If the dielectric fin parts 229-1a and 229-1c are too narrow (such as less than 10 nm), the risk of accidental merging of the S / D components 260-1 and 260-2 increases, and the coupling capacitance between adjacent S / D components 260 also undesirably increases. In this embodiment, the core of the dielectric fin 229-1 is a low-k dielectric layer 233, which helps reduce this coupling capacitance. Having the width w2 within the disclosed range (such as from about 5 nm to about 15 nm) helps ensure that the gate trench is wide enough to form a high-quality metal gate 243 (including gate segments 243a and 243b), but the dielectric fin part 229-1b is thick enough to isolate the metal gate segments 243a and 243b. If the dielectric fin part 229-1b is too wide (such as greater than 15 nm), the gate trench will become narrow, and it may be difficult to properly fill the gate trench with the metal gate 243, resulting in transistor non-uniformity and / or long-term reliability issues. If the dielectric fin part 229-1b is too narrow (such as less than 5 nm), the coupling capacitance between adjacent metal gate segments 243a and 243b undesirably increases, and the isolation between adjacent metal gate segments 243a and 243b may be insufficient, resulting in a degradation of the TDDB performance of the device. In some embodiments, the dielectric fin 229-2 also has a similar three-part configuration, where the dielectric fin 229-2 is narrower in the gate region and wider in the S / D region and the gate spacer region. Additionally, the widths of the three parts of the dielectric fin 229-2 can be respectively similar to the widths of the three parts of the dielectric fin 229-1.In such an embodiment, the portion of the dielectric fin 229-2 inside the gate region may have a width in the range of about 5 nm to about 15 nm, and the portion of the dielectric fin 229-2 inside the S / D region and the gate spacer region may have a width in the range of about 10 nm to about 20 nm. In some embodiments, the portion of the dielectric fin 229-2 inside the gate region is completely removed by operation 132.

[0050] Referring Figure 27B , the high-k dielectric cap 234 has a thickness or height h1 in the S / D region (i.e., in the dielectric fin portion 229-1a). Referring Figure 27C and Figure 27D , the high-k dielectric cap 234 has a thickness or height h2 in the gate region (i.e., in the dielectric fin portion 229-1b) and in the gate spacer region. In the present embodiment, due to the S / D trench etching process of operation 120 (see Figure 13 ), the height h1 is less than the height h2. In some embodiments, the height h2 is in the range of about 15 nm to about 35 nm, and the height h1 is at most 30 nm (i.e., from 0 nm to about 30 nm). Keeping the height h2 within the disclosed range helps ensure process margin in the self-aligned metal gate cutting process in operation 142.

[0051] Referring Figure 27B , Figure 27C and Figure 27D , the low-k dielectric fill layer 233 has a thickness or height h3. In some embodiments, the height h3 is in the range of about 45 nm to about 65 nm to ensure that the dielectric fin 229 has sufficient height to isolate the S / D components 260. The low-k dielectric layer 233 helps reduce the coupling capacitance between adjacent S / D components 260-1 and 260-2 and adjacent metal gates 243a and 243b. In various embodiments, as previously discussed, the top surface of the low-k dielectric layer 233 may be flush with the top surface of the topmost channel layer 215, 5 nm higher than the top surface of the topmost channel layer 215, or at most 5 nm lower than the top surface of the topmost channel layer 215.

[0052] Referring Figure 27B and Figure 27D, the dielectric fin portions 229-1a and 229-1c include high-k dielectric liners 232 at the bottom and on the sidewalls of the low-k dielectric fill layer 233. In some embodiments, the thickness w3 of the high-k dielectric liner 232 is in the range of about 1 nm to about 6 nm. If the thickness w3 is too small (such as less than 1 nm), the high-k dielectric liner 232 may not be able to withstand the various etching processes described above during S / D trench etching and inner spacer formation. As a result, the low-k dielectric fill layer 233 may be exposed, which may adversely affect the S / D components 260-1 and 260-2 (for example, elements of the low-k dielectric fill layer 233 may diffuse into the S / D components 260-1 and 260-2). If the thickness w3 is too large (such as greater than 6 nm), the coupling capacitance between the S / D components 260-1 and 260-2 will increase unnecessarily, which may adversely slow down the operating speed of the circuit. Refer to Figure 27C , a high-k gate dielectric layer 349 is disposed on the sidewalls of the low-k dielectric fill layer 233 in the dielectric fin portion 229-1b.

[0053] Figure 27E A top view of a portion of the device 200 according to an alternative embodiment is shown. In this embodiment, due to the trimming process of operation 138, the corners of the dielectric fin portions 229-1a and 229-1c are rounded.

[0054] Figure 28 A cross-sectional view of a portion of the device 200 in the gate region is shown, where the device 200 is fabricated according to another embodiment of the method 100. In this embodiment, the method 100 similarly performs operations 102 to 146 as discussed above. However, the operation 138 (trimming process) does not completely remove the high-k dielectric liner 232 from the sidewalls of the low-k dielectric fill layer 233. As a result, the dielectric fin portion 229-1b includes a low-k dielectric fill layer 233 surrounded by a high-k dielectric liner 232 and a high-k dielectric cap 234. In addition, a high-k gate dielectric layer 349 is disposed above the high-k dielectric liner 232 and the high-k dielectric cap 234.

[0055] Figure 29 A portion of the device 200 fabricated according to yet another embodiment of the method 100 is shown. In this embodiment, the method 100 similarly performs operations 102 to 108. Then, during operation 110, the high-k dielectric liner 232 completely fills the gap between adjacent overclads 231, such as Figure 29 shown. Subsequently, the method 100 skips operations 112, 114, and 116 and proceeds to operation 118. Figure 30A A top view of a portion of the device 200 after the method 100 completes operations 118 to 146 is shown, and Figure 30B and Figure 30C respectively show along Figure 30ACross-sectional views of portions of device 200 along line B-B and line C-C therein. In particular, line B-B cuts through the S / D region of device 200 in the "y" direction, while line C-C cuts through the channel region (or gate region) of device 200 in the "y" direction. In this embodiment, dielectric fin 229 consists only of high-k dielectric liner 232. Other aspects of device 200 in this embodiment (including various dimensions w1, w2, and h1) are the same as those described above with reference to Figures 27A to 27D Notably, the height of dielectric fin 229-1b is the same as the height of high-k dielectric liner 232, which is the sum of h2, h3, and w3 described with reference to Figure 27C and Figure 27D As shown in Figure 30D , in some cases, dielectric fin portions 229-1a and 229-1c in this embodiment may also have rounded corners.

[0056] Figure 31 Shows a portion of device 200 fabricated according to another embodiment of method 100. In this embodiment, method 100 similarly performs operations 102 to 112. Then, method 100 skips operation 114 and proceeds to operation 116. Figure 32A Shows a top view of a portion of device 200 after method 100 completes operations 116 to 146, and Figure 32B and Figure 32C Show cross-sectional views of portions of device 200 along line B-B and line C-C in Figure 32A respectively. In particular, line B-B cuts through the S / D region of device 200 in the "y" direction, and line C-C cuts through the channel region (or gate region) of device 200 in the "y" direction. In this embodiment, dielectric fin 229 consists of high-k dielectric liner 232 and low-k dielectric fill layer 233, and high-k dielectric cap 234 is omitted. Other aspects of device 200 in this embodiment (including various dimensions w1, w2, and h1) are the same as those described above with reference to Figures 27A to 27D Notably, the height of low-k dielectric fill layer 233 is the sum of h2 and h3 described with reference to Figure 27C and Figure 27D As shown in Figure 32D , in some cases, dielectric fin portions 229-1a and 229-1c in this embodiment may also have rounded corners.

[0057] Although not intended to be limiting, embodiments of the present invention provide one or more of the following advantages. For example, embodiments of the present invention form dielectric fins to separate S / D components and to separate metal gates. The dielectric fins are trimmed to be narrower between the metal gates than between the S / D components. This provides more space for the formation of the metal gates, such that the metal gates can be formed more uniformly and with higher quality. At the same time, the dielectric fins provide good isolation between adjacent S / D components to avoid accidental merging of the S / D components. Embodiments of the present invention can be easily integrated into existing semiconductor manufacturing processes.

[0058] In one exemplary aspect, the present invention is directed to a method that includes providing a structure having: two fins extending from a substrate; an isolation structure isolating bottoms of the fins; source / drain (S / D) components located above each fin; a dielectric fin longitudinally parallel to the fins and disposed between the two fins and above the isolation structure; a dummy gate stack located above the isolation structure, the fins, and the dielectric fin; and one or more dielectric layers above sidewalls of the dummy gate stack. The method further includes: removing the dummy gate stack to create gate trenches in the one or more dielectric layers, wherein the dielectric fin is exposed in the gate trenches; trimming the dielectric fin to reduce a width of the dielectric fin; and after trimming, forming a high-k metal gate in the gate trenches.

[0059] In an embodiment, the method further includes back-etching the high-k metal gate to a level below a top surface of the dielectric fin, thereby dividing the high-k metal gate into two segments disposed on two sides of the dielectric fin; and depositing a dielectric cap above the two segments of the high-k metal gate and above the dielectric fin. In another embodiment, the dielectric fin includes a low-k dielectric layer and a high-k dielectric layer located above the low-k dielectric layer, wherein top surfaces of the two segments of the high-k metal gate are located above a top surface of the low-k dielectric layer and below a top surface of the high-k dielectric layer.

[0060] In some embodiments of the method, the dielectric fin includes a low-k dielectric layer and a high-k dielectric layer disposed on sidewalls of the low-k dielectric layer, wherein trimming of the dielectric fin includes completely removing the high-k dielectric layer from sidewalls of the low-k dielectric layer. In another embodiment, trimming of the dielectric fin further includes etching the low-k dielectric layer after completely removing the high-k dielectric layer from sidewalls of the low-k dielectric layer.

[0061] In an embodiment of the method, trimming of the dielectric fin reduces the width of the dielectric fin by about 2 nm to about 12 nm. In another embodiment of the method, the dielectric fin includes a low-k dielectric layer and a high-k dielectric layer disposed on sidewalls of the low-k dielectric layer, wherein trimming of the dielectric fin includes partially removing the high-k dielectric layer from sidewalls of the low-k dielectric layer and maintaining at least a portion of the high-k dielectric layer disposed on the sidewalls of the low-k dielectric layer.

[0062] In one embodiment of the method, the dielectric fin includes one or more high-k dielectric layers extending across the entire width of the dielectric fin. In an embodiment where the dielectric fin is a first dielectric fin and the structure further includes a second dielectric fin adjacent to one of the fins, prior to removing the dummy gate stack, the method further includes partially recessing the dummy gate stack to a level below the top surfaces of the first dielectric fin and the second dielectric fin; forming an etch mask that covers the first dielectric fin and exposes the second dielectric fin; recessing the second dielectric fin; and removing the etch mask.

[0063] In another exemplary aspect, the present invention is directed to a method that includes providing a structure having: fins extending from a substrate; an isolation structure isolating the bottoms of the fins; source / drain (S / D) components located above the fins; dielectric fins longitudinally oriented parallel to the fins, disposed between adjacent fins and located above the isolation structure and isolating the S / D components; a dummy gate stack located above the isolation structure, the fins, and the dielectric fins; and one or more dielectric layers located above the sidewalls of the dummy gate stack. The method further includes partially recessing the dummy gate stack to expose portions of the dielectric fins; forming an etch mask that covers a first dielectric fin among the dielectric fins and exposes a second dielectric fin among the dielectric fins; partially etching the second dielectric fin through the etch mask such that the top surface of the second dielectric fin is below the top surface of the first dielectric fin; removing the etch mask; removing the dummy gate stack to create a gate trench within the one or more dielectric layers, wherein at least the first dielectric fin is exposed within the gate trench; trimming the first dielectric fin to reduce the width of the first dielectric fin; and after trimming, forming a high-k metal gate within the gate trench.

[0064] In an embodiment, the method further includes back-etching the high-k metal gate to a level below the top surface of the first dielectric fin and above the top surface of the second dielectric fin, thereby dividing the high-k metal gate into two segments disposed on both sides of the first dielectric fin; and depositing a dielectric cap above the two segments of the high-k metal gate and the first dielectric fin.

[0065] In an embodiment of the method, each of the first dielectric fin and the second dielectric fin includes a low-k dielectric layer and a high-k dielectric layer located above the low-k dielectric layer, wherein partial etching of the second dielectric fin completely removes the high-k dielectric layer of the second dielectric fin. In another embodiment, each of the first dielectric fin and the second dielectric fin includes a low-k dielectric layer and a high-k dielectric layer located above the low-k dielectric layer, wherein partial etching of the second dielectric fin partially removes the high-k dielectric layer of the second dielectric fin.

[0066] In an embodiment of the method, trimming of the first dielectric fin also reduces the width of the second dielectric fin. In another embodiment, the first dielectric fin includes a low-k dielectric layer and a high-k dielectric layer disposed on sidewalls of the low-k dielectric layer, wherein trimming of the first dielectric fin includes completely removing the high-k dielectric layer from the sidewalls of the low-k dielectric layer. In yet another embodiment, the first dielectric fin includes a low-k dielectric layer and a high-k dielectric layer disposed on sidewalls of the low-k dielectric layer, wherein trimming of the first dielectric fin includes partially removing the high-k dielectric layer from the sidewalls of the low-k dielectric layer and maintaining at least a portion of the high-k dielectric layer disposed on the sidewalls of the low-k dielectric layer.

[0067] In yet another exemplary aspect, the present invention is directed to a semiconductor structure, comprising a substrate; an isolation structure over the substrate; two source / drain (S / D) components over the isolation structure; one or more channel semiconductor layers laterally connecting the two S / D components; a high-k metal gate disposed between the two S / D components and in contact with the one or more channel semiconductor layers; and a dielectric fin disposed on the isolation structure and adjacent to the two S / D components and the high-k metal gate. A top surface of the dielectric fin is above a top surface of the high-k metal gate. A first portion of the dielectric fin adjacent to the high-k metal gate is narrower than a second portion of the dielectric fin adjacent to the two S / D components.

[0068] In an embodiment of the semiconductor structure, the first portion of the dielectric fin is narrower than the second portion of the dielectric fin by about 2 nm to about 12 nm. In another embodiment, each of the first and second portions of the dielectric fin includes a low-k dielectric layer and a high-k dielectric layer disposed on sidewalls of the low-k dielectric layer. In another embodiment, the low-k dielectric layer of the first portion is narrower than the low-k dielectric layer of the second portion.

[0069] The features of several embodiments are outlined above so that those skilled in the art can better understand aspects of the present invention. Those skilled in the art should understand that they can readily use the present invention as a basis to design or modify other processes and structures for implementing the same purposes and / or achieving the same advantages as the embodiments introduced herein. Those skilled in the art should also realize that such equivalent configurations do not depart from the spirit and scope of the present invention, and that various changes, substitutions, and alterations can be made herein without departing from the spirit and scope of the present invention.

Claims

1. A method of forming a semiconductor structure, comprising: providing a structure having: two fins extending from a substrate; an isolation structure isolating bottoms of the fins; source / drain (S / D) components located above each of the fins; a dielectric fin longitudinally oriented parallel to the fins and disposed between the two fins and above the isolation structure; a dummy gate stack located above the isolation structure, the fins, and the dielectric fin; and one or more dielectric layers located above sidewall surfaces of the dummy gate stack; removing the dummy gate stack to create a gate trench in the one or more dielectric layers, wherein the dielectric fin is exposed in the gate trench; trimming the dielectric fin to reduce a width of the dielectric fin; and after the trimming, forming a high-k metal gate in the gate trench.

2. The method according to claim 1, further comprising: etching the high-k metal gate back to a level below a top surface of the dielectric fin, thereby dividing the high-k metal gate into two segments disposed on two sides of the dielectric fin; and depositing a dielectric cap above the two segments of the high-k metal gate and the dielectric fin.

3. The method according to claim 2, wherein, the dielectric fin includes a low-k dielectric layer and a high-k dielectric layer located above the low-k dielectric layer, wherein top surfaces of the two segments of the high-k metal gate are located above a top surface of the low-k dielectric layer and below a top surface of the high-k dielectric layer.

4. The method according to claim 1, wherein, the dielectric fin includes a low-k dielectric layer and a high-k dielectric layer disposed on sidewalls of the low-k dielectric layer, wherein trimming of the dielectric fin includes completely removing the high-k dielectric layer from sidewalls of the low-k dielectric layer.

5. The method according to claim 4, wherein, trimming of the dielectric fin further includes etching the low-k dielectric layer after completely removing the high-k dielectric layer from sidewalls of the low-k dielectric layer.

6. The method according to claim 1, wherein, trimming of the dielectric fin reduces the width of the dielectric fin by 2 nm to 12 nm.

7. The method according to claim 1, wherein, the dielectric fin includes a low-k dielectric layer and a high-k dielectric layer disposed on sidewalls of the low-k dielectric layer, wherein trimming of the dielectric fin includes partially removing the high-k dielectric layer from sidewalls of the low-k dielectric layer and maintaining at least a portion of the high-k dielectric layer disposed on sidewalls of the low-k dielectric layer.

8. The method according to claim 1, wherein, the dielectric fin includes one or more high-k dielectric layers extending across an entire width of the dielectric fin.

9. The method according to claim 1, wherein, the dielectric fin is a first dielectric fin and the structure further includes a second dielectric fin adjacent to one of the fins, and before removing the dummy gate stack, further comprising: partially recessing the dummy gate stack to a level below top surfaces of the first dielectric fin and the second dielectric fin; forming an etch mask covering the first dielectric fin and exposing the second dielectric fin; recessing the second dielectric fin; and removing the etch mask.

10. A method of forming a semiconductor structure, comprising: providing a structure having: fins extending from a substrate; an isolation structure isolating bottoms of the fins; source / drain (S / D) components located above the fins; dielectric fins longitudinally oriented parallel to the fins, disposed between adjacent ones of the fins and above the isolation structure and isolating the source / drain components; a dummy gate stack located above the isolation structure, the fins, and the dielectric fins; and one or more dielectric layers located above sidewall surfaces of the dummy gate stack; partially recessing the dummy gate stack to expose portions of the dielectric fins; forming an etch mask that covers a first dielectric fin of the dielectric fins and exposes a second dielectric fin of the dielectric fins; partially etching the second dielectric fin through the etch mask such that a top surface of the second dielectric fin is below a top surface of the first dielectric fin; removing the etch mask; removing the dummy gate stack to create a gate trench in the one or more dielectric layers, wherein at least the first dielectric fin is exposed in the gate trench; trimming the first dielectric fin to reduce a width of the first dielectric fin; and after the trimming, forming a high-k metal gate in the gate trench.

11. The method of claim 10, further comprising: recessing the high-k metal gate to a level below a top surface of the first dielectric fin and above a top surface of the second dielectric fin, thereby dividing the high-k metal gate into two segments disposed on opposite sides of the first dielectric fin; and depositing a dielectric cap above the two segments of the high-k metal gate and above the first dielectric fin.

12. The method of claim 10, wherein, each of the first dielectric fin and the second dielectric fin includes a low-k dielectric layer and a high-k dielectric layer located above the low-k dielectric layer, wherein partial etching of the second dielectric fin completely removes the high-k dielectric layer of the second dielectric fin.

13. The method of claim 10, wherein, each of the first dielectric fin and the second dielectric fin includes a low-k dielectric layer and a high-k dielectric layer located above the low-k dielectric layer, wherein partial etching of the second dielectric fin partially removes the high-k dielectric layer of the second dielectric fin.

14. The method of claim 10, wherein, trimming of the first dielectric fin also reduces a width of the second dielectric fin.

15. The method of claim 10, wherein, the first dielectric fin includes a low-k dielectric layer and a high-k dielectric layer disposed on sidewalls of the low-k dielectric layer, wherein trimming of the first dielectric fin includes completely removing the high-k dielectric layer from sidewalls of the low-k dielectric layer.

16. The method of claim 10, wherein, The first dielectric fin includes a low-k dielectric layer and a high-k dielectric layer disposed on sidewalls of the low-k dielectric layer. Wherein, trimming of the first dielectric fin includes partially removing the high-k dielectric layer from the sidewalls of the low-k dielectric layer, and maintaining at least a portion of the high-k dielectric layer disposed on the sidewalls of the low-k dielectric layer.

17. A semiconductor structure, comprising: a substrate; an isolation structure located above the substrate; two source / drain (S / D) components located above the isolation structure; one or more channel semiconductor layers laterally connecting the two source / drain components; a high-k metal gate located between the two source / drain components and engaging the one or more channel semiconductor layers; and a dielectric fin located above the isolation structure and adjacent to the two source / drain components and the high-k metal gate, wherein a top surface of the dielectric fin is above a top surface of the high-k metal gate, and a first portion of the dielectric fin adjacent to the high-k metal gate is narrower than a second portion of the dielectric fin adjacent to the two source / drain components.

18. The semiconductor structure according to claim 17, wherein, the first portion of the dielectric fin is narrower than the second portion of the dielectric fin by 2 nm to 12 nm.

19. The semiconductor structure according to claim 17, wherein, each of the first portion and the second portion of the dielectric fin includes a low-k dielectric layer and a high-k dielectric layer disposed on sidewalls of the low-k dielectric layer.

20. The semiconductor structure according to claim 19, wherein, the low-k dielectric layer of the first portion is narrower than the low-k dielectric layer of the second portion.

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