Semiconductor devices

Abstract

The occurrence of short circuit can be suppressed. The wiring unit (70) comprises: a first lead frame (71) which is electrically connected to the conductive pattern (23b3) and has a first wiring portion (71a) which is wired in parallel with the main surface of the ceramic circuit substrate (20b); a second lead frame (72) which is electrically connected to the conductive pattern (23a3) and has a second wiring portion (72a) which is wired in a wiring direction of the first wiring portion (71a) by overlapping with a gap provided on the front surface of the first wiring portion (71a); and a wiring holding portion (73) which includes the first lead frame (71) and the second lead frame (72). The wiring holding portion (73) includes a wiring gap portion which fills the gap in the overlapping region where the first wiring portion (71a) and the second wiring portion (72a) overlap, and a wiring front portion which covers the front surface of the second wiring portion (72a).

Description

Technical Field

[0001] The present invention relates to semiconductor devices. Background Art

[0002] The semiconductor device includes semiconductor elements such as IGBT (Insulated Gate Bipolar Transistor) and power MOSFET (Metal Oxide Semiconductor Field Effect Transistor). Such semiconductor devices are used as power conversion devices, for example.

[0003] The semiconductor device includes a semiconductor element including the above-mentioned semiconductor element. For the semiconductor device, such a semiconductor element is arranged on a conductive pattern. The semiconductor elements of the semiconductor device and the semiconductor elements and the conductive pattern are electrically connected by bonding wires. In addition, one end of the lead frame is electrically connected to the conductive pattern, and the other end of the lead frame is exposed from the cover of the shell to input a control signal from the outside. If such a lead frame is a single body, it is difficult to ensure rigidity and it is difficult to ensure the distance between the terminals. Therefore, a lead frame obtained by integrating a plurality of lead frames by insert molding is used. In addition, the semiconductor element, the bonding wire, and the plurality of lead frames integrated by insert molding are encapsulated by silicone gel or the like.

[0004] Prior art literature

[0005] Patent Literature

[0006] Patent Document 1: Japanese Patent Application Publication No. 2015-198227 Summary of the invention

[0007] Technical issues

[0008] However, in the above-mentioned semiconductor device, sometimes the silicone gel filled in the housing cannot completely encapsulate the semiconductor element, bonding wires, and multiple lead frames integrated by insert molding. In this case, if the encapsulation surface of the silicone gel crosses the multiple integrated lead frames, when a high voltage is applied, the current may flow along the encapsulation surface between the lead frames, causing a short circuit.

[0009] The present invention has been made in view of the above situation, and an object of the present invention is to provide a semiconductor device capable of suppressing the occurrence of a short circuit.

[0010] Technical Solution

[0011] According to one aspect of the present invention, there is provided a semiconductor device comprising: a semiconductor element, a substrate and a wiring unit, wherein the substrate comprises an insulating plate and a first conductive plate and a second conductive plate arranged on the insulating plate, and is provided with the semiconductor element, and the wiring unit comprises: a first lead frame, which is electrically connected to the first conductive plate and comprises a first wiring portion wired parallel to the main surface of the substrate; a second lead frame, which is electrically connected to the second conductive plate and comprises a second wiring portion which is overlapped by a gap set relative to the front side of the first wiring portion and wired along the wiring direction of the first wiring portion; and a wiring holding portion, which comprises the first lead frame and the second lead frame, the wiring holding portion comprising a wiring gap portion which fills the gap in an overlapping area where the first wiring portion overlaps the second wiring portion, and a wiring front portion which covers the overlapping area and side surfaces in the front side of the second wiring portion.

[0012] Effects of the Invention

[0013] According to the disclosed technology, it is possible to suppress the occurrence of short circuits in a semiconductor device used at a high voltage, and to suppress a decrease in the reliability of the semiconductor device.

[0014] The above and other objects, features and advantages of the present invention will become apparent from the accompanying drawings showing preferred embodiments as examples of the present invention and the related description below. BRIEF DESCRIPTION OF THE DRAWINGS

[0015] Figure 1 It is a side cross-sectional view of the semiconductor device according to the first embodiment.

[0016] Figure 2 It is a plan view of a ceramic circuit substrate included in the semiconductor device according to the first embodiment.

[0017] Figure 3 This is a diagram for explaining a wiring unit included in the semiconductor device according to the first embodiment (part 1).

[0018] Figure 4 This is a diagram for explaining the wiring unit included in the semiconductor device according to the first embodiment (second one).

[0019] Figure 5 It is a diagram showing a circuit configuration included in the semiconductor device according to the first embodiment.

[0020] Figure 6 is a side cross-sectional view of a semiconductor device according to a reference example.

[0021] Figure 7 It is a side cross-sectional view of the semiconductor device according to the second embodiment.

[0022] Figure 8It is a diagram for explaining a wiring unit included in the semiconductor device according to the second embodiment.

[0023] Explanation of symbols

[0024] 10, 10a Semiconductor device

[0025] 20a, 20b Ceramic circuit substrate

[0026] 21a, 21b Insulation board

[0027] 22a, 22b Metal plate

[0028] 23a1~23a3,23b1~23b4 Conductive pattern

[0029] 30 heat sink

[0030] 41a~44a,41b~44b Semiconductor element

[0031] 41a1, 42a1, 41b1, 42b1 Control electrode

[0032] 51a~54a,51b~54b,55,56 Bonding wire

[0033] 60 Shell

[0034] 61 cover

[0035] 61a Top Plate

[0036] 61b Side

[0037] 61c protrusion

[0038] 70, 70a wiring unit

[0039] 71 first lead frame

[0040] 71a First wiring portion

[0041] 71b First joint portion

[0042] 71c First terminal portion

[0043] 72 Second lead frame

[0044] 72a Second wiring portion

[0045] 72b Second joint portion

[0046] 72c Second terminal portion

[0047] 73 Wiring holding section

[0048] 73a Wiring clearance section

[0049] 73b Wiring front part

[0050] 73c Terminal clearance section

[0051] 73c1 Front

[0052] 73d Wiring back part

[0053] 73e Joint gap section

[0054] 73e1 Bottom

[0055] 73f concave part

[0056] 74 Third lead frame

[0057] 74a Third wiring portion

[0058] 74b Third joint

[0059] 74c Third terminal portion

[0060] 75 Overlapping Area

[0061] 80 Package Components DETAILED DESCRIPTION

[0062] Hereinafter, the embodiments will be described with reference to the accompanying drawings. Figure 1 Similarly, "upper" refers to the surface of the semiconductor device 10 facing upward. Figure 1 The "back surface" and "lower surface" refer to the direction of the upper side of the semiconductor device 10. Figure 1 Similarly, "lower" refers to the surface of the semiconductor device 10 facing downward. Figure 1 The direction of the lower side of the semiconductor device 10. The same directionality is also meant in other drawings as needed. "Front", "upper surface", "upper", "back", "lower surface", "lower", and "side" are just convenient expressions for determining relative positional relationships and do not limit the technical concept of the present invention. For example, "upper" and "lower" do not necessarily mean the vertical direction relative to the ground. That is, the directions of "upper" and "lower" are not limited to the direction of gravity.

[0063] [First embodiment]

[0064] use Figures 1 to 5 A semiconductor device according to a first embodiment will be described. Figure 1 It is a side cross-sectional view of the semiconductor device according to the first embodiment. Figure 2 It is a plan view of a ceramic circuit substrate included in the semiconductor device according to the first embodiment. Figure 3 and Figure 4It is a diagram for explaining a wiring unit included in the semiconductor device according to the first embodiment. Figure 5 1 is a diagram showing a circuit configuration included in a semiconductor device according to a first embodiment. Figure 1 is with Figure 2 The cross section of the single-point dashed line XX corresponds to the figure. In addition, Figure 3 A side cross-sectional view showing the wiring unit 70, Figure 4 (A) shows a top view of the wiring unit 70, Figure 4 (B) shows a bottom view of the wiring unit 70, Figure 4 (C) means Figure 3 and Figure 4 The cross-sectional view at the dotted line XX of (B). Figure 3 In the present invention, the type of hatching is different for each part in order to explain the parts of the wiring holding part 73 of the wiring unit 70. In fact, all the wiring holding parts 73 are made of the same material.

[0065] like Figure 1 As shown in FIG. 1 , the semiconductor device 10 includes ceramic circuit substrates 20a and 20b and a heat sink 30 on which the ceramic circuit substrates 20a and 20b are provided. Figure 2 As shown in FIG. 1 , semiconductor elements 41a to 44a and 41b to 44b are arranged on ceramic circuit substrates 20a and 20b. Figure 1 The semiconductor elements 42a, 44a, 42b, and 44b are omitted from the illustration. In addition, the semiconductor device 10 includes: a housing portion 60, which is provided at the peripheral portion of the heat sink 30 and surrounds the ceramic circuit substrates 20a and 20b, and is provided on the heat sink 30; and a cover portion 61, which is provided at the upper portion of the opening of the housing portion 60. In addition, external connection terminals for electrical connection with external devices are installed in the housing portion 60 and the cover portion 61. A first lead frame 71, a second lead frame 72, and a third lead frame 74 are installed as external connection terminals for main current. It should be noted that the illustration of the lead frame for control is omitted. One end of the first lead frame 71 is electrically connected to the ceramic circuit substrate 20b, and the first terminal portion 71c of the other end is exposed on the front surface of the cover portion 61. One end of the second lead frame 72 is electrically connected to the ceramic circuit substrate 20a, and the second terminal portion 72c of the other end is exposed on the front surface of the cover portion 61. One end of the third lead frame 74 is electrically connected to the ceramic circuit substrate 20a, and the third terminal portion 74c of the other end is exposed on the front surface of the cover portion 61. The first lead frame 71 and the second lead frame 72 are included in the wiring unit 70 integrally formed in the wiring holding portion 73. In addition, at this time, the first lead frame 71 and the second lead frame 72 are insulated by the wiring holding portion 73. It should be noted that the details of the wiring unit 70 will be described later ( Figure 3Then, the ceramic circuit substrates 20a, 20b (and bonding wires) in the housing 60 are packaged by the packaging component 80. The packaging component 80 is filled into Figure 1 The wiring unit 70 shown in the figure extends to directly below the back surface of the first lead frame 71. That is, a gap (second interface gap) is left between the back surface of the wiring unit 70 and the front surface of the packaging component 80.

[0066] like Figure 1 and Figure 2 As shown, the ceramic circuit substrates 20a and 20b have insulating plates 21a and 21b, metal plates 22a and 22b formed on the back of the insulating plates 21a and 21b, and conductive patterns 23a1 to 23a3 and 23b1 to 23b4 formed on the front of the insulating plates 21a and 21b. It should be noted that the shape and number of the conductive patterns 23a1 to 23a3 and 23b1 to 23b4 are examples. The insulating plates 21a and 21b are made of ceramics with excellent thermal conductivity. The ceramics are, for example, aluminum oxide, aluminum nitride, and silicon nitride. The metal plates 22a and 22b are made of metals with excellent thermal conductivity. The metal is, for example, aluminum, iron, silver, copper, or an alloy containing at least one of these metals. The conductive patterns 23a1 to 23a3 and 23b1 to 23b4 are made of metals such as copper or copper alloys with excellent electrical conductivity. As the ceramic circuit substrates 20a and 20b having such a structure, for example, DCB (Direct Copper Bonding) substrates and AMB (Active Metal Brazed) substrates can be used. The ceramic circuit substrates 20a and 20b can conduct the heat generated by the semiconductor elements 41a to 44a and 41b to the semiconductor elements 41a to 44b through the conductive patterns 23a2 and 23b3, the insulating plates 21a and 21b, and the metal plates 22a and 22b. Figure 1 In addition, the first lead frame 71 (first bonding portion 71b ( Figure 3 )). The second lead frame 72 (second bonding portion 72b ( Figure 3 )). The third lead frame 74 (third bonding portion 74b ( Figure 3 )). It should be noted that the square shown in the conductive pattern 23a2 represents the bonding area of ​​the third lead frame 74, the square shown in the conductive pattern 23a3 represents the bonding area of ​​the second lead frame 72, and the square shown in the conductive pattern 23b3 represents the bonding area of ​​the first lead frame 71.

[0067] The semiconductor elements 41a, 42a, 41b, 42b are switching elements. The switching elements are, for example, IGBTs and power MOSFETs. Such semiconductor elements 41a, 42a, 41b, 42b, for example, have an input electrode (drain electrode or collector electrode) as a main electrode on the back side, and control electrodes (gate electrodes) 41a1, 42a1, 41b1, 42b1 and an output electrode (source electrode or emitter electrode) as a main electrode on the front side. The back side of the above-mentioned semiconductor elements 41a, 42a, 41b, 42b is joined to the conductive patterns 23a2, 23b3 by solder (not shown). The semiconductor elements 43a, 44a, 43b, 44b include diodes. The diodes are, for example, SBDs (Schottky Barrier Diodes) and FWDs (Free Wheeling Diodes). Such semiconductor elements 43a, 44a, 43b, 44b have an output electrode (cathode electrode) as a main electrode on the back side and an input electrode (anode electrode) as a main electrode on the front side. The back side of the semiconductor elements 43a, 44a, 43b, 44b is joined to the conductive patterns 23a2, 23b3 by solder (not shown).

[0068] The following bonding wires 51a to 54a, 51b to 54b, 55, and 56 are arranged for such ceramic circuit substrates 20a and 20b and semiconductor elements 41a to 44a and 41b to 44b. The bonding wires 51a and 52a as control wiring electrically connect the conductive pattern 23a1 to the control electrode 41a1 of the semiconductor element 41a and the control electrode 42a1 of the semiconductor element 42a, respectively. The bonding wire 53a electrically connects the conductive pattern 23a3, the main electrode of the semiconductor element 41a, and the main electrode of the semiconductor element 43a, and the bonding wire 54a electrically connects the conductive pattern 23a3, the main electrode of the semiconductor element 42a, and the main electrode of the semiconductor element 44a. The bonding wires 51b and 52b as control wiring electrically connect the conductive pattern 23b4 to the control electrode 41b1 of the semiconductor element 41b and the control electrode 42b1 of the semiconductor element 42b, respectively. The bonding wire 53b electrically connects the conductive pattern 23b2, the main electrode of the semiconductor element 41b, and the main electrode of the semiconductor element 43b. The bonding wire 54b electrically connects the conductive pattern 23b1, the main electrode of the semiconductor element 42b, and the main electrode of the semiconductor element 44b. Furthermore, the bonding wires 55 and 56 electrically connect the conductive pattern 23a2 of the ceramic circuit substrate 20a to the conductive patterns 23b2 and 23b1 of the ceramic circuit substrate 20b, respectively. It should be noted that the bonding wires 51a to 54a, 51b to 54b, 55, and 56 are made of a material with excellent conductivity. The material is a metal such as aluminum or copper, or an alloy containing at least one of them.

[0069] In such ceramic circuit substrates 20a and 20b, one end of the first lead frame 71 is bonded to the conductive pattern 23b3. The conductive pattern 23b3 is also bonded to the main electrode on the back side of the semiconductor element 41b, 42b, 43b, and 44b. Therefore, the first lead frame 71 is electrically connected to the main electrode of the semiconductor element 41b, 42b, 43b, and 44b, and the main current flows. In addition, one end of the second lead frame 72 is bonded to the conductive pattern 23a3. The conductive pattern 23a3 is electrically connected to the main electrode on the front side of the semiconductor element 41a, 42a, 43a, and 44a through the bonding wires 53a and 54a. Therefore, the second lead frame 72 is electrically connected to the main electrode of the semiconductor element 41a, 42a, 43a, and 44a, and the main current flows.

[0070] like Figure 1 As shown in FIG. 1 , the wiring unit 70 is disposed above the semiconductor elements 41b to 44b provided on the ceramic circuit substrate 20b. In addition, the wiring unit 70 is disposed with a gap (second interface gap) between it and the packaging component 80. Figure 3 As shown in FIG. 1 , such a wiring unit 70 includes a first lead frame 71, a second lead frame 72, and a wiring holding portion 73 that includes and holds the first lead frame 71 and the second lead frame 72. Figure 3 , the configuration position of the wiring unit 70 is indicated by a dotted line. The first lead frame 71 includes a first wiring portion 71a, a first bonding portion 71b, and a first terminal portion 71c. The first wiring portion 71a is wired in parallel with the front surface of the ceramic circuit substrate 20b. The first bonding portion 71b is integrally connected to the side portion of one end of the first wiring portion 71a, extends to the bottom of the semiconductor device 10, and is bonded to the conductive pattern 23b3 by solder. The first bonding portion 71b may extend perpendicularly to the first wiring portion 71a from the side portion of one end of the first wiring portion 71a toward the front surface of the ceramic circuit substrate 20b. In addition, a portion extending parallel to the first wiring portion 71a may be provided at the bonding portion bonded to the conductive pattern 23b3. The first terminal portion 71c is integrally connected to the other end of the first wiring portion 71a, extends to the top of the semiconductor device 10, and is exposed from the cover portion 61. The first terminal portion 71c may extend perpendicularly to the first wiring portion 71a from the side of the other end of the first wiring portion 71a in a direction opposite to the first bonding portion 71b. In addition, the portion extending from the cover portion 61 may include a portion extending parallel to the first wiring portion 71a along the front surface of the cover portion 61.

[0071] The second lead frame 72 includes a second wiring portion 72a, a second bonding portion 72b, and a second terminal portion 72c. The second wiring portion 72a is provided with a gap above the front surface of the first wiring portion 71a and partially overlaps. The second wiring portion 72a may be the same thickness and width as the first wiring portion 71a. Moreover, the second wiring portion 72a is wired along the wiring direction of the first wiring portion 71a. At this time, the second wiring portion 72a is parallel to the wiring direction and shifted by a predetermined length toward the ceramic circuit substrate 20a side. The second bonding portion 72b is integrally connected to one end of the second wiring portion 72a, extends to the bottom of the semiconductor device 10, and is bonded to the conductive pattern 23a3 by solder. The second bonding portion 72b may extend perpendicularly to the second wiring portion 72a from the side of one end of the second wiring portion 72a toward the front surface of the ceramic circuit substrate 20a. At this time, a gap is formed between the second bonding portion 72b and the first bonding portion 71b. In addition, the gap is formed to follow the gap between the first wiring portion 71a and the second wiring portion 72a. The gap between the first bonding portion 71b and the second bonding portion 72b is larger than the gap between the first wiring portion 71a and the second wiring portion 72a. In addition, a portion extending in parallel with the second wiring portion 72a may be provided at the bonding portion bonded to the conductive pattern 23a3. The second terminal portion 72c is integrally connected to the other end of the second wiring portion 72a, extends upward from the semiconductor device 10 and is exposed from the cover portion 61. The second terminal portion 72c may extend perpendicularly to the second wiring portion 72a from the side of the other end of the second wiring portion 72a in the direction opposite to the second bonding portion 72b. At this time, a gap is formed between the second terminal portion 72c and the first terminal portion 71c. In addition, the gap is formed to follow the gap between the first wiring portion 71a and the second wiring portion 72a. The gap between the first terminal portion 71c and the second terminal portion 72c is larger than the gap between the first wiring portion 71a and the second wiring portion 72a. In addition, in the portion extending from the cover portion 61, a portion extending in parallel with the second wiring portion 72a along the front surface of the cover portion 61 may be provided. Portions of the first terminal portion 71 c and the second terminal portion 72 c extending along the front surface of the cover portion 61 may extend in opposite directions such that their ends are separated from each other.

[0072] It should be explained that Figure 3 The shapes of the first bonding portion 71b, the second bonding portion 72b and the first terminal portion 71c, the second terminal portion 72c shown are just an example. The first bonding portion 71b, the second bonding portion 72b can be any shape as long as it can electrically connect the first wiring portion 71a, the second wiring portion 72a to the conductive patterns 23b3, 23a3. In addition, the first terminal portion 71c, the second terminal portion 72c can be any shape as long as it can be exposed from the cover portion 61 and electrically connected to an external device.

[0073] The third lead frame 74 includes a third wiring portion 74a, a third bonding portion 74b, and a third terminal portion 74c. The third wiring portion 74a is wired in parallel with the front surface of the ceramic circuit substrate 20a. The third bonding portion 74b is integrally connected to one end of the third wiring portion 74a and is bonded to the conductive pattern 23a2 by solder. The third terminal portion 74c is integrally connected to the other end of the third wiring portion 74a and extends above the semiconductor device 10 to be exposed from the cover portion 61.

[0074] The first lead frame 71, the second lead frame 72 and the third lead frame 74 are made of materials with excellent electrical conductivity. The material is, for example, aluminum, iron, silver, copper or an alloy comprising at least one of them. In addition, in order to improve corrosion resistance, a plating material can be formed on the surface of the first lead frame 71, the second lead frame 72 and the third lead frame 74 by plating treatment or the like. As specific examples of plating materials, there are nickel, gold, nickel-phosphorus alloy and / or nickel-boron alloy. Moreover, gold can be stacked on the nickel-phosphorus alloy. It should be noted that the bonding between the first lead frame 71, the second lead frame 72 and the third lead frame 74 and the conductive patterns 23b3, 23a3, 23a2 can be based on sintered parts such as silver solder, or directly bonded using ultrasonic waves or lasers, in addition to bonding based on tin solder.

[0075] like Figure 3 As shown in FIG. 1 , the wiring holding portion 73 includes at least a wiring gap portion 73a and a wiring front portion 73b, thereby including the first lead frame 71 and the second lead frame 72. In addition, the wiring holding portion 73 may include a terminal gap portion 73c, a wiring back portion 73d, and a bonding gap portion 73e. Figure 3 , the figure shows a case where these parts are included. In this case, the wiring unit 70 is arranged above the semiconductor elements 41b to 44b, and the wiring back surface portion 73d and the joint gap portion 73e form a gap (second interface gap) relative to the packaging component 80. The wiring gap portion 73a is provided at least in the gap of the overlapping area 75 where the first wiring portion 71a of the first lead frame 71 overlaps with the second wiring portion 72a of the second lead frame 72. It should be noted that in Figure 3 The case where the wiring gap portion 73a reaches a range including the overlapping area 75 is shown in FIG. In addition, the terminal gap portion 73c can be provided continuously from the wiring gap portion 73a and in the lower part of the gap between the first terminal portion 71c and the second terminal portion 72c. In this case, the first terminal portion 71c and the second terminal portion 72c protrude from the front side 73c1 of the terminal gap portion 73c. ​​In addition, the wiring front side portion 73b is provided at least on the outer surface (front side) and side surface of the second wiring portion 72a of the second lead frame 72 in the overlapping area 75 overlapping with the first wiring portion 71a. It should be noted that in Figure 3, the wiring front portion 73b is shown to reach the range including the overlapping area 75. In addition, the wiring front portion 73b may be provided on the outer surface of the lower portion of the second terminal portion 72c and in the overlapping area 75 ( Figure 3 Therefore, the second wiring portion 72a is entirely covered by the wiring gap portion 73a and the wiring front portion 73b in the overlapping region 75 with the first wiring portion 71a ( Figure 4 (C)). It should be noted that the first lead frame 71 and the second lead frame 72 have the gap side as the inner surface and the surface and side surface opposite to the inner surface as the outer surface.

[0076] In addition, when the wiring holding portion 73 has only the wiring gap portion 73a and the wiring front portion 73b, the outer surface of the first lead frame 71 corresponding to the back surface of the wiring unit 70 is exposed. In this case, the back surface of the exposed first wiring portion 71a of the first lead frame 71 forms a gap (first interface gap) with respect to the packaging component 80. Moreover, in this case, the inner surface of the second lead frame 72 that is not the overlapping region 75 with the first lead frame 71 is also exposed. The insulation of the gap between the first wiring portion 71a of the first lead frame 71 and the second wiring portion 72a of the second lead frame 72 can be maintained by the wiring gap portion 73a of the wiring holding portion 73. In addition, the insulation between the outer surface of the first wiring portion 71a of the first lead frame 71 and the outer surface of the second wiring portion 72a of the second lead frame 72 can be maintained by the wiring front portion 73b of the wiring holding portion 73. It should be noted that in the wiring unit 70, the first terminal portion 71c and the second terminal portion 72c are spaced apart from each other in such a manner that the first terminal portion 71c and the second terminal portion 72c are not short-circuited along the front surface 73c1 with respect to the magnitude of the conducted current and voltage. The wiring unit 70 in which the first lead frame 71 and the second lead frame 72 are integrally formed on the wiring holding portion 73 is arranged on the ceramic circuit substrates 20a and 20b (for example, Figure 3 The configuration position of the wiring unit 70 is shown by a dotted line in FIG.

[0077] It should be noted that by forming a gap with respect to the packaging component 80 by the wiring holding portion 73 (the first wiring portion 71a in the case where there is no wiring back side portion 73d), the interface between the semiconductor elements 41a to 44a, 41b to 44b and the packaging component 80 is suppressed from peeling off even if the semiconductor device 10 is thermally deformed. As a result, the reliability of the semiconductor device 10 can be improved. Assuming that the wiring holding portion 73 (the first wiring portion 71a in the case where there is no wiring back side portion 73d) does not form a gap with respect to the packaging component 80, when the semiconductor device 10 is thermally deformed, the packaging component 80 is attracted by the wiring unit 70, and the interface between the semiconductor elements 41a to 44a, 41b to 44b and the packaging component 80 may be peeled off, resulting in a decrease in the reliability of the semiconductor device 10.

[0078] The wiring holding portion 73 having such a structure is made of, for example, a thermoplastic resin, such as polyphenylene sulfide (PPS) resin, polybutylene terephthalate (PBT) resin, polybutylene succinate (PBS) resin, polyamide (PA) resin, or acrylonitrile butadiene styrene copolymer (ABS) resin.

[0079] The heat sink 30 is made of a material with excellent thermal conductivity. The material is, for example, aluminum, iron, silver, copper, magnesium, or an alloy containing at least one of these metals. In addition, in order to improve corrosion resistance, a plated material can be formed on the surface of the heat sink 30 by plating treatment or the like. Specific examples of the plated material include nickel, nickel-phosphorus alloy, and nickel-boron alloy. It should be noted that a cooler (not shown) can also be installed on the back side of the heat sink 30 by tin solder or silver solder to improve heat dissipation. The cooler at this time is made of, for example, a material with excellent thermal conductivity. The material is, for example, aluminum, iron, silver, copper, magnesium, or an alloy containing at least one of these metals. In addition, as a cooler, a radiator composed of fins or multiple fins, and a cooling device based on water cooling, etc. can be applied. In addition, the heat sink 30 can be constructed as a whole with such a cooler. In this case, it is made of a material with excellent thermal conductivity. The material is, for example, aluminum, iron, silver, copper, magnesium, or an alloy containing at least one of these metals. Furthermore, in order to improve corrosion resistance, a plating material may be formed on the surface of the heat sink 30 integrated with the cooler by plating treatment, etc. Specific examples of the plating material include nickel, nickel-phosphorus alloy, and nickel-boron alloy.

[0080] The housing 60 is frame-shaped and is disposed on the outer peripheral upper surface of the heat sink 30, in a box-shaped shape with an upper opening. The cover 61 may have a top plate 61a. The cover 61 may also have a side 61b and be in a box-shaped shape with an lower opening. By disposing the cover 61 on the heat sink 30 and the housing 60, it is in a box-shaped shape that surrounds six directions. The boundary between the housing 60 and the cover 61 may be located at a position that is higher than the packaging component 80 and lower than the first wiring portion 71a. The housing 60 and the cover 61 are made of thermoplastic resin. Such resins include, for example, PPS resin, PBT resin, PBS resin, PA resin, and ABS resin. In addition, the first terminal portion 71c of the first lead frame 71, the second terminal portion 72c of the second lead frame 72, and the third terminal portion 74c of the third lead frame 74 are exposed on the front of the cover 61.

[0081] The packaging component 80 includes a thermosetting resin and a filling material contained in the thermosetting resin. The thermosetting resin is, for example, a maleimide-modified epoxy resin, a maleimide-modified phenolic resin, and a maleimide resin. Moreover, as a specific example thereof, there is an epoxy resin, and a filler containing a filling material in the epoxy resin. The filling material is, for example, silicon oxide, aluminum oxide, boron nitride or aluminum nitride. In addition, as the packaging component 80, silicone gel can be used. In addition, the packaging component 80 is filled in the housing portion 60 to the lower part of the outer surface of the first lead frame 71 (first wiring portion 71a) of the wiring unit 70, thereby packaging the ceramic circuit substrate 20a, 20b and / or the semiconductor elements 41a, 42a, 41b, 42b, and the bonding wires 51a~54a, 51b~54b, 55, 56, etc. At this time, the first lead frame 71 and the second lead frame 72 of the wiring unit 70 are packaged by the wiring holding portion 73 as described above. Therefore, the first lead frame 71 and the second lead frame 72 are kept insulated even though they are not encapsulated by the encapsulation member 80. Therefore, the encapsulation member 80 can be set to a height that can bury the ceramic circuit substrates 20a, 20b and / or the semiconductor elements 41a, 42a, 41b, 42b, and the bonding wires 51a to 54a, 51b to 54b, 55, 56. In addition, in order to fill the encapsulation member 80, the height of the housing 60 needs to be higher than the height of the encapsulation member 80. Therefore, the height of the housing 60 can be a height corresponding to the ceramic circuit substrates 20a, 20b and / or the semiconductor elements 41a, 42a, 41b, 42b, and the bonding wires 51a to 54a, 51b to 54b, 55, 56.

[0082] The semiconductor device 10 ( Figure 2 and Figure 3 ) can be achieved Figure 5The circuit structure shown. Such a circuit structure is an inverter circuit composed of upper and lower arms. In the semiconductor device 10, the collector electrode of the transistor T1 composed of semiconductor elements 41b and 42b and the cathode electrode of the diode D1 composed of semiconductor elements 43b and 44b are connected to the first lead frame 71 via the conductive pattern 23b3 and connected to the first terminal portion 71c. The first terminal portion 71c is the positive input terminal C1. The control electrodes 41b1 and 42b1 of the semiconductor elements 41b and 42b are the gate electrodes G1 of the transistor T1, and are connected to the terminals omitted from the figure via the bonding wires 51b and 52b and the conductive pattern 23b4. The emitter electrode of the transistor T1 and the anode electrode of the diode D1 are electrically connected via the bonding wires 53b and 54b. The emitter electrode of the transistor T1 is also connected to the third lead frame 74 via the bonding wires 53b, 54b, the conductive patterns 23b2, 23b1, the bonding wires 55, 56 and the conductive pattern 23a2, and is connected to the third terminal portion 74c. The third terminal portion 74c is the output terminal C2E1.

[0083] In addition, the collector electrode of the transistor T2 composed of the semiconductor elements 41a and 42a and the cathode electrode of the diode D2 composed of the semiconductor elements 43a and 44a are connected to the third lead frame 74 via the conductive pattern 23a2, and are connected to the third terminal portion 74c. The third terminal portion 74c is the output terminal C2E1 as described above. The control electrodes 41a1 and 42a1 of the semiconductor elements 41a and 42a are the gate electrodes G2 of the transistor T2, and are connected to the terminals omitted from the figure via the bonding wires 51a and 52a and the conductive pattern 23a1. The emitter electrode of the transistor T2 and the anode electrode of the diode D2 are electrically connected via the bonding wires 53a and 54a. The emitter electrode of the transistor T2 is also connected to the second lead frame 72 via the bonding wires 53a and 54a and the conductive pattern 23a3, and is connected to the second terminal portion 72c. The second terminal portion 72c is the negative input terminal E2.

[0084] Here, use Figure 6 A semiconductor device which is a reference example to the semiconductor device 10 will be described. Figure 6 1 is a side cross-sectional view of a semiconductor device of a reference example. Figure 6 In the semiconductor device 100, Figure 1The same reference numerals are given to the same structures of the semiconductor device 10 as those of the semiconductor device 100, and their description is omitted. The wiring unit 70b included in such a semiconductor device 100 includes the first lead frame 71 and the second lead frame 72 through the wiring holding portion 90. The wiring holding portion 90 only integrates the first lead frame 71 and the second lead frame 72 in the middle of the first wiring portion 71a of the first lead frame 71 and the second wiring portion 72a of the second lead frame 72. Therefore, in the semiconductor device 100, in order to maintain the insulation between the first lead frame 71 and the second lead frame 72 of the wiring unit 70b, it is necessary to encapsulate at least the entire first wiring portion 71a and the entire second wiring portion 72a by the encapsulation component 80. Therefore, the height of the housing portion 60a corresponds to at least the height of the first wiring portion 71a and the second wiring portion 72a, and is higher than the height of the housing portion 60 of the semiconductor device 10. In addition, for such a housing portion 60a, the encapsulation component 80 is sufficiently filled in a manner to encapsulate the entire first wiring portion 71a and the second wiring portion 72a. In addition, assuming that the packaging component 80 does not fully package the first wiring portion 71a and the second wiring portion 72a, current flows along the atmosphere between the first wiring portion 71a of the first lead frame 71 and the second wiring portion 72a of the second lead frame 72 and / or the surface of the packaging component 80, causing a short circuit.

[0085] On the other hand, the semiconductor device 10 includes semiconductor elements 41a to 44a, 41b to 44b, ceramic circuit substrates 20a and 20b, and a wiring unit 70. The wiring unit 70 includes a first lead frame 71 electrically connected to the conductive pattern 23b3 and including a first wiring portion 71a wired in parallel with the main surface of the ceramic circuit substrate 20b; a second lead frame 72 electrically connected to the conductive pattern 23a3 and including a second wiring portion 72a wired along the wiring direction of the first wiring portion 71a by overlapping with a gap provided with respect to the front surface of the first wiring portion 71a; and a wiring holding portion 73 including the first lead frame 71 and the second lead frame 72. The wiring holding portion 73 includes a wiring gap portion 73a that fills the gap in the overlapping region 75 where the first wiring portion 71a and the second wiring portion 72a overlap, and a wiring front portion 73b that covers the overlapping region 75 on the front surface and the side surface of the second wiring portion 72a.

[0086] Thus, the insulation between the first lead frame 71 and the second lead frame 72 is maintained. At the same time, the ceramic circuit substrates 20a and 20b and the bonding wires 51a to 54a, 51b to 54b, 55, 56, etc. do not need to be encapsulated by the encapsulation component 80. Therefore, the semiconductor device 10 can reduce the amount of the encapsulation component 80 compared to the semiconductor device 100. Therefore, the semiconductor device 10 can be made lighter. In addition, by reducing the amount of the encapsulation component 80, the influence of the expansion and contraction caused by the heat of the encapsulation component 80 can be suppressed. Therefore, the stress on the bonding wires 51a to 54a, 51b to 54b, 55, 56 caused by the expansion and contraction of the encapsulation component 80 is suppressed, and the peeling of the bonding wires 51a to 54a, 51b to 54b, 55, 56 is suppressed, thereby improving the durability. In addition, since the amount of the encapsulation component 80 can be reduced, the height of the housing 60 can be made lower than that of the semiconductor device 100.

[0087] Therefore, the case portion 60 easily follows the warping of the heat sink 30, and the resistance to cracking of the case portion 60 is improved. As a result, it is possible to suppress a decrease in the reliability of the semiconductor device 10.

[0088] In fact, if the semiconductor device 10 is powered on, the following occurs. In the semiconductor device 10, when the transistor T1 is turned on, current flows from the positive input terminal C1 to the output terminal C2E1 via the transistor T1. That is, in the first lead frame 71, current flows from the first terminal portion 71c to the first wiring portion 71a, and then to the first bonding portion 71b. In addition, when the transistor T2 is turned on, current flows from the output terminal C2E1 to the negative input terminal E2 via the transistor T2. That is, in the second lead frame 72, current flows from the second bonding portion 72b to the second wiring portion 72a, and then to the second terminal portion 72c. Therefore, in the first wiring portion 71a, current flows from the first terminal portion 71c to the first wiring portion 71a, and then to the second terminal portion 72c. Figure 1 The current flows from the right to the left in the paper. In the second wiring portion 72a, the current flows from Figure 1 The flow in the middle of the paper goes from left to right.

[0089] Thus, in the semiconductor device 10, currents in opposite directions flow in the overlapping region 75 where the first wiring portion 71a of the first lead frame 71 and the second wiring portion 72a of the second lead frame 72 overlap. In addition, in the overlapping region 75, a wiring gap portion 73a is arranged in the gap between the first wiring portion 71a and the second wiring portion 72a.

[0090] Therefore, the semiconductor device 10 can ensure the insulation between the first wiring portion 71a and the second wiring portion 72a and can arrange the first wiring portion 71a and the second wiring portion 72a close to each other. Therefore, the inductance can be reduced, and the loss can be reduced.

[0091] [Second Embodiment]

[0092] In a second embodiment, using Figure 7 and Figure 8 A wiring unit different from that in the first embodiment will be described. Figure 7 It is a side cross-sectional view of the semiconductor device according to the second embodiment. Figure 8 1 is a diagram for explaining a wiring unit included in a semiconductor device according to the second embodiment. In the semiconductor device 10a according to the second embodiment, the same reference numerals are used for the same structures as those in the semiconductor device 10, and their descriptions are omitted. Figure 7 correspond Figure 1 In addition, Figure 8 2 is a side view of the wiring unit 70 a .

[0093] like Figure 7 As shown, the semiconductor device 10a also includes: ceramic circuit substrates 20a and 20b; a heat sink 30, on which the ceramic circuit substrates 20a and 20b are provided on the front; and a wiring unit 70a, which is provided on the ceramic circuit substrates 20a and 20b. In addition, the semiconductor device 10a includes: a housing 60, which is provided at the peripheral portion of the heat sink 30, surrounds the ceramic circuit substrates 20a and 20b, and is provided on the heat sink 30; a cover 61, which is provided at the upper portion of the opening of the housing 60; and a packaging component 80, which is filled in the housing 60. It should be noted that a protrusion 61c is formed on the back side (the surface facing the ceramic circuit substrates 20a and 20b) of the cover 61.

[0094] like Figure 7 and Figure 8 As shown, the wiring holding portion 73 of the wiring unit 70a further includes the terminal gap portion 73c, the wiring back portion 73d, and the joint gap portion 73e described in the first embodiment. In addition, a recess 73f is formed on the front surface 73c1 of the terminal gap portion 73c. ​​When the wiring unit 70a is arranged on the ceramic circuit substrate 20a, 20b and covered by the cover portion 61, the protrusion 61c formed on the cover portion 61 enters the recess 73f. Therefore, the protrusion 61c has a shape and size that can enter the recess 73f. In such a wiring unit 70a, the upper side of the second joint portion 72b of the second lead frame 72, the lower side of the second wiring portion 72a and the second terminal portion 72c are covered by the wiring holding portion 73. In addition, the packaging component 80 is filled to the upper side of the bottom surface 73e1 of the joint gap portion 73e of the wiring holding portion 73 of the second joint portion 72b. In the semiconductor device 10a, the wiring holding portion 73 (the first wiring portion 71a when there is no wiring back surface portion 73d) also forms a gap with respect to the packaging component 80. Figure 7 and Figure 8In this case, the lower part of the portion of the joint gap portion 73e covering the second joint portion 72b is encapsulated by the encapsulation component 80. The portion of the joint gap portion 73e covering the second wiring portion 72a forms a gap (a second interface gap) relative to the encapsulation component 80. In addition, such a semiconductor device 10a also includes the same circuit structure as the semiconductor device 10 of the first embodiment.

[0095] For example, in the first embodiment, when the interval between the first terminal portion 71c and the second terminal portion 72c of the wiring unit 70 is sufficiently small, the current may flow along the front surface 73c1 between the first terminal portion 71c and the second terminal portion 72c. Alternatively, even if the interval between the first terminal portion 71c and the second terminal portion 72c of the wiring unit 70 is sufficiently large, the same situation may occur when the current and voltage that cause the first lead frame 71 and the second lead frame 72 to conduct are sufficiently large.

[0096] Therefore, in the wiring unit 70a, a recess 73f is provided on the front surface 73c1 of the terminal gap portion 73c filling the gap between the first terminal portion 71c and the second terminal portion 72c. When such a wiring unit 70a is mounted on the ceramic circuit substrate 20a, 20b and the cover portion 61 is mounted, the protrusion 61c enters the recess 73f. As a result, the creepage distance between the first terminal portion 71c and the second terminal portion 72c can be obtained, and the insulation between the first lead frame 71 and the second lead frame 72 can be maintained when the interval between the first terminal portion 71c and the second terminal portion 72c is small and the current and voltage for conducting the first lead frame 71 and the second lead frame 72 are large enough. In addition, by the wiring back surface portion 73d and the joint gap portion 73e of the wiring unit 70a, the insulation between the first lead frame 71 and the second lead frame 72 can be maintained even when the current and voltage for conducting the first lead frame 71 and the second lead frame 72 are large enough. In addition, the upper side of the second joint portion 72b of the second lead frame 72 and the lower side of the second wiring portion 72a and the second terminal portion 72c are covered by the wiring holding portion 73. On this basis, the packaging component 80 is filled to the upper side of the bottom surface 73e1 of the joint gap portion 73e of the wiring holding portion 73 of the second joint portion 72b. Thus, even if the current and voltage for conducting the first lead frame 71 and the second lead frame 72 are sufficiently large, the insulation of the first lead frame 71 and the second lead frame 72 can be maintained.

[0097] Therefore, the semiconductor device 10a can reliably maintain insulation even when a larger current and voltage than the semiconductor device 10 are applied. Moreover, the semiconductor device 10a can also reduce the amount of the packaging component 80 compared to the semiconductor device 100. Therefore, the semiconductor device 10a can be made lighter. In addition, by reducing the amount of the packaging component 80, the influence of the expansion and contraction caused by the heat of the packaging component 80 can be suppressed. Therefore, the stress on the bonding wires 51a to 54a, 51b to 54b, 55, and 56 caused by the expansion and contraction of the packaging component 80 is suppressed, and the peeling of the bonding wires 51a to 54a, 51b to 54b, 55, and 56 is suppressed, thereby improving durability. Moreover, since the amount of the packaging component 80 can be reduced, the height of the housing 60 can be made lower than that of the semiconductor device 100. Therefore, it is easy to follow the warping of the heat sink 30, and the tolerance to the cracking of the housing 60 is improved. As a result, the reduction in the reliability of the semiconductor device 10a can be suppressed.

[0098] It should be noted that, in the semiconductor device 10a, since it also includes the same circuit structure as the semiconductor device 10, in the first wiring portion 71a, the current flows from Figure 7 The current flows from the right to the left in the paper. In the second wiring portion 72a, the current flows from Figure 7 The current flows from the left to the right in the middle of the paper. In this way, in the semiconductor device 10a, the current in the opposite direction also flows in the overlapping region 75 where the first wiring portion 71a of the first lead frame 71 overlaps the second wiring portion 72a of the second lead frame 72. Moreover, in the overlapping region 75, a wiring gap portion 73a is arranged in the gap between the first wiring portion 71a and the second wiring portion 72a. Therefore, the semiconductor device 10a can ensure that the first wiring portion 71a and the second wiring portion 72a are insulated, and the first wiring portion 71a and the second wiring portion 72a can be arranged close to each other. Therefore, the inductance can be reduced, and the loss can be reduced.

[0099] The above only illustrates the principle of the present invention. For those skilled in the art, a large number of modifications and changes can be further made. The present invention is not limited to the accurate configuration and application examples shown and described above, and all corresponding modifications and equivalents are regarded as the scope of the present invention defined by the attached claims and their equivalents.

Claims

1. A semiconductor device, characterized in that: A semiconductor element, a first insulating plate, a first conductive plate provided on the first insulating plate and provided with the semiconductor element, a second insulating plate, a second conductive plate provided on the second insulating plate, a wiring unit, and a packaging component packaging the first insulating plate, the first conductive plate, the second insulating plate, the second conductive plate, and the semiconductor element, The wiring unit comprises: A first lead frame electrically connected to the first conductive plate, wired in parallel with the main surfaces of the first insulating plate and the second insulating plate, and having a first wiring portion; A second lead frame electrically connected to the second conductive plate and having a second wiring portion which overlaps the front surface of the first wiring portion with a gap and is wired along a wiring direction of the first wiring portion; as well as a wiring holding portion including the first lead frame and the second lead frame, By arranging the packaging component over the entire region where the semiconductor element and the first lead frame overlap in a plan view, the first lead frame is spaced upward from the semiconductor element. The wiring holding portion includes a wiring gap portion that fills the gap in an overlapping region where the first wiring portion and the second wiring portion overlap, and a wiring front portion that covers the overlapping region in the front surface and side surfaces of the second wiring portion.

2. The semiconductor device according to claim 1, wherein: A housing is provided which surrounds the first insulating plate, the first conductive plate, the second insulating plate, and the second conductive plate. The sealing member is filled in the housing to a position directly below the back surface of the first wiring portion to seal the first insulating plate, the first conductive plate, the second insulating plate, the second conductive plate, and the semiconductor element.

3. The semiconductor device according to claim 2, wherein: A first interface gap is formed as a gap between the rear surface of the first wiring portion and the front surface of the packaging component.

4. The semiconductor device according to claim 2 or 3, characterized in that The first lead frame comprises: a first bonding portion electrically bonded to the first conductive plate and connected to one end of the first wiring portion; and The first terminal portion is connected to the other end of the first wiring portion and extends to the opposite side to the first insulating plate, the first conductive plate, the second insulating plate, and the second conductive plate.

5. The semiconductor device according to claim 4, wherein: The second lead frame comprises: a second bonding portion electrically bonded to the second conductive plate and connected to one end of the second wiring portion; and The second terminal portion is connected to the other end of the second wiring portion and extends to the opposite side to the first insulating plate, the first conductive plate, the second insulating plate, and the second conductive plate.

6. The semiconductor device according to claim 5, wherein: The semiconductor device further includes a cover portion provided on the housing and exposing the first terminal portion and the second terminal portion.

7. The semiconductor device according to claim 6, wherein: A boundary between the cover and the case is located above an upper surface of the packaging component and below the first wiring portion.

8. The semiconductor device according to claim 6 or 7, characterized in that: The wiring holding portion further includes a terminal gap portion that fills a gap between the first terminal portion and the second terminal portion at a lower portion of the cover portion and is continuous with the wiring gap portion.

9. The semiconductor device according to claim 4, wherein: The wiring holding portion further includes a wiring back surface portion that covers the back surface and side surfaces of the first wiring portion and the outer surface of the first terminal portion.

10. The semiconductor device according to claim 9, wherein: A second interface gap is formed as a gap between the rear surface of the wiring rear surface portion and the front surface of the package component.

11. The semiconductor device according to claim 7, wherein: The wiring holding portion further includes a joint gap portion including a portion of the second wiring portion that does not overlap with the first wiring portion and the second joint portion, and the joint gap portion is continuous with the wiring gap portion.

12. The semiconductor device according to claim 8, wherein: A recess is formed on the front side of the terminal gap portion. A protrusion that enters the recess is formed on the back surface of the cover.

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