Method for manufacturing a semiconductor device

Abstract

A method for manufacturing a semiconductor device includes forming a first fin over a substrate. The method includes forming a dummy gate stack on the first fin. The method includes forming a first gate spacer along sides of the dummy gate stack. The first gate spacer includes a first dielectric material. The method includes forming a second gate spacer along sides of the first gate spacer. The second gate spacer includes a semiconductor material. The method includes forming a source / drain region in the first fin adjacent to the second gate spacer. The method includes removing at least a portion of the second gate spacer to form a void extending between the first gate spacer and the source / drain region.

Description

Technical Field

[0001] This disclosure generally relates to semiconductor devices and methods for manufacturing semiconductor devices, and more specifically to methods for manufacturing nonplanar transistors. Background Technology

[0002] Semiconductor devices are used in a variety of electronic applications such as personal computers, mobile phones, digital cameras, and other electronic devices. Semiconductor devices are typically manufactured by sequentially depositing an insulating or dielectric layer, a conductive layer, and a semiconductor material layer on a semiconductor substrate, and then using photolithography to pattern the individual material layers to form circuit components and elements on each material layer.

[0003] The semiconductor industry continuously improves the integration density of individual electrical components (e.g., transistors, diodes, resistors, capacitors, etc.) by constantly reducing the size of the smallest component, which allows more components to be integrated into a given area. However, as the size of the smallest component decreases, other problems arise that need to be addressed. Summary of the Invention

[0004] Some embodiments of this application provide a method for manufacturing a semiconductor device, comprising: forming a first fin over a substrate; forming a dummy gate stack on the first fin; forming a first gate spacer along a side of the dummy gate stack, the first gate spacer comprising a first dielectric material; forming a second gate spacer along a side of the first gate spacer, the second gate spacer comprising a semiconductor material; forming a source / drain region in the first fin adjacent to the second gate spacer; and removing at least a portion of the second gate spacer to form a gap extending between the first gate spacer and the source / drain region.

[0005] Other embodiments of this application provide a method for manufacturing a semiconductor device, comprising: forming a first fin and a second fin above a substrate, the first fin and the second fin being adjacent to each other; forming a dummy gate stack on the first fin and the second fin; forming a first gate spacer along a side of the dummy gate stack, the first gate spacer comprising a first dielectric material; forming a second gate spacer along a side of the first gate spacer, the second gate spacer comprising a semiconductor material; forming a source / drain region in both the first fin and the second fin adjacent to the second gate spacer, the source / drain region comprising a merged portion between the first fin and the second fin; and removing at least a portion of the second gate spacer to form a gap extending between the first gate spacer and the source / drain region.

[0006] Further embodiments of this application provide a method for manufacturing a semiconductor device, comprising: forming a fin over a substrate; forming a dummy gate stack over the fin; forming a gate spacer along a side of the dummy gate stack, the gate spacer comprising a first layer formed of a dielectric material and a second layer formed of a semiconductor material; forming a source / drain region in the fin adjacent to the gate spacer; replacing the dummy gate stack with an active gate stack; and removing at least a portion of the second layer of the gate spacer to form a gap extending between the active gate stack and the source / drain region. Attached Figure Description

[0007] The various aspects of the invention will be best understood from the following detailed description when read in conjunction with the accompanying drawings. It should be noted that, in accordance with standard industrial practice, the components are not drawn to scale. In fact, for clarity of discussion, the dimensions of the components may be arbitrarily increased or decreased.

[0008] Figure 1 A perspective view of a FinFET (Fin Field-Effect Transistor) according to some embodiments is shown.

[0009] Figure 2 , Figure 3 , Figure 4 , Figure 5 , Figure 6 , Figure 7A , Figure 7B , Figure 7C , Figure 7D , Figure 7E , Figure 8A , Figure 8B , Figure 8C , Figure 8D , Figure 8E , Figure 9A , Figure 9B , Figure 9C , Figure 9D , Figure 9E , Figure 10A , Figure 10B , Figure 10C , Figure 10D , Figure 10E , Figure 11A , Figure 11B , Figure 11C , Figure 11D , Figure 11E , Figure 12A , Figure 12B , Figure 12C , Figure 12D , Figure 12E , Figure 12F , Figure 13A , Figure 13B , Figure 13C , Figure 13D , Figure 13E , Figure 14A , Figure 14B , Figure 14C , Figure 14D , Figure 14E , Figure 15A , Figure 15B , Figure 15C , Figure 15D and Figure 15E The following are illustrated during various manufacturing stages according to some embodiments. Figure 1 A cross-sectional view of an exemplary FinFET.

[0010] Figure 16 A flowchart of an exemplary method for manufacturing a nonplanar transistor device according to some embodiments is shown. Detailed Implementation

[0011] The following disclosure provides numerous different embodiments or instances for implementing various features of the provided subject matter. Specific examples of components and arrangements are described below to simplify the invention. Of course, these are merely examples and are not intended to limit the invention. For example, in the following description, forming a first component on or over a second component can include embodiments where the first and second components are in direct contact, and can also include embodiments where an additional component can be formed between the first and second components, such that the first and second components are not in direct contact. Furthermore, reference numerals and / or characters may be repeated in various embodiments. This repetition is for simplicity and clarity and does not in itself indicate a relationship between the various embodiments and / or configurations discussed.

[0012] Furthermore, for ease of description, spatial relative terms such as "below," "under," "lower," "above," and "upper" may be used to describe the relationship between one element or component and another (or other) element or component as shown in the figure. In addition to the orientation shown in the figure, spatial relative terms are intended to include different orientations of the device during use or operation. The device may be oriented in other ways (rotated 90 degrees or in other orientations), and the spatial relative descriptors used herein can be interpreted accordingly.

[0013] According to some embodiments, a plurality of gate spacers for a FinFET are formed, and one of the gate spacers is removed to define a gap in the resulting FinFET. The gap occupies at least a portion of the region previously occupied by the removed gate spacer and remains in the final FinFET device. The gap may be filled with air or may be in a vacuum, thereby allowing the region between the gate electrode and the source / drain region of the FinFET to have a lower relative permittivity. The capacitance between the gate electrode and the source / drain contacts of the FinFET can therefore be reduced, thereby reducing current leakage in the FinFET.

[0014] Figure 1 A simplified example of a FinFET 100 according to various embodiments is shown in a perspective view. For clarity, some other components of the FinFET (discussed below) are omitted. The FinFET shown can be electrically connected or coupled in a manner that allows it to operate, for example, as one transistor or multiple transistors (such as two transistors).

[0015] The FinFET 100 includes fins 52 extending from a substrate 50. Isolation regions 56 are disposed above the substrate 50, and fins 52 project over and between adjacent isolation regions 56. Although isolation regions 56 are described / shown as separate from the substrate 50, as used herein, the term "substrate" may be used to refer only to a semiconductor substrate or a semiconductor substrate including the isolation regions. Additionally, although fins 52 are shown as a single continuous material of the substrate 50, fins 52 and / or the substrate 50 may comprise a single material or multiple materials. In this document, fin 52 refers to the portion extending between adjacent isolation regions 56.

[0016] A gate dielectric 106 runs along the sidewall of fin 52 and is located above the top surface of fin 52, and a gate electrode 108 is located above the gate dielectric 106. Source / drain regions 92 are disposed on the opposite sides of fin 52 relative to the gate dielectric 106 and gate electrode 108. A gate spacer 86 separates the source / drain regions 92 from the gate dielectric 106 and gate electrode 108. In embodiments forming multiple transistors, the source / drain regions 92 may be shared among the individual transistors. In embodiments where one transistor is formed by multiple fins 52, adjacent source / drain regions 92 may be electrically connected, such as by agglomerating the source / drain regions 92 through epitaxial growth or by coupling the source / drain regions 92 to the same source / drain contacts.

[0017] Figure 1Several reference cross sections are further shown. For example, cross section AA is the portion of the isolation region 56 below the adjacent source / drain region 92; cross section BB is parallel to cross section AA and along the longitudinal axis of fin 52; cross section CC is parallel to cross section AA and along the portion of the isolation region 56 between the coalesced source / drain regions 92; cross section DD is perpendicular to cross section AA and along the longitudinal axis of gate electrode 108; and cross section EE is perpendicular to cross section AA and spans the adjacent source / drain region 92. For clarity, the following figures refer to these reference cross sections.

[0018] Some of the embodiments discussed herein are discussed in the context of FinFETs formed using a post-gate process. In other embodiments, a gate-before process may be used. Moreover, some embodiments contemplate various aspects used in planar devices such as planar FETs and / or other non-planar devices such as gate-all-around (GAA) transistors.

[0019] Figure 2 , Figure 3 , Figure 4 , Figure 5 and Figure 6 A perspective view of an intermediate stage in the manufacture of an exemplary FinFET 100, according to some embodiments, is shown.

[0020] exist Figure 2 A substrate 50 is provided. The substrate 50 can be a semiconductor substrate, such as a bulk semiconductor, a semiconductor-on-insulator (SOI) substrate, etc., which can be doped (e.g., doped with p-type or n-type dopants) or undoped. The substrate 50 can be a wafer, such as a silicon wafer. Typically, an SOI substrate is a layer of semiconductor material formed on an insulating layer. The insulating layer can be, for example, a buried oxide (BOX) layer, a silicon oxide layer, etc. The insulating layer is disposed on a substrate that is typically a silicon or glass substrate. Other substrates, such as multilayer or gradient substrates, can also be used. In some embodiments, the semiconductor material of the substrate 50 can include silicon; germanium; compound semiconductors, including silicon carbide, gallium arsenide, gallium phosphide, indium phosphide, indium arsenide, and / or indium antimonide; alloy semiconductors, including SiGe, GaAsP, AlInAs, AlGaAs, GaInAs, GaInP, and / or GaInAsP; or combinations thereof.

[0021] Substrate 50 has region 50N and region 50P. Region 50N can be used to form n-type devices, such as NMOS transistors, for example, n-type FinFETs. Region 50P can be used to form p-type devices, such as PMOS transistors, for example, p-type FinFETs. Region 50N can be physically separated from region 50P, and any number of device components (e.g., other active devices, doped regions, isolation structures, etc.) can be placed between region 50N and region 50P.

[0022] exist Figure 3 In this embodiment, fins 52 are formed in the substrate 50. Fins 52 are semiconductor strips. In some embodiments, fins 52 can be formed in the substrate 50 by etching trenches in the substrate 50. The etching can be any acceptable etching process, such as reactive ion etching (RIE), neutral beam etching (NBE), or a combination thereof. The etching can be anisotropic.

[0023] The fin 52 can be patterned using any suitable method. For example, the fin 52 can be patterned using one or more photolithography processes, including dual patterning or multiple patterning processes. Typically, dual or multiple patterning processes combine photolithography and self-alignment processes, thereby allowing the creation of patterns with, for example, a pitch smaller than that achievable using a single direct photolithography process. For example, in one embodiment, a sacrificial layer is formed over a substrate and patterned using a photolithography process. Spacers are formed next to the patterned sacrificial layer using a self-alignment process. The sacrificial layer is then removed, and the remaining spacers can then be used to pattern the fin.

[0024] exist Figure 4In this configuration, an isolation region 56 (sometimes referred to as shallow trench isolation (STI) 56) is formed above the substrate 50 and between adjacent fins 52. As an example of forming the STI region 56, an insulating material is formed over the intermediate structure. The insulating material can be an oxide such as silicon oxide, a nitride, or a combination thereof, and can be formed by high-density plasma chemical vapor deposition (HDP-CVD), flowable chemical vapor deposition (FCVD) (e.g., chemical vapor deposition (CVD) based material deposition in a remote plasma system followed by post-curing to transform it into another material, such as an oxide), or combinations thereof. Other insulating materials formed by any acceptable method can be used. In the illustrated embodiment, the insulating material is silicon oxide formed by an FCVD process. Once the insulating material is formed, an annealing process can be performed. In the embodiment, the insulating material is formed such that an excess of insulating material covers the fins 52. Some embodiments may utilize multiple layers. For example, in some embodiments, a pad (not shown) may first be formed along the surfaces of the substrate 50 and the fins 52. Subsequently, a filler material such as the filler material described above may be formed over the pad. An insulation removal process is applied to remove excess insulation material above fin 52. In some embodiments, a planarization process, such as chemical mechanical polishing (CMP), etching back, or a combination thereof, may be used. The planarization process exposes fin 52 so that the top surface of fin 52 and insulation material is flush after the planarization process is completed. The insulation material is then recessed, with the remaining portion forming STI region 56. The insulation material is recessed such that the upper portion of fin 52 in regions 50N and 50P protrudes between adjacent STI regions 56. The top surface of STI region 56 may have a flat surface, a convex surface, a concave surface (such as a recess), or a combination thereof, as shown. The top surface of STI region 56 may be formed as flat, convex, and / or concave by appropriate etching. STI region 56 may be recessed using an acceptable etching process, such as an etching process selective for the material of the insulation material (e.g., etching the material of the insulation material at a faster rate than the material of fin 52). For example, a chemical oxide can be removed using, for example, diluted hydrofluoric acid (dHF) by an appropriate etching process.

[0025] The above process is merely one example of how fin 52 can be formed. In some embodiments, the fin can be formed by an epitaxial growth process. For example, a dielectric layer can be formed over the top surface of substrate 50, and trenches can be etched through the dielectric layer to expose the underlying substrate 50. Homoethelic epitaxial structures can be epitaxially grown in the trenches, and the dielectric layer can be recessed such that the homoethelic epitaxial structure protrudes from the dielectric layer to form the fin. Alternatively, in some embodiments, heteroethelic epitaxial structures can be used for fin 52. For example, after the insulating material of STI region 56 is planarized with fin 52, fin 52 can be recessed, and a material different from fin 52 can be epitaxially grown over the recessed fin 52. In such embodiments, fin 52 includes the recessed material and the epitaxially grown material disposed over the recessed material. In a further embodiment, a dielectric layer can be formed over the top surface of substrate 50, and trenches can be etched through the dielectric layer. A heteroethelic epitaxial structure can then be epitaxially grown in the trenches using a material different from substrate 50, and the dielectric layer can be recessed such that the heteroethelic epitaxial structure protrudes from the dielectric layer to form the fin 52. In some embodiments where the homoepitaxial or heteroepitaxial structure is epitaxially grown, the epitaxial growth material can be doped in situ during growth, which can avoid prior and subsequent implantation, but in situ and implantation doping can be used together.

[0026] Furthermore, it may be advantageous to epitaxially grow a material different from that in region 50P (e.g., the PMOS region) in region 50N (e.g., the NMOS region). In various embodiments, the upper portion of fin 52 may be made of silicon-germanium (Si). x Ge 1-x (where x can be in the range of 0 to 1), silicon carbide, pure or substantially pure germanium, III-V compound semiconductors, II-VI compound semiconductors, etc. For example, materials that can be used to form III-V compound semiconductors include, but are not limited to, InAs, AlAs, GaAs, InP, GaN, InGaAs, InAlAs, GaSb, AlSb, AlP, GaP, etc.

[0027] Furthermore, suitable wells (not shown) may be formed in fin 52 and / or substrate 50. In some embodiments, a P-well may be formed in region 50N and an N-well may be formed in region 50P. In some embodiments, either a P-well or an N-well may be formed in both region 50N and region 50P.

[0028] In embodiments with different well types, photoresist or other masks (not shown) can be used to implement different implantation steps for regions 50N and 50P. For example, photoresist can be formed over fin 52 and STI region 56 in region 50N. The photoresist is patterned to expose region 50P of substrate 50, such as a PMOS region. The photoresist can be formed using spin coating techniques, and the photoresist can be patterned using acceptable photolithography techniques. Once the photoresist is patterned, n-type impurity implantation is performed in region 50P, and the photoresist can be used as a mask to substantially prevent n-type impurities from being implanted into region 50N, such as an NMOS region. The n-type impurity can be phosphorus, arsenic, antimony, etc., implanted into the region, with a concentration equal to or less than 10. 18 cm -3 Such as in about 10 17 cm -3 Peace Treaty 10 18 cm -3 Between. After implantation, the photoresist is removed, for example, through an acceptable ashing process.

[0029] Following implantation in region 50P, photoresist is formed over fin 52 and STI region 56 in region 50P. The photoresist is patterned to expose region 50N of substrate 50, such as an NMOS region. The photoresist can be formed using spin coating, and patterned using acceptable photolithography techniques. Once the photoresist is patterned, p-type impurity implantation can be performed in region 50N, and the photoresist can be used as a mask to substantially prevent p-type impurities from being implanted into region 50P, such as a PMOS region. The p-type impurities can be boron, BF2, indium, etc., implanted into the region, with a concentration equal to or less than 10. 18 cm -3 Such as in about 10 17 cm -3 To about 10 18 cm -3 Between. After implantation, the photoresist can be removed, for example, by an acceptable ashing process.

[0030] After implantation into regions 50N and 50P, annealing can be performed to activate the implanted p-type and / or n-type impurities. In some embodiments, the growth material of the epitaxial fins can be doped in situ during growth, which can avoid implantation, but in-situ and implantation doping can be used together.

[0031] exist Figure 5In this process, a dummy dielectric layer 60 is formed on fin 52. The dummy dielectric layer 60 can be, for example, silicon oxide, silicon nitride, or combinations thereof, and can be deposited or thermally grown according to acceptable techniques. A dummy gate layer 62 is formed above the dummy dielectric layer 60, and a mask layer 64 is formed above the dummy gate layer 62. The dummy gate layer 62 can be deposited above the dummy dielectric layer 60 and then planarized, for example, by CMP. The mask layer 64 can be deposited above the dummy gate layer 62. The dummy gate layer 62 can be a conductive material and can be selected from the group consisting of amorphous silicon, polysilicon, poly-SiGe, metal nitrides, metal silicides, metal oxides, and metals. The dummy gate layer 62 can be deposited by physical vapor deposition (PVD), CVD, sputtering deposition, or other techniques known in the art and used for depositing conductive materials. The dummy gate layer 62 can be made of other materials that have high etch selectivity for etching the isolation region. The mask layer 64 can include, for example, SiN, SiON, etc. In this example, a single dummy gate layer 62 and a single mask layer 64 are formed across regions 50N and 50P. It should be noted that, for illustrative purposes only, the dummy dielectric layer 60 shown only covers fin 52. In some embodiments, the dummy dielectric layer 60 may be deposited such that it covers an STI region 56 that extends between the dummy gate layer 62 and the STI region 56.

[0032] exist Figure 6 In this process, an acceptable photolithography and etching technique is used to pattern the mask layer 64 to form a mask 74. The pattern of the mask 74 is then transferred to the dummy gate layer 62 using an acceptable etching technique to form a dummy gate 72. The pattern of the mask 74 is further transferred to the dummy gate dielectric layer 60 to form a dummy gate dielectric 70. The dummy gate 72 covers the corresponding channel region of the fin 52. The dummy gate dielectric 70 and the dummy gate 72 may sometimes be collectively referred to as a “dummy gate stack.” The pattern of the mask 74 can be used to physically separate each dummy gate 72 from adjacent dummy gates. The dummy gate 72 may also have a longitudinal orientation substantially perpendicular to the longitudinal direction of the corresponding epitaxial fin 52.

[0033] Figures 7A to 15E This is a cross-sectional view of other intermediate stages in the manufacture of FinFET 10 according to some embodiments. Figures 7A to 15E Components in either region 50N or region 50P are shown. For example, the structure shown can be applied to both region 50N and region 50P. Structural differences between region 50N and region 50P (if any) are described in the accompanying text to each figure. Brief summary... Figure 7A , Figure 8A , Figure 9A , Figure 10A , Figure 11A , Figure 12A , Figure 13A , Figure 14A and Figure 15A Shown as along Figure 1 The reference section AA is shown. Figure 7B , Figure 8B , Figure 9B , Figure 10B , Figure 11B , Figure 12B , Figure 13B , Figure 14B and Figure 15B Shown as along Figure 1 The reference section BB is shown. Figure 7C , Figure 8C , Figure 9C , Figure 10C , Figure 11C , Figure 12C , Figure 13C , Figure 14C and Figure 15C Shown as along Figure 1 The reference section CC is shown. Figure 7D , Figure 8D , Figure 9D , Figure 10D , Figure 11D , Figure 12D , Figure 13D , Figure 14D and Figure 15D Shown as along Figure 1 The reference section DD is shown; and Figure 7E , Figure 8E , Figure 9E , Figure 10E , Figure 11E , Figure 12E , Figure 13E , Figure 14E and Figure 15E Shown as along Figure 1 The reference section EE is shown.

[0034] exist Figures 7A to 7E In this process, a first gate spacer layer 80 is formed on the exposed surfaces of the mask 74, the dummy gate 72, the dummy gate dielectric 70, the STI region 56, and / or the fin 52. The first gate spacer layer 80 is formed of a dielectric material such as silicon nitride, silicon carbonitride, silicon carbonitride, silicon carbonoxide, silicon, metal oxide, or combinations thereof, and can be formed by a conformal deposition process such as CVD, PECVD, etc.

[0035] After forming the first gate spacer layer 80, implantation is performed for the lightly doped source / drain (LDD) region 82. In embodiments with different device types, a mask, such as photoresist, can be formed over region 50N while exposing region 50P, and an impurity of an appropriate type (e.g., p-type) can be implanted into the exposed fins 52 in region 50P. The mask can then be removed. Subsequently, a mask, such as photoresist, can be formed over region 50P while exposing region 50N, and an impurity of an appropriate type (e.g., n-type) can be implanted into the exposed fins 52 in region 50N. The mask can then be removed. The n-type impurity can be any n-type impurity discussed previously, and the p-type impurity can be any p-type impurity discussed previously. The lightly doped source / drain region can have approximately 10 15 cm -3 To about 10 16 cm -3 The concentration of impurities. Annealing can be used to activate the injected impurities.

[0036] After forming the LDD region 82, a second gate spacer layer 84 is formed on the first gate spacer layer 80. The second gate spacer layer 84 is made of a material such as Si. 1-x Ge x A semiconductor material is formed, comprising a molar ratio of less than 50% (x < 0.5) Ge. Ge may contain Si in a molar ratio. 1-x Ge x The second gate spacer layer 84 comprises approximately 10% to 40% of the first gate spacer layer 80. The second gate spacer layer 84 can be formed by conformal deposition processes such as molecular beam deposition (MBD), ALD, PECVD, etc. The second gate spacer layer 84 is doped and may be doped with n-type impurities (e.g., phosphorus) or p-type impurities (e.g., boron). As shown, the second gate spacer layer 84 is a different material from the first gate spacer layer 80. The second gate spacer layer 84 and the first gate spacer layer 80 have high etch selectivity with respect to the same etch process; for example, during the same etch process, the etch rate of the second gate spacer layer 84 is greater than the etch rate of the first gate spacer layer 80. In some embodiments, the second gate spacer layer 84 may be doped in subsequent processing to further increase the etch selectivity between the second gate spacer layer 84 and the first gate spacer layer 80, which will be discussed in more detail below.

[0037] After forming the second gate spacer layer 84, a third gate spacer layer 90 is formed on the second gate spacer layer 84. The third gate spacer layer 90 is formed of a dielectric material selected from candidate dielectric materials of the first gate spacer layer 80, and can be formed by a method selected from candidate methods for forming the first gate spacer layer 80, or by different methods. In some other embodiments, the third gate spacer layer 90 is formed of a different material than the first gate spacer layer 80. In particular, the third gate spacer layer 90 and the first gate spacer layer 80 may have high etch selectivity. As will be discussed further below, the third gate spacer layer 90 is also doped in a subsequent process, which further increases the etch selectivity between the third gate spacer layer 90 and the first gate spacer layer 80.

[0038] exist Figures 8A to 8E In the fin 52, epitaxial source / drain regions 92 are formed to apply stress in the corresponding channel regions 58, thereby improving performance. The epitaxial source / drain regions 92 are formed in the fin 52 such that each dummy gate 72 is disposed between corresponding adjacent pairs of epitaxial source / drain regions 92. In some embodiments, the epitaxial source / drain regions 92 may extend into and penetrate the fin 52. A first gate spacer layer 80, a second gate spacer layer 84, and a third gate spacer layer 90 are used to separate the epitaxial source / drain regions 92 from the dummy gates 72 by an appropriate lateral distance, such that the epitaxial source / drain regions 92 do not short-circuit the subsequently formed gate of the resulting FinFET.

[0039] An epitaxial source / drain region 92 in region 50N (e.g., NMOS region) can be formed by masking region 50P, for example, a PMOS region, and etching the source / drain regions of fin 52 in region 50N to form a groove in fin 52. The epitaxial source / drain region 92 in region 50N is then epitaxially grown in the groove. The epitaxial source / drain region 92 can comprise any acceptable material, such as that suitable for an n-type FinFET. For example, if fin 52 is silicon, the epitaxial source / drain region 92 in region 50N can comprise a material to which tensile strain is applied in channel region 58, such as silicon, SiC, SiCP, SiP, etc. The epitaxial source / drain region 92 in region 50N can have a surface protruding from the corresponding surface of fin 52 and can have a small facet.

[0040] An epitaxial source / drain region 92 in region 50P (e.g., a PMOS region) can be formed by masking region 50N (e.g., an NMOS region) and etching the source / drain regions of fin 52 in region 50P to form a groove in fin 52. The epitaxial source / drain region 92 in region 50P is then epitaxially grown in the groove. The epitaxial source / drain region 92 can include any acceptable material, such as that suitable for a p-type FinFET. For example, if fin 52 is silicon, the epitaxial source / drain region 92 in region 50P can include a material to which compressive strain is applied in channel region 58, such as SiGe, SiGeB, Ge, GeSn, etc. The epitaxial source / drain region 92 in region 50P can also have a surface protruding from the corresponding surface of fin 52 and can have a small facet.

[0041] In some embodiments, a third gate spacer layer 90 is formed prior to the process of forming the epitaxial source / drain regions 92, and the third gate spacer layer 90 can be formed in each region. For example, the third gate spacer layer 90 can be formed with the epitaxial source / drain regions 92 in region 50N while region 50P is masked, or the third gate spacer layer 90 can be formed with the epitaxial source / drain regions 92 in region 50P while region 50N is masked. The third gate spacer layer 90 serves as an additional etch mask during the recessing of the source / drain regions of the fin 52, thereby protecting the vertical portions of the second gate spacer layer 84 during the etching of the source / drain regions of the fin 52. The source / drain recesses can therefore be formed with a greater depth and a narrower width.

[0042] During the recessing of the source / drain regions of fin 52, the first gate spacer layer 80, the second gate spacer layer 84, and the third gate spacer layer 90 are etched. Openings are formed in the first gate spacer layer 80, the second gate spacer layer 84, and the third gate spacer layer 90 to expose the source / drain regions of fin 52, and these openings extend into fin 52 to form grooves for epitaxial source / drain regions 92. The etching can be, for example, anisotropic etching, such as dry etching. The first gate spacer layer 80, the second gate spacer layer 84, and the third gate spacer layer 90 may (or may not) be etched using different processes.

[0043] The epitaxial source / drain regions 92 and / or fins 52 can be implanted with dopants to form source / drain regions, similar to the previously discussed process for forming lightly doped source / drain regions followed by annealing. The impurity concentration of the source / drain regions can be around 10. 19 cm -3 To about 10 21 cm -3Between. The n-type and / or p-type impurities used for the source / drain regions can be any impurities discussed previously. In some embodiments, the epitaxial source / drain regions 92 can be doped in situ during growth.

[0044] Due to the epitaxial process used to form the epitaxial source / drain regions 92 in regions 50N and 50P, the upper surfaces of the epitaxial source / drain regions have small facets that extend laterally outward beyond the sidewalls of the fins 52. In some embodiments, these facets cause adjacent epitaxial source / drain regions 92 of the same FinFET to merge as shown. A gap 94 may be formed below the merged epitaxial source / drain regions 92 between adjacent fins 52. Figure 8E This is better illustrated in the diagram. Two or more adjacent regions may be merged. In other embodiments (discussed further below), adjacent epitaxial source / drain regions 92 remain separated after the epitaxial process is complete. On the isolation region 56 and between the fins 52 (e.g., Figure 8A as well as Figure 9A , Figure 10A , Figure 11A , Figure 12A , Figure 13A , Figure 14A and Figure 15A In the cut cross-sectional view, the remainder of the third gate spacer layer 90 is shown as observable, for example, extending (in physical contact with) the bottom surface and at least one sidewall of each of the source / drain regions 92. However, it should be understood that such a remainder of the third gate spacer layer 90 may be etched, for example, to form part of a void 94, while remaining within the scope of this disclosure.

[0045] During doping of the epitaxial source / drain region 92, the first gate spacer layer 80, the second gate spacer layer 84, and the third gate spacer layer 90 may also be doped. For example, when doping is performed by implantation, some impurities can be implanted into the respective spacers. Similarly, when doping is performed in situ during growth, the respective spacers may be exposed to the dopant precursor of the epitaxial process. Because the third gate spacer layer 90 covers the second gate spacer layer 84, the second gate spacer layer 84 may have a lower dopant concentration than the third gate spacer layer 90. Similarly, because the second gate spacer layer 84 covers the first gate spacer layer 80, the first gate spacer layer 80 may have a lower dopant concentration than the second gate spacer layer 84. Furthermore, some regions (e.g., the upper regions) of the first gate spacer layer 80, the second gate spacer layer 84, and the third gate spacer layer 90 may be doped to a higher impurity concentration compared to other regions of the spacer layers (e.g., the lower regions). Due to the masking steps discussed above, the first gate spacer layer 80, the second gate spacer layer 84, and the third gate spacer layer 90 in region 50N are doped with the same impurities as the epitaxial source / drain regions 92 in region 50N. Similarly, the first gate spacer layer 80, the second gate spacer layer 84, and the third gate spacer layer 90 in region 50P are doped with the same impurities as the epitaxial source / drain regions 92 in region 50P. Thus, the conductivity type (e.g., majority carrier type) of each epitaxial source / drain region 92 is the same as the portion of the first gate spacer layer 80, the second gate spacer layer 84, and the third gate spacer layer 90 adjacent to the epitaxial source / drain region 92.

[0046] After forming the epitaxial source / drain region 92, the remaining portions of the first gate spacer layer 80 and the second gate spacer layer 84 form the first gate spacer 86 and the second gate spacer 88, respectively. Furthermore, the third gate spacer layer 90 can be partially removed. Removal can be achieved by a suitable etching process, such as wet etching using hot H3PO4 acid. In some embodiments, a residual portion of the third gate spacer layer 90 is retained after removal; this residual portion is disposed between the second gate spacer 88 and the raised surface of the epitaxial source / drain region 92, and is located in the void 94 of the epitaxial source / drain region 92. The residual portion of the third gate spacer layer 90 is referred to as the residual spacer 96.

[0047] exist Figures 9A to 9EIn this process, a contact etch stop layer (CESL) 98 is formed along the second gate spacer 88 and over the epitaxial source / drain region 92 and the residual spacer 96. The CESL 98 may be formed of a candidate dielectric material selected from the first gate spacer layer 80 (86), or may include a different dielectric material. The CESL 98 may be formed by a method selected from candidate methods for forming the first gate spacer layer 80, or may be formed by a different method. As shown, the CESL 98 is a different dielectric material from the second gate spacer layer 84 (88). The second gate spacer layer 84 and the CESL 98 have high etch selectivity with respect to the same etch process; for example, the etch rate of the second gate spacer layer 84 is greater than the etch rate of the CESL 98 during the etch process. In some embodiments, the CESL 98 and the first gate spacer layer 80 are formed of the same dielectric material.

[0048] Furthermore, a first interlayer dielectric (ILD) 101 is deposited over CESL 98. ILD 101 can be formed of a dielectric material and can be deposited by any suitable method, such as CVD, plasma-enhanced CVD (PECVD), or FCVD. The dielectric material can include phosphosilicate glass (PSG), borosilicate glass (BSG), boron-doped phosphosilicate glass (BPSG), undoped silicate glass (USG), etc. Other insulating materials formed by any acceptable method can be used.

[0049] exist Figures 10A to 10E In this process, a planarization process such as chemical mechanical polishing (CMP) can be performed to make the top surface of ILD 101 flush with the top surface of dummy gate 72 or mask 74. The planarization process removes a portion of CESL 98 above mask 74 and also removes mask 74 over dummy gate 72. After the planarization process, the top surfaces of dummy gate 72, first gate spacer 86, second gate spacer 88, CESL 98, and ILD 101 are flush. Therefore, the top surface of dummy gate 72 is exposed through ILD 101. In some embodiments, mask 74 can be retained, in which case the planarization process makes the top surface of ILD 101 flush with the top surface of mask 74.

[0050] exist Figures 11A to 11EIn the etching step, the dummy gate 72 and mask 74 (if present) are removed to form a recess 104. The dummy gate dielectric 70 in the recess 104 may also be removed. In some embodiments, only the dummy gate 72 is removed, and the dummy gate dielectric 70 is retained and exposed by the recess 104. In some embodiments, the dummy gate dielectric 70 is removed from the recess 104 in a first region of the die (e.g., a core logic region) and retained in the recess 104 in a second region of the die (e.g., an input / output region). In some embodiments, the dummy gate 72 is removed by an anisotropic dry etching process. For example, the etching process may include a dry etching process using a reactive gas that selectively etches the dummy gate 72 without etching the first gate spacer 86, the second gate spacer 88, CESL 98, or ILD 101. Each recess 104 exposes a channel region 58 of a corresponding fin 52. Each channel region 58 is disposed between adjacent pairs of epitaxial source / drain regions 92. During removal, the dummy gate dielectric 70 can be used as an etch stop layer when etching the dummy gate 72. Then, after removing the dummy gate 72, the dummy gate dielectric 70 can optionally be removed.

[0051] exist Figures 12A to 12E In this process, a gate dielectric 106 and a gate electrode 108 are formed to replace the gate. Figure 12F It shows Figure 12B A detailed view of region 11. Gate dielectric 106 is conformally deposited in recess 104, such as on the top surface and sidewalls of fin 52 and on the sidewalls of the first gate spacer 86. Gate dielectric 106 may also be formed on the top surface of ILD 101. According to some embodiments, gate dielectric 106 comprises silicon oxide, silicon nitride, or a multilayer thereof. In some embodiments, gate dielectric 106 comprises a high-k dielectric material, and in these embodiments, gate dielectric 106 may have a k value greater than about 7.0, and may comprise metal oxides or silicates of Hf, Al, Zr, La, Mg, Ba, Ti, Pb, or combinations thereof. Methods for forming gate dielectric 106 may include molecular beam deposition (MBD), ALD, PECVD, etc. In embodiments where dummy gate dielectric 70 is retained in recess 104, gate dielectric 106 comprises the material of dummy gate dielectric 70 (e.g., SiO2).

[0052] Gate electrodes 108 are deposited over gate dielectric 106 and fill the remaining portion of trench 104. Gate electrodes 108 may comprise a metallic material such as TiN, TiO, TaN, TaC, Co, Ru, Al, W, combinations thereof, or multiple layers. For example, although... Figures 12A to 12DThe diagram shows a single-layer gate electrode 108, but the gate electrode 108 may include any number of pad layers 108A, any number of work function adjustment layers 108B, and filler material 108C, such as... Figure 12F As shown. After filling the gate electrode 108, a planarization process such as CMP can be performed to remove excess portions of the material of the gate dielectric 106 and the gate electrode 108, which are located above the top surface of the ILD 101. The remaining portions of the material of the gate electrode 108 and the gate dielectric 106 thus form the replacement gate of the resulting FinFET. The gate electrode 108 and the gate dielectric 106 may sometimes be collectively referred to as the “active gate stack”. The active gate stack may extend along the sidewalls of the channel region 58 of the fin 52.

[0053] The formation of the gate dielectric 106 in regions 50N and 50P can occur simultaneously, such that the gate dielectric 106 in each region is formed of the same material, and the formation of the gate electrode 108 can occur simultaneously, such that the gate electrode 108 in each region is formed of the same material. In some embodiments, the gate dielectric 106 in each region can be formed by different processes, such that the gate dielectric 106 can be made of different materials, and / or the gate electrode 108 in each region can be formed by different processes, such that the gate electrode 108 can be made of different materials. When using different processes, separate masking steps can be used to mask and expose appropriate regions.

[0054] exist Figures 13A to 13E In this process, the second gate spacer 88 is removed to extend the gap 94 along the active gate stack. According to various embodiments, due to the high etch selectivity between the second gate spacer 88 and both the first gate spacer 86 and the residual spacer 96, the first gate spacer 86 and the residual spacer 96 can be retained substantially intact when the second gate spacer 88 is removed. Therefore, the gap 94 can inherit the dimensions and profile of the second gate spacer 88, whose profile can have conformal spacing traveling along the gap 94. In some other embodiments, adjacent layers / parts (e.g., 86, 96, 98) along the gap 94 can also be etched simultaneously with the removal of the second gate spacer 88, but in much smaller quantities. Therefore, the gap 94 can exhibit non-uniform spacing traveling along the gap 94. For example, the etch selectivity between gate spacers 86 and 88 and between gate spacers 88 and 96 can be different, which can result in different spacing in different portions of the gap 94.

[0055] As mentioned above Figure 8AAs mentioned, during the formation of the source / drain regions 92, residual spacers 96 can be maintained extending along the bottom surface and sidewalls of the merged portion of adjacent source / drain regions 92. Such residual spacers 96 can further protect the source / drain regions 92 during the removal of the second gate spacer 88. Furthermore, due to the high etch selectivity between the second gate spacer 88 and ILD 101, ILD 101 can remain substantially intact even without a protective helmet formed on top. After removal, a void 94 separates the active gate stack from the epitaxial source / drain regions 92. Specifically, the void 94 physically separates a portion of the first gate spacer layer 86 from portions of CESL 98 and ILD 101.

[0056] The second gate spacer 88 is removed by one or more etching processes. As described above, the second gate spacer 88 has high etch selectivity relative to the materials of the first gate spacer 86, the residual spacer 96, and the ILD 101. Therefore, the etching process can etch the material of the second gate spacer 88 at a higher rate than the materials of the first gate spacer 86, the residual spacer 96, and the ILD 101.

[0057] In some embodiments, the etching process is a single etching process. A single etching process may include a dry etching process using plasma (e.g., fluorine-containing plasma using gaseous hydrogen fluoride (HF) and / or fluorine (F2)). HF can help partially remove Ge due to the migration of hydrogen atoms. The etching process includes processes performed below about 50°C, specifically below about 40°C, and more specifically in the range of about 25°C to 35°C. The active gate stack has less lateral support as the void 94 extends along the active gate stack. Performing a single etching process at low temperature and low pressure can help avoid deformation of the active gate stack when reducing lateral support.

[0058] In some embodiments, the etching process includes multiple etching processes, such as a first etching process and a second etching process. As described above, when forming the epitaxial source / drain region 92, the second gate spacer 88 may be doped with impurities of the epitaxial source / drain region 92, and the upper region may be doped with a higher impurity concentration than the lower region. The first etching process has a higher etching rate at a higher impurity concentration and is used to remove the upper region of the second gate spacer 88, and the second etching process has a higher etching rate at a lower impurity concentration and is used to remove the lower region of the second gate spacer 88. Each of the first and second etching processes may include a dry etching process using plasma (e.g., fluorine-containing plasma (using gaseous hydrogen fluoride (HF) and / or fluorine (F2))). Each of the first and second etching processes includes a process implemented at a temperature below about 50°C, specifically below about 40°C, and more specifically in the range of about 25°C to 35°C.

[0059] In some embodiments, regions 50P and the second gate spacer 88 in 50P can be removed at different rates. Specifically, the second gate spacer 88 doped with n-type impurities (e.g., in region 50N) is removed at a faster rate than the second gate spacer 88 doped with p-type impurities (e.g., in region 50P). Therefore, some residue (not shown) may remain in region 50P but not in region 50N. The residue may be the dielectric material of the second gate spacer 88.

[0060] exist Figures 14A to 14E In this process, a dielectric layer 114 is formed on the first gate spacer 86, ILD 101, gate dielectric 106, and gate electrode 108. The dielectric layer 114 can be formed of a dielectric material such as silicon nitride, silicon oxide, silicon carbonitride, silicon carbonitride, silicon carbonoxide, etc., and can be formed by a deposition process such as ALD. As shown, the dielectric layer 114 partially fills the upper portion of the void 94. The void 94 is thus sealed, so that material can not be deposited in the void 94 during subsequent processes.

[0061] exist Figures 15A to 15E In this process, a planarization process can be performed to remove the portion of dielectric layer 114 located above ILD 101. The planarization process can be polishing, CMP, etc. The remaining portion of dielectric layer 114 forms dielectric plug 116, thereby sealing the void 94. After the planarization process, the top surfaces of ILD 101, dielectric plug 116, first gate spacer 86, CESL 98, gate dielectric 106, and gate electrode 108 are flush.

[0062] Figure 16A flowchart of a method 1600 for forming a nonplanar transistor device according to one or more embodiments of the present invention is shown. For example, at least some operations (or steps) of method 1600 can be used to form a FinFET 100. However, it should be understood that some operations of method 1600 can be used to fabricate other types of nonplanar devices, such as, for example, any of nanosheet transistor devices, nanowire transistor devices, vertical transistor devices, gate all-around (GAA) transistor devices, etc., while still remaining within the scope of the present invention. It should be noted that method 1600 is merely an example and is not intended to limit the invention. Therefore, it should be understood that... Figure 16 Method 1600 provides additional operations before, during, and after, and only a few other operations are briefly described here.

[0063] In some embodiments, the operation of method 1600 can be respectively related to, for example, Figure 2 , Figure 3 , Figure 4 , Figure 5 , Figure 6 , Figures 7A to 7E , Figures 8A to 8E , Figures 9A to 9E , Figures 10A to 10E , Figures 11A to 11E , Figures 12A to 12F , Figures 13A to 13E , Figures 14A to 14E and Figures 15A to 15E The cross-sectional views of the exemplary FinFET 100 at each of the manufacturing stages are shown in the diagram.

[0064] Method 1600 starts from providing a substrate (e.g., Figure 2 Operation 1602 of method 50) begins. Method 1600 continues to form multiple fins (e.g., Figure 3 Operation 1604 of (52). Method 1600 continues to form an isolation region (e.g., Figure 4 Operation 1606 of (56). Method 1600 continues to operation 1608, which forms a pseudo dielectric layer, a pseudo gate layer, and a mask layer (e.g., respectively). Figure 5 (60, 62, and 64). Method 1600 proceeds to form one or more dummy gate stacks (e.g., Figure 6 Operation 1610 of (70 and 72). Method 1600 continues to form a first gate spacer layer, a second gate spacer layer and a third gate spacer layer (e.g., respectively). Figures 7A to 7E Operation 1612 (of 80, 84, and 90). Method 1600 continues to form the source / drain region (e.g., Figures 8A to 8E Operation 1614 of (92). Method 1600 continues to form the ILD (e.g., Figures 9A to 9EOperation 1616 of 101). Method 1600 continues to implement CMP (e.g., Figures 10A to 10E Operation 1618. Method 1600 continues to remove the dummy gate stack (e.g., Figures 11A to 11E Operation 1620. Method 1600 continues to form the gate dielectric and gate electrode (e.g., respectively). Figures 12A to 12F Operation 1622 of (106 and 108). Method 1600 continues to remove the second gate spacer layer (e.g., Figures 13A to 13E Operation 1624. By removing the second gate spacer layer, a void can be formed or expanded. Method 1600 continues to form a dielectric layer (e.g., Figures 14A to 14E Operation 1626 of (114). Method 1600 continues to form a dielectric plug (e.g., Figures 15A to 15E Operation 1628 of 116). Dielectric plugs are formed by planarizing the dielectric layer to seal the gaps.

[0065] Various embodiments of the present invention can achieve several advantages. The void 94 comprises air or vacuum, both of which have a lower relative permittivity than the dielectric material of the removed second gate spacer 88. In a smaller device size, the capacitance between the source / drain contacts connecting the source / drain regions 92 (not shown) and the gate electrode 108 can be a significant source of circuit capacitance. Reducing the relative permittivity of the space between the source / drain contacts and the gate electrode 108 can reduce this capacitance. Capacitance reduction can improve the final device performance of the resulting FinFET 100.

[0066] In one aspect of this disclosure, a method for manufacturing a semiconductor device is disclosed. The method includes forming a first fin over a substrate. The method includes forming a dummy gate stack on the first fin. The method includes forming a first gate spacer along a side of the dummy gate stack. The first gate spacer includes a first dielectric material. The method includes forming a second gate spacer along a side of the first gate spacer. The second gate spacer includes a semiconductor material. The method includes forming a source / drain region in a first fin adjacent to the second gate spacer. The method includes removing at least a portion of the second gate spacer to form a void extending between the first gate spacer and the source / drain region.

[0067] In some embodiments, the method further includes: depositing an interlayer dielectric (ILD) over a source / drain region, the interlayer dielectric comprising a second dielectric material; and exposing the top surface of the interlayer dielectric during a step of removing at least a portion of the second gate spacer. In some embodiments, the step of removing at least a portion of the second gate spacer leaves the first gate spacer and the interlayer dielectric intact. In some embodiments, the gap further extends between the first gate spacer and the interlayer dielectric. In some embodiments, the semiconductor material comprises silicon germanium. In some embodiments, the step of removing at least a portion of the second gate spacer includes performing a dry etching process using at least one of gaseous hydrogen fluoride (HF) or fluorine (F2). In some embodiments, the method further includes: depositing a dielectric layer over the gap; and removing portions of the dielectric layer disposed outside the gap by a planarization process, thereby causing the remaining portion of the dielectric layer to form the dielectric plug to seal the gap. In some embodiments, the method further includes: forming a second fin over the substrate, the dummy gate stack also being formed over the second fin, the source / drain region also being formed in the second fin, and the gap further extending below the source / drain region. In some embodiments, the method further includes: replacing the dummy gate stack with an active gate stack, the first gate spacer extending along a side of the active gate stack. In some embodiments, the gap further extends between the active gate stack and the source / drain region.

[0068] In another aspect of this disclosure, a method for manufacturing a semiconductor device is disclosed. The method includes forming a first fin and a second fin over a substrate. The first fin and the second fin are adjacent to each other. The method includes forming a dummy gate stack on the first fin and the second fin. The method includes forming a first gate spacer along a side of the dummy gate stack, the first gate spacer comprising a first dielectric material. The method includes forming a second gate spacer along a side of the first gate spacer. The second gate spacer comprises a semiconductor material. The method includes forming a source / drain region in both the first fin and the second fin adjacent to the second gate spacer. The source / drain region includes a merged portion between the first fin and the second fin. The method includes removing at least a portion of the second gate spacer to form a void extending between the first gate spacer and the source / drain region.

[0069] In some embodiments, the gap further extends below the merged portion of the source / drain regions. In some embodiments, the semiconductor material comprises silicon-germanium. In some embodiments, the method further comprises: depositing an interlayer dielectric (ILD) over the source / drain regions, the interlayer dielectric comprising a second dielectric material; and exposing the top surface of the interlayer dielectric during a step of removing at least a portion of the second gate spacer. In some embodiments, the step of removing at least a portion of the second gate spacer leaves the first gate spacer and the interlayer dielectric intact. In some embodiments, the gap also extends between the first gate spacer and the interlayer dielectric. In some embodiments, the step of removing at least a portion of the second gate spacer comprises: performing a dry etching process using at least one of gaseous hydrogen fluoride (HF) or fluorine (F2). In some embodiments, the method further comprises: replacing the dummy gate stack with an active gate stack, the first gate spacer extending along a side of the active gate stack, the gap further extending between the active gate stack and the source / drain regions.

[0070] In another aspect of this disclosure, a method for manufacturing a semiconductor device is disclosed. The method includes forming a fin over a substrate. The method includes forming a dummy gate stack over the fin. The method includes forming a gate spacer along a side of the dummy gate stack. The gate spacer includes a first layer formed of a dielectric material and a second layer formed of a semiconductor material. The method includes forming a source / drain region in a fin adjacent to the gate spacer. The method includes replacing the dummy gate stack with an active gate stack. The method includes removing at least a portion of the second layer of the gate spacer to form a gap extending between the active gate stack and the source / drain region.

[0071] In some embodiments, the method further includes: depositing an interlayer dielectric (ILD) over the source / drain regions; and exposing the top surface of the interlayer dielectric during a step of removing at least a portion of the second layer of the gate spacer.

[0072] The components of several embodiments have been outlined above to enable those skilled in the art to better understand aspects of the invention. Those skilled in the art should understand that they can readily use this invention as a basis to design or modify other processes and structures for implementing the same purposes and / or achieving the same advantages as the embodiments described herein. Those skilled in the art should also recognize that such equivalent constructions do not depart from the spirit and scope of the invention, and that various changes, substitutions, and modifications can be made to them herein without departing from the spirit and scope of the invention.

Claims

1. A method for manufacturing a semiconductor device, comprising: The first fin is formed above the substrate; A dummy gate stack is formed on the first fin; A first gate spacer is formed along the sidewall of the dummy gate stack, the first gate spacer comprising a first dielectric material; A second gate spacer is formed along the sidewall of the first gate spacer, the second gate spacer comprising a semiconductor material; A third gate spacer is formed along the sidewall of the second gate spacer, the third gate spacer comprising a second dielectric material. A source / drain region is formed in the first fin adjacent to the third gate spacer, wherein the second gate spacer extends along the bottom surface and sidewalls of the source / drain region; An interlayer dielectric (ILD) is deposited over the source / drain regions, the interlayer dielectric comprising a third dielectric material; and At least a portion of the second gate spacer is removed to form a void extending between the first gate spacer and the bottom surface and sidewalls of the source / drain region, and during the removal, the top surface of the interlayer dielectric is exposed, and the step of removing at least a portion of the second gate spacer leaves the first gate spacer, the third gate spacer, and the interlayer dielectric intact. The third gate spacer extends along the bottom surface and sidewall of the merged portion of the adjacent source / drain regions. A portion of the gap is located between the third gate spacer and the bottom surface of the merged portion of the source / drain regions. A portion of the gap is located between the third gate spacer and the first gate spacer. Another portion of the gap is located between the first gate spacer and the interlayer dielectric.

2. The method according to claim 1, wherein: The semiconductor material has higher etching selectivity compared to the third dielectric material.

3. The method according to claim 1, wherein, The gap includes a horizontal portion extending below the source / drain region.

4. The method according to claim 1, wherein, The gap further extends between the first gate spacer and the interlayer dielectric.

5. The method according to claim 1, wherein, The semiconductor material includes silicon and germanium.

6. The method according to claim 1, wherein, The step of removing at least a portion of the second gate spacer includes performing a dry etching process using at least one of gaseous hydrogen fluoride (HF) or fluorine (F2).

7. The method according to claim 1, further comprising: A dielectric layer is deposited over the void; as well as A portion of the dielectric layer disposed outside the gap is removed by a planarization process, thereby forming a dielectric plug to seal the gap by the remaining portion of the dielectric layer.

8. The method according to claim 1, further comprising: A second fin is formed above the substrate, the dummy gate stack is also formed above the second fin, the source / drain region is also formed in the second fin, and the void further extends below the source / drain region.

9. The method according to claim 1, further comprising: The dummy gate stack is replaced with an active gate stack, wherein the first gate spacer extends along the sidewall of the active gate stack.

10. The method according to claim 9, wherein, The gap further extends between the active gate stack and the source / drain regions.

11. A method for manufacturing a semiconductor device, comprising: A first fin and a second fin are formed above the substrate, the first fin and the second fin being adjacent to each other; A dummy gate stack is formed on the first fin and the second fin; A first gate spacer is formed along the sidewall of the dummy gate stack, the first gate spacer comprising a first dielectric material; A second gate spacer is formed along the sidewall of the first gate spacer, the second gate spacer comprising a semiconductor material; A third gate spacer is formed along the sidewall of the second gate spacer, the third gate spacer comprising a second dielectric material. A source / drain region is formed in both the first fin and the second fin adjacent to the third gate spacer, wherein the second gate spacer extends along the bottom surface and sidewalls of the source / drain region, and the source / drain region includes a merged portion between the first fin and the second fin; An interlayer dielectric (ILD) is deposited over the source / drain regions, the interlayer dielectric comprising a third dielectric material; and At least a portion of the second gate spacer is removed to form a void extending between the first gate spacer and the bottom surface and sidewalls of the source / drain region, and during the removal, the top surface of the interlayer dielectric is exposed. The step of removing at least a portion of the second gate spacer ensures that the first gate spacer, the third gate spacer, and the interlayer dielectric remain intact. The third gate spacer extends along the bottom surface and sidewall of the merged portion of the adjacent source / drain regions. A portion of the gap is located between the third gate spacer and the bottom surface of the merged portion of the source / drain regions. A portion of the gap is located between the third gate spacer and the first gate spacer. Another portion of the gap is located between the first gate spacer and the interlayer dielectric.

12. The method according to claim 11, wherein, The gap further extends below the merged portion of the source / drain regions.

13. The method according to claim 11, wherein, The semiconductor material includes silicon and germanium.

14. The method of claim 11, wherein: The semiconductor material has higher etching selectivity compared to the third dielectric material.

15. The method according to claim 14, wherein, The gap includes a horizontal portion extending below the source / drain region.

16. The method of claim 14, wherein, The gap also extends between the first gate spacer and the interlayer dielectric.

17. The method according to claim 11, wherein, The step of removing at least a portion of the second gate spacer includes performing a dry etching process using at least one of gaseous hydrogen fluoride (HF) or fluorine (F2).

18. The method of claim 11, further comprising: The dummy gate stack is replaced with an active gate stack, the first gate spacer extending along the sidewall of the active gate stack, and the gap further extending between the active gate stack and the source / drain region.

19. A method for manufacturing a semiconductor device, comprising: Fins are formed above the substrate; A dummy gate stack is formed above the fin; A gate spacer is formed along the sidewall of the dummy gate stack, the gate spacer comprising a first layer formed of a first dielectric material, a second layer formed of a semiconductor material, and a third layer formed of a second dielectric material; A source / drain region is formed in the fin adjacent to the gate spacer, wherein the second layer extends along the bottom surface and sidewalls of the source / drain region; An interlayer dielectric (ILD) is deposited above the source / drain regions; and Replace the dummy gate stack with an active gate stack; At least a portion of the second layer of the gate spacer is removed to form a void extending between the bottom surface and the sidewalls of the active gate stack and the source / drain regions, and during the removal, the top surface of the interlayer dielectric is exposed, and the step of removing at least a portion of the second layer of the gate spacer leaves the first layer of the gate spacer, the third layer of the gate spacer, and the interlayer dielectric intact. The third layer of the gate spacer extends along the bottom surface and sidewalls of the merged portion of the adjacent source / drain regions. A portion of the gap is located between the third layer of the gate spacer and the bottom surface of the merged portion of the source / drain regions. A portion of the gap is located between the third layer of the gate spacer and the first layer of the gate spacer. Another portion of the gap is located between the first layer of the gate spacer and the interlayer dielectric.

20. The method of claim 19, wherein: The material of the second layer has high etching selectivity compared to the material of the interlayer dielectric.

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