Semiconductor device structure and manufacturing method thereof

Abstract

A semiconductor device structure and a manufacturing method thereof are provided. The semiconductor device structure includes a first insulating layer formed on a conductive feature component and a capacitor structure embedded in the first insulating layer. The semiconductor device also includes a bonding pad formed on the first insulating layer and corresponding to the capacitor structure. The bonding pad has an upper surface and a multi-step edge to form at least three corners. In addition, the semiconductor device structure includes a second insulating layer that conformably covers at least three corners formed by the upper surface of the bonding pad and the multi-step edge.

Description

Technical Field

[0001] The present disclosure relates to a semiconductor technology, and more particularly to a semiconductor device structure and a method for manufacturing the same. Background Art

[0002] As electronic technology advances, electronic devices become more complex and involve an increasing number of integrated circuits to achieve the required multifunctionality. As a result, the manufacture of such electronic devices includes an increasing number of operating steps and a variety of different types of materials to produce semiconductor devices for use in electronic devices.

[0003] Semiconductor devices may include active and / or passive devices, such as transistors and capacitors. These devices are initially isolated from each other, but are subsequently interconnected. Typical interconnect structures include lateral interconnects, such as metal wires (wiring), and vertical interconnects, such as vias and contacts. Bonding pads are formed above the interconnect structures and exposed to the surface of the corresponding chip. Electrical connections are made through the bonding pads to connect the chip to another component.

[0004] During the manufacturing process, semiconductor devices are assembled from many components made of various materials. As more components made of different materials are involved and the complexity of the manufacturing process increases, more challenges arise in modifying the structure of semiconductor devices and improving the manufacturing process. Summary of the invention

[0005] In some embodiments, a semiconductor device structure includes: a first insulating layer formed on a conductive feature component; a capacitor structure buried in the first insulating layer; a bonding pad formed on the first insulating layer and corresponding to the capacitor structure, wherein the bonding pad has an upper surface and a multi-step edge to form at least three corners; and a second insulating layer that conformally covers at least three corners formed by the upper surface of the bonding pad and the multi-step edge.

[0006] In some embodiments, a semiconductor device structure includes: a first insulating layer formed on a topmost metal layer of an internal connection structure; a metal-insulator-metal capacitor buried in the first insulating layer; a bonding pad formed on the metal-insulator-metal capacitor and separated from the metal-insulator-metal capacitor by the first insulating layer, wherein the bonding pad has a side wall having a non-linear profile, wherein a path from an upper surface of the bonding pad along the side wall of the bonding pad to an upper surface of the first insulating layer includes at least three turning angles, and the sum of the turning angles is greater than 90°.

[0007] In some embodiments, a method for manufacturing a semiconductor device structure includes: forming a first insulating layer and a metal-insulator-metal capacitor on a topmost metal layer of an internal connection structure, wherein the metal-insulator-metal capacitor is buried in the first insulating layer; forming a conductive layer on the first insulating layer; patterning the conductive layer to form a bonding pad on the first insulating layer, corresponding to the metal-insulator-metal capacitor, wherein the bonding pad has an upper surface and a multi-step edge to form at least three corners; conformally forming a second insulating layer to cover at least three corners formed by the upper surface and the multi-step edge of the bonding pad; forming a third insulating layer on the second insulating layer; and forming an under-bump metal layer on the third insulating layer, and passing through the third insulating layer and the second insulating layer to contact the upper surface of the bonding pad. BRIEF DESCRIPTION OF THE DRAWINGS

[0008] Figure 1A-Figure 1K Schematic cross-sectional views of various stages of fabricating a semiconductor device structure according to some embodiments are shown.

[0009] Figure 2A A cross-sectional schematic diagram of a package structure according to some embodiments is shown.

[0010] Figure 2B A cross-sectional schematic diagram of a package structure according to some embodiments is shown.

[0011] Figure 3 A partial enlarged cross-sectional schematic diagram of a bonding pad according to some embodiments is shown.

[0012] Figure 4 A partial enlarged cross-sectional schematic diagram of a bonding pad according to some embodiments is shown.

[0013] Figure 5 A partial enlarged cross-sectional schematic diagram of a bonding pad according to some embodiments is shown.

[0014] Figure 6 A partial enlarged cross-sectional schematic diagram of a bonding pad according to some embodiments is shown.

[0015] Figure 7 A partial enlarged cross-sectional schematic diagram of a bonding pad according to some embodiments is shown.

[0016] The reference numerals are described as follows:

[0017] 100: Base

[0018] 102: Isolation Structure

[0019] 106: Gate dielectric layer

[0020] 108: Gate electrode layer

[0021] 109: Gate structure

[0022] 110: Source / drain structure

[0023] 112, 130, 142, 170, 176: Insulation layer

[0024] 114: Contact structure

[0025] 120: Top metal layer

[0026] 122: Multilayer dielectric layer

[0027] 124: Inner connection structure

[0028] 132, 136, 139: Capacitor metal electrode layer

[0029] 134, 138: Capacitor insulation layer

[0030] 140: Metal-Insulator-Metal (MIM) Capacitors

[0031] 140a: Super High Density Metal-Insulator-Metal (SHDMIM) Capacitor

[0032] 142a, 152a: upper surface

[0033] 150: Adhesive layer

[0034] 152: Conductive layer

[0035] 153, 154: Patterned mask layer

[0036] 153a: Groove

[0037] 155: Path

[0038] 160, 160', 160", 160'": Bonding pads

[0039] 160a, 160a', 160a", 160a'": first stage

[0040] 160b, 160b', 160b", 160b'": Second stage

[0041] 160c", 160c'": third stage

[0042] 161a, 161a', 161a", 161a'", 161b, 161b', 161b", 160b'", 161c", 160c'": Side wall

[0043] 162, 162', 162", 162'", 262: Multi-order edge

[0044] 163a, 163b, 163c: Corner

[0045] 172, 178: Opening

[0046] 180: Under Bump Metal (UBM) layer

[0047] 182: Bump

[0048] 190, 254: Connectors

[0049] 192: Welding material area

[0050] 200: Semiconductor device structure

[0051] 250: Packaging components

[0052] 252: Conductive features

[0053] 260: Base glue material layer

[0054] 270: Sealing layer

[0055] 300, 400: packaging structure

[0056] A, B: Point

[0057] W1, W2: Width

[0058] θ1, θ1', θ2, θ2', θ3, θ3', θ4, θ4', θ5, θ5', θ6, θ6', θ7, θ7', θ8, θ8': Steering angle DETAILED DESCRIPTION

[0059] The following disclosure provides many different embodiments or examples to implement different characteristic components of the present disclosure. The following disclosure is a specific example describing each component and its arrangement in order to simplify the present disclosure. Of course, these are only examples and are not used to define the present invention. For example, if the following disclosure describes that a first characteristic component is formed on or above a second characteristic component, it means that it includes an embodiment in which the first characteristic component formed is in direct contact with the second characteristic component, and also includes an embodiment in which an additional characteristic component can be formed between the first characteristic component and the second characteristic component, so that the first characteristic component and the second characteristic component may not be in direct contact. In addition, the present disclosure will repeat numbers and / or text in each different example. The repetition is for the purpose of simplification and clarification, rather than specifying the relationship between the various different embodiments and / or configurations discussed.

[0060] Furthermore, spatially related terms such as "below", "under", "lower", "above", "upper", etc. are used here to easily express the relationship between an element or feature in the drawings shown in this specification and another element or feature. These spatially related terms not only cover the orientation shown in the drawings, but also cover different orientations of the device during use or operation. The device can have different orientations (rotated 90 degrees or other orientations) and the spatially related symbols used here are also interpreted accordingly.

[0061] As used herein, the terms "approximately," "substantially," "equivalent to," and "about" are used to describe and illustrate minor variations. When used with events or circumstances, these terms can indicate examples where the events or circumstances occurred exactly as well as examples where the events or circumstances occurred very nearly. For example, when used with a numerical value, the terms can indicate a range of variation that is less than or equal to ±5% of the numerical value. For example, two numerical values ​​can be considered "substantially" the same or equal if the difference between the two values ​​is less than or equal to ±5% of the average of the values.

[0062] The present disclosure describes some embodiments. Additional operating steps may be provided before, during and / or after the stages described in these embodiments. For different embodiments, some of the stages described may be replaced or removed. Additional features may be added to the semiconductor device structure. For different embodiments, some of the features described below may be replaced or removed. Although some embodiments are described with operating steps performed in a specific order, these operating steps may be performed in another logical order.

[0063] Other features and processes may also be included. For example, a test structure may be included to assist in verification testing of a 3D package or 3DIC device. For example, the test structure may include forming a test pad in a redistribution layer or on a substrate (allowing testing of the 3D package or 3DIC, using probes and / or probe cards, etc.). Verification testing may be performed on intermediate structures as well as final structures. In addition, the structures and methods disclosed herein may be used in conjunction with test methods that include intermediate verification of qualified chips to improve yield and reduce costs.

[0064] The following provides an embodiment for manufacturing a semiconductor device structure. The semiconductor device structure may include a bonding pad formed between a first insulating layer below and a second insulating layer above. A capacitor structure (e.g., a metal-insulator-metal (MIM) capacitor) is embedded in the first insulating layer and corresponds to the bonding pad. The bonding pad has a multi-step edge or a sidewall with a non-linear profile. In this way, the path from the upper surface of the bonding pad to the upper surface of the first insulating layer along the multi-step edge or the sidewall with a non-linear profile of the bonding pad includes at least three corners to define three turning angles. The sum of the turning angles is greater than 90°. The production of the bonding pad includes patterning a conductive layer by a first etching process using at least a first mask layer and a second etching process using a second mask layer. The area of ​​the first mask layer is greater than the area of ​​the second mask layer. The above-mentioned bonding pad provides more surface area than a bonding pad without a multi-step edge to share the stress in the second insulating layer. Thus, the bonding pad with multi-step edges can act as a stress buffer or crack stopper to prevent cracks from expanding or penetrating into the capacitor structure below the bonding pad, thereby improving the quality, yield and reliability of the semiconductor device structure.

[0065] An embodiment of a semiconductor device structure and a method for manufacturing the same is provided below. Figure 1A-Figure 1K A cross-sectional schematic diagram of various stages of manufacturing a semiconductor device structure 200 according to some embodiments is depicted. In some embodiments, the semiconductor device structure 200 includes a capacitor structure (e.g., a metal-insulator-metal (MIM) capacitor). Formed on a conductive feature (e.g., an uppermost metal layer, also referred to as a top metal layer of an interconnect structure). A bonding pad having an upper surface and a multi-step edge (or a sidewall with a non-linear profile) is formed on the metal-insulator-metal (MIM) capacitor to prevent cracks from extending into the capacitor structure. The upper surface of the bonding pad and the multi-step edge form at least three corners to correspond to at least three turning angles defining the multi-step edge.

[0066] In some embodiments, Figure 1A As shown, a substrate 100, such as a device wafer, is provided. Feature components are formed on the upper surface of the substrate 100. The substrate 100 may be made of silicon or other semiconductor materials. Alternatively or in addition, the substrate 100 may include other elemental semiconductor materials, such as germanium. In some embodiments, the substrate 100 is made of a compound semiconductor, such as silicon carbide, gallium arsenide, indium arsenide, or indium phosphide. In some embodiments, the substrate 100 is made of an alloy semiconductor, such as silicon germanium, silicon germanium carbide, gallium arsenic phosphide, or indium gallium phosphide. In some embodiments, the substrate 100 includes an epitaxial layer. For example, the substrate 100 has an epitaxial layer located above the bulk semiconductor.

[0067] like Figure 1AAs shown, an isolation structure 102 (e.g., a shallow trench isolation (STI) structure) is formed in the substrate 100 to isolate the active region in the substrate 100. Although not shown, through-vias may be formed to extend into the substrate 100. The through-via electrodes are used to electrically couple feature components located on two opposite sides of the substrate 100.

[0068] like Figure 1A As shown, an insulating layer 112 and a gate structure 109 buried in the insulating layer 112 are formed on the upper surface of the substrate 100. The gate structure 109 may include a gate dielectric layer 106 and a gate electrode layer 108 formed on the gate dielectric layer 106. Before the insulating layer 112 is formed and after the gate structure 109 is formed, a source / drain structure 110 is formed in the substrate 100 and next to the corresponding gate structure 109. Thereafter, a contact structure 114 (e.g., a contact plug) is formed above each gate structure 109 and electrically connected to the gate structure 109.

[0069] In some embodiments, the insulating layer 112 is an inter-layer dielectric (ILD) layer formed on the substrate 100 and filling the space between the gate stacks of the transistors (not shown) in the integrated circuit device 26. In some embodiments, the insulating layer 112 is formed of phospho silicate glass (PSG), boro silicate glass (BSG), boron-doped phospho silicate glass (BPSG), fluorine-doped silicate glass (FSG), tetraethoxysilane (TEOS) oxide, or the like. The insulating layer 112 can be formed by spin coating, flowable chemical vapor deposition (FCVD), plasma enhanced chemical vapor deposition (PECVD), low pressure chemical vapor deposition (LPCVD), or the like.

[0070] The contact structure 114 formed in the insulating layer 112 is also used to electrically connect the gate structure 109 to the metal lines and vias located above. In some embodiments, the contact structure 114 is formed of a conductive material, such as tungsten, aluminum, copper, titanium, tantalum, titanium nitride, tantalum nitride or alloys thereof. The fabrication of the contact structure 114 may include forming a plurality of contact openings in the insulating layer 112, filling the contact openings with a conductive material, and performing a planarization process (e.g., a chemical mechanical polishing (CMP) process or a mechanical grinding process) to make the upper surface of the contact structure 114 flush with the upper surface of the insulating layer 112.

[0071] After forming the contact structure 114, an internal connection structure 124 is formed on the insulating layer 112. The internal connection structure 124 can be used as a redistribution layer (RDL) structure for wiring. The internal connection structure 124 includes a plurality of metal lines and via connection windows formed in a multilayer dielectric layer 122 (also referred to as an inter-metal dielectric (IMD) layer). Metal lines located at the same layer are collectively referred to as a metal layer hereinafter. In some embodiments, the internal connection structure 124 has a metal layer including an uppermost metal layer 120 (which is internally connected together through via connection windows). The metal layer and the via connection windows can be formed of copper or copper alloys, but can also be formed of other metals. In some embodiments, the multilayer dielectric layer 122 is formed of silicon oxide, silicon carbide, silicon nitride, silicon nitride oxide, or a low-k dielectric material. The dielectric constant (k value) of the low-k dielectric material may include carbon-containing low-k dielectric materials, hydrogen silsesquioxane (HSQ), methylsilsesquioxane (MSQ) or similar materials. The multi-layer dielectric layer 122 may be formed by the same or similar method as the insulating layer 112.

[0072] The formation of the metal layer and the via connection window may include a single damascene process and / or a dual damascene process. In a single damascene process, a trench is first formed in one of the multi-layer dielectric layers 122, and then the trench is filled with a conductive material. A planarization process (e.g., a chemical mechanical polishing (CMP) process or a mechanical grinding process) is then performed to remove any excess portion of the conductive material that is higher than the upper surface of the corresponding intermetallic dielectric (IMD) layer, and the metal layer remains in the trench. In a dual damascene process, a trench opening and a via opening are simultaneously formed in the intermetallic dielectric (IMD) layer, and the via opening is located below and connected to the corresponding trench. Then a conductive material is filled into the trench opening and the via opening to form a metal layer and a via connection window. The conductive material may include a diffusion barrier layer and a metal material located on the diffusion barrier layer. The metal material may be made of copper (Cu), copper alloy, aluminum (Al), aluminum alloy, tungsten (W), tungsten alloy, titanium (Ti), titanium alloy, tantalum (Ta) or tantalum alloy. The metal layer and the via connection window can be formed by electroplating, electroless plating, printing, chemical vapor deposition (CVD) process or physical vapor deposition (PVD). The diffusion barrier layer may include titanium, titanium nitride, tantalum, tantalum nitride or similar materials.

[0073] According to some embodiments, Figure 1B and Figure 1C As shown, after forming the inner connection structure 124 , a capacitor structure is formed on the inner connection structure 124 .

[0074] In some embodiments, a selective etching stop layer (not shown) is formed on the interconnect structure 124, and an insulating layer 130 is formed on the etching stop layer. Then, according to some embodiments, a capacitor metal electrode layer 132 is formed on the insulating layer 130, such as Figure 1B As shown. The etching stop layer can be made of silicon carbide (SiC), silicon nitride (Si x N y ), silicon carbide nitride (SiCN), silicon oxycarbide (SiOC), silicon oxycarbon nitride (SiOCN) or other suitable materials. The etch stop layer can be formed by a deposition process, such as chemical vapor deposition (CVD), physical vapor deposition (PVD), atomic layer deposition (ALD) or another suitable process. Furthermore, the insulating layer 130 can be formed of undoped silicate glass (USG), silicon oxide or another suitable material. The insulating layer 130 can be formed by a deposition process, such as chemical vapor deposition (CVD), physical vapor deposition (PVD), atomic layer deposition (ALD) or another suitable process.

[0075] The capacitor metal electrode layer 132 is formed of a conductive material, such as titanium (Ti), titanium nitride (TiN), tantalum (Ta), tantalum nitride (TaN), copper (Cu), copper alloy, aluminum (Al), aluminum (Al) alloy, copper-aluminum alloy (AlCu), tungsten (W) or tungsten (W) alloy or another suitable material.

[0076] The production of the capacitor metal electrode layer 132 includes deposition, lithography and etching processes. The deposition process includes chemical vapor deposition (CVD), physical vapor deposition (PVD), atomic layer deposition (ALD) or a suitable process. The lithography process includes photoresist coating (e.g., spin coating), soft baking, mask alignment, exposure, post-exposure baking, developing photoresist, cleaning and drying (e.g., hard baking). The etching process includes a dry etching process or a wet etching process.

[0077] In some embodiments, after the lithography process, a cleaning process is performed to remove some residues remaining on the capacitor metal electrode layer 132 .

[0078] Then, according to some embodiments of the present disclosure, a capacitor insulating layer 134 is formed on the capacitor metal electrode layer 132, and a capacitor metal electrode layer 136 is formed on the capacitor insulating layer 134. Figure 1C In some embodiments, the capacitor metal electrode layer 136 and the capacitor insulating layer 134 located thereunder are Z-shaped. The capacitor metal electrode layer 136 and the capacitor insulating layer 134 located thereunder each have a lower horizontal portion, an upper horizontal portion, and a vertical portion. The vertical portion extends between the lower horizontal portion and the upper horizontal portion, as shown in FIG. Figure 1C The capacitor structure includes a capacitor metal electrode layer 132, a capacitor insulating layer 134, and a capacitor metal electrode layer 136 to form a metal-insulator-metal (MIM) capacitor 140. The capacitor metal electrode layer 132 is a lower electrode of the metal-insulator-metal (MIM) capacitor 140, and the capacitor metal electrode layer 136 is an upper electrode of the metal-insulator-metal (MIM) capacitor 140. Although not shown, the metal-insulator-metal (MIM) capacitor 140 can be electrically connected to the uppermost metal layer 120 of the inner connection structure 124 through one or more via connection windows.

[0079] In some embodiments, the capacitor insulating layer 134 is formed of a high-k dielectric material. In some embodiments, the high-k dielectric material has a dielectric constant (k value) of not less than 4. For example, the high-k dielectric material may include zirconium dioxide (ZrO2), aluminum oxide (Al2O3), titanium oxide (TiO2), and the like. x O y , where x is a real number and y is a real number), tantalum oxide (Ta x O y, where x is a real number and y is a real number). Titanium oxynitride (Ti x O y N z , where x is a real number, y is a real number, and z is a real number) or tantalum oxynitride (Ta x O y N z , where x is a real number, y is a real number, and z is a real number). In some other embodiments, the capacitor insulating layer 134 is a ZrO2-Al2O3-ZrO2 (ZAZ) laminate layer.

[0080] The capacitor metal electrode layer 136 is formed of a conductive material, such as titanium (Ti), titanium nitride (TiN), tantalum (Ta), tantalum nitride (TaN), copper (Cu), copper alloy, aluminum (Al), aluminum (Al) alloy, copper-aluminum alloy (AlCu), tungsten (W) or tungsten (W) alloy or other suitable materials.

[0081] Then, according to some embodiments, Figure 1D As shown, an insulating layer 142 is formed on the metal-insulator-metal (MIM) capacitor 140. In some embodiments, the materials and methods used to form the insulating layer 142 are the same or similar to the materials and methods used to form the insulating layer 130. The two insulating layers 130 and 142 are sometimes collectively referred to as a passivation layer. Therefore, the metal-insulator-metal (MIM) capacitor 140 is buried in the passivation layer including the insulating layers 130 and 142.

[0082] According to some embodiments, after forming the passivation layer including the insulating layers 130 and 142, a bonding pad 160 is formed on the passivation layer and corresponds to the capacitor structure (eg, metal-insulator-metal (MIM) capacitor 140), such as Figure 1E to Figure 1G More specifically, Figure 1E As shown, an adhesive layer 150 is formed on the insulating layer 142 of the passivation layer, and a conductive layer 152 is formed on the adhesive layer 150, which is used for the subsequent production of the bonding pad 160. In some embodiments, when the conductive layer 152 is formed of a copper-containing material, the adhesive layer 150 can also serve as a diffusion barrier layer. In some other embodiments, when the conductive layer 152 is formed by an electroplating process, the adhesive layer 150 is used as a sub-layer.

[0083] The adhesion layer 150 may be made of a metal material, such as titanium (Ti), titanium alloy, titanium nitride (TiN), tantalum (Ta), tantalum alloy, tantalum nitride (TaN) or other suitable metal materials. Furthermore, the adhesion layer 150 may be formed by a deposition process, such as sputtering, electroplating, chemical vapor deposition (CVD), physical vapor deposition (PVD), atomic layer deposition (ALD) or another suitable process.

[0084] The conductive layer 152 may be made of a metal material, such as aluminum (Al), copper (Cu), aluminum copper (AlCu), or another suitable metal material. In addition, the conductive layer 152 may be formed by a deposition process, such as sputtering, chemical vapor deposition (CVD), physical vapor deposition (PVD), atomic layer deposition (ALD), or other suitable processes.

[0085] Then, in some embodiments, as Figure 1F As shown, the conductive layer 152 is patterned to form grooves 153a on both sides of the bonding pad region (not shown) of the conductive layer 152. More specifically, according to some embodiments, the groove 153a is formed in the conductive layer 152 by lithography and etching processes. After the lithography process is performed, a patterned mask layer 153 (e.g., a photoresist layer) having a width W1 is formed on the conductive layer 152 and is located directly above the bonding pad region of the conductive layer 152. Thereafter, the conductive layer 152 is partially removed by an etching process (e.g., a dry etching process) and using the patterned mask layer 153 as an etching mask layer. In this way, the portion of the conductive layer 152 not covered by the patterned mask layer 153 is removed to form the groove 153a. Therefore, the conductive layer 152 corresponding to the bonding pad region has an upper surface that is higher than the bottom of the groove 153a.

[0086] After forming the groove 153a, the patterned mask layer 153 is removed. Then, in some embodiments, the remaining conductive layer 152 is patterned again to form a bonding pad 160, such as Figure 1G More specifically, according to some embodiments, the bonding pad 160 is formed by a lithography process and an etching process. After the lithography process, a patterned mask layer 154 (e.g., a photoresist layer) having a width W2 is formed on the conductive layer 152. In some embodiments, the width W2 of the patterned mask layer 154 is smaller than the width W1 of the patterned mask layer 153, so the area of ​​the patterned mask layer 154 is smaller than the area of ​​the patterned mask layer 153 (e.g., Figure 1F Afterwards, the conductive layer 152 and the adhesive layer 150 located thereunder are partially removed by an etching process (e.g., a dry etching process) using the patterned mask layer 154 as an etching mask layer. In this way, a portion of the conductive layer 152 and a portion of the adhesive layer 150 are removed in sequence to expose the upper surface of the insulating layer 142, and to form a bonding pad 160 including the remaining conductive layer 152 and the remaining adhesive layer 150. Although not shown, the bonding pad 160 can be electrically connected to the metal-insulator-metal (MIM) capacitor 140 and / or the uppermost metal layer 120 of the inner connection structure 124 through one or more via connection windows.

[0087] like Figure 1GAs shown, since the area of ​​the patterned mask layer 154 is smaller than the area of ​​the patterned mask layer 153, the formed bonding pad 160 has a multi-step edge (or a sidewall with a non-linear profile) 162. In subsequent processes, the patterned mask layer 154 will be removed.

[0088] Figure 3 Depicted are some embodiments of the Figure 1G . More specifically, the multi-step edge (or sidewall with a non-linear profile) 162 of the bonding pad 160 defines a first step 160a and a second step 160b located on the first step 160a. In some embodiments, the first step 160a has a substantially vertical sidewall 161a, and the second step 160b has a substantially vertical sidewall 161b. In some other embodiments, the substantially vertical sidewalls 161a and 161b are substantially perpendicular to the upper surface 142a of the insulating layer 142.

[0089] In these cases, path 155 extends from the upper surface 152a of the bonding pad 160 (as shown at point A) along the sidewall of the non-straight profile (i.e., multi-step edge) 162 of the bonding pad 160 to the upper surface 142a of the insulating layer 142 (as shown at point B) and includes three corners 163a, 163b and 163c. In other words, the upper surface 152a of the bonding pad 160 and the sidewall having a non-linear profile (i.e., a multi-step edge) 162 include three corners 163a, 163b, and 163c. These corners 163a, 163b, and 163c define three turning angles θ1, θ2, and θ3, respectively. The turning angle θ1 is the angle between the substantially vertical sidewall 161b and the extension direction along the upper surface of the second step 160b. The turning angle θ2 is the angle between the extension direction along the substantially vertical sidewall 161b and the upper surface of the first step 160a. The turning angle θ3 is the angle between the substantially vertical sidewall 161a and the extension direction along the upper surface of the first step 160a. The total of the turning angles 163a, 163b, and 163c is greater than 90°. Figure 3 In the illustrated embodiment, since the first step 160a has a substantially vertical sidewall 161a and the second step 160b has a substantially vertical sidewall 161b, the turning angles 163a, 163b and 163c are each substantially equal to 90°.

[0090] Figure 4 FIG. 1 is a partial enlarged cross-sectional view of a bonding pad 160 ′ according to some embodiments. In some embodiments, Figure 1G The bonding pad 160 shown in FIG. 1 may be replaced by Figure 4 In some embodiments, the structure and method for forming the bonding pad 160' are similar to those for forming the bonding pad 160'. Figure 1GThe structure and method of the bonding pad 160 shown in FIG. Similar to the bonding pad 160, the multi-step edge (or sidewall with a non-linear profile) 162' of the bonding pad 160' defines a first step 160a' and a second step 160b' on the first step 160a'. In some embodiments, the first step 160a' has a tapered (or inclined) sidewall 161a', and the second step 160b' has a tapered (or inclined) sidewall 161b'.

[0091] In these cases, the path (not shown, but similar to Figure 3 The path 155 shown in FIG. 1 includes three turning angles from the upper surface of the bonding pad 160' along the side wall of the non-straight profile (i.e., multi-step edge) 162' of the bonding pad 160' to the upper surface of the insulating layer 142. These turning angles define three turning angles θ1', θ2', and θ3'. The turning angle θ1' is the angle between the tapered (or inclined) sidewall 161b' and the extension direction along the upper surface of the second step 160b'. The turning angle θ2' is the angle between the extension direction along the tapered (or inclined) sidewall 161b' and the upper surface of the first step 160a'. The turning angle θ3' is the angle between the extension direction along the tapered (or inclined) sidewall 161a and the extension direction along the upper surface of the first step 160a'. The sum of the turning angles θ1', θ2', and θ3' is greater than 90°. Figure 4 In the illustrated embodiment, since the first step 160a' has a tapered sidewall 161a' and the second step 160b' has a tapered sidewall 161b', the turning angles θ1', θ2' and θ3' are each less than 90°.

[0092] Figure 5 FIG. 1 is a partial enlarged cross-sectional view of a bonding pad 160 "according to some embodiments. In some embodiments, Figure 1G The bonding pad 160 shown in FIG. 1 may be replaced by Figure 5 In some embodiments, the structure and method for forming the bonding pad 160" are similar to those for forming the bonding pad 160". Figure 1G Similar to the bonding pad 160, the multi-step edge (or sidewall with a non-linear profile) 162" of the bonding pad 160" defines a first step 160a", a second step 160b" located on the first step 160a", and a third step 160c" located on the second step 160b". In some embodiments, similar to Figure 3 In the illustrated bonding pad 160 , the first step 160 a ″ has a substantially vertical sidewall 161 a ″, the second step 160 b ″ has a substantially vertical sidewall 161 b ″, and the third step 160 c ″ has a substantially vertical sidewall 161 c ″.

[0093] In these cases, the path (not shown, and similar to Figure 3 The path 155 shown in FIG. 1 includes five corners from the upper surface of the bonding pad 160″ along the sidewall of the non-linear profile (i.e., multi-step edge) 162″ of the bonding pad 160″ to the upper surface of the insulating layer 142. These corners define five turning angles θ4, θ5, θ6, θ7, and θ8. The turning angle θ4 is the angle between the substantially vertical sidewall 161c″ and the extension direction along the upper surface of the third step 160c″. The turning angle θ5 is the angle between the substantially vertical sidewall 161c″ and the extension direction along the upper surface of the second step 160b″. The turning angle θ6 is the angle between the substantially vertical side wall 161b" and the extension direction of the upper surface of the second step 160b". The turning angle θ7 is the angle between the extension direction of the substantially vertical side wall 161b" and the upper surface of the first step 160a". The turning angle θ8 is the angle between the substantially vertical side wall 161a" and the extension direction of the upper surface of the first step 160a". The sum of the turning angles θ4, θ5, θ6, θ7 and θ8 is greater than 90°. Similar to the bonding pad 160, at Figure 5 In the illustrated embodiment, steering angles θ4, θ5, θ6, θ7, and θ8 are each substantially equal to 90°. In some embodiments, the horizontal distance between sidewall 161a″ and sidewall 161b″ is different from the horizontal distance between sidewall 161b″ and sidewall 161c″. For example, the horizontal distance between sidewall 161a″ and sidewall 161b″ is greater than the horizontal distance between sidewall 161b″ and sidewall 161c″.

[0094] In these cases, the upper surface area of ​​the first step 160a" is also greater than the upper surface area of ​​the second step 160b".

[0095] Figure 6 FIG. 1 is a partial enlarged cross-sectional view of a bonding pad 160 ′″ according to some embodiments. In some embodiments, Figure 1G The bonding pad 160 shown in FIG. 1 may be replaced by Figure 6 In some embodiments, the structure and method for forming the bonding pad 160'" are similar to those for forming the bonding pad 160'. Figure 1G Similar to the bonding pad 160, the multi-step edge (or sidewall with a non-linear profile) 162'' of the bonding pad 160'' defines a first step 160a'', a second step 160b'' located on the first step 160a'', and a third step 160c'' located on the second step 160b''. In some embodiments, similar to Figure 4The bonding pad 160'' shown in FIG. 1 has a first step 160a'' having a tapered (or inclined) sidewall 161a'', a second step 160b'' having a tapered (or inclined) sidewall 161b'', and a third step 160c'' having a tapered (or inclined) sidewall 161c''.

[0096] In these cases, the path (not shown and similar to Figure 3 The path 155 shown in FIG. 1 includes five corners from the upper surface of the bonding pad 160'" along the sidewall of the non-straight profile (i.e., multi-step edge) 162'" of the bonding pad 160'" to the upper surface of the insulating layer 142. These corners define five turning angles θ4', θ5', θ6', θ7', and θ8'. The turning angle θ4' is the angle between the tapered (or inclined) sidewall 161c'" and the extension direction along the upper surface of the third step 160c'". The turning angle θ5' is the angle between the extension direction along the tapered (or inclined) sidewall 161c'" and the upper surface of the second step 160b'". The turning angle θ6' is the angle between the extending direction along the tapered (or inclined) side wall 161b'" and the upper surface of the second step 160b'". The turning angle θ7' is the angle between the extending direction along the tapered (or inclined) side wall 161b'" and the upper surface of the first step 160a'". The turning angle θ8' is the angle between the extending direction along the tapered (or inclined) side wall 161a'" and the upper surface of the first step 160a'". The sum of the turning angles θ4', θ5', θ6', θ7' and θ8' is greater than 90°. Similar to the bonding pad 160', at Figure 6 In the illustrated embodiment, steering angles θ4', θ5', θ6', θ7', and θ8' are each less than 90°. In some embodiments, the horizontal distance between side wall 161a'" and side wall 161b'" is different from the horizontal distance between side wall 161b'" and side wall 161c'". For example, the horizontal distance between side wall 161a'" and side wall 161b'" is greater than the horizontal distance between side wall 161b'" and side wall 161c'".

[0097] In these cases, the upper surface area of ​​the first step 160a'" is also greater than the upper surface area of ​​the second step 160b'".

[0098] Figure 7 FIG. 2 is a schematic diagram of a partial enlarged cross-section of a bonding pad 260 according to some embodiments. In some embodiments, Figure 1G The bonding pad 160 shown in FIG. 1 may be replaced by Figure 7 In some embodiments, the structure and method for forming the bonding pad 260 are similar to those for forming the bonding pad 260. Figure 1G The structure and method of the bonding pad 160 shown in FIG. Figure 5 The bonding pad 160 shown in FIG. Figure 6 In the bonding pad 160'' shown in the figure, the upper surface of the bonding pad 260 and the sidewall with multi-step edges (or called the sidewall with a non-straight profile) 262 define three curved steps. The three curved steps form a curved profile with at least two curved corners (for example, it may have five curved corners). In some embodiments, each curved step has a concave or convex profile, and these concave and convex profiles are arranged alternately.

[0099] It should be understood that the number of steps defined by the multi-step edge of the bonding pad depends on the design requirements and is not limited to Figures 3 to 7 For example, the multi-step edge of the bonding pad may define more than three steps.

[0100] According to some embodiments, after removing the patterned mask layer 154 to expose the upper surface 152a of the bonding pad 160, an insulating layer 170 (also referred to as a passivation layer) conformally covers the upper surface 152a of the bonding pad 160 and the multi-step edge 162, such as Figure 1H As shown. In some embodiments, the compliant insulating layer (or passivation protective layer) 170 also extends to cover the insulating layer 142. The insulating layer 170 serves as a protective layer for the bonding pad 160 below, and has an opening 172 to expose a portion of the upper surface 152a of the bonding pad 160. In some embodiments, the insulating layer 170 is a single layer or multi-layer structure. For example, the insulating layer 170 is a multi-layer structure. In this case, the insulating layer 170 includes an undoped silicate glass (USG) layer and a silicon nitride (Si x N y ) layer. To simplify the illustration, only a single layer is depicted. The formation of the insulating layer 170 includes deposition, lithography and etching processes. The deposition process includes chemical vapor deposition (CVD), physical vapor deposition (PVD), atomic layer deposition (ALD) or a suitable process. The lithography process includes photoresist coating (e.g., spin coating), soft baking, mask alignment, exposure, post-exposure baking, developing photoresist, cleaning and drying (e.g., hard baking). The etching process includes a dry etching process or a wet etching process.

[0101] Figures 3 to 6The bonding pads 160, 160', 160", and 160'" shown in the figure each serve as a stress buffer or crack stopper to prevent cracks from extending into the metal-insulator-metal (MIM) capacitor 140. In some embodiments, cracks are formed in the passivation protective layer (i.e., insulating layer 170) above the bonding pad 160 and the insulating layer 142, and then the cracks penetrate into the insulating layer 142 below. The thick bonding pad 160, 160', 160", or 160'" exhibits ductility and plasticity characteristics because it is formed of a metal material. In addition, the multi-step edges 162, 162', 162", or 162'" provide more surface area to share the stress within the insulating layer 170. Therefore, the crack can stop at the bonding pad 160, 160', 160", or 160'". As a result, it is difficult for the crack to penetrate into the MIM capacitor 140 , so that the embedded MIM capacitor 140 is not damaged by the crack.

[0102] According to some embodiments, after forming the insulating layer 170, an insulating layer 176 is formed on the insulating layer 170, such as Fig. 1I In some embodiments, the insulating layer 176 also extends to the opening 172 of the insulating layer 170 (eg, Figure 1H ) and exposes the upper surface 152a of the bonding pad 160 through the opening 178 formed therein. The insulating layer 176 also serves as a protective layer for the passivation protective layer (i.e., the insulating layer 170) located below. The insulating layer 176 can be formed of one or more polymer materials, or include one or more polymer materials, such as polybenzoxazole (PBO), polyimide (PI), one or more other suitable polymer materials or a combination thereof. The production of the insulating layer 176 includes deposition, lithography and etching processes. The deposition process includes spin coating, chemical vapor deposition (CVD) or a suitable process. The lithography process includes photoresist coating (e.g., spin coating), soft baking, mask alignment, exposure, post-exposure baking, developing photoresist, cleaning and drying (e.g., hard baking). The etching process includes a dry etching process or a wet etching process.

[0103] Then, according to some embodiments, an under bump metallurgy (UBM) layer 180 is formed in the opening 178 (eg, Fig. 1I As shown) and located above the insulating layer 176 covering a portion of the bonding pad 160, as shown Figure 1JAs shown. The under bump metallization (UBM) layer 180 directly contacts the exposed upper surface 152 of the bonding pad 160 through the opening 178. The under bump metallization (UBM) layer 180 may be formed of a conductive material, such as copper (Cu), a copper alloy, aluminum (Al), an aluminum alloy, tungsten (W), a tungsten alloy, titanium (Ti), a titanium alloy, tantalum (Ta) or a tantalum alloy. In addition, the under bump metallization (UBM) layer 180 may include an adhesion layer and / or a wetting layer. In some embodiments, the under bump metallization (UBM) layer 180 also includes a copper seed layer. In some embodiments, the under bump metallization (UBM) layer 180 includes an adhesion layer formed of Ti / Cu and a wetting layer formed of Cu. In some embodiments, the under bump metallization (UBM) layer 180 is formed by an electroplating process, such as an electrochemical plating process or an electroless process.

[0104] According to some embodiments, after forming the under bump metallization (UBM) layer 180, a bump 182 is formed on the under bump metallization (UBM) layer 180, and a solder material region 192 is formed on the bump 182, such as Figure 1K The bump 182 and the underlying under bump metal (UBM) layer 180 are sometimes collectively referred to as a connector 190. After forming the solder material region 192, a semiconductor device structure 200 is formed. The bump 182 is electrically connected to the bonding pad 160 through the under bump metal (UBM) layer 180.

[0105] In some embodiments, the bump 182 is formed of a metal layer, such as copper, copper alloy, nickel, nickel alloy, aluminum, aluminum alloy, tin, tin alloy, lead, lead alloy, silver, silver alloy or a combination thereof. In some embodiments, the bump 182 is formed by an electroplating process, such as an electrochemical plating process or an electroless process. The solder material region 192 can be formed of a Sn-Ag alloy, a Sn-Ag-Cu alloy or a similar material, and can be lead-free or lead-containing. The solder material region 192 can be formed by electroplating.

[0106] Figure 2A FIG. 3 is a cross-sectional view of a package structure 300 according to some embodiments. In some embodiments, the package structure 300 may be a chip-on-wafer-on-substrate (CoWoS) package or other suitable packages. In some embodiments, the package structure 300 includes Figure 1K The semiconductor device structure 200 shown in FIG. 1 is bonded to a conductive feature 252 in a package component 250 (which may be an interposer, a package substrate, a package body, a device chip, a printed circuit board, or the like). In some embodiments, the bonding may be performed via a solder material region 192.

[0107] In some embodiments, the package structure 300 further includes a primer material layer 260 formed on the semiconductor device structure 200 (eg, Figure 1K ) and the gap between the package component 250. The bottom glue material layer 260 can directly contact the upper surface of the insulating layer 176 of the semiconductor device structure 200, and can contact the sidewall of the connector 190 of the semiconductor device structure 200 to protect the connector 190. Furthermore, a sealing layer 270 is formed on the bottom glue material layer 260. The sealing layer 270 surrounds and protects the semiconductor device structure 200.

[0108] In some embodiments, the primer material layer 260 is formed by a polymer material. For example, the primer material layer 260 may include an epoxy resin. In some embodiments, the primer material layer 260 includes a filler dispersed in the epoxy resin. In some embodiments, the making of the primer material layer 260 involves an injection process, a spin coating process, a dispensing process, a lamination process, a coating process, one or more other suitable processes or a combination thereof. In some embodiments, a thermal curing process is used during the formation of the primer material layer 260.

[0109] The sealing layer 270 is formed of a molding compound material. The molding compound material may include a polymer material, such as an epoxy resin having a filler dispersed therein. In some embodiments, a liquid molding compound material is applied to the semiconductor device 200. A thermal process is then used to cure the liquid molding compound material and convert it into the sealing layer 270.

[0110] In some embodiments, the package structure 300 further includes a connector 254 (eg, a solder ball) formed on the package component 250 and facing away from the underfill material layer 260 .

[0111] The semiconductor device 200 and the package component 250 in the package structure 300 have different coefficients of thermal expansion (CTE), and cracks are formed due to the mismatch of the coefficients of thermal expansion (CTE). In some embodiments, the cracks are formed in the insulating layer 170 (i.e., the passivation layer), and then the cracks pass through the insulating layer 170. If a bonding pad without a multi-step edge (or a sidewall with a non-linear profile) is formed on the metal-insulator-metal (MIM) capacitor 140, the cracks may penetrate the film layer in the metal-insulator-metal (MIM) capacitor 140, and the film layer of the metal-insulator-metal (MIM) capacitor 140 may delaminate. In order to prevent the expansion of the cracks, a bonding pad 160 with a multi-step edge 162 is formed between the insulating layer 170 and the metal-insulator-metal (MIM) capacitor 140. Therefore, the buried metal-insulator-metal (MIM) capacitor 140 is not damaged by the cracks, and the quality, yield and reliability of the package structure 300 are improved.

[0112] Figure 2B FIG. 4 is a cross-sectional view of a package structure 400 according to some embodiments. Some processes and materials used to form the package structure 400 are similar or the same as those used to form the package structure 400. Figure 2A The manufacturing process and materials of the package structure 300 are not repeated here. The structure of the package structure 400 is similar to that of the package structure 300. Different from the package structure 300, the package structure 400 includes a capacitor structure composed of a capacitor metal electrode layer 132, a capacitor insulating layer 134, a capacitor metal electrode layer 136, a capacitor insulating layer 138 and a capacitor metal electrode layer 139, wherein the capacitor insulating layer 138 is formed on the capacitor metal electrode layer 136, and the capacitor metal electrode layer 139 is formed on the capacitor insulating layer 138. The capacitor structure includes two stacked metal-insulator-metal (MIM) capacitors, and is sometimes referred to as a super high density metal-insulator-metal (SMIM, SHDMIM) capacitor 140a.

[0113] In some other embodiments, the super high density metal-insulator-metal (SHDMIM) capacitor 140a includes more than two metal-insulator-metal (MIM) capacitors, which are stacked between the inner connection structure 124 and the bonding pad 160 and buried in the passivation layer including the insulating layers 130 and 142.

[0114] An embodiment of a semiconductor device structure and a method for manufacturing the same are provided. The semiconductor device structure includes a capacitor structure embedded in a first insulating layer. A bonding pad having a multi-step edge is formed on the first insulating layer and corresponds to the capacitor structure. A second insulating layer conformally covers the upper surface and the multi-step edge of the bonding pad. The multi-step edge of the bonding pad provides more surface area to share the stress in the second insulating layer. In this way, the bonding pad having a multi-step edge can be used as a stress buffer or a crack stopper to prevent cracks from expanding or penetrating into the capacitor structure below the bonding pad. Since the capacitor structure is protected by the bonding pad having a multi-step edge, the generation of cracks can be reduced or prevented, thereby improving the quality, yield and reliability of the semiconductor device structure.

[0115] In some embodiments, a semiconductor device structure is provided. The semiconductor device structure includes a first insulating layer formed on a conductive feature component, and a capacitor structure embedded in the first insulating layer. The semiconductor device also includes a bonding pad formed on the first insulating layer and corresponding to the capacitor structure. The bonding pad has an upper surface and a multi-step edge to form at least three corners. Furthermore, the semiconductor device structure includes a second insulating layer, which conformably covers at least three corners formed by the upper surface of the bonding pad and the multi-step edge.

[0116] In some embodiments, a semiconductor device structure is provided. The semiconductor device structure includes a first insulating layer formed on an uppermost metal layer of an internal connection structure, and a metal-insulator-metal capacitor buried in the first insulating layer. The semiconductor device structure also includes a bonding pad formed above the metal-insulator-metal capacitor and separated from the metal-insulator-metal capacitor by the first insulating layer. The bonding pad has a side wall having a non-linear profile. A path from an upper surface of the bonding pad along the side wall of the bonding pad to an upper surface of the first insulating layer includes at least three turning angles. The sum of the turning angles is greater than 90°.

[0117] In some embodiments, a method for forming a semiconductor device structure is provided. The method includes forming a first insulating layer and a metal-insulator-metal capacitor on a topmost metal layer of an internal connection structure. The metal-insulator-metal capacitor is buried in the first insulating layer. The method also includes forming a conductive layer on the first insulating layer and patterning the conductive layer to form a bonding pad on the first insulating layer, corresponding to the metal-insulator-metal capacitor. The bonding pad has a multi-step edge. The method also includes conformally forming a second insulating layer to cover an upper surface and multi-step edges of the bonding pad. In addition, the method includes forming a third insulating layer on the second insulating layer. The method also includes forming an under-bump metal layer on the third insulating layer, and passing through the third insulating layer and the second insulating layer to contact the upper surface of the bonding pad.

[0118] The above briefly describes the features of several embodiments of the present invention, so that those with ordinary knowledge in the art can more easily understand the types of the present disclosure. Anyone with ordinary knowledge in the art should understand that the present disclosure can be easily used as a basis for the change or design of other processes or structures to achieve the same purpose and / or obtain the same advantages as the embodiments described herein. Anyone with ordinary knowledge in the art can also understand that structures equivalent to the above do not depart from the spirit and scope of protection of the present disclosure, and can be changed, replaced and modified without departing from the spirit and scope of the present disclosure.

Claims

1. A semiconductor device structure, comprising: a first insulating layer formed on a conductive feature; a capacitor structure embedded in the first insulating layer; a bonding pad formed on the first insulating layer and corresponding to the capacitor structure, wherein the bonding pad has an upper surface and a multi-step edge to form at least three corners; a second insulating layer conformably covering the at least three corners formed by the upper surface of the bonding pad and the multi-step edge; a third insulating layer formed on the second insulating layer; as well as An under bump metal layer is formed on the third insulating layer and passes through the third insulating layer and the second insulating layer to contact the upper surface of the bonding pad.

2. The semiconductor device structure according to claim 1, wherein: The multi-step edge of the bonding pad defines a first step and a second step located on the first step, wherein the first step and the second step each have a substantially vertical sidewall.

3. The semiconductor device structure according to claim 1, wherein: The multi-step edge of the bonding pad defines a first step and a second step located on the first step, wherein the first step and the second step each have a tapered sidewall.

4. The semiconductor device structure according to claim 1, wherein: The multi-step edge of the bonding pad defines a first step, a second step on the first step, and a third step on the second step, wherein the first step, the second step, and the third step each have a substantially vertical sidewall.

5. The semiconductor device structure according to claim 4, wherein: An upper surface area of ​​the first step is different from an upper surface area of ​​the second step.

6. The semiconductor device structure according to claim 1, wherein: The multi-step edge of the bonding pad forms a curved profile with at least two corners.

7. The semiconductor device structure according to claim 1, wherein: The capacitor structure is a metal-insulator-metal capacitor and comprises: a first capacitor metal electrode layer; a first capacitor insulating layer formed on the first capacitor metal electrode layer; and A second capacitor metal electrode layer is formed on the first capacitor insulating layer.

8. The semiconductor device structure of claim 7, further comprising: a second capacitor insulating layer formed on the capacitor metal electrode layer; as well as A third capacitor metal electrode layer is formed on the second capacitor insulating layer.

9. The semiconductor device structure according to claim 1, wherein: The conductive feature is a topmost metal layer of an interconnect structure.

10. A semiconductor device structure, comprising: a first insulating layer formed on an uppermost metal layer of an inner connection structure; a metal-insulator-metal capacitor embedded in the first insulating layer; A bonding pad is formed on the metal-insulator-metal capacitor and separated from the metal-insulator-metal capacitor by the first insulating layer, wherein the bonding pad has a side wall having a non-linear profile, wherein a path from an upper surface of the bonding pad along the side wall of the bonding pad to an upper surface of the first insulating layer includes at least three turning angles, and the sum of the at least three turning angles is greater than 90°.

11. The semiconductor device structure of claim 10, further comprising: a second insulating layer conformably covering an upper surface and the side wall of the bonding pad; a third insulating layer formed on the second insulating layer; as well as An under bump metal layer is formed on the third insulating layer and passes through the third insulating layer and the second insulating layer to contact the upper surface of the bonding pad.

12. The semiconductor device structure according to claim 10, wherein: The at least three steering angles are each substantially equal to 90°.

13. The semiconductor device structure according to claim 10, wherein: The at least three turning angles are each smaller than 90°.

14. The semiconductor device structure according to claim 10, wherein: The side wall with the non-linear profile forms a first step, a second step located on the first step, and a third step located on the second step, wherein an upper surface area of ​​the first step is greater than an upper surface area of ​​the second step.

15. The semiconductor device structure according to claim 10, wherein: The non-straight profile is a curved profile.

16. A method for manufacturing a semiconductor device structure, comprising: Forming a first insulating layer and a metal-insulator-metal capacitor on an uppermost metal layer of an inner connection structure, wherein the metal-insulator-metal capacitor is buried in the first insulating layer; forming a conductive layer on the first insulating layer; Patterning the conductive layer to form a bonding pad on the first insulating layer and corresponding to the metal-insulator-metal capacitor, wherein the bonding pad has an upper surface and a multi-step edge to form at least three corners; Conformally forming a second insulating layer to cover the at least three corners formed by the upper surface of the bonding pad and the multi-step edge; forming a third insulating layer on the second insulating layer; as well as An under bump metal layer is formed on the third insulating layer and passes through the third insulating layer and the second insulating layer to contact the upper surface of the bonding pad.

17. The method for manufacturing a semiconductor device structure according to claim 16, wherein: The conductive layer is patterned by a first etching process using a first mask layer as an etching mask and subsequently a second etching process using a second mask layer as an etching mask, wherein the first mask layer has an area larger than the second mask layer.

18. The method for manufacturing a semiconductor device structure according to claim 16, wherein: A path from the upper surface of the bonding pad along the multi-step edge of the bonding pad to an upper surface of the first insulating layer includes at least three turning angles corresponding to the at least three turning angles, and the sum of the at least three turning angles is greater than 90°. 19 . The method for manufacturing a semiconductor device structure as claimed in claim 18 , wherein each of the at least three turning angles is substantially equal to or less than 90°.

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