Integrated semiconductor device, transistor and method for manufacturing protruding field effect transistor

Abstract

A transistor, an integrated semiconductor device and a manufacturing method are provided. The transistor includes: a dielectric layer having a plurality of dielectric protrusions; a channel layer that conformally covers the protrusions of the dielectric layer to form a plurality of grooves between two adjacent dielectric protrusions; and a gate layer disposed on the channel layer. The gate layer 106 has a plurality of gate protrusions coupled to the grooves. The transistor also includes an active region next to the gate layer. The active region is electrically connected to the channel layer.

Description

Technical Field

[0001] Embodiments of the present application relate to integrated semiconductor devices, transistors, and methods of manufacturing protruding field effect transistors. Background Art

[0002] In the semiconductor industry, it is always desirable to increase the area density of integrated circuits. To this end, individual transistors have become smaller and smaller. However, the speed at which individual transistors can be made smaller has been slowing down. It may be advantageous to move peripheral transistors from the front end of line (FEOL) of manufacturing to the back end of line (BEOL) of manufacturing, because functions can be added in the BEOL, while valuable chip area can be made available in the FEOL. Thin film transistors (TFTs) made of oxide semiconductors are an attractive option for BEOL integration, because TFTs can be processed at low temperatures and therefore will not damage previously manufactured devices. However, thin film transistors are generally planar. Therefore, they have a relatively large footprint, which hinders their use for wiring and is therefore not conducive to chip area scaling. Summary of the invention

[0003] Some embodiments of the present application provide a transistor, comprising: a dielectric layer having a plurality of dielectric protrusions; a channel layer conformally covering the plurality of dielectric protrusions to form a plurality of grooves between two adjacent dielectric protrusions; a gate layer disposed on the channel layer, wherein the gate layer has a plurality of gate protrusions matched in the grooves; and an active region formed on either side of the gate layer, wherein the active region is electrically connected to the channel layer.

[0004] Other embodiments of the present application provide an integrated semiconductor device, comprising: a protrusion field effect transistor located in the back-end of the line (BEOL) portion of the integrated semiconductor device, the protrusion field effect transistor comprising: a dielectric layer having a plurality of dielectric protrusions; a channel layer conformally covering the plurality of dielectric protrusions to form a plurality of grooves between two adjacent dielectric protrusions; a gate layer disposed on the channel layer, wherein the gate layer has a plurality of gate protrusions matched in the grooves; and an active region formed on either side of the gate layer, wherein the active region is electrically connected to the channel layer.

[0005] Still other embodiments of the present application provide a method for manufacturing a protrusion field effect transistor, comprising: providing a substrate, the substrate comprising a dielectric layer having a plurality of dielectric protrusions; conformally forming a channel layer covering the plurality of dielectric protrusions to form a plurality of grooves between two adjacent dielectric protrusions; forming a gate layer disposed on the channel layer, wherein the gate layer has a plurality of gate protrusions matched in the grooves; and forming an active region on either side of the gate layer, wherein the active region is electrically connected to the channel layer. BRIEF DESCRIPTION OF THE DRAWINGS

[0006] Aspects of the present invention will be best understood from the following detailed description when read in conjunction with the accompanying drawings. It should be noted that, in accordance with standard practice in the industry, the various components are not drawn to scale. In fact, the dimensions of the various components may be arbitrarily increased or decreased for clarity of discussion.

[0007] Figure 1A is a vertical cross-sectional view of a first exemplary structure before forming a protrusion field effect transistor array according to an embodiment of the present invention.

[0008] Figure 1B is a vertical cross-sectional view of a first exemplary structure after forming a protrusion field effect transistor array according to an embodiment of the present invention.

[0009] Figure 1C is a vertical cross-sectional view of the first exemplary structure after forming a high-level metal interconnect structure according to an embodiment of the present invention.

[0010] Figure 2A is a top view illustrating a step of forming a protrusion in a substrate in a method of manufacturing a transistor according to an embodiment of the present invention.

[0011] Figure 2B It passes through Figure 2A A vertical cross-sectional view along line AA'.

[0012] Figure 2C It passes through Figure 2A A vertical cross-sectional view of line BB'.

[0013] Figure 3A is a top view illustrating a step of depositing a continuous channel layer over a substrate in a method of manufacturing a transistor according to an embodiment of the present invention.

[0014] Figure 3B It passes through Figure 3A A vertical cross-sectional view along line AA'.

[0015] Figure 3C It passes through Figure 3A A vertical cross-sectional view of line BB'.

[0016] Figure 4A is a top view illustrating a step of patterning a channel layer in a method of manufacturing a transistor according to an embodiment of the present invention.

[0017] Figure 4B It passes through Figure 4A A vertical cross-sectional view along line AA'.

[0018] Figure 4C It passes through Figure 4A A vertical cross-sectional view of line BB'.

[0019] Figure 5A is a top view illustrating a step of depositing a high-k dielectric layer and a metal gate layer over a channel layer in a method of manufacturing a transistor according to an embodiment of the present invention.

[0020] Figure 5B It passes through Figure 5A A vertical cross-sectional view along line AA'.

[0021] Figure 5C It passes through Figure 5A A vertical cross-sectional view of line BB'.

[0022] Fig. 6A is a top view illustrating a step of performing ion implantation on a channel layer to form an active region in a method of manufacturing a transistor according to an embodiment of the present invention.

[0023] Figure 6B It passes through Fig. 6A A vertical cross-sectional view along line AA'.

[0024] Figure 6C It passes through Fig. 6A A vertical cross-sectional view of line BB'.

[0025] Fig. 7A FIG. 1 is a diagram showing a method for manufacturing a transistor according to an embodiment of the present invention. FIG. 6A to FIG. 6C A top view of the steps of depositing an interconnect level dielectric layer and forming active area contacts over the intermediate structure is shown.

[0026] Figure 7B It passes through Fig. 7A A vertical cross-sectional view along line AA'.

[0027] Figure 7C It passes through Fig. 7A A vertical cross-sectional view of line BB'.

[0028] Fig. 8A is a diagram showing the embodiment of the present invention. FIG. 7A to FIG. 7C A top view of an alternative embodiment of a transistor in which protrusions are formed in a direction perpendicular to the direction of the protrusions formed in the illustrated embodiment.

[0029] Figure 8B It passes through Fig. 8A A vertical cross-sectional view along line AA'.

[0030] Figure 8C It passes through Fig. 8A A vertical cross-sectional view of line BB'.

[0031] Fig. 9 is a top view showing an alternative embodiment of a substrate having a two-dimensional array of protrusions according to an embodiment of the present invention.

[0032] Fig. 10A FIG. 1 is a diagram showing a method of performing a Fig. 9 Top view of an alternative embodiment of a transistor having a two-dimensional protrusion array made on a substrate shown in FIG.

[0033] Fig. 10B It passes through Fig. 10A A vertical cross-sectional view along line AA'.

[0034] Fig. 10C It passes through Fig. 10A A vertical cross-sectional view of line BB'.

[0035] Fig.11A is a top view illustrating an alternative embodiment of a substrate in which protrusions have a triangular cross-sectional profile in accordance with an embodiment of the present invention.

[0036] Fig. 11B It passes through Fig.11A A vertical cross-sectional view along line AA'.

[0037] Fig. 11C It passes through Fig.11A A vertical cross-sectional view of line BB'.

[0038] Fig. 12A is a top view illustrating an alternative embodiment of a substrate in which protrusions have rounded triangular cross-sectional profiles in accordance with an embodiment of the present invention.

[0039] Fig. 12B It passes through Fig. 12A A vertical cross-sectional view along line AA'.

[0040] Fig. 12C It passes through Fig. 12A A vertical cross-sectional view of line BB'.

[0041] Fig.13 is a flow chart showing the general processing steps of the method of the present invention. DETAILED DESCRIPTION

[0042] The following disclosure provides many different embodiments or examples for realizing the different features of the provided subject matter. Specific examples of components and arrangements are described below to simplify the present invention. Of course, these are merely examples and are not intended to limit the present invention. For example, in the following description, forming a first component above or on a second component may include an embodiment in which the first component and the second component are directly contacted, and may also include an embodiment in which an additional component may be formed between the first component and the second component so that the first component and the second component may not be in direct contact. In addition, the present invention may repeat reference numerals and / or characters in various examples. This repetition is for the purpose of simplicity and clarity, and does not itself indicate the relationship between the various embodiments and / or configurations discussed.

[0043] Furthermore, for ease of description, spatially relative terms such as "below," "beneath," "lower," "above," "upper," etc. may be used herein to describe the relationship of one element or component to another (or additional) elements or components as shown in the figures. The spatially relative terms are intended to encompass different orientations of the device in use or operation in addition to the orientation depicted in the figures. The device may be otherwise oriented (rotated 90 degrees or at other orientations), and the spatially relative descriptors used herein should likewise be interpreted accordingly.

[0044] The present invention relates to semiconductor devices, and in particular to protrusion field effect transistors and methods for forming the same. Embodiments also include integrated circuits having protrusion field effect transistors, in particular protrusion thin film field effect transistors located in BEOL. In various embodiments, the protrusion field effect transistor may have one or more protrusions having a protrusion width P of 3-30 nm. W and a protrusion height P of 10-250nm H .

[0045] Thin-film transistors (TFTs) have several advantages for BEOL integration. For example, TFTs can be processed at low temperatures, and functionality can be added to the BEOL while valuable chip area can be made available in the FEOL. The use of TFTs in the BEOL can be used as a scaling path to 3nm node manufacturing (N3) or beyond by moving peripheral devices (such as power gates or input / output (I / O) devices) from the FEOL to higher metal levels of the BEOL. For a given device, moving TFTs from the FEOL to the BEOL can produce an area reduction of about 5-10%.

[0046] TFTs that can be moved from FEOL to BEOL include, but are not limited to, power gates, input / output elements, and memory selectors. In current technology, a power gate is a logic transistor located in the FEOL. A power gate can be used to turn off a logic block in standby mode, thereby reducing static power consumption. I / O devices are interfaces between computing elements (e.g., a CPU) and the outside world (e.g., a hard drive) and are also processed in the FEOL. Selectors for storage elements, such as magnetoresistive random access memory (MRAM) or resistive random access memory (RRAM) are currently located in the FEOL and can be moved to the BEOL. Typically, each storage element has a selector TFT.

[0047] Compared with the top-gate transistor in which the gate electrode is located at the top of the transistor, the back-gate or bottom-gate transistor has a gate electrode at the bottom of the TFT. In general, the bottom-gate TFT can be manufactured as follows. First, a gate metal layer can be deposited on a substrate and the gate metal layer can be patterned to form a gate electrode. The substrate can be made of any suitable material, such as silicon or silicon on insulator. The gate metal can be made of copper, aluminum, zirconium, titanium, tungsten, tantalum, ruthenium, palladium, platinum, cobalt, nickel or its alloy. Other suitable materials are within the conceivable scope of the present invention. The gate metal can be deposited by any suitable technique, such as chemical vapor deposition (CVD), physical vapor deposition (PVD), plasma enhanced chemical vapor deposition (PECVD) or atomic layer deposition (ALD).

[0048] Next, a high-k dielectric layer may be deposited over the gate electrode. High-k dielectric materials are materials with a higher dielectric constant than silicon dioxide, and include, but are not limited to, hafnium dioxide (HfO2), hafnium silicon oxide (HfSiO), hafnium tantalum oxide (HfTaO), hafnium titanium oxide (HfTiO), hafnium zirconium oxide (HfZrO), zirconium oxide, titanium oxide, aluminum oxide, and hafnium dioxide-aluminum oxide (HfO2-Al2O3). Other suitable materials are within the contemplated scope of the present invention.

[0049] Next, a semiconductor material layer can be deposited over the high-k dielectric layer. The semiconductor material layer can be patterned and ion implanted to form an active region (source / drain region) and a channel region between the active regions. The semiconductor material can be made of amorphous silicon or semiconductor oxides, such as InGaZnO, InWO, InZnO, InSnO, GaOx, InOx, etc. Other suitable materials are within the conceivable scope of the present invention. The semiconductor material can be formed by any suitable method, such as CVD, PECVD or atomic layer deposition ALD.

[0050] Figure 1A is a vertical cross-sectional view of a first exemplary structure before forming a protrusion field effect transistor array according to an embodiment of the present invention. Figure 1A , wherein a first exemplary structure according to an embodiment of the present invention is shown before forming an array of protruding field effect transistors. The first exemplary structure includes a substrate 8, which includes a semiconductor material layer 10. The substrate 8 may include a bulk semiconductor substrate, such as a silicon substrate, wherein the semiconductor material layer extends continuously from the top surface of the substrate 8 to the bottom surface of the substrate 8, or an insulator-on-semiconductor layer including the semiconductor material layer 10, the semiconductor material layer 10 being the top semiconductor layer above a buried insulator layer (such as a silicon oxide layer). The exemplary structure may include various device regions, which may include a memory array region 100, in which at least one array of protruding field effect transistors may be subsequently formed. The exemplary structure may also include a peripheral region 200, in which electrical connections between each array of protruding field effect transistors and a peripheral circuit including field effect transistors may be subsequently formed. The regions of the memory array region 100 and the peripheral region 200 may be used to form various elements of the peripheral circuit.

[0051] Semiconductor devices such as field effect transistors can be formed on and / or in the semiconductor material layer 10. For example, a shallow trench isolation structure 12 can be formed in the upper portion of the semiconductor material layer 10 by forming a shallow trench and then filling the shallow trench with a dielectric material such as silicon oxide. Other suitable dielectric materials are within the contemplated scope of the present invention. Various doped wells (not explicitly shown) can be formed in various regions of the upper portion of the semiconductor material layer 10 by performing a masked ion implantation process.

[0052] A gate structure 20 may be formed above the top surface of the substrate 8 by depositing and patterning a gate dielectric layer, a gate electrode layer, and a gate cap dielectric layer. Each gate structure 20 may include a vertical stack of a gate dielectric 22, a gate electrode 24, and a gate cap dielectric 28, which are referred to herein as gate stacks (22, 24, 28). An ion implantation process may be performed to form an extended implant region, which may include a source extension region and a drain extension region. A dielectric gate spacer 26 may be formed around the gate stack (22, 24, 28). Each component of the gate stack (22, 24, 28) and the dielectric gate spacer 26 constitutes the gate structure 20. An additional ion implantation process may be performed, which uses the gate structure 20 as a self-aligned implantation mask to form a deep active region. Such a deep active region may include a deep source region and a deep drain region. The upper portion of the deep active region may overlap with a portion of the extended implant region. Each combination of the extended implant region and the deep active region can constitute an active region 14, which can be a source region or a drain region, depending on the electrical bias. A semiconductor channel 15 can be formed below each gate stack (22, 24, 28) between adjacent pairs of active regions 14. A metal-semiconductor alloy region 18 can be formed on the top surface of each active region 14. Field effect transistors can be formed on and / or in the semiconductor material layer 10. Each field effect transistor may include a gate structure 20, a semiconductor channel 15, a pair of active regions 14 (one of which is used as a source region and the other as a drain region) and an optional metal-semiconductor alloy region 18. A complementary metal oxide semiconductor (CMOS) circuit 330 can be provided on the semiconductor material layer 10, which may include peripheral circuits for an array of subsequently formed protruding field effect transistors.

[0053] As mentioned above and Figure 1A As shown, the transistors in circuit 330 may be planar transistors. However, as discussed in more detail below, the planar transistors shown in circuit 330 may also be replaced with FIG. 2A to FIG. 12B FinFET or protrusion field effect transistor described. That is, in various embodiments, the semiconductor channel 15 of these transistors can have a three-dimensional "fin" shape extending outward from the plane of the substrate 8 surface. In addition to the top surface of the channel, the gate structure 20 can be formed on the sidewalls of the fin-shaped channel. In an optional embodiment described in more detail below, the substrate 8 (or any other dielectric layer of the interconnection hierarchy) may include a dielectric protrusion instead of the semiconductor channel 15. Thus, the semiconductor channel 15 formed above the dielectric protrusion will also have a three-dimensional structure.

[0054] Each interconnection level structure may be subsequently formed, which is formed before forming an array of protruding field effect transistors and is referred to herein as a lower interconnection level structure (L0, L1, L2). If a two-dimensional array of protruding field effect transistors is subsequently formed above two levels of interconnection level metal lines, the lower interconnection level structure (L0, L1, L2) may include a contact level structure L0, a first interconnection level structure L1, and a second interconnection level structure L2. The contact level structure L0 may include a planarization dielectric layer 31A, which includes a planarization dielectric material such as silicon oxide, and a plurality of contact via structures 41V that contact a corresponding one of the active area 14 or the gate electrode 24 and are formed in the planarization dielectric layer 31A. The first interconnection level structure L1 includes a first interconnection level dielectric layer 31B and a first metal line 41L formed in the first interconnection level dielectric layer 31B. The first interconnection level dielectric layer 31B is also referred to as a first line level dielectric layer. The first metal line 41L may contact a corresponding one of the contact via structures 41V. The second interconnection level structure L2 includes a second interconnection level dielectric layer 32, which may include a first via level dielectric material layer and a second line level dielectric material layer or a stack of line and via level dielectric material layers. The second interconnection level dielectric layer 32 may have formed therein a second interconnection level metal interconnect structure (42V, 42L), which includes a first metal via structure 42V and a second metal line 42L. The top surface of the second metal line 42L may be coplanar with the top surface of the second interconnection level dielectric layer 32.

[0055] Figure 1B is a vertical cross-sectional view of a first exemplary structure after forming a protrusion field effect transistor array according to an embodiment of the present invention. Figure 1B , an array 95 of protruding field effect transistors can be formed in the memory array region 100 above the second interconnect hierarchy structure L2. The details of the structure and processing steps of the array 95 of protruding field effect transistors are described in detail below. A third interconnect hierarchy dielectric layer 33 can be formed during the formation of the array 95 of protruding field effect transistors. The collection of all structures formed at the level of the array 95 of protruding field effect transistors is referred to herein as the third interconnect hierarchy structure L3.

[0056] Figure 1C is a vertical cross-sectional view of a first exemplary structure during formation of a high-level metal interconnect structure according to an embodiment of the present invention. Figure 1C, a third interconnection level metal interconnect structure (43V, 43L) may be formed in the third interconnection level dielectric layer 33. The third interconnection level metal interconnect structure (43V, 43L) may include a second metal via structure 43V and a third metal line 43L. Additional interconnection level structures may be subsequently formed, which are referred to herein as upper interconnection level structures (L4, L5, L6, L7). For example, the upper interconnection level structures (L4, L5, L6, L7) may include a fourth interconnection level structure L4, a fifth interconnection level structure L5, a sixth interconnection level structure L6, and a seventh interconnection level structure L7. The fourth interconnection level structure L4 may include a fourth interconnection level dielectric layer 34 having a fourth interconnection level metal interconnect structure (44V, 44L) formed therein, which may include a third metal via structure 44V and a fourth metal line 44L. The fifth interconnection level structure L5 may include a fifth interconnection level dielectric layer 35 having a fifth interconnection level metal interconnection structure (45V, 45L) formed therein, which may include a fourth metal via structure 45V and a fifth metal line 45L. The sixth interconnection level structure L6 may include a sixth interconnection level dielectric layer 36 having a sixth interconnection level metal interconnection structure (46V, 46L) formed therein, which may include a fifth metal via structure 46V and a sixth metal line 46L. The seventh interconnection level structure L7 may include a seventh interconnection level dielectric layer 37 having a sixth metal via structure 47V (which is a seventh interconnection level metal interconnection structure) and a metal bonding pad 47B formed therein. Metal bond pad 47B may be configured for solder bonding (which may employ C4 ball bonding or wire bonding), or may be configured for metal-to-metal bonding (such as copper-to-copper bonding).

[0057] Each interconnect level dielectric layer may be referred to as an interconnect level dielectric layer (ILD) layer 30. Each interconnect level metal interconnect structure may be referred to as a metal interconnect structure 40. Each continuous combination of a metal via structure and a metal line located above the same interconnect level structure (L2-L7) may be formed into two different structures in sequence by using two single damascene processes, or may be formed into an integral structure simultaneously by using a dual damascene process. Each metal interconnect structure 40 may include a corresponding metal liner (such as a TiN, TaN or WN layer having a thickness in the range of 2nm to 20nm) and a corresponding metal filling material (such as W, Cu, Co, Mo, Ru, other elemental metals or alloys or combinations thereof). Other suitable materials used as metal liner and metal filling material are within the scope of the conceivable invention disclosure. A plurality of etch stop dielectric layers and dielectric protection layers may be inserted between a plurality of pairs of vertically adjacent ILD layers 30, or may be incorporated into one or more ILD layers 30.

[0058] Although the present invention is described using an embodiment in which an array 95 of protruding field effect transistors can be formed as a component of a third interconnect hierarchy L3, embodiments in which an array 95 of protruding field effect transistors can be formed as a component of any other interconnect hierarchy (e.g., L1-L7) are expressly contemplated herein. Furthermore, although the present invention describes an embodiment in which a set of eight interconnect hierarchy structures are formed, embodiments in which a different number of interconnect hierarchy structures are expressly contemplated herein. Furthermore, embodiments in which two or more arrays 95 of protruding field effect transistors can be provided within a plurality of interconnect hierarchy structures in a memory array region 100 are expressly contemplated herein. Although the present invention is described using an embodiment in which an array 95 of protruding field effect transistors is formed in a single interconnect hierarchy structure, embodiments in which an array 95 of protruding field effect transistors can be formed above two vertically adjacent interconnect hierarchy structures are expressly contemplated herein.

[0059] FIG. 2A to FIG. 12B A plurality of protrusion TFTs and a method of manufacturing the plurality of protrusion TFTs are shown. Figure 2A is a top view showing a step of forming a protrusion in a substrate in a method of manufacturing a transistor according to an embodiment of the present invention. Figure 2B It passes through Figure 2A A vertical cross-sectional view along line AA'. Figure 2C It passes through Figure 2A A vertical cross-sectional view of line BB'. FIG. 2A to FIG. 2C The dielectric layer 102 may be provided with a plurality of dielectric protrusions 103 that may be formed thereon. The plurality of protrusions may be formed in a one-dimensional array. As defined herein, a one-dimensional array of protrusions is one in which there are Figure 2AAs shown, a one-dimensional array of dielectric protrusions 103 is formed along line AA'. Fig. 9 The two-dimensional array of dielectric protrusions 103 shown in the figure includes multiple rows and columns of protrusions in the same device. The one-dimensional array can be formed along a second direction perpendicular to the first direction between the active areas. In various embodiments, multiple dielectric protrusions 103 can be formed by masking the dielectric layer 102 with a photoresist (not shown) and etching the grooves 105 in the dielectric layer 102, thereby forming multiple dielectric protrusions 103 between the grooves 105. Optionally, the dielectric layer 102 can be masked with a photoresist (not shown) and multiple dielectric protrusions 103 are grown in the openings in the dielectric layer 102. In various embodiments, the dielectric layer 102 can be made of a dielectric material such as SiO2. In an optional embodiment, the dielectric layer 102 can be the top of a substrate made of a dielectric material. In various embodiments, the multiple dielectric protrusions 103 may have a height P in the range of 10-250nm. H and a width P in the range of 3-30 nm W In various embodiments, the plurality of dielectric protrusions 103 may have a protrusion height P in the range of 20-200 nm. H , although higher or lower protrusion heights may be used. In various embodiments, each of the plurality of dielectric protrusions 103 may have a protrusion width P in the range of 5-25 nm. W , although wider or narrower protrusion widths may be used.

[0060] Figure 3A is a top view illustrating a step of depositing a continuous channel layer over a substrate in a method of manufacturing a transistor according to an embodiment of the present invention. Figure 3B It passes through Figure 3A A vertical cross-sectional view along line AA'. Figure 3C It passes through Figure 3A A vertical cross-sectional view of line BB'. FIG. 3A to FIG. 3C, a continuous channel layer 104L can be conformally deposited on the dielectric layer 102 to cover a plurality of dielectric protrusions 103, thereby forming a plurality of grooves between two adjacent dielectric protrusions 103. In this way, a layer having a substantially uniform thickness can be formed above the plurality of dielectric protrusions 103 and in the grooves 105. In an embodiment, the protruding TFT can be formed as part of an interconnect structure in an integrated semiconductor device. For example, the protruding TFT can be formed as part of a third interconnection level structure L3, in which case the second interconnection level dielectric layer 32 can replace the dielectric layer 102. The continuous channel layer 104L can be made of any suitable semiconductor material, such as amorphous silicon or a semiconductor oxide, such as InGaZnO, InWO, InZnO, InSnO, GaOx, InOx, etc. Other suitable materials are within the conceivable scope of the present invention. In various embodiments, the thickness of the continuous channel layer 104L can be in the range of 1-20nm, such as 5-15nm, but a larger or smaller thickness can be used. The continuous channel layer 104L may be deposited by any suitable technique, such as chemical vapor deposition (CVD), plasma enhanced chemical vapor deposition (PECVD), or atomic layer deposition (ALD).

[0061] Figure 4A is a top view illustrating a step of patterning a channel layer in a method of manufacturing a transistor according to an embodiment of the present invention. Figure 4B It passes through Figure 4A A vertical cross-sectional view along line AA'. Figure 4C It passes through Figure 4A A vertical cross-sectional view of line BB'. FIG. 4A to FIG. 4C , the continuous channel layer 104L can be patterned. In order to pattern the continuous channel layer 104L, a photoresist (not shown) can be deposited on the continuous channel layer 104L and patterned. Then, when the continuous channel layer 104L is patterned, the patterned photoresist can be used as a mask. The continuous channel layer 104L is patterned to obtain a patterned channel layer 104. Patterning can be performed by wet etching or dry etching. After etching, any residual photoresist can be removed by ashing or dissolving with a solvent.

[0062] Figure 5A is a top view illustrating the step of depositing a high-k dielectric layer and a metal gate layer over a channel layer in a method of manufacturing a transistor according to an embodiment of the present invention. Figure 5B It passes through Figure 5A A vertical cross-sectional view along line AA'. Figure 5C It passes through Figure 5A A vertical cross-sectional view of line BB'. FIG. 5A to FIG. 5C, a high-k dielectric layer 108 may be conformally deposited over the dielectric layer 102 and the patterned channel layer 104. Next, a gate layer 106 may be deposited over the high-k dielectric layer 108. The high-k dielectric layer 108 may include, but is not limited to, hafnium dioxide (HfO2), hafnium silicon oxide (HfSiO), hafnium tantalum oxide (HfTaO), hafnium titanium oxide (HfTiO), hafnium zirconium oxide (HfZrO), zirconium oxide, titanium oxide, aluminum oxide, hafnium dioxide-aluminum oxide (HfO2-Al2O3). Other suitable materials are within the conceivable scope of the present invention. The gate layer 106 may be made of any suitable metal, such as copper, aluminum, zirconium, titanium, tungsten, tantalum, ruthenium, palladium, platinum, cobalt, nickel, or alloys thereof. Other suitable materials are within the conceivable scope of the present invention. The gate layer 106 may be deposited by any suitable technique, such as chemical vapor deposition (CVD), plasma enhanced chemical vapor deposition (PECVD), or atomic layer deposition (ALD). The high-k dielectric layer 108 and the gate layer 106 may be formed by first depositing a photoresist layer (not shown) and patterning it so that the high-k dielectric layer 108 and the gate layer 106 have a certain thickness. Figure 5A and Figure 5C Furthermore, Figure 5B As shown, when the trench 105 between the protrusions on the dielectric layer 102 can be filled with the gate material of the gate layer 106, a gate protrusion 106P can be formed. In various embodiments, the high-k dielectric layer 108 can have a thickness t in the range of 0.5-5 nm. hk , such as 1-4 nm, such as 2.5-3.5 nm, but greater or lesser thicknesses may be used.

[0063] refer to FIG. 6A to FIG. 6C ion implantation 111 may be performed on the portion of the patterned channel layer 104 exposed below the gate layer 106 to form an active region (e.g., source / drain region) 113 on either side of the channel region 104R. The active region 113 may be implanted so that the average atomic concentration of atoms in the active region 113 is between 1.0×10 16 / cm 3 to 1.0×10 20 / cm 3 range, such as from 1.0×10 17 / cm 3 Up to 5.0×10 19 / cm 3 , but a greater or lesser atomic concentration may be used. In addition, since the gate layer 106 may be used as a mask when forming the active region 113, it can be said that the active region 113 is self-aligned with the channel region 104R.

[0064] Fig. 7AFIG. 1 is a diagram showing a method for manufacturing a transistor according to an embodiment of the present invention. FIG. 6A to FIG. 6C A top view of the steps of depositing an interconnect level dielectric layer and forming active area contacts over the intermediate structure is shown. Figure 7B It passes through Fig. 7A A vertical cross-sectional view along line AA'. Figure 7C It passes through Fig. 7A A vertical cross-sectional view of line BB'. FIG. 7A to FIG. 7C , the interconnect level dielectric layer 30 may be deposited on FIG. 7A to FIG. 7C Above the intermediate structure shown. The interconnection level dielectric layer 30 can be made of any suitable material, including but not limited to SiO2. Other suitable materials are within the conceivable scope of the present invention. Then a through hole (not shown) can be formed in the interconnection level dielectric layer 30 down to the surface of the active area 113. Next, the through hole can be filled with a conductive material to form an active area through hole contact 112. The conductive material can be TiN, W, Al, Cu or any other suitable material. After forming the active area through hole contact 112, a planarization step can be performed to planarize the surface of the interconnection level dielectric layer 30 and the top surface of the active area through hole contact 112. The planarization step can be performed by, for example, chemical mechanical polishing (CMP). Finally, a protruding field effect transistor 300 is obtained.

[0065] refer to Figure 7B As shown, similar to FinFET, the resulting protrusion field effect transistor 300 has a three-dimensionally patterned channel layer 104. Unlike a planar channel, a three-dimensional construction such as FinFET technology or the protrusion field effect transistor 300 in the embodiment provides several advantages over a planar FET. For example, the fin structure can enable higher drive current for a given transistor footprint, resulting in higher speed. The three-dimensional structure can also achieve lower leakage, resulting in lower power consumption. The three-dimensional structure can also achieve reduced dopant fluctuations, resulting in better mobility and transistor scaling. Therefore, the resulting protrusion field effect transistor 300 can be referred to as a three-dimensional field effect transistor. As Figure 7B As shown, the effective channel width W of the protrusion field effect transistor 300 is obtained. eff The channel width W may be significantly wider than the channel width W (wherein the channel length is the distance from active region to active region, e.g., the distance from source to drain, and the channel width is the distance perpendicular to the channel length). Although the channel width W may be the lateral distance of the channel material 108, since the patterned channel layer 104 follows the contours of the dielectric layer 102 and the plurality of dielectric protrusions 103 as shown by the arrows, the effective channel width W of the patterned channel layer 104 is eff As discussed above, in various embodiments, the plurality of dielectric protrusions 103 may have a protrusion height P in the range of 10-250 nm.H and protrusion length P in the range of 3-100 nm L . Protrusion height P H can significantly affect the effective channel width W eff .

[0066] FIG. 8A to FIG. 8C Another embodiment of a protrusion field effect transistor 400 is shown. Fig. 8A is a diagram showing an embodiment of the present invention, in FIG. 7A to FIG. 7C A top view of an alternative embodiment of a transistor in which protrusions are formed in a direction perpendicular to the protrusions formed in the illustrated embodiment. Figure 8B It passes through Fig. 8A A vertical cross-sectional view along line AA'. Figure 8C It passes through Fig. 8A This embodiment is similar to FIG. 7A to FIG. 7C However, in this optional embodiment, a one-dimensional array of multiple dielectric protrusions 103 can be formed in the first direction between the active regions 113. A one-dimensional array of multiple dielectric protrusions 103 can be formed along the channel length L, that is, the distance between the active regions 113. Figure 8C As shown, since the patterned channel layer follows the contours of the dielectric layer 102 and the plurality of dielectric protrusions 103 from the first active region 113 to the second active region 113 as indicated by the arrows, the effective channel length L of the protrusion field effect transistor 400 obtained is eff Significantly longer than the length L of the patterned channel layer 104. The effective channel length L eff The number of the plurality of dielectric protrusions 103 and the size of the protrusions 103 may vary. As discussed above, in various embodiments, the plurality of dielectric protrusions 103 may have a protrusion height P in the range of 10-250 nm. H and protrusion length P in the range of 3-100 nm L The protrusion height PH can significantly affect the effective channel length L eff .

[0067] Fig. 9 1 is a top view showing a step of forming a protrusion in a substrate in a method of manufacturing a transistor according to a third embodiment of the present invention. FIG. 8A to FIG. 8CIn the third embodiment of the present invention shown, an array of dielectric protrusions 103 can be formed in the x and y directions. Channel layer 104 and dielectric layer 108 can be conformally deposited above the array of dielectric protrusions 103. Continuous channel layer 104L can be made of any suitable semiconductor material, such as amorphous silicon or semiconductor oxide, such as InGaZnO, InWO, InZnO, InSnO, GaOx, InOx, etc. Other suitable materials belong to the conceivable scope of the present invention. In various embodiments, the thickness of continuous channel layer 104L can be in the range of 1-20nm, such as 5-15nm, but a larger or smaller thickness can be used. Continuous channel layer 104L can be deposited by any suitable technology, such as chemical vapor deposition (CVD), plasma enhanced chemical vapor deposition (PECVD) or atomic layer deposition (ALD). The high-k dielectric layer 108 may include, but is not limited to, hafnium dioxide (HfO2), hafnium silicon oxide (HfSiO), hafnium tantalum oxide (HfTaO), hafnium titanium oxide (HfTiO), hafnium zirconium oxide (HfZrO), zirconium oxide, titanium oxide, aluminum oxide, hafnium dioxide-aluminum oxide (HfO2-Al2O3). Other suitable materials are within the conceivable scope of the present invention. A gate layer 106 may then be deposited over the high-k dielectric layer 108. The gate layer 106 may be made of any suitable metal, such as copper, aluminum, zirconium, titanium, tungsten, tantalum, ruthenium, palladium, platinum, cobalt, nickel, or alloys thereof. Other suitable materials are within the conceivable scope of the present invention. The gate layer 106 may be deposited by any suitable technique, such as chemical vapor deposition (CVD), plasma enhanced chemical vapor deposition (PECVD), or atomic layer deposition (ALD).

[0068] FIG. 10A to FIG. 10C A top view and a vertical cross-sectional view of a completed protrusion field effect transistor 500 of a third embodiment of the present invention are shown. This embodiment is similar to the first two embodiments. However, as mentioned above, the protrusion field effect transistor 500 of this embodiment includes a two-dimensional array of dielectric protrusions 103 along both the channel width W and the channel length L. Therefore, the effective channel width Weff and the effective channel length L eff The channel width W and the channel length L may be larger than the channel width W and the channel length L as measured by the actual distance W between the active regions 113 and along the gate layer 106 .

[0069] FIG. 11A to FIG. 11C 1 shows a dielectric layer 102 according to yet another embodiment. Figure 2A and Figure 2B In contrast to the embodiment shown, Figure 2A and Figure 2B The illustrated embodiment includes a dielectric protrusion 103 of rectangular cross-section, FIG. 11A to FIG. 11CIn the illustrated embodiment, the dielectric protrusion 103 may have a substantially triangular cross-sectional profile. That is, the base of the dielectric protrusion 103 near the top surface of the dielectric layer 102 may be wider than the tip portion away from the top surface of the dielectric layer 102. The plurality of dielectric protrusions 103 may include a first end near the substrate 102 and a second end away from the substrate 102, and wherein the width of the first end is wider than the width of the second end. The triangular cross-sectional protrusion 103 of the present embodiment enables the effective channel length L eff and / or effective channel width W eff However, the protrusion height P H and the protrusion base width P BW May affect the effective channel width W eff and the effective channel length L eff .

[0070] FIG. 12A to FIG. 12C FIG. 1 shows a dielectric layer 102 according to yet another embodiment. Figure 2A and Figure 2B In contrast to the embodiment shown, Figure 2A and Figure 2B The illustrated embodiment includes a dielectric protrusion 103 of rectangular cross-section, FIG. 12A to FIG. 12C In the illustrated embodiment, the dielectric protrusion 103 may have a "rounded triangle" cross-sectional profile. As in the previous embodiment, the base of the dielectric protrusion 103 near the top surface of the dielectric layer 102 may be wider than the tip portion away from the top surface of the dielectric layer 102. However, in this embodiment, the cross-section of the dielectric protrusion 103 may have a sine, parabolic or other curved shape. That is, the base of the protrusion 103 near the top surface of the dielectric layer 102 may be wider than the tip portion away from the top surface of the dielectric layer 102. The "rounded triangle" cross-sectional protrusion 103 of this embodiment makes the effective channel length L eff and / or effective channel width W eff However, the protrusion height P H and the protrusion base width P BW And the curvature radius may affect the effective channel width W eff and the effective channel length L eff .

[0071] In another embodiment, the continuous channel layer 104L of any of the above embodiments may be doped with a dopant selected to improve the stability of the continuous channel layer 104L. The dopant may improve the stability of the channel layer 104L. For example, the channel layer 104L may be doped with Si. Other suitable dopants for improving the stability of the channel layer 104L are within the contemplated scope of the present invention.

[0072] In another embodiment, the continuous channel layer 104L may include a laminate structure. In one aspect, the laminate structure of multiple layers includes In x Ga y Zn z O layers. In an embodiment, 0 < x ≤ 0.5, 0 < y ≤ 0.5, and 0 < z ≤ 0.5. In various embodiments, the laminate structure of multiple layers includes other oxide layers, such as but not limited to InWO, InZnO, InSnO, GaO x and InO x .

[0073] Fig.13 is a flowchart showing a general method 600 of manufacturing the protrusion field effect transistors 300, 400, 500. Referring to step 602, the method includes the step of providing a substrate including a dielectric layer 102 having a plurality of dielectric protrusions 103. Referring to step 604, the method includes the step of conformally depositing a channel layer 104 over the plurality of dielectric protrusions 103 of the dielectric layer 102 to form a plurality of trenches 105 between two adjacent dielectric protrusions 103. Referring to step 606, the method includes the step of forming a gate layer 106 disposed on the channel layer 104, wherein the gate layer 106 has a plurality of gate protrusions 106P that are mated to the trenches 105. Referring to step 608, the method includes the step of forming active regions 113 on either side of the gate layer 106, wherein the active regions 113 may be electrically connected to the channel layer 104.

[0074] Generally, the structures and methods of the present invention can be used to form a protrusion field effect transistor and at least a two-dimensional array of protrusion field effect transistors in the metal interconnect level of the back-end-of-line process. Field effect transistors (TFTs) are attractive for BEOL integration because they can be processed at low temperatures, can add functionality to the BEOL, and can free up area in the FEOL. By moving peripheral devices (such as power gates or I / O devices) from the FEOL to higher metal levels in the BEOL, using TFTs in the BEOL can be used as a scaling path for N3 and beyond. For a given device, moving the TFT from the FEOL to the BEOL can result in an area reduction of approximately 5 - 10%.

[0075] Embodiments relate to a transistor including a dielectric layer 102 having a plurality of dielectric protrusions 103; a channel layer 104 that conformally covers the plurality of dielectric protrusions 103 of the dielectric layer 102 to form a plurality of channels 105 between two adjacent dielectric protrusions 103; a gate layer 106 disposed on the channel layer. The gate layer 106 has a plurality of gate protrusions 106P that are mated to the trenches 105. The transistor further includes active regions 113 formed on either side of the gate layer 106. The active regions 113 are electrically connected to the channel layer 104.

[0076] Another embodiment relates to an integrated semiconductor device, which includes a protrusion field effect transistor 300, 400, 500 located in a back-end of line (BEOL) portion of the integrated semiconductor device. The protrusion field effect transistor 300, 400, 500 includes a dielectric layer 102 having a plurality of dielectric protrusions 103; a channel layer 104, which conformally covers the protrusions 103 of the dielectric layer 102 to form a plurality of trenches 105 between two adjacent dielectric protrusions 103; and a gate layer 106 disposed on the channel layer 104. The gate layer 106 has a plurality of gate protrusions 106P coupled to the trenches 105. The protrusion field effect transistor 300, 400, 500 also includes an active region 113 that can be formed on either side of the gate layer 106. The active region 113 is electrically connected to the channel layer 104.

[0077] Another embodiment relates to a method of manufacturing a protrusion field effect transistor 300, 400, 500, the method comprising providing a substrate comprising a dielectric layer 102 having a plurality of dielectric protrusions 103; conformally forming a channel layer 104 covering the protrusions 103 of the dielectric layer 102 to form a plurality of trenches 105 between two adjacent dielectric protrusions 103; and forming a gate layer 106 disposed on the channel layer. The gate layer 106 has a plurality of gate protrusions 106P coupled to the trenches 105. The method further comprises forming an active region 113 on either side of the gate layer 106. The active region 113 is electrically connected to the channel layer 104.

[0078] Some embodiments of the present application provide a transistor, comprising: a dielectric layer having a plurality of dielectric protrusions; a channel layer conformally covering the plurality of dielectric protrusions to form a plurality of grooves between two adjacent dielectric protrusions; a gate layer disposed on the channel layer, wherein the gate layer has a plurality of gate protrusions fitted in the grooves; and an active region formed on either side of the gate layer, wherein the active region is electrically connected to the channel layer. In some embodiments, the plurality of gate protrusions are formed into a one-dimensional array along a first direction starting from the active region. In some embodiments, the plurality of gate protrusions are formed into a one-dimensional array along a second direction perpendicular to the first direction starting from the active region. In some embodiments, the plurality of gate protrusions include a two-dimensional array along a first direction starting from the active region and a second direction perpendicular to the first direction. In some embodiments, the plurality of dielectric protrusions include a first end close to a substrate and a second end away from the substrate, and wherein the width of the first end is wider than the width of the second end. In some embodiments, each dielectric protrusion of the plurality of dielectric protrusions has a triangular cross-sectional profile. In some embodiments, each dielectric protrusion of the plurality of dielectric protrusions has a rounded triangular cross-sectional profile. In some embodiments, the channel layer is a laminated structure comprising an InWO layer, an InZnO layer, an InSnO layer, a GaO x layer, InO x In some embodiments, the transistor further comprises an active region through-hole contact contacting the active region, wherein the active region through-hole contact comprises TiN, W, Al, Cu or a combination thereof. In some embodiments, the channel layer is a laminated structure comprising a plurality of InGaZnO layers having different concentrations of In, Ga and Zn.

[0079] Some other embodiments of the present application provide an integrated semiconductor device, comprising: a protrusion field effect transistor, located in a back-end of line (BEOL) portion of the integrated semiconductor device, the protrusion field effect transistor comprising: a dielectric layer having a plurality of dielectric protrusions; a channel layer conformally covering the plurality of dielectric protrusions to form a plurality of trenches between two adjacent dielectric protrusions; a gate layer disposed on the channel layer, wherein the gate layer has a plurality of gate protrusions fitted in the trenches; and an active region formed on either side of the gate layer, wherein the active region is electrically connected to the channel layer. In some embodiments, the protrusion field effect transistor comprises a power gate, a logic transistor, an input / output device, or a selector for a memory element.

[0080] Some other embodiments of the present application provide a method for manufacturing a protrusion field effect transistor, comprising: providing a substrate, the substrate comprising a dielectric layer having a plurality of dielectric protrusions; conformally forming a channel layer covering the plurality of dielectric protrusions to form a plurality of grooves between two adjacent dielectric protrusions; forming a gate layer disposed on the channel layer, wherein the gate layer has a plurality of gate protrusions fitted in the grooves; and forming an active region on either side of the gate layer, wherein the active region is electrically connected to the channel layer. In some embodiments, the gate layer is formed so that the plurality of gate protrusions are formed into a one-dimensional array along a first direction between the active regions. In some embodiments, the gate layer is formed so that the plurality of gate protrusions are formed into a one-dimensional array along a second direction perpendicular to the first direction between the active regions. In some embodiments, the gate layer is formed so that a two-dimensional array of protrusions is generated along a first direction between the active regions and a second direction perpendicular to the first direction. In some embodiments, providing a substrate including a dielectric layer having a plurality of dielectric protrusions includes: forming the plurality of dielectric protrusions so that the dielectric protrusions include a first end proximal to the substrate and a second end distal to the substrate, and wherein the width of the first end is wider than the width of the second end. In some embodiments, the method further includes forming each of the plurality of dielectric protrusions having a triangular cross-sectional profile. In some embodiments, conformally forming a channel layer includes: forming a laminated structure including InGaZnO layers having different concentrations of In, Ga, and Zn. In some embodiments, the method further includes forming each of the plurality of dielectric protrusions having a rounded triangular cross-sectional profile.

[0081] The features of several embodiments are summarized above so that those skilled in the art can better understand aspects of the present invention. Those skilled in the art should understand that they can easily use the present invention as a basis to design or modify other processes and structures for implementing the same purpose and / or achieving the same advantages as the embodiments introduced herein. Those skilled in the art should also appreciate that such equivalent constructions do not deviate from the spirit and scope of the present invention, and that they can make various changes, substitutions and modifications herein without departing from the spirit and scope of the present invention.

Claims

1. A transistor comprising: a dielectric layer having a plurality of dielectric protrusions; a channel layer conformally covering the plurality of dielectric protrusions to form a plurality of trenches between two adjacent dielectric protrusions; a gate layer disposed on the channel layer, wherein the gate layer has a two-dimensional array of gate protrusions matched in the trench; and An active region is formed on either side of the gate layer, wherein the active region is electrically connected to the channel layer.

2. The transistor according to claim 1, wherein The plurality of dielectric protrusions have a protrusion height in a range of 20 nm to 200 nm.

3. The transistor according to claim 1, wherein: Each of the plurality of dielectric protrusions has a protrusion width in a range of 5 nm to 25 nm.

4. The transistor according to claim 1, wherein The two-dimensional array of gate protrusions has gate protrusions along a first direction starting from the active region and a second direction perpendicular to the first direction.

5. The transistor according to claim 1, wherein The plurality of dielectric protrusions include a first end close to a substrate and a second end away from the substrate, and wherein a width of the first end is wider than a width of the second end.

6. The transistor according to claim 5, wherein: Each dielectric protrusion of the plurality of dielectric protrusions has a triangular cross-sectional profile.

7. The transistor according to claim 5, wherein: Each dielectric protrusion of the plurality of dielectric protrusions has a rounded triangular cross-sectional profile.

8. The transistor according to claim 1, wherein The channel layer is a laminated structure, which includes an InWO layer, an InZnO layer, an InSnO layer, a GaO x layer, InO x layer or a combination thereof. 9 . The transistor of claim 1 , further comprising an active area via contact contacting the active area, the active area via contact comprising TiN, W, Al, Cu, or a combination thereof.

10. The transistor according to claim 1, wherein The channel layer is a laminated structure including a plurality of InGaZnO layers having different concentrations of In, Ga, and Zn.

11. An integrated semiconductor device comprising: protrusion field effect transistor, Located in a back-end-of-line (BEOL) portion of the integrated semiconductor device, the protrusion field effect transistor comprises: a dielectric layer having a plurality of dielectric protrusions; a channel layer conformally covering the plurality of dielectric protrusions to form a plurality of trenches between two adjacent dielectric protrusions; a gate layer disposed on the channel layer, wherein the gate layer has a two-dimensional array of gate protrusions matched in the trench; and An active region is formed on either side of the gate layer, wherein the active region is electrically connected to the channel layer.

12. The integrated semiconductor device according to claim 11, wherein: The protruding field effect transistor includes a power gate, a logic transistor, an input / output device, or a selector for a memory element.

13. A method for manufacturing a protrusion field effect transistor, comprising: providing a substrate comprising a dielectric layer having a plurality of dielectric protrusions; conformally forming a channel layer covering the plurality of dielectric protrusions to form a plurality of trenches between two adjacent dielectric protrusions; forming a gate layer disposed on the channel layer, wherein the gate layer has a two-dimensional array of gate protrusions fitted in the trench; and An active region is formed on either side of the gate layer, wherein the active region is electrically connected to the channel layer.

14. The method according to claim 13, wherein: The plurality of dielectric protrusions have a protrusion height in a range of 20 nm to 200 nm.

15. The method according to claim 13, wherein: Each of the plurality of dielectric protrusions has a protrusion width in a range of 5 nm to 25 nm.

16. The method according to claim 13, wherein: The gate layer is formed so as to generate the two-dimensional array of the gate protrusions along a first direction between the active regions and a second direction perpendicular to the first direction.

17. The method according to claim 13, wherein: Providing a substrate including a dielectric layer having a plurality of dielectric protrusions includes forming the plurality of dielectric protrusions such that the dielectric protrusions include a first end close to the substrate and a second end away from the substrate, and wherein a width of the first end is wider than a width of the second end. 18 . The method of claim 17 , further comprising forming each of the plurality of dielectric protrusions to have a triangular cross-sectional profile.

19. The method according to claim 13, wherein: Conformally forming the channel layer includes forming a laminated structure including InGaZnO layers having different concentrations of In, Ga, and Zn.

20. The method of claim 17, further comprising forming each of the plurality of dielectric protrusions having a rounded triangular cross-sectional profile.

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