Method of manufacturing a semiconductor device and semiconductor device

Abstract

The semiconductor device includes: a gate structure disposed over a channel region and a source / drain region. The gate structure includes: a gate dielectric layer located over the channel region; one or more work function adjustment material layers located over the gate dielectric layer; and a metal gate electrode layer located over the one or more work function adjustment material layers. The one or more work function adjustment layers include an aluminum-containing layer, and a diffusion barrier layer is disposed at least at one of a bottom and a top of the aluminum-containing layer. The diffusion barrier layer is one or more of a titanium-rich layer, a titanium-doped layer, a tantalum-rich layer, a tantalum-doped layer, and a silicon-doped layer. Embodiments of the present application also relate to a method of manufacturing a semiconductor device.

Description

Technical Field

[0001] Embodiments of the present application relate to methods of manufacturing semiconductor devices and semiconductor devices. Background Art

[0002] With the growth of the scaling down of integrated circuits and the increasing requirements for the speed of integrated circuits, transistors need to have a larger drive current and an increasingly smaller size. Therefore, three-dimensional field-effect transistors (FETs) have been developed. The three-dimensional (3D) FETs include vertical semiconductor nanostructures (such as fins, nanowires, nanosheets, etc.) on a substrate. The semiconductor nanostructures are used to form source and drain regions and a channel region between the source and drain regions. Shallow trench isolation (STI) regions are formed to define the semiconductor nanostructures. The 3D FETs also include a gate stack, which is formed on the sidewalls and the top surface of the semiconductor fin or on all sides of the nanowire or nanosheet. Since the 3D FETs have a three-dimensional channel structure, extra care is needed for the ion implantation process of the channel to reduce any geometric effects. Summary of the Invention

[0003] Some embodiments of the present application provide a semiconductor device, including: a gate structure disposed above a channel region; and source / drain regions, wherein: the gate structure includes: a gate dielectric layer located above the channel region; one or more work function adjustment material layers located above the gate dielectric layer; and a metal gate electrode layer located above the one or more work function adjustment material layers; the one or more work function adjustment layers include an aluminum-containing layer, and a diffusion barrier layer is disposed at least at one of the bottom and the top of the aluminum-containing layer, and the diffusion barrier layer is one or more of a titanium-rich layer having a higher titanium concentration than the center of the aluminum-containing layer, a titanium-doped layer, a tantalum-rich layer having a higher tantalum concentration than the center of the aluminum-containing layer, a tantalum-doped layer, and a silicon-doped layer.

[0004] Some other embodiments of the present application provide a complementary metal oxide semiconductor (CMOS) device, comprising: a first field effect transistor (FET) including a first gate structure disposed over a first channel region; and a second field effect transistor including a second gate structure disposed over a second channel region, wherein: the first field effect transistor is an n-type field effect transistor, the second field effect transistor is a p-type field effect transistor, and the first gate structure includes: a gate dielectric layer; a first work function adjustment material layer located over the gate dielectric layer; and a metal gate electrode layer located over the first work function adjustment material layer, the second gate structure includes: a gate dielectric layer; a second work function adjustment material layer located over the gate dielectric layer; the first work function adjustment material layer located over the second work function adjustment material layer; and a metal gate electrode layer located over the first work function adjustment material layer, the metal gate electrode and the first work function adjustment material layer are continuous between the first field effect transistor and the second field effect transistor, such that the metal gate electrode is disposed over the gate dielectric layer of the first field effect transistor, over the second work function adjustment material layer of the second field effect transistor, and over the sidewalls of the second work function adjustment material layer at the boundary between the first field effect transistor and the second field effect transistor, the first work function adjustment layer includes aluminum, and the first work function adjustment layer includes a diffusion barrier layer at at least one of the bottom and the top of the first work function adjustment layer, the diffusion barrier layer being one or more of a titanium-rich layer having a higher titanium concentration than the center of the first work function adjustment layer, a titanium-doped layer, a tantalum-rich layer having a higher tantalum concentration than the center of the first work function adjustment layer, a tantalum-doped layer, and a silicon-doped layer.

[0005] Some further embodiments of the present application provide a method of manufacturing a semiconductor device, comprising: forming a gate dielectric layer over a channel region made of a semiconductor material; forming a first work function adjustment layer over the gate dielectric layer; and forming a metal gate electrode layer over the first work function adjustment layer, wherein: the first work function adjustment layer includes aluminum, and forming the first work function adjustment layer includes forming a diffusion barrier layer at at least one of the bottom and the top of the first work function adjustment layer, the diffusion barrier layer being one or more of a titanium-rich layer having a higher titanium concentration than the center of the first work function adjustment layer, a titanium-doped layer, a tantalum-rich layer having a higher tantalum concentration than the center of the first work function adjustment layer, a tantalum-doped layer, and a silicon-doped layer. BRIEF DESCRIPTION OF THE DRAWINGS

[0006] The present invention is best understood from the following detailed description when read in conjunction with the accompanying drawings. It should be emphasized that, in accordance with standard practice in the industry, the various components are not drawn to scale and are for illustrative purposes only. In fact, for the sake of clarity of discussion, the dimensions of the various components may be arbitrarily increased or decreased.

[0007] Figure 1A Shows a cross-sectional view of a semiconductor device according to an embodiment of the present invention, and Figure 1B shows a perspective view of a semiconductor device according to an embodiment of the present invention.

[0008] Figure 2A 、 Figure 2B 、 Figure 2C 、 Figure 2D 、 Figure 2E and Figure 2F show cross-sectional views of respective stages of a sequential manufacturing process of a semiconductor device according to an embodiment of the present invention.

[0009] Figure 3A 、 Figure 3B 、 Figure 3C 、 Figure 3D 、 Figure 3E and Figure 3F show cross-sectional views of respective stages of a sequential manufacturing process of a semiconductor device according to an embodiment of the present invention. Figure 3G shows a process flow for manufacturing a semiconductor device according to an embodiment of the present invention.

[0010] Figure 4A shows gate structures of multiple FETs having different threshold voltages according to an embodiment of the present invention. Figure 4B and Figure 4C show respective work function adjustment material layers and high-k gate dielectric layers for multiple FETs having different threshold voltages according to an embodiment of the present invention.

[0011] Figure 5A shows a plan view (layout) of a CMOS circuit according to an embodiment of the present invention, Figure 5B shows a cross-sectional view corresponding to Figure 5A region A1 according to an embodiment of the present invention, and Figure 5C shows an enlarged view of Figure 5B region B1 according to an embodiment of the present invention.

[0012] Figure 6A shows a plan view (layout) of a CMOS circuit according to an embodiment of the present invention, Figure 6B shows a cross-sectional view corresponding to Figure 6A region A1 according to an embodiment of the present invention, and Figure 6C shows an enlarged view of Figure 6B region B1 according to an embodiment of the present invention.

[0013] Figure 7A 、 Figure 7B 、 Figure 7C 、 Figure 7D 、 Figure 7Eand Figure 7F Shows cross-sectional views of an n-type work function adjustment material (WFM) layer according to embodiments of the present invention.

[0014] Figure 8A and Figure 8B Shows a cross-sectional view and Ti concentration of an n-type work function adjustment material (WFM) layer according to embodiments of the present invention.

[0015] Figure 9 Shows a process flow for manufacturing a semiconductor device according to embodiments of the present invention.

[0016] Figure 10A 、 Figure 10B 、 Figure 10C 、 Figure 10D 、 Figure 10E and Figure 10F Shows cross-sectional views of respective stages of a sequential manufacturing process of a semiconductor device according to embodiments of the present invention.

[0017] Figure 11 Shows the suppression of Al diffusion by a diffusion barrier layer according to embodiments of the present invention.

[0018] Figure 12A and Figure 12B Shows the effect of reducing the thickness of an interface layer according to embodiments of the present invention. Detailed Description

[0019] It should be understood that the following disclosure provides many different embodiments or examples for implementing different features of the present invention. Specific examples of components and arrangements are described below to simplify the present invention. Of course, these are merely examples and are not intended to limit the present invention. For example, the dimensions of the elements are not limited to the disclosed ranges or values, but may depend on process conditions and / or desired characteristics of the device. Additionally, in the following description, forming a first component above or on a second component may include embodiments where the first component and the second component are formed in direct contact, and may also include embodiments where additional components may be formed between the first component and the second component such that the first component and the second component may not be in direct contact. For simplicity and clarity, the various components may be drawn at arbitrary scales. In the drawings, some layers / components may be omitted for simplicity.

[0020] Moreover, for ease of description, spatial relative terms such as "under", "below", "lower", "above", "upper", etc. may be used herein to describe the relationship of one element or component to another (or other) element or component as shown in the figures. In addition to the orientation shown in the figures, the spatial relative terms are intended to include different orientations of the device during use or operation. The device may be oriented in other ways (rotated 90 degrees or in other orientations), and the spatial relative descriptors used herein may be interpreted accordingly. In addition, the term "made of" may mean "comprising" or "consisting of". In addition, in subsequent manufacturing processes, there may be one or more additional operations between the described operations, and the order of the operations may be changed. In the present invention, unless otherwise specified, the phrase "one of A, B, and C" means "A, B, and / or C" (A, B, C, A and B, A and C, B and C, or A, B, and C), and does not mean one element from A, one element from B, and one element from C. Throughout the disclosure, the source and drain may be used interchangeably, and the source / drain refers to one or both of the source and drain. In subsequent embodiments, the materials, configurations, dimensions, processes, and / or operations described with respect to one embodiment (e.g., one or more of the figures) may be employed in other embodiments, and their detailed descriptions may be omitted.

[0021] The disclosed embodiments relate to semiconductor devices, and in particular, to a gate structure of a field effect transistor (FET) and a method of manufacturing the same. Embodiments such as those disclosed herein are generally applicable not only to planar FETs, but also to fin field effect transistors (FinFETs), double-gate FETs, gate-all-around FETs, omega-gate FETs, or gate-all-around (GAA) FETs (such as lateral gate-all-around FETs or vertical gate-all-around FETs) and / or nanowire transistors, nanosheet transistors, nanosheet fork transistors, nanostructure transistors, nanoplane transistors, or any suitable device having one or more work function adjustment material (WFM) layers in the gate structure.

[0022] With the growth of the scaling down of integrated circuits, the spacing between neighboring devices decreases, and different threshold voltage devices are brought close together, such that the threshold voltage is shifted due to diffusion of metals (such as Al) from one device into another. In FET structures, fabricating multiple Vt devices with low Vt is crucial for reducing power consumption and improving device performance. The composition and thickness of the metal gate film play a crucial role in defining the device work function Vt. By adjusting the material and / or thickness of one or more work function adjustment material layers (WFM) disposed between the gate dielectric layer and the bulk metal gate electrode layer (e.g., a W layer), multiple FETs with different threshold voltages can be achieved. For n-type FETs with Si channels and / or p-type FETs with SiGe channels, an aluminum-containing layer such as TiAl, TiAlC, TaAl, and / or TaAlC is used as the WFM layer. However, when an aluminum-containing layer is formed as the WFM layer over a layer such as a WCN, WN, and / or TiN layer, Al diffusion into the WCN, WN, and / or TiN layers of neighboring devices causes threshold voltage changes and / or other degradations in FET performance.

[0023] The present invention relates to the use of an aluminum diffusion barrier layer at the upper surface and / or bottom surface of a WFM layer containing aluminum. As will be discussed subsequently, the present disclosure provides devices and methods that can protect underlying layers on the same FET device and also protect high-k and / or WFM layers in neighboring FET devices from Al diffusion from the aluminum-containing WFM layer.

[0024] Figure 1A A cross-sectional view of a semiconductor device according to an embodiment of the present invention is shown.

[0025] In some embodiments, the semiconductor device includes a gate stack 80 disposed over a channel region of a fin structure 20. The gate stack 80 includes an interface layer 81, a gate dielectric layer 82, a first conductive layer 83 as a capping layer, a second conductive layer 84 as a first barrier layer, a work function adjustment material layer or work function adjustment layer (WFM layer) 86, a glue layer 87, and a bulk gate electrode layer 88 as shown. In some embodiments, the fin structure 20 is provided over a substrate 10 and protrudes from an isolation insulating layer 30. Further, gate sidewall spacers 46 are disposed on opposite sides of the gate stack 80, and one or more dielectric layers 50 are formed to cover the gate sidewall spacers 46. In some embodiments, insulating material blocks 42 are disposed between the gate sidewall spacers 46 and the isolation insulating layer 30. Further, as shown, a source / drain epitaxial layer 60 is formed over a recessed fin structure. Although Figure 1A shows two fin structures, and Figure 1B shows three fin structures, the number of fin structures is not limited to Figure 1A and Figure 1B shows, and Figure 1A andFigure 1B Those shown.

[0026] In some embodiments, the fin structures (channel regions) are made of Si for n-type FETs and made of SiGe for p-type FETs. In some embodiments, the Ge concentration of the SiGe is in the range from about 20% atomic to 60% atomic, and in other embodiments, in the range from about 30% atomic to 50% atomic. In some embodiments, the channel region of the n-type FET includes Ge, and the amount of Ge is less than that of the SiGe channel of the p-type FET. In other embodiments, the channel regions of the p-type FET and the n-type FET are made of Si or compound semiconductors.

[0027] In some embodiments, the first conductive layer 83 includes a metal nitride, such as WN, TaN, TiN, and TiSiN. In some embodiments, TiN is used. In some embodiments, the thickness of the first conductive layer 83 is in the range from about 0.3 nm to about 30 nm, and in other embodiments, in the range from about 0.5 nm to about 25 nm. In some embodiments, the first conductive layer 83 is a crystal having, for example, columnar crystal grains. In some embodiments, the first conductive layer 83 is not formed. In some embodiments, the first conductive layer 83 is formed and then removed after an annealing operation using a wet etching process.

[0028] In some embodiments, the second conductive layer 84 includes a metal nitride, such as WN, TaN, TiN, and TiSiN. In some embodiments, TaN is used. In some embodiments, the thickness of the second conductive layer 84 is in the range from about 0.3 nm to about 30 nm, and in other embodiments, in the range from about 0.5 nm to about 25 nm. In some embodiments, the second conductive layer 84 serves as a barrier layer or an etch stop layer. In some embodiments, the second conductive layer 84 is thinner than the first conductive layer 83. In some embodiments, the second conductive layer 84 is not formed.

[0029] In some embodiments, the WFM layer 86 is made of a conductive material, such as a single layer of TiN, WN, WCN, Ru, W, TaAlC, TiC, TaAl, TaC, Co, Al, TiAl, or TiAlC, or a multi-layer of two or more of these materials. For an n-type FET with an Si channel, an aluminum-containing layer, such as TiAl, TiAlC, TaAl, and / or TaAlC, is used. In some embodiments, optionally, one or more of TaN, TiN, WN, TiC, WCN, MoN, and / or Co formed under the aluminum-containing layer are used. For a p-type FET with an SiGe channel, one or more of TaN, TiN, WN, TiC, WCN, MoN, and Co are used. In some embodiments, one or more of TiAl, TiAlC, TaAl, and TaAlC formed thereon are used.

[0030] In some embodiments, the glue layer 87 is made of one or more of TiN, Ti, and Co. In some embodiments, the body gate electrode layer 88 includes one or more layers of conductive materials, such as polysilicon, aluminum, copper, titanium, tantalum, tungsten, cobalt, molybdenum, tantalum nitride, nickel silicide, cobalt silicide, TiN, WN, TiAl, TiAlN, TaCN, TaC, TaSiN, metal alloys, other suitable materials, and / or combinations thereof.

[0031] As described above, in some embodiments, the first conductive layer 83 and the second conductive layer 84 are not formed. In this case, one or more WFM layers are formed directly on the gate dielectric layer 82.

[0032] Figures 2A to 3F Cross-sectional views showing various stages of a sequential manufacturing process of a semiconductor device according to an embodiment of the present invention are shown. Figure 3G A process flow for manufacturing a semiconductor device according to an embodiment of the present invention is shown. It should be understood that in the sequential manufacturing process, one or more additional operations may be provided before, during, and after the stages shown. For additional embodiments of the method, some of the operations described below may be replaced or eliminated. The order of the operations / processes may be interchanged. Figures 2A to 3F As shown, one or more fin structures 20 are fabricated above the substrate 10. The substrate 10 is, for example, a p-type silicon substrate having an impurity concentration in the range of about 1×10

[0033] As Figure 2A shown, the substrate 10 is, for example, a p-type silicon substrate having an impurity concentration in the range of about 1×10 15 cm -3 to about 1×10 18 cm -3 In other embodiments, the substrate 10 is a p-type silicon substrate having an impurity concentration in the range of about 1×10 15 cm -3 to about 1×10 18 cm -3An n-type silicon substrate with an impurity concentration within a certain range. Optionally, substrate 10 may include another elemental semiconductor, such as germanium; compound semiconductors, including group IV-IV compound semiconductors (such as SiC and SiGe), group III-V compound semiconductors (such as GaAs, GaP, GaN, InP, InAs, InSb, GaAsP, AlGaN, AlInAs, AlGaAs, GaInAs, GaInP, and / or GaInAsP); or a combination thereof. In one embodiment, substrate 10 is the silicon layer of a SOI (silicon on insulator) substrate. An amorphous substrate such as amorphous Si or amorphous SiC or an insulating material such as silicon oxide may also be used as substrate 10. Substrate 10 may include respective regions that have been suitably doped with impurities (e.g., p-type or n-type conductivity).

[0034] In some embodiments, a portion of substrate 10 for a p-type FET is recessed by etching, and a SiGe layer is formed over the recess. Figures 2A to 3F The case of an n-type FET is shown, but for a p-type FET, most of the manufacturing processes are substantially the same.

[0035] The fin structure 20 can be patterned by any suitable method. For example, the fin structure 20 can be patterned using one or more lithography processes, which include double patterning or multiple patterning processes. Generally, double patterning or multiple patterning processes combine lithography and self-alignment processes, thus allowing the creation of patterns with, for example, a pitch smaller than that obtainable using a single direct lithography process. For example, in one embodiment, a sacrificial layer is formed over the substrate and patterned using a lithography process. Spacers are formed beside the patterned sacrificial layer using a self-alignment process. Then the sacrificial layer is removed, and then the fin structure 20 can be patterned using the remaining spacers.

[0036] As Figure 2AAs shown, two fin structures 20 extending in the Y direction are disposed adjacent to each other in the X direction. However, the number of fin structures is not limited to two. The number can be one, three, four, five or more. In addition, one or more dummy fin structures can be disposed near both sides of the fin structure 20 to improve pattern fidelity in a patterning process. In some embodiments, the width of the fin structure 20 is in the range of about 5 nm to about 40 nm, and in certain embodiments, in the range of about 7 nm to about 15 nm. In some embodiments, the height of the fin structure 20 is in the range of about 100 nm to about 300 nm, and in other embodiments, in the range of about 50 nm to 100 nm. In some embodiments, the spacing between the fin structures 20 is in the range of about 5 nm to about 80 nm, and in other embodiments, in the range of about 7 nm to 15 nm. However, those skilled in the art will recognize that the dimensions and values described throughout the specification are merely examples and can be varied to suit different scales of integrated circuits.

[0037] After forming the fin structure 20, as Figure 2B shown, an isolation insulating layer 30 is formed over the fin structure 20.

[0038] The isolation insulating layer 30 includes one or more layers of insulating material formed by LPCVD (low pressure chemical vapor deposition), plasma CVD or flowable CVD, such as silicon oxide, silicon oxynitride or silicon nitride. In flowable CVD, a flowable dielectric material is deposited instead of silicon oxide. As the name implies, the flowable dielectric material can "flow" during deposition to fill gaps or spaces with a high aspect ratio. Typically, various chemicals are added to a silicon-containing precursor to allow the deposited film to flow. In some embodiments, hydrogen-nitrogen bonds are added. Examples of flowable dielectric precursors (especially flowable silicon oxide precursors) include silicates, siloxanes, methylsilsesquioxane (MSQ), hydrogen silsesquioxane (HSQ), mixtures of MSQ and HSQ, perhydrosilazane (TCPS), perhydro-polysilazane (PSZ), tetraethyl orthosilicate (TEOS) or silylamines (such as trimethylsilylamine (TSA)). These flowable silicon oxide materials are formed in a plurality of processing steps. After depositing the flowable film, the flowable film is cured and then annealed to remove undesirable elements to form silicon oxide. The flowable film can be doped with boron and / or phosphorus. In some embodiments, the isolation insulating layer 30 can be formed of one or more layers of spin-on glass (SOG), SiO, SiON, SiOCN and / or fluoride-doped silicate glass (FSG).

[0039] After forming the isolation insulating layer 30 over the fin structure 20, a planarization operation is performed to remove a portion of the isolation insulating layer 30 and the mask layers (pad oxide layer and silicon nitride mask layer). The planarization operation may include chemical mechanical polishing (CMP) and / or an etch-back process. Then, as Figure 2B shown, the isolation insulating layer 30 is further removed to expose the upper portion of the fin structure 20 that will become the channel layer.

[0040] In some embodiments, a wet etching process may be used to perform the partial removal of the isolation insulating layer 30. For example, by immersing the substrate in hydrofluoric acid (HF). In another embodiment, a dry etching process may be used to perform the partial removal of the insulating insulating layer 30. For example, a dry etching process using CHF3 or BF3 as the etching gas may be used.

[0041] After forming the isolation insulating layer 30, a thermal process, such as an annealing process, may be performed to improve the quality of the isolation insulating layer 30. In some embodiments, in an inert gas environment such as N2, Ar, or He, the thermal process is performed by using rapid thermal annealing (RTA) at a temperature in the range of about 900 °C to about 1050 °C for about 1.5 seconds to about 10 seconds.

[0042] Then, as Figure 2C shown, a dummy gate structure 40 is formed over a portion of the fin structure 20.

[0043] A dielectric layer and a polysilicon layer are formed over the isolation insulating layer 30 and the exposed fin structure 20, and then a patterning operation is performed to obtain a dummy gate structure including a dummy gate electrode layer 44 made of polysilicon and a dummy gate dielectric layer 42. In some embodiments, the patterning of the polysilicon layer is performed by using a hard mask including a silicon nitride layer and an oxide layer. The dummy gate dielectric layer 42 may be silicon oxide formed by CVD, PVD, ALD, electron beam evaporation, or other suitable processes. In some embodiments, the dummy gate dielectric layer 42 includes one or more layers of silicon oxide, silicon nitride, silicon oxynitride, or a high-k dielectric. In some embodiments, the thickness of the dummy gate dielectric layer is in the range of about 1 nm to about 5 nm.

[0044] In some embodiments, the dummy gate electrode layer 44 is doped polysilicon with uniform or non-uniform doping. In this embodiment, the width of the dummy gate electrode layer 44 is in the range of about 30 nm to about 60 nm. In some embodiments, the thickness of the dummy gate electrode layer is in the range of about 30 nm to about 50 nm. Additionally, one or more dummy gate structures may be disposed near both sides of the dummy gate structure 40 to improve the pattern fidelity in the patterning process. In some embodiments, the width of the dummy gate structure 40 is in the range of about 5 nm to about 40 nm, and in some embodiments, in the range of about 7 nm to about 15 nm.

[0045] In addition, as Figure 2C and Figure 2D shown, sidewall spacers 46 are formed on opposite sides of the dummy gate structure 40. Figure 2D is a cross-section in the y-x plane. An insulating material layer for the sidewall spacers 46 is formed above the dummy gate structure 40. The insulating material layer is deposited in a conformal manner such that it is formed to have substantially equal thicknesses on vertical surfaces such as sidewalls, horizontal surfaces, and the top of the dummy gate structure 40, respectively. In some embodiments, the thickness of the insulating material layer ranges from about 5 nm to about 20 nm. The insulating material layer includes one or more of SiN, SiON, and SiCN or any other suitable dielectric material. The insulating material layer can be formed by ALD or CVD or any other suitable method. Next, the bottom of the insulating material layer is removed by anisotropic etching to form the gate sidewall spacers 46. In some embodiments, the sidewall spacers 46 include two to four different insulating materials. In some embodiments, a portion of the dummy gate dielectric layer 42 is disposed between the sidewall spacers 46 and the isolation insulating layer 30. In other embodiments, no portion of the dummy gate dielectric layer 42 is disposed between the sidewall spacers 46 and the isolation insulating layer 30.

[0046] Subsequently, in some embodiments, the source / drain regions of the fin structure 20 not covered by the dummy gate structure 40 are etched downward (recessed) to form source / drain grooves. After forming the source / drain grooves, one or more source / drain epitaxial layers 60 are formed in the source / drain grooves (see Figure 1B ). In some embodiments, a first epitaxial layer, a second epitaxial layer, and a third epitaxial layer are formed. In other embodiments, no grooves are formed, and an epitaxial layer is formed above the fin structure.

[0047] In some embodiments, the first epitaxial layer includes SiP or SiCP for n-type FinFETs, and B-doped SiGe or Ge for p-type FinFETs. In some embodiments, the amount of P (phosphorus) in the first epitaxial layer ranges from about 1×10 18 atoms / cm 3 to about 1×10 20 atoms / cm 3Within a range. In some embodiments, the thickness of the first epitaxial layer is in the range of about 5 nm to 20 nm, and in other embodiments, in the range of about 5 nm to about 15 nm. When the first epitaxial layer is SiGe, in some embodiments, the amount of Ge is about 25% atomic to about 32% atomic, and in other embodiments is about 28% atomic to about 30% atomic. In some embodiments, the second epitaxial layer includes SiP or SiCP for n-type FinFETs, and SiGe doped with B for p-type FinFETs. In some embodiments, the amount of phosphorus in the second epitaxial layer is higher than the amount of phosphorus in the first epitaxial layer, and is in the range of about 1×10 20 atoms / cm 3 to about 2×10 20 atoms / cm 3 range. In this embodiment, the thickness of the second epitaxial layer is in the range of about 20 nm to 40 nm, or in other embodiments, in the range of about 25 nm to about 35 nm. When the second epitaxial layer is SiGe, in some embodiments, the amount of Ge is about 35% atomic to about 55% atomic, and in other embodiments is about 41% atomic to about 46% atomic. In some embodiments, the third epitaxial layer includes a SiP epitaxial layer. The third epitaxial layer is a sacrificial layer for forming silicide in the source / drain. In some embodiments, the amount of phosphorus in the third epitaxial layer is less than the amount of phosphorus in the second epitaxial layer, and is in the range of about 1×10 18 atoms / cm 3 to about 1×10 21 atoms / cm 3 range. When the third epitaxial layer is SiGe, in some embodiments, the amount of Ge is less than about 20% atomic, and in other embodiments, the amount of Ge is less than about 1% atomic to about 18% atomic.

[0048] In at least one embodiment, the epitaxial layer 60 is epitaxially grown by an LPCVD process, molecular beam epitaxy, atomic layer deposition, or any other suitable method. A silicon source gas such as SiH4, Si2H6, or Si3H8; a germanium source gas such as GeH4 or G2H6; a carbon source gas such as CH4 or SiH3CH3; and a phosphorus source gas such as PH3 are used to implement the LPCVD process at a temperature of about 400 to 850 °C and a pressure of about 1 Torr to 200 Torr.

[0049] Then, as Figure 2C and Figure 2D shown, an interlayer dielectric (ILD) layer 50 is formed over the S / D epitaxial layer 60 and the dummy gate structure 40. Materials for the ILD layer 50 include compounds of Si, O, C, and / or H, such as silicon oxide, SiCOH, and SiOC. Organic materials such as polymers can be used for the ILD layer 50.

[0050] After forming the ILD layer 50, a planarization operation such as CMP is performed to expose the top of the dummy gate electrode layer 44, as Figure 2C and Figure 2D shown. In some embodiments, a contact etch stop layer, such as a silicon nitride layer or a silicon oxynitride layer, is formed before forming the ILD layer 50.

[0051] Then, the dummy gate electrode layer 44 and the dummy gate dielectric layer 42 are removed to form a gate spacer 47 as Figure 2E and Figure 2F shown. Figure 2F is a cross-section in the y-x plane. The dummy gate structure can be removed using plasma dry etching and / or wet etching. When the dummy gate electrode layer 44 is polysilicon and the ILD layer 40 is silicon oxide, a wet etchant such as a TMAH solution can be used to selectively remove the dummy gate electrode layer 44. Thereafter, the dummy gate dielectric layer 42 is removed using plasma dry etching and / or wet etching.

[0052] Figure 3A shows the structure after the channel region of the fin structure 20 is exposed in the gate spacer 47. In Figures 3A to 3F the sidewall spacers 46 and the ILD layer 50 are omitted.

[0053] As Figure 3B shown, in Figure 3G S301, an interface layer 81 is formed on the fin structure 20, and in Figure 3G S303, a gate dielectric layer 82 is formed on the interface layer 81. In some embodiments, the interface layer is formed by chemical oxidation. In some embodiments, the interface layer 81 includes one of silicon oxide, silicon nitride, and mixed silicon germanium oxide. In some embodiments, when the channel is made of Si, the interface layer is a silicon oxide layer 81N, and when the channel is made of SiGe, the interface layer is a silicon germanium oxide layer 81P (see Figure 4A)。In some embodiments, the thickness of the interface layer 81 ranges from about 0.6 nm to about 2 nm. In some embodiments, the gate dielectric layer 82 includes one or more dielectric materials such as silicon oxide, silicon nitride, or high-k dielectric materials, other suitable dielectric materials, and / or combinations thereof. Examples of high-k dielectric materials include HfO2, HfSiO, HfSiON, HfTaO, HfTiO, HfZrO, zirconium oxide, aluminum oxide, titanium dioxide, hafnium dioxide-aluminum oxide (HfO2-Al2O3) alloy, La2O3, HfO2-La2O3, Y2O3, Dy2O3, Sc2O3, MgO, or other suitable high-k dielectric materials, and / or combinations thereof. The gate dielectric layer 82 can be formed by CVD, ALD, or any suitable method. In one embodiment, the gate dielectric layer 82 is formed using a highly conformal deposition process such as ALD to ensure that a gate dielectric layer with a uniform thickness is formed around each channel layer. In one embodiment, the thickness of the gate dielectric layer 82 ranges from about 1 nm to about 30 nm.

[0054] Then, as Figure 3C shown, in Figure 3G S305, a first conductive layer 83 is formed. In some embodiments, the first conductive layer 83 can be formed by CVD, ALD, or any suitable method. In some embodiments, the first conductive layer 83 is made of TiN or TiSiN. In some embodiments, the first conductive layer 83 is not formed.

[0055] In some embodiments, in Figure 3G S307, after the first conductive layer 83 is formed, in some embodiments, the first annealing operation is performed at a temperature of about 600 °C to about 950 °C for about 1 ns (spike annealing such as laser annealing and / or isothermal annealing) to about 360 sec. The first annealing can help densify the gate dielectric layer 82 and incorporate nitrogen into the gate dielectric layer 82. Nitrogen helps passivate oxygen vacancies, reduce leakage, and improve device reliability. The first annealing can also help form a stable mixed layer, which helps provide a stable platform for subsequent metal gate film deposition onto the dielectric layer. When the temperature is too high, the first annealing may cause crystallization and grain boundary formation in the high-k gate dielectric layer 82, which affects the leakage performance and regrowth of the interface layer 81 and slows down the device speed. On the contrary, when the temperature is too low, the first annealing may not provide sufficient densification and / or nitridation in the high-k gate dielectric layer and cause device instability / variation during subsequent metal gate deposition processes. In some embodiments, when the first conductive layer 83 is not formed, no annealing operation is performed at this stage. In some embodiments, the first conductive layer 83 is formed and then the annealing operation is performed; afterwards, the first conductive layer 83 is removed by a wet etching process.

[0056] In some embodiments, a stack structure including an interface layer 81, a gate dielectric layer 82, and a first conductive layer 83 is immersed in a fluorine-containing gas (e.g., F2 and / or NF3) at a temperature of from about room temperature (25 °C) to about 550 °C for about 4 seconds to about 15 minutes. The incorporation of fluorine helps to appropriately improve work function tuning, reduce the Vt of PMOS devices, passivate oxygen vacancies in the gate dielectric layer 82, reduce leakage, and reduce dangling bonds in the gate dielectric. Thereafter, a capping layer made of, for example, crystalline, polycrystalline, or amorphous silicon is formed over the first conductive layer 83, and in some embodiments, a second annealing operation is performed at a temperature of from about 550 °C to about 1300 °C for about 1 nsec (spike annealing, such as laser annealing) to about 360 sec. In some embodiments, the annealing temperature is from 900 °C to 1100 °C. In some embodiments, this causes fluorine to diffuse into the capping layer, the first conductive layer 83, and the gate dielectric layer 82. After the second annealing operation, the capping layer is removed. The second annealing with a silicon capping layer also helps to improve the quality of the gate dielectric layer 82. The gate dielectric layer, such as a high-k dielectric layer, is formed at a relatively low temperature to avoid crystallization and grain boundary formation, while the metal gate film is deposited at a relatively high temperature. Therefore, it is desirable to make the high-k dielectric layer more thermally stable before the metal gate deposition. The second annealing with a capping layer within the temperature range as described above can densify the high-k dielectric layer and make it thermally stable without any thermal oxide conversion during the metal gate deposition. The second annealing also helps to thermally diffuse fluorine from the outer layer (e.g., the capping layer) into the first conductive layer 83, the gate dielectric layer 82, and the interface layer 81. The capping layer is used to protect the gate dielectric layer 82 and the first conductive layer 83 from undesired oxidation damage and to isolate these films from the annealing atmosphere. After the gate dielectric is thermally stable, the capping layer is no longer needed in the final device structure and is thus removed.

[0057] In other embodiments, the fluorine soaking operation accompanied by the formation of a silicon capping layer and the second annealing operation is not performed.

[0058] Subsequently, in Figure 3G S309 thereof, a second conductive layer is formed as the first barrier layer 84, and then in Figure 3G S311 thereof, one or more WFM layers 86 are formed. In Figure 3G S313 thereof, a metal gate layer including an adhesive layer 87 and a bulk metal layer (gate electrode layer) 88 is formed over the work function tuning layer 86.

[0059] In some embodiments, the second conductive layer 84 is made of TaN and serves as an etch stop barrier layer. The barrier layer 86 serves as a wet etch stop layer during the subsequent patterning to form p-type and n-type WFM layers for forming multiple Vt devices. In some embodiments, the second conductive layer 84 is not formed.

[0060] The work function adjustment material (WFM) layer 86 can be formed by ALD, PVD, CVD, electron beam evaporation, or other suitable processes. Additionally, the WFM layer can be formed separately for n-channel FETs and p-channel FETs that can use different metal layers. The gate electrode layer (main body metal layer) 88 and the glue layer 87 can be formed by CVD, ALD, electroplating, or other suitable methods. When the first conductive layer and the second conductive layer are not formed, the WFM layer 86 is formed directly on the gate dielectric layer 82. In some embodiments, the first conductive layer 83 is formed and then removed after the annealing operation S307, after which the second conductive layer is not formed, and the WFM layer 86 is formed directly on the gate dielectric layer 82.

[0061] Figure 4A A cross-sectional view of a gate structure of an FET having different threshold voltages according to an embodiment of the present invention is shown. Figure 4B and Figure 4C A work function adjustment material layer for each of a plurality of FETs having different threshold voltages according to an embodiment of the present invention is shown.

[0062] In some embodiments, the semiconductor device includes a first n-type FET N1 having a WFM layer structure WF1, a second n-type FET N2 having a WFM layer structure WF2, a third n-type FET N3 having a WFM layer structure WF3, a first p-type FET P1 having a WFM layer structure WF3, a second p-type FET P2 having a WFM layer structure WF2, and a third p-type FET P3 having a WFM layer structure WF1. The absolute value of the threshold voltage of the first n-type FET N1 (ultra-low voltage FET) is less than the absolute value of the threshold voltage of the second n-type FET N2 (low voltage FET), and the absolute value of the threshold voltage of the second n-type FET N2 is less than the absolute value of the threshold voltage of the third n-type FET N3 (standard voltage FET). Similarly, the absolute value of the threshold voltage of the first p-type FET P1 (ultra-low voltage FET) is less than the absolute value of the threshold voltage of the second p-type FET P2 (low voltage FET), and the absolute value of the threshold voltage of the second p-type FET P2 is less than the absolute value of the threshold voltage of the third p-type FET P3 (standard voltage FET). The absolute value of the threshold voltage of the first n-type FET N1 is designed to be the same as the absolute value of the threshold voltage of the first p-type FET P1, the absolute value of the threshold voltage of the second n-type FET N2 is designed to be the same as the absolute value of the threshold voltage of the second p-type FET P2, and the absolute value of the threshold voltage of the third n-type FET N3 is designed to be the same as the absolute value of the threshold voltage of the third p-type FET P3.

[0063] In some embodiments, the WFM layer structure WF1 includes a first WFM layer 100, the WFM layer structure WF2 includes a second WFM layer 89-2 closer to the gate dielectric layer 82 and the first WFM layer 100, and the third WFM layer structure WF3 includes a third WFM layer 89-1 closer to the gate dielectric layer 82, the second WFM layer 89-2, and the first WFM layer 100, as Figure 4A shown.

[0064] In Figure 4B , the semiconductor device includes three different threshold voltage levels. In other embodiments, as Figure 4C shown, more than three, for example eight different threshold voltages are utilized for n-type FETs and p-type FETs respectively. In Figure 4C , not only the WFM layer structure is adjusted, but also the configurations HK1, HK2, and HK3 (e.g., materials, thicknesses, etc.) of the gate dielectric layer 82 are adjusted to obtain the desired threshold voltage. HK1, HK2, HK3 are composed of different materials such as HfO2, HfSiO, HfSiON, HfTaO, HfTiO, HfZrO, zirconia, alumina, titanium oxide, hafnium dioxide-aluminum oxide (HfO2-Al2O3) alloy, La2O3, HfO2-La2O3, Y2O3, Dy2O3, Sc2O3, MgO, or other suitable high-k dielectric materials and / or combinations thereof. In some embodiments, HK1, HK2, and HK3 are composed of high-k dielectrics with different concentrations of rare earth metals and / or group III dopants (such as La, Al, Mg, Sc, Dy, Y, Ti, Lu, Sr, etc.). In some embodiments, HK3 is composed of HfO x , HK2 is composed of HfLaO x (or HfYO x , HfLuO x , HfSrO x , HfScO x , HfDyO x ), and HK1 is composed of HfLaO x (or HfYO x , HfLuO x , HfSrO x , HfScO x , HfDyO x ), such that the amount of La (or Y, Lu, Sr, Sc, Dy) in HK1 is higher than that in HK2. In some embodiments, HK1 is composed of HfO x , HK2 is composed of HfAlO x (or HfZrO x , HfTiO x ), and HK3 is composed of HfAlOx (or HfZrO x , HfTiO x ), such that the amount of Al (or Zr, Ti) in HK3 is higher than that in HK2. In some embodiments, HK2 consists of HfO x , HK1 consists of HfLaO x (or HfYO x , HfLuO x , HfSrO x , HfScO x , HfDyO x ), and HK3 consists of HfAlO x (or HfZrO x , HfTiO x ). In some embodiments, HK1 includes an amount of La greater than that of HK2, and HK3 does not include La. In some embodiments, HK3 includes an amount of Al greater than that of HK2, and HK1 does not include Al. In some embodiments, HK1 includes La, HK3 includes Al, and HK2 does not include Al and La. In some embodiments, the thicknesses of HK1, HK2, and HK3 are in the range from about 0.6 nm to about 30 nm. In some embodiments, more than three different high-k dielectric films are used.

[0065] In a CMOS device, a gate electrode is typically used (shared by) for both n-type FETs and p-type FETs, and thus n-type FETs and p-type FETs with substantially the same threshold voltage are selected. For example, a CMOS device with ultra-low voltage FETs includes a first n-type FET N1 and a first p-type FET P1. Figure 5A A plan view (layout) of such a CMOS device is shown.

[0066] As Figure 5A shown, a gate electrode 80 is disposed above one or more fin structures 20 (channel regions). In some embodiments, each of the n-type FET NFET and the p-type FET PFET includes two fin structures. In other embodiments, the number of fin structures for each FET is one or three or more (e.g., up to 10). Figure 5B A cross-sectional view corresponding to region A1 of Figure 5A is shown, and Figure 5C a magnified view of region B1 of Figure 5B is shown. In Figure 5B and Figure 5C , the glue layer 87 and the body metal layer 88 (shown in dashed lines) are omitted.

[0067] As described above, the n-type FET NFET (e.g., N1) has a WFM layer structure WF1 that (only) has the first WFM layer 100, and the p-type FET (e.g., P1) has a WFM layer structure WF3 that has the second and third WFM layers (89-2 and 89-1, collectively referred to as 89 in Figure 5B ), as well as the first WFM layer 100. Thus, in the boundary MB between the n-type FET NFET and the p-type FET PFET, the second and third WFM layers 89 are discontinuously formed.

[0068] Similarly, in Figures 6A to 6C , the CMOS device having a threshold voltage Vt3 includes an n-type FET having a WFM layer structure WF2 and a p-type FET having a WFM layer structure WF3 (see Figure 4C ). Figure 6B A cross-sectional view corresponding to the region A2 of Figure 6A is shown, and Figure 6C shows an enlarged view of the region B2 of Figure 6B . In Figure 6B and Figure 6C , the glue layer 87 and the body metal layer 88 are omitted.

[0069] As Figure 6A shown, the gate electrode 80 is disposed above one or more fin structures 20 (channel regions). As described above, the n-type FET NFET has a WFM layer structure WF2 that has the first WFM layer 100 and the second WFM layer 89-2, and the p-type FET has a WFM layer structure WF3 that has the second and third WFM layers as well as the first WFM layer 100. Thus, at the boundary MB between the n-type FET NFET and the p-type FET PFET, the third WFM layer 89-1 is discontinuously formed.

[0070] When the first WFM layer 100 includes aluminum, the aluminum can diffuse across the boundary MB into the second and / or third WFM layers 89, and can change the threshold voltage of the p-type FET PFET (and can change the threshold voltage of the n-type FET NFET). In particular, when the diffused Al forms aluminum oxide having a high resistivity, the device performance of the p-type FET PFET will be reduced. In addition, the lateral diffusion of Al into the third WFM layer 89-1 has a greater impact on the threshold voltage than the vertical diffusion of Al from the top of the second WFM layer 89-2. As the integrated circuit scales down, the spacing between adjacent p-type and n-type FET devices decreases, and these FET devices are close together. Thus, the lateral diffusion across adjacent devices becomes critical and results in significant threshold voltage shifts and performance degradation.

[0071] According to some embodiments of the present invention, the WFM layer 100 comprises aluminum (e.g., TiAl and TiAlC), and further includes a diffusion barrier layer at least at one of the bottom surface region and the top surface region of the WFM layer 100. In some embodiments, the diffusion barrier layer is at least one of a Ta-rich, Ta-doped, Si-doped, Ti-doped, or Ti-rich layer. The diffusion barrier layer inhibits the diffusion of aluminum into the WFM layers 89-1 and 89-2 of nearby FET devices made of, for example, WCN, WN, Ru, TiN, or TiSiN. In some embodiments, the diffusion barrier layer of the WFM layer 100 comprises a Ti-rich TiAl layer, a Ti-doped TaAl layer, a Ta-rich TaAl layer, a Ta-doped TiAl layer, a Si-doped TiAl layer, and a Si-doped TaAl layer.

[0072] In some embodiments, the body (central region) of the WFM layer 100 is made of TiAl or TiAlC, and comprises 5 atomic % to about 15 atomic % of Ti, and the Al content ranges from about 10 atomic % to about 30 atomic %, while in some embodiments, the remainder comprises carbon (e.g., about 8 atomic % to about 25 atomic %) and / or oxygen. In some embodiments, the Al / Ti ratio ranges from about 1.5 to about 3.0.

[0073] In some embodiments, the diffusion barrier layer contains a higher amount of titanium than the central region adjacent to the diffusion barrier layer, and the amount of Ti ranges from about 20 atomic % to about 50 atomic %, and in other embodiments, ranges from about 30 atomic % to about 40 atomic %. In some embodiments, the Al / Ti ratio of the diffusion barrier layer ranges from about 0.2 to about 1.2. In some embodiments, when the diffusion barrier layer is a Ti-rich layer, the Al / Ti ratio of the Ti-rich layer ranges from about 0.2 to about 1.2. In some embodiments, when the diffusion barrier layer is a Ta-doped layer, the Ta-doped layer contains a higher amount of tantalum than the central region adjacent to the Ta-rich layer, and the amount of Ta ranges from about 20 atomic % to about 50 atomic %, and in other embodiments, ranges from about 30 atomic % to 40 atomic %. In some embodiments, the Al / Ta ratio of the Ta-doped layer ranges from about 0.2 to about 1.2. The Ta-doped TiAl layer is formed by an ALD, PEALD or CVD process, and cycles of alternating pulses and purges of Ta precursors (e.g., PDMAT / TaCl5), Al precursors and Ti precursors and Ar, He inert gas purges. In some embodiments, the process temperature ranges from about 300 °C to about 550 °C. In some embodiments, when the diffusion barrier layer is a Si-doped layer, the silicon-doped layer contains a higher amount of silicon than the central region adjacent to the Si-rich layer, and the amount of Si ranges from about 20 atomic % to about 50 atomic %, and in other embodiments, ranges from about 30 atomic % to about 40 atomic %. In some embodiments, the Al / Si ratio of the Si-doped layer ranges from about 0.2 to about 1.2. The Si-doped TiAl layer is formed by an ALD, PEALD or CVD process, and cycles of alternating pulses and purges of Si precursors (SiCl4, SiHCl3, etc.), Al precursors and Ti precursors and Ar, He inert gas purges. In some embodiments, the process temperature ranges from about 300 °C to about 550 °C.

[0074] In some embodiments, as Figure 7A and Figure 7B shown, the WFM layer 100 includes a top diffusion barrier layer 140 and a bottom diffusion barrier layer 145. Figure 7B illustrates a structure similar to Figure 5C at the boundary MB of the n-type FET and the p-type FET. In some embodiments, as Figure 7C and Figure 7DAs shown, the WFM layer 100 only includes the bottom diffusion barrier layer 145. In these configurations, at least the bottom diffusion barrier layer 145 can inhibit the diffusion of aluminum from the WFM layer 100 of one FET to the WFM layers 89-1 and / or 89-2 of nearby FETs. In the absence of a diffusion barrier layer, Al diffuses at the metal boundary between the left FET and the right FET. Due to the loss of Al from the WFM 100 of the left FET, the overall effective work function of the left FET increases, and due to the gain of Al in the WFM layer 89-1 and / or 89-2 of the right FET, the overall work function of the right FET decreases. However, by using one or more diffusion barrier layers, this Al diffusion across the metal boundary of nearby FETs can be inhibited, thereby providing better isolation for nearby devices.

[0075] In addition, in some embodiments, as Figure 7E and Figure 7F shown, the WFM layer 100 only includes the top diffusion barrier layer 140. In this case, the top diffusion barrier layer 140 improves the quality of the bulk TiAl or TiAlC layer (the central region of the WFM layer 100), which in turn can also inhibit the diffusion of aluminum from the WFM layer 100 to the WFM layers 89-1 and / or 89-2. Although the mechanism for inhibiting Al diffusion is not clear, an improvement in device electrical performance has been observed.

[0076] Figure 8A and Figure 8B show the Ta or Si or Ti distribution in the WFM layer 100 with top and bottom diffusion barrier layers according to some embodiments.

[0077] In some embodiments, as Figure 8A shown, the Ta or Si or Ti concentration has a substantially constant portion S2 with an atomic concentration of X1%, and the Ta or Si or Ti concentration gradually increases to X2% atomic at the edges (top and bottom surfaces). In some embodiments, the Ta or Si or Ti concentration increases linearly, and in other embodiments, the Ta or Si or Ti concentration increases gradually (non-linearly). In Figure 8B it, the Ta or Si or Ti concentration has a stepped distribution.

[0078] In some embodiments, when the WFM layer 100 is made of TiAl or TiAlC, the Ti concentration ranges from about 5 at% to about 15 at%, and in other embodiments, from about 8 at% to about 12 at%; the Al concentration ranges from about 10 at% to about 30 at%; the balance is carbon and / or oxygen. In some embodiments, the Al / Ti ratio ranges from about 1.5 to 4.8. When the diffusion barrier layer is a Ti-rich layer, the Ti concentration of the Ti-rich layer ranges from about 20 at% to about 50 at%, and in some embodiments, the Al / Ti ratio ranges from about 0.2 to about 1.2. When the diffusion barrier layer is a Ta-doped layer, the Ta concentration of the Ta-doped layer ranges from about 20 at% to about 50 at%. When the diffusion barrier layer is an Si-doped layer, the Si concentration of the Si-doped layer ranges from about 20 at% to about 50 at%. In some embodiments, the diffusion barrier layer is a substantially pure Ti layer (95 - 100 at%). In some embodiments, the diffusion barrier layer is a TiSi layer having an Si concentration in the range from about 25 at% to about 65 at%.

[0079] In some embodiments, when the WFM layer 100 is made of TaAl or TaAlC, the Ta concentration ranges from about 5 at% to about 15 at%, and in other embodiments, from about 8 at% to about 12 at%; the Al concentration ranges from about 10 at% to about 30 at%; the balance is carbon and / or oxygen. In some embodiments, the Al / Ta ratio ranges from about 1.5 to 3.0. When the diffusion barrier layer is a Ta-rich layer, the Ta concentration of the Ta-rich layer ranges from about 20 at% to about 50 at%, and in some embodiments, the Al / Ta ratio ranges from about 0.2 to about 1.2. When the diffusion barrier layer is a Ti-doped layer, the Ti concentration of the Ti-doped layer ranges from about 20 at% to about 50 at%. When the diffusion barrier layer is an Si-doped layer, the Si concentration of the Si-doped layer ranges from about 20 at% to about 50 at%. In some embodiments, the diffusion barrier layer is a substantially pure Ta layer (95 - 100 at%). In some embodiments, the diffusion barrier layer is a TiSi layer having an Si concentration in the range from about 25 at% to about 65 at%.

[0080] In some embodiments, X1 in X1% of Ti atoms ranges from about 5 to about 15, and in other embodiments, ranges from about 8 to about 12. In some embodiments, X1 in X1% of Ti atoms ranges from about 0 to about 2, where the WFM layer 100 is TaAl or TaAlC. In some embodiments, X1 in X1% of Ti atoms ranges from about 0 to about 2, where the WFM layer 100 is TaAl or TaAlC, and in other embodiments, ranges from about 5 to about 15. In some embodiments, X1 in X1% of Si atoms in the Si doping layer ranges from about 0 to about 5. In some embodiments, X2 ranges from about 20 to about 50, and in other embodiments, ranges from about 30 to about 40. In some embodiments, a Ti layer without aluminum is used as the Ti-rich layer. In some embodiments, a Ta layer without aluminum is used as the Ta-rich layer. In some embodiments, a Si layer without aluminum is used as the Si-rich layer. In some embodiments, the thickness of the constant portion S2 is at least about 20% of the total thickness of the WFM layer 100, and in other embodiments, at least about 40% of the total thickness of the WFM layer 100. In some embodiments, the thickness of the constant portion S2 is at most about 90% of the total thickness of the WFM layer 100, and in other embodiments, at most about 60% of the total thickness of the WFM layer 100.

[0081] In some embodiments, the thickness of the diffusion barrier layer 140 / 145 is adjusted based on the Ta, Si, or Ti concentration of the diffusion barrier layer. When the Ta, Si, or Ti concentration in the diffusion barrier layer 140 / 145 is high, the thickness of the diffusion barrier layer 140 / 145 can be small. In some embodiments, the thickness and / or Ta / Si / Ti concentration of the diffusion barrier layer in the WFM layer 100 is adjusted based on the desired work function of the WFM layer 100.

[0082] In some embodiments, the diffusion barrier layer 140 / 145 can be formed by an ALD method. In the ALD method, at least one of the amount of source gas (precursor), the flow time of the source gas (precursor), the gas flow ratio, the deposition temperature, and the deposition pressure is changed to obtain the Ta / Si / Ti concentration distribution as described above.

[0083] Figure 9 A process flow according to an embodiment of the present invention is shown, and Figures 10A to 10F A cross-sectional view showing each stage of manufacturing a semiconductor device according to an embodiment of the present invention is shown. It should be understood that in the sequential manufacturing process, it can be at Figure 9 and Figures 10A to 10FOne or more additional operations are provided before, during, and after the stages shown. For additional embodiments of the method, some of the operations described below may be replaced or eliminated. The order of operations / processes may be interchanged. Embodiments described with respect to Figures 1A to 8B may be employed in subsequent embodiments, and the detailed description may be omitted. Although Figures 10A to 10F is shown with respect to Figure 7A and Figure 8A the WFM layer 100 explained, any structure shown in Figure 7C , Figure 7E and Figure 8B may be used as the WFM layer 100.

[0084] In Figure 9 S901, the channel regions of the fin structures are exposed for the first n-type FET N1, the second n-type FET N2, the third n-type FET N3, the first p-type FET P1, the second p-type FET P2, and the third p-type FET P3, respectively. In some embodiments, the channel regions for the n-type FETs are made of Si, and the channel regions for the p-type FETs are made of SiGe.

[0085] In Figure 9 S902, an interface layer 81N and 81P is formed on each of the channel regions 20 using a chemical oxidation method. In some embodiments, when the channel is made of Si, the interface layer is a silicon oxide layer 81N, and when the channel is made of SiGe, the interface layer is a silicon germanium oxide layer 81P. In Figure 9 S903, a gate dielectric layer (e.g., a high-k gate dielectric layer) 82 is formed on the interface layer 81N / 81P. In some embodiments, different gate dielectric layers are formed at different FET devices. In some embodiments, in Figure 9 S904, a capping layer 83 is formed on the gate dielectric layer 82, followed by an annealing operation in S905, and in Figure 9 S906, a barrier layer 84 is formed on the capping layer 83. In other embodiments, no capping layer and barrier layer are formed. In other embodiments, a capping layer is formed, annealing is performed, and then the capping layer is removed and no barrier layer is formed.

[0086] In Figure 9 S907, in as Figure 10AA third WFM layer 89-1 is formed on the gate dielectric layer 82 shown. The third WFM layer 89-1 includes WN, WCN, W, Ru, TiN, or TiSiN formed by, for example, CVD, ALD, PVD, or any other suitable film formation method. In some embodiments, the thickness of the third WFM layer 89-1 ranges from about 0.5 nm to about 20 nm, and in other embodiments, from about 1 nm to about 10 nm.

[0087] In Figure 9 S908 of, a first patterning operation is performed to remove the third WFM layer 89-1 from the regions for the first n-type FET N1, the second n-type FET N2, the second p-type FET P2, and the third p-type FET P3. In some embodiments, a bottom anti-reflective coating 200 made of an organic material is formed on the third WFM layer 89-1, and a photoresist layer 205 is formed on the bottom anti-reflective coating 200, as Figure 10A shown. By using one or more lithography operations, the photoresist layer 205 is patterned to expose the bottom anti-reflective coating 200 at the regions for the first and second n-type FETs and the second and third p-type FETs. Then, the exposed bottom anti-reflective coating 200 is removed by one or more plasma etching operations to expose the third WFM layer 89-1 at the regions for the first and second n-type FETs and the second and third p-type FETs, as Figure 10A shown. The plasma etching operation utilizes a gas including N2 and H2, a gas including O2 / Cl2, and / or O2 gas. In some embodiments, no bottom anti-reflective layer is used, and a photoresist layer made of an organic material is formed on the third WFM layer 89-1.

[0088] Subsequently, the third WFM layer 89-1 in the first and second n-type FETs and the second and third p-type FETs is removed by an appropriate etching operation, as Figure 10B shown. In some embodiments, the etching operation includes a wet etching operation. The etching solution (etchant) includes: an aqueous solution of HCl and H2O2; an aqueous solution of a combination of NH4OH and H2O2; an aqueous solution of a combination of HCl, NH4OH, and H2O2; an aqueous solution of HF, NH4OH, and H2O2; and / or an aqueous solution of H3PO4 and H2O2.

[0089] In Figure 9 S909 of, a second WFM layer 89-2 is formed on the gate dielectric layer 82 in the regions for the first and second n-type FETs and the second and third p-type FETs and on the third WFM layer 89-1 in the regions for the third n-type FET and the first p-type FET, as Figure 10CAs shown. The second WFM layer 89-2 includes WN, WCN, W, Ru, TiN, or TiSiN formed by, for example, CVD, ALD, PVD, or any other suitable film-forming method. In some embodiments, the thickness of the second WFM layer 89-2 ranges from about 0.5 nm to about 20 nm, and in other embodiments, from about 1 nm to about 10 nm. In some embodiments, the second and third WFM layers are made of the same material.

[0090] In Figure 9 S910, a second patterning operation is performed to remove the second WFM layer 89-2 from the regions for the first n-type FET N1 and the third p-type FET P3. The second patterning operation is substantially the same as or similar to the first patterning operation. Figure 10D The structure after removing the second WFM layer 89-2 from the regions for the first n-type FET N1 and the third p-type FET P3 is shown.

[0091] In Figure 9 S911, a first WFM layer 100 is formed on the gate dielectric layer 82 in the regions for the first n-type FET and the third p-type FET and on the second WFM layer 89-2 in the regions for the second and third n-type FETs and the first and second p-type FETs, as Figure 10E shown. In some embodiments, the first WFM layer 100 is formed by ALD, for example. In some embodiments, the thickness of the first WFM layer 100 ranges from about 0.6 nm to about 40 nm, and in other embodiments, from about 1 nm to about 20 nm. In some embodiments, the thickness of the first WFM layer 100 is greater than each of the second and third WFM layers.

[0092] In Figure 9 S912, a capping layer 110 is formed on the first WFM layer 100. In some embodiments, the capping layer 110 includes one or more metal nitride layers, such as TiN, TaN, TaTiN, WN, TiSiN, WCN, and MoN. In other embodiments, no capping layer is formed.

[0093] In Figure 9 S913, a glue layer 87 is formed, and then in Figure 9 S914, a body gate metal layer 88 is formed, as Figure 10E shown. In some embodiments, the glue layer 87 is made of TiN, Ti, and / or Co. In some embodiments, the body metal layer 88 is made of W, Al, Co, or any other suitable metal material.

[0094] As described above, the Ti-rich layer of the first WFM layer 100 suppresses the diffusion of Al from the WFM layer 100 to the underlying WFM layer 89 and the gate dielectric layer 82 and / or to adjacent FETs, as Figure 11 shown.

[0095] In addition, using a diffusion barrier layer can also reduce the thickness of the interface layer 81 by removing oxygen from the interface layer 81. Figure 12A and Figure 12B show the effect of reducing the thickness of the interface layer according to an embodiment of the present invention.

[0096] As Figure 12A and Figure 12B shown, as the thickness of the diffusion barrier layer increases and / or the Ti / Al ratio or the amount of Ta or the amount of Si in the diffusion barrier layer increases, the thickness of the interface layer decreases, which improves the operating speed of the device. In some embodiments, the thickness of the interface layer can be reduced to about 0.6 nm or less (greater than zero).

[0097] It should be understood that not all advantages have been discussed herein, that no particular advantage is required for all embodiments, and that other embodiments may provide different advantages.

[0098] According to one aspect of the present invention, a semiconductor device includes: a gate structure disposed over a channel region; and source / drain regions. The gate structure includes: a gate dielectric layer located over the channel region; one or more work function adjustment material layers located over the gate dielectric layer; and a metal gate electrode layer located over the one or more work function adjustment material layers. The one or more work function adjustment layers include an aluminum-containing layer, and a diffusion barrier layer is disposed at at least one of the bottom and the top of the aluminum-containing layer, and the diffusion barrier layer is one or more of a Ti-rich layer having a higher Ti concentration than the center of the aluminum-containing layer, a Ti-doped layer, a Ta-rich layer having a higher Ta concentration than the center of the aluminum-containing layer, a Ta-doped layer, and an Si-doped layer. In one or more of the above and below embodiments, the aluminum-containing layer has a work function of less than 4.4 eV and is made of one selected from the group consisting of TaAl, TaAlC, TiAl, and TiAlC. In one or more of the above and below embodiments, the central portion of the aluminum-containing layer has a lower Ta, Si, or Ti concentration than the diffusion barrier layer. In one or more of the above and below embodiments, the concentration of Ti, Ta, or Si in the diffusion barrier layer is in the range of 20 atomic % to 50 atomic %, and the concentration of Ti or Ta in the central portion is in the range of 5 atomic % to 15 atomic %. In one or more of the above and below embodiments, the concentration of Ti, Ta, or Si in the diffusion barrier layer gradually increases from one side on the central portion to the surface of the aluminum-containing layer. In one or more of the above and below embodiments, the concentration of Ti, Ta, or Si in the diffusion barrier layer is constant. In one or more of the above and below embodiments, the concentration of Ti or Ta in the central portion is constant. In one or more of the above and below embodiments, the aluminum concentration of the aluminum-containing layer is in the range of 10 atomic % to 30 atomic %. In one or more of the above and below embodiments, the thickness of the central portion is in the range of 20% to 60% of the total thickness of the aluminum-containing layer. In one or more of the above and below embodiments, the one or more work function adjustment material layers include a high work function material layer (having a work function greater than 4.4 eV), including at least one of WN, WCN, W, Ru, TiN, or TiSiN between the aluminum-containing layer and the gate dielectric layer or between the aluminum-containing layer and the glue layer.

[0099] According to another aspect of the present invention, a complementary metal oxide semiconductor (CMOS) device includes: a first field effect transistor (FET) including a first gate structure disposed over a first channel region; and a second FET including a second gate structure disposed over a second channel region. The first FET is an n-type FET and the second FET is a p-type FET. The first gate structure includes: a gate dielectric layer; a first work function adjustment material layer disposed over the gate dielectric layer; and a glue and metal gate electrode layer disposed over the first work function adjustment material layer. The second gate structure includes: a gate dielectric layer; a second work function adjustment material layer disposed over the gate dielectric layer; the first work function adjustment material layer disposed over the second work function adjustment material layer; and a glue and metal gate electrode layer disposed over the first work function adjustment material layer. The metal gate electrode and the first work function adjustment material layer are continuous between the first FET and the second FET. The first work function adjustment layer includes aluminum (such as TiAl, TiAlC, TaAl, or TaAlC), and the first work function adjustment layer includes a diffusion barrier layer at at least one of the bottom and the top of the first work function adjustment layer, and the diffusion barrier layer is one or more of a Ti-rich layer having a higher Ti concentration than the center of the first work function adjustment layer, a Ti-doped layer, a Ta-rich layer having a higher Ta concentration than the center of the first work function adjustment layer, a Ta-doped layer, and a Si-doped layer.

[0100] In one or more of the above and below embodiments, the second work function adjustment layer includes at least one of WCN, WN, W, Ru, TiN, TiCN, and TiSiN. In one or more of the above and below embodiments, the second work function adjustment layer includes one or more layers made of WCN, WN, W, Ru, TiN, TiCN, or TiSiN, and at least one of the one or more layers is discontinuous between the first FET and the second FET. In one or more of the above and below embodiments, the first work function adjustment layer covers the top surface and the side surface of at least one of the one or more layers at the metal boundary between the first FET and the second FET. In one or more of the above and below embodiments, the diffusion barrier layer is disposed at the bottom of the first work function adjustment layer. In one or more of the above and below embodiments, the second work function adjustment material layer in the second FET does not contain Al. In one or more of the above and below embodiments, the first work function adjustment material layer further includes Ti, the diffusion barrier layer is a Ti-rich layer or a Ti-doped layer having a higher Ti concentration than the center of the first work function adjustment layer, the Ti concentration of the Ti-rich layer or the Ti-doped layer is in the range of 20% to 50% by atoms, and the Ti concentration of the central portion is in the range of 5% to 15% by atoms. In one or more of the above and below embodiments, the first work function adjustment material layer is directly disposed on the gate dielectric layer. In one or more of the above and below embodiments, the thickness of the central portion is in the range of 20% to 90% of the total thickness of the aluminum-containing layer.

[0101] According to another aspect of the present disclosure, in a method of manufacturing a semiconductor device, a gate dielectric layer is formed over a channel region made of a semiconductor material, a first work function adjustment layer is formed over the gate dielectric layer, and a metal gate electrode layer is formed over the first work function adjustment layer. The first work function adjustment layer includes aluminum, and forming the first work function adjustment layer includes forming a diffusion barrier layer at at least one of the bottom and the top of the first work function adjustment layer, and the diffusion barrier layer is one or more of a Ti-rich layer having a higher Ti concentration than the center of the first work function adjustment layer, a Ti-doped layer, a Ta-rich layer having a higher Ta concentration than the center of the first work function adjustment layer, a Ta-doped layer, and a Si-doped layer. In one or more of the above and below embodiments, forming the Ti-rich layer or the Ti-doped layer includes gradually changing a source gas for at least one of aluminum and titanium during TiAl deposition, or introducing a Ti source precursor during TaAl or TaAlC deposition. In one or more of the above and below embodiments, forming the Ta-rich layer or the Ta-doped layer includes gradually changing a source gas for at least one of aluminum and tantalum during TaAl deposition, or introducing a Ta source precursor during TiAl or TiAlC deposition. In one or more of the above and below embodiments, forming the Si-doped layer includes introducing a third Si source precursor during cyclic ALD deposition of TiAl, such as by performing a cyclic pulse purge operation on an Al-based precursor, a Si-based precursor, and a Ti(or Ta)-based precursor.

[0102] The features of several embodiments or examples are outlined above so that those skilled in the art can better understand aspects of the present invention. Those skilled in the art should understand that they can readily use the present invention as a basis to design or modify other processes and structures for implementing the same purposes and / or achieving the same advantages as the embodiments or examples introduced herein. Those skilled in the art should also realize that such equivalent constructs do not depart from the spirit and scope of the present invention, and various changes, substitutions, and alterations can be made to them herein without departing from the spirit and scope of the present invention.

Claims

1. A semiconductor device, comprising: A gate structure disposed above a channel region; And Source / drain regions, wherein: The gate structure comprises: A gate dielectric layer located above the channel region; One or more work function adjustment material layers located above the gate dielectric layer; and A metal gate electrode layer located above the one or more work function adjustment material layers; The one or more work function adjustment material layers include an aluminum-containing layer, and A diffusion barrier layer is disposed at least at one of the bottom and the top of the aluminum-containing layer, and the diffusion barrier layer is one or more of a tantalum-rich layer, a tantalum-doped layer, and a silicon-doped layer having a higher tantalum concentration than the center of the aluminum-containing layer, Wherein, when the aluminum-containing layer includes tantalum, the diffusion barrier layer has a higher tantalum concentration than the aluminum-containing layer; when the aluminum-containing layer includes silicon, the diffusion barrier layer has a higher silicon concentration than the aluminum-containing layer. In the diffusion barrier layer and the aluminum-containing layer, the tantalum concentration or the silicon concentration in the central portion of the aluminum-containing layer is constant, and the tantalum concentration or the silicon concentration in the diffusion barrier layer gradually increases in a direction away from the central portion.

2. The semiconductor device according to claim 1, wherein, The aluminum-containing layer has a work function of less than 4.4 eV and is made of one selected from the group consisting of TaAl, TaAlC, and.

3. The semiconductor device according to claim 1, wherein, The gate dielectric layer includes one or more dielectric materials.

4. The semiconductor device according to claim 2, wherein: The concentration of tantalum or silicon in the diffusion barrier layer is in the range of 20% to 50% by atoms, and The tantalum concentration in the central portion is in the range of 5% to 15% by atoms.

5. The semiconductor device according to claim 2, wherein, The diffusion barrier layer is located between the aluminum-containing layer and the gate dielectric layer and is in contact with the gate dielectric layer.

6. The semiconductor device according to claim 2, wherein, The diffusion barrier layer is disposed at the bottom and the top of the aluminum-containing layer.

7. The semiconductor device according to claim 1, wherein, The thickness of the gate dielectric layer is in the range of 1 nm to 30 nm.

8. The semiconductor device according to claim 2, wherein, The aluminum concentration in the aluminum-containing layer is in the range of 10% to 30% by atoms.

9. The semiconductor device according to claim 2, wherein, The thickness of the central portion is in the range of 20% to 60% of the total thickness of the aluminum-containing layer.

10. The semiconductor device according to claim 1, wherein, The one or more work function adjustment material layers include a work function material layer having a work function greater than 4.4 eV and include at least one of WCN, WN, W, Ru, TiN, or TiSiN disposed between the aluminum-containing layer and the gate dielectric layer.

11. A complementary metal oxide semiconductor device, comprising: A first field effect transistor including a first gate structure disposed above a first channel region; And A second field effect transistor including a second gate structure disposed above a second channel region, wherein: The first field effect transistor is an n-type field effect transistor, the second field effect transistor is a p-type field effect transistor, and The first gate structure comprises: A gate dielectric layer; A first work function adjustment material layer located above the gate dielectric layer; and A metal gate electrode layer located above the first work function adjustment material layer, The second gate structure comprises: A gate dielectric layer; A second work function adjustment material layer located above the gate dielectric layer; The first work function adjusting material layer is located above the second work function adjusting material layer; and A metal gate electrode layer is located above the first work function adjusting material layer, The metal gate electrode and the first work function adjusting material layer are continuous between the first field effect transistor and the second field effect transistor, so that the metal gate electrode is disposed above the gate dielectric layer of the first field effect transistor, above the second work function adjusting material layer of the second field effect transistor and above the side wall of the second work function adjusting material layer at the boundary between the first field effect transistor and the second field effect transistor. The first work function adjusting material layer includes aluminum, and The first work function adjusting material layer includes a diffusion barrier layer at at least one of the bottom and the top of the first work function adjusting material layer. The diffusion barrier layer is one or more of a tantalum-rich layer, a tantalum-doped layer and a silicon-doped layer having a higher tantalum concentration than the center of the first work function adjusting material layer, Wherein, when the first work function adjusting material layer includes tantalum, the diffusion barrier layer has a higher tantalum concentration than the tantalum concentration of the first work function adjusting material layer; when the first work function adjusting material layer includes silicon, the diffusion barrier layer has a higher silicon concentration than the silicon concentration of the first work function adjusting material layer. In the diffusion barrier layer and the first work function adjusting material layer, the tantalum concentration or the silicon concentration of the central portion of the first work function adjusting material layer is constant, and the tantalum concentration or the silicon concentration in the diffusion barrier layer gradually increases in a direction away from the central portion.

12. The complementary metal oxide semiconductor device according to claim 11, wherein, The second work function adjusting material layer includes at least one of WN, WCN, W, Ru, TiN and TiSiN.

13. The complementary metal oxide semiconductor device according to claim 11, wherein: The second work function adjusting material layer includes at least one of WN, WCN, W, Ru, TiN and TiSiN, and At least one of one or more layers of the second work function adjusting material layer between the first field effect transistor and the second field effect transistor is discontinuous.

14. The complementary metal oxide semiconductor device according to claim 13, wherein, The first work function adjusting material layer covers the top surface and the side surface of at least one of the one or more layers at the metal boundary between the first field effect transistor and the second field effect transistor.

15. The complementary metal oxide semiconductor device according to claim 11, wherein, The diffusion barrier layer is disposed at the bottom of the first work function adjusting material layer.

16. The complementary metal oxide semiconductor device according to claim 11, wherein, The second work function adjusting material layer in the second field effect transistor does not contain aluminum.

17. The complementary metal oxide semiconductor device according to claim 11, wherein: The gate dielectric layer includes one or more layers of dielectric material.

18. The complementary metal oxide semiconductor device according to claim 11, wherein, The first work function adjusting material layer is directly disposed on the gate dielectric layer.

19. The complementary metal oxide semiconductor device according to claim 11, wherein, The thickness of the central portion is in the range of 20% to 90% of the total thickness of the first work function adjusting material layer.

20. A method of manufacturing a semiconductor device, comprising: Forming a gate dielectric layer above a channel region made of a semiconductor material; Forming a first work function adjusting layer above the gate dielectric layer; And Forming a metal gate electrode layer above the first work function adjusting layer, wherein: The first work function adjusting layer includes aluminum, Forming the first work function adjustment layer includes forming a diffusion barrier layer at at least one of the bottom and the top of the first work function adjustment layer, and the diffusion barrier layer is one or more of a tantalum-rich layer, a tantalum-doped layer, and a silicon-doped layer having a higher tantalum concentration than the center of the first work function adjustment layer. Wherein, when the first work function adjustment layer includes tantalum, the diffusion barrier layer has a higher tantalum concentration than the first work function adjustment layer; when the first work function adjustment layer includes silicon, the diffusion barrier layer has a higher silicon concentration than the first work function adjustment layer. In the diffusion barrier layer and the first work function adjustment layer, the tantalum concentration or the silicon concentration of the central portion of the first work function adjustment layer is constant, and the tantalum concentration or the silicon concentration in the diffusion barrier layer gradually increases in a direction away from the central portion.

Images