System and method for providing intelligent constant on-time control

Abstract

A system for providing intelligent constant on-time control may include a first switch coupled to a power supply input; a second switch coupled to the first switch; a switch node between the first switch and the second switch, the switch node being configured to be connected to an inductor and a power supply output; a feedback path coupled to (1) the switch node and (2) the power supply output, the feedback path implementing feedback of signals from (1) the switch node and (2) the power supply output; and a processor coupled to the feedback path. The processor may be configured to control a voltage at the power supply output based on a combination of signals carried by the feedback path.

Description

[0001] This application is a divisional application, and its original application is an application with application number 201810801313.5 and application date July 20, 2018, and its name is “System and method for providing intelligent constant on-time control”.

[0002] CROSS-REFERENCE TO RELATED APPLICATIONS

[0003] This application claims priority to U.S. Provisional Application No. 62 / 536,598, entitled “SYSTEMS AND METHODS FOR PROVIDING INTELLIGENT CONSTANT ON-TIME CONTROL,” filed on July 25, 2017. The entire contents of the above application are incorporated herein by reference. Technical Field

[0004] The present disclosure relates generally to on-time control, and more particularly to providing intelligent constant on-time (COT) control. Background Art

[0005] A switching regulator with ripple-based control (i.e., a "ripple regulator") can have a fast transient response to both line disturbances and load disturbances. In particular, some ripple regulators can operate at a switching frequency that is proportional to the load current in DCM (discontinuous conduction mode), and because the load changes slowly, the transition between CCM (continuous conduction mode) and DCM may introduce only a small output voltage overshoot or undershoot. The above characteristics may make these ripple regulators very suitable for power management applications in computers and portable electronic devices. However, ripple regulators have some disadvantages, such as (1) tendency to large signal instability and noise-induced jitter (especially in the case of ceramic output capacitors); (2) inadequate DC regulation; and (3) poorly defined switching frequency under CCM operation. Summary of the invention

[0006] One aspect of the present disclosure relates to a system for providing intelligent constant on-time control. The system may include a first switch coupled to a power supply input; a second switch coupled to the first switch; a switch node between the first switch and the second switch, the switch node being configured to be connected to an inductor and a power supply output; a feedback path coupled to (1) the switch node and (2) the power supply output, the feedback path implementing feedback of signals from (1) the switch node and (2) the power supply output; and a processor coupled to the feedback path. The processor may be configured to control a voltage at the power supply output based on a combination of signals carried by the feedback path.

[0007] One aspect of the present disclosure relates to a method for providing intelligent constant on-time control for a system, the system comprising a first switch coupled to a power supply input; a second switch coupled to the first switch; a switch node between the first switch and the second switch, the switch node being configured to be connected to an inductor and a power supply output; and a feedback path coupled to (1) the switch node and (2) the power supply output, the feedback path implementing feedback of signals from (1) the switch node and (2) the power supply output. A combination of signals carried by the feedback path can be received. A voltage at the power supply output can be controlled based on the combination of signals carried by the feedback path.

[0008] In some embodiments, the on-time of the first switch can be controlled based on a combination of signals carried by the feedback path. In some embodiments, the on-time can be dynamically generated in real time. In some embodiments, the on-time can be controlled by digitally changing the capacitance value, current mirror ratio, or threshold voltage of the system via a phase-locked loop. In some embodiments, the phase-locked loop can include a sequential phase detector, a state machine, and an n-bit bidirectional counter.

[0009] In some embodiments, the switching frequency of the first switch may be controlled based on a combination of signals carried by the feedback path.

[0010] In some embodiments, the combination of signals carried by the feedback path may include: (1) a first combination of a DC signal from a switch node and an AC signal from a power supply output terminal, the first combination excluding the DC signal from the power supply output terminal; and (2) a second combination of a DC signal from the power supply output terminal and an AC signal from the first combination, the second combination excluding the DC signal from the first combination.

[0011] In some embodiments, the combination of signals carried by the feedback path may include: (1) a first combination of a DC signal from a switch node and AC coupled to ground, the first combination not including DC attenuation referenced to ground; and (2) a second combination of a DC signal from an output of the power supply and an AC signal from the first combination, the second combination not including the DC signal from the first combination.

[0012] In some embodiments, the voltage at the output of the power supply may be determined based on the value of an external resistor coupled to the system.

[0013] In some embodiments, the active error amplifier may be configured to amplify the ripple of the combination of signals carried by the feedback path.

[0014] In some embodiments, the feedback path may be coupled to the synthesis node instead of to the switch node between the first switch and the second switch. The feedback path implements feedback of signals from (1) the synthesis node and (2) the power supply output terminal.

[0015] In some embodiments, the combination of signals carried by the feedback path may include: (1) a DC signal from the power supply output; and (2) an AC signal from a synthesis node. The combination may not include the DC signal from the synthesis node. In some embodiments, the signal from the synthesis node may be provided by an inductor current simulator.

[0016] These and other objects, features and characteristics of the systems and / or methods disclosed herein, as well as the functions and methods of operation of the related structural elements, the combination of parts and the economy of manufacturing will become more apparent by considering the following description and the appended claims with reference to the accompanying drawings, all of which form a part of this specification, wherein like reference numerals represent corresponding parts in the various figures. It should be expressly understood, however, that the drawings are for illustration and description purposes only and are not intended as a definition of the limits of the invention. BRIEF DESCRIPTION OF THE DRAWINGS

[0017] Figure 1A An example system for providing intelligent constant on-time control according to some embodiments of the present disclosure is shown.

[0018] Figure 1B-1D Example combinations of signals for providing intelligent constant on-time control according to some embodiments of the present disclosure are shown.

[0019] Figure 2A-2B An example system for providing intelligent constant on-time control according to some embodiments of the present disclosure is shown.

[0020] Figure 2C According to some embodiments of the present disclosure, Figure 2A-2B An example combination of signals for providing intelligent constant on-time control of the system shown in FIG.

[0021] Figure 3A-3B An example system for providing intelligent constant on-time control according to some embodiments of the present disclosure is shown.

[0022] Figure 3C According to some embodiments of the present disclosure, Figure 3A-3B An example combination of signals for providing intelligent constant on-time control of the system shown in FIG.

[0023] Figure 4A-4B An example system for providing intelligent constant on-time control according to some embodiments of the present disclosure is shown.

[0024] Figure 4C According to some embodiments of the present disclosure, Figure 4A-4BAn example combination of signals for providing intelligent constant on-time control of the system shown in FIG.

[0025] Figure 5A Example signals without intelligent constant on-time control are shown.

[0026] Figure 5B Example signals with intelligent constant on-time control are shown.

[0027] Figure 6 An example system for improving the DC accuracy of a ripple regulator is shown.

[0028] Figure 7 An example system for reducing switching frequency variation is shown.

[0029] Figure 8-10 Shown is the method for implementing Figure 7 Example circuit for the on-time generator in .

[0030] Fig.11 Shown is the method for implementing Figure 7 Example block diagram of a PLL in .

[0031] Fig.12 An example ripple regulator architecture is shown.

[0032] Fig.13 A method for providing intelligent constant on-time control according to some embodiments of the present disclosure is shown. DETAILED DESCRIPTION

[0033] Figure 1A An example system 100 for providing intelligent constant on-time control is shown. System 100 may include one or more of switch A 102, switch B 104, inductor 106, feedback path 108, controller 110, and / or other components. One or more components of system 100 may be coupled to one or more other components of system 100. The term "coupled" as used herein may refer to direct coupling or indirect coupling. Switch A 102 may be coupled to provide an input voltage (V I ) power input terminal (P IN ) 112. Switch B 104 may be coupled to switch A 102 and ground 118. A node 120 (eg, a switch node) may exist between switch A 102 and switch B 104. The voltage at node 120 may be referred to as a switch node voltage (V N Node 120 may be configured to be connected (eg, via a connector) to inductor 106 and the power supply output terminal (P OUT ) 114. The voltage at the power supply output terminal 114 may be referred to as the output voltage (V OThe power supply output 114 may be coupled to a capacitor 116 (eg, an output capacitor), which may be coupled to a ground 118 .

[0034] Feedback path 108 can be coupled to (1) node 120 and (2) power supply output 114. Feedback path 108 can implement feedback of signals from (1) node 120 and (2) power supply output 114. Controller 110 (e.g., a ripple-based controller) can be coupled to feedback path 108. Controller 110 can receive a combination of signals carried by feedback path 108. For example, controller 110 can receive a combination of voltage signals carried by feedback path 108. The voltage signal received by controller 110 from feedback path 108 can be referred to as feedback voltage (V FB ). The controller 110 may be configured to compare the feedback voltage with a reference voltage (V REF ) and operates switch A 102 and switch B 104 based on the comparison. The operation of switch A 102 and switch B 104 by controller 110 can control the output voltage (V O ), the switching frequency of switch A 102 / switch B 104 and / or the on-time of switch A 102 / switch B 104.

[0035] In some embodiments, the on-time of switch A 102 / switch B 104 may be controlled by digitally changing the capacitance value, current mirror ratio, or threshold voltage of system 100 via a phase-locked loop (e.g., as shown in FIG. Figure 7 In some embodiments, the on-time may be dynamically generated in real time (e.g., as shown and described in reference Figure 8-10 In some embodiments, the phase-locked loop may include a sequential phase detector, a state machine, and an n-bit bidirectional counter (e.g., such as reference Fig.11 One or more circuits / functions described herein may be combined together (e.g., as shown and described in reference Fig.12 shown and described).

[0036] Figure 1B-1D An example combination of signals 110, 120, 130 for providing intelligent constant on-time control is shown. Figure 1B, the systems and methods disclosed herein can use different combinations of voltage signals from different parts of the system to provide intelligent constant on-time control. The combination of voltage signals can include a DC component of the switch node voltage, an AC component of the switch node voltage, a DC component of the output voltage, an AC component of the output voltage, a DC component of the combination of the switch node voltage and the output voltage, an AC component of the combination of the switch node voltage and the output voltage, and / or other signals. One or more components of the voltage signal can be scaled down (e.g., via a feedback voltage divider resistor) or scaled up (e.g., increased via a gain). The combination of voltage signals can be provided to a ripple-based controller (e.g., controller 110) as a feedback voltage.

[0037] refer to Figure 1C , the feedback voltage may be provided by (1) combining the DC and / or AC components of the switch node voltage and the DC and / or AC components of the output voltage, and (2) providing the DC and / or AC components of the combined voltage. Figure 1D , one or more components can be scaled up via a gain (G). Figure 1D The various gains shown in may be selectable—that is, one or more components of the signal may be amplified, and one or more components of the signal may not be amplified.

[0038] Figure 2A-2B Example systems 200, 210 for providing intelligent constant on-time control are shown. Figure 2A , the circuit shown inside the polygon 205 can be integrated into the chip as a whole. Figure 2B , the circuit shown inside polygon 215 can be integrated as a whole in the chip. The output voltage of systems 200, 210 can be changed by changing the reference voltage or by changing the value of the voltage-dividing resistors (R1, R2). The voltage-dividing resistors can be implemented inside the chip (e.g., via non-volatile memory / fuses), as shown in system 200, or can be implemented via external discrete resistors, as shown in system 210. Figure 2B As shown, the use of external resistors may require the chip to have additional pins (eg, additional pins connected to the output voltage divider).

[0039] The feedback paths 207 and 217 of the systems 200 and 210 can be respectively Figure 2A-2B. The feedback paths 207, 217 may include a path through a resistor (R3) that carries a node voltage, a path through a capacitor (C1) that carries an output voltage, a path through a capacitor (C2) that carries a combination of a node voltage and an output voltage, a path that carries an output voltage (reduced via a voltage divider resistor), and / or other paths. The capacitor in the feedback path may allow the AC component of the signal to pass while blocking the DC component of the signal. The resistor in the feedback path may allow both the DC and AC components of the signal to pass. The DC component may be much larger than the AC component of the signal, and passing both the DC component and the AC component may be considered as passing only the DC component (e.g., effectively blocking the AC component).

[0040] The combination of signals carried by feedback paths 207, 217 can enable the controller of systems 200, 210 to improve the stability and noise immunity of systems 200, 210. The combination of the resistor (R3) and capacitor (C1) on feedback paths 207, 217 (across the inductor (L)) can generate a triangular ripple signal at V1 that synchronizes the waveform of the inductor current. The triangular ripple signal at V1 may have an amplitude of approximately tens of millivolts. This waveform can be injected through capacitor (C2) so that the feedback voltage can have a ripple with an amplitude that is almost the same as V1. The time constant of the filter (R3 and C1) is not affected by the inductor time constant (R L / L) and does not need to be compared with the inductor time constant (R L / L). The ripple amplitude of the feedback voltage is proportional to R C and R L Not sensitive. Even if R C and R L The value of becomes zero, and systems 200 and 210 can also operate.

[0041] Figure 2C An example combination of signals 220 carried by feedback paths 207, 217 with respect to systems 200, 210 is shown. The combination of signals 220 may include a first combination (V1) of a DC component of a node voltage and an AC component of an output voltage. The first combination may effectively exclude the AC component of the node voltage (via resistor R3). The first combination may exclude the DC component of the output voltage (via capacitor C1). The combination of signals 220 may include a second combination of a DC component of the output voltage reduced (via voltage-dividing resistors R1, R2) and an AC component of the first combination (V1). The second combination may exclude the DC component of the first combination (via capacitor C2). The second combination may effectively exclude the AC component of the output voltage (via resistors R1, R2).

[0042] Figure 3A-3B Example systems 300, 310 for providing intelligent constant on-time control are shown. Figure 3A , the circuit shown inside the polygon 305 can be integrated into the chip as a whole. Figure 3B , the circuit shown inside polygon 315 can be integrated as a whole in the chip. The output voltage of systems 300, 310 can be changed by changing the reference voltage or by changing the value of the voltage-dividing resistors (R1, R2). The voltage-dividing resistors can be implemented inside the chip (e.g., via non-volatile memory / fuses), as shown in system 300, or can be implemented via external discrete resistors, as shown in system 310. Figure 3B As shown, the use of external resistors may not require the chip to have additional pins (compared to the additional pins required in system 210).

[0043] The combination of signals carried by feedback paths 307, 317 can enable the controller of system 300, 310 to improve the stability and noise immunity of system 300, 310. The combination of resistor (R3) and capacitor (C1) (connected to ground) on feedback paths 307, 317 can generate a triangular ripple signal at V1 that synchronizes the waveform of the inductor current. The triangular ripple signal at V1 can have an amplitude of about tens of millivolts. This waveform can be injected through capacitor (C2) so that the feedback voltage can have a ripple with almost the same amplitude as V1. The time constant of the filter (R3 and C1) is not affected by the inductor time constant (R L / L) and does not need to be related to the inductor time constant (R L / L). The ripple amplitude of the feedback voltage can be adjusted to R C and R L Not sensitive. Even if R C and R L Even if the value of becomes zero, systems 300 and 310 can still operate.

[0044] The transient behavior of the system 300, 310 may not be as good as that of the system 200, 210. This is because the feedback voltage in the system 300, 310 does not have the inductor (L) current information as in the system 200, 210. The system 300, 310 may provide a simpler chip design / smaller chip size than the system 200, 210.

[0045] The feedback paths 307 and 317 of the systems 300 and 310 can be respectively Figure 3A-3B Feedback paths 307, 317 may include a path carrying the node voltage through resistor (R3), a path coupling AC to ground through capacitor (C1), a path carrying the filtered switch node voltage, a path carrying the output voltage (reduced via a voltage divider resistor), and / or other paths.

[0046] Figure 3CAn example combination of signals 320 carried by feedback paths 307, 317 with respect to systems 300, 310 is shown. The combination of signals 320 may include a first combination (V1) of a DC component of the switch node voltage and AC coupled to ground. The first combination may effectively exclude the AC component of the node voltage (via resistor R3). The first combination may exclude ground-referenced DC attenuation (via capacitor C1). The combination of signals 320 may include a second combination of a DC component of the reduced output voltage (via voltage divider resistors R1, R2) and an AC component of the first combination (V1). The second combination may exclude the DC component of the first combination (via capacitor C2). The second combination may effectively exclude the AC component of the output voltage (via resistors R1, R2).

[0047] refer to Figure 1A In some embodiments, the feedback path 108 may be coupled to a synthesis node instead of the switch node 120 (between switch A 102 and switch B 104). The synthesis node may simulate changes in the signal at node 120. For example, Figure 4A-4B Example systems 400, 410 for providing intelligent constant on-time control using synthesis nodes are shown. Figure 4A , the circuit shown inside the polygon 405 can be integrated into the chip as a whole. Figure 4B , the circuit shown inside polygon 415 can be integrated as a whole in the chip. The output voltage of systems 400, 410 can be changed by changing the reference voltage or by changing the value of the voltage divider resistors (R1, R2). The voltage divider resistors can be implemented inside the chip (e.g., via non-volatile memory / fuses), as shown in system 400, or can be implemented via external discrete resistors, as shown in system 410. Figure 4B As shown, the use of external resistors may not require the chip to have additional pins (compared to the additional pins required in system 210).

[0048] The feedback paths 407 and 417 of the systems 400 and 410 can be respectively Figure 4A-4B The feedback paths 407, 417 may include a path through the capacitor (C2) that carries the voltage at the synthesis node (V1), a path that carries the output voltage (reduced via a voltage divider resistor), and / or other paths. The voltage at the synthesis node may be referred to as the synthesis node voltage (V1). The synthesis voltage may be provided by an inductor current simulator. Figure 4A-4B An example inductor current simulator is shown in FIG. 1 , which includes two current sources (I1, I2), a switch (S), a capacitor (C1), and a resistor (Rb) (with a DC bias (V B)). Other types of inductor current simulators may also be considered. Feedback paths 407, 417 may implement feedback of signals from (1) the synthesis node and (2) the power supply output terminal.

[0049] The systems 400 and 410 can use active circuits to generate ripple signals to obtain better information about the inductor (L) current. In the systems 400 and 410, the inductor current simulator can generate a ripple signal that follows the inductor current waveform and has a DC bias V B The current sources (I1, I2) may include active analog circuits that generate currents to charge and discharge the capacitor (C1). To make the V1 waveform follow the inductor waveform, the I1 current may be I Proportional (for example, I1 = Gm*V I ), and can make the I2 current and V O Proportional (for example, I2 = Gm*V O ). The switch (S) can be synchronized with the high-side control signal (pwm). This can produce a waveform V1 with a ripple of several tens of millivolts. This waveform can be injected through a capacitor (C2) so that the feedback voltage can have a ripple of almost the same amplitude as V1. The ripple amplitude of the feedback voltage can have an effect on R C and R L Not sensitive. Even if R C and R L The value of becomes zero, and systems 400 and 410 can also operate.

[0050] and Figure 2A , 2B The systems 200, 210 and Figure 3A , 3B Compared to the systems 300 , 310 shown in , the systems 400 , 410 may produce better inductor (L) current information in the V1 waveform, which may be used to implement other control functions.

[0051] Figure 4C An example combination of signals 420 carried by feedback paths 407, 417 for systems 400, 410 is shown. The combination of signals 420 may include a combination of an AC component of the synthesized node voltage and a DC component of the reduced output voltage (via voltage divider resistors R1, R2). The combination may exclude the DC component of the synthesized node voltage (via capacitor C2). The combination may effectively exclude the AC component of the output voltage (via resistors R1, R2).

[0052] In some embodiments, the system may include one or more designs / functionalities of systems 200, 210, 300, 310, 400, 410. For example, the chip may be programmed (via hardware / firmware / software) to be able to flexibly change between the designs / functionalities shown in systems 200, 210, 300, 310, 400, 410. Based on the needs of the power system and / or power limitations, the chip may be used to provide higher / lower stability and noise immunity. In some embodiments, the system may be further configured to increase one of the multiple signals (e.g., via gain G).

[0053] Figure 5A-5B The effectiveness of the systems 200, 210 is shown. Figure 5A Example signals without intelligent constant on-time control are shown. Figure 5B 2 shows example signals with intelligent constant on-time control, as implemented in systems 200, 210. Figure 5A and 5B In the example, the system load changes from 10mA to 3A in 1.6ms and changes back from 3A to 10mA in 1.65ms. I ) can be 12V, and the output voltage (V O ) is 1.6V. The inductor inductance (L) is 1uH, and the inductor resistance (R L ) is 0Ω. The output capacitor (C O ) is 44uF, the capacitor resistance (R C ) is 1mΩ. Figure 5A The output voltage (V O ), inductor current and feedback voltage (V FB ). Figure 5B The output voltage (V O ), inductor current, V1 voltage, and feedback voltage (V FB ).like Figure 5A As shown in Figure 2, under the above conditions and parameters, COT control is unstable. Figure 5B As shown, the intelligent COT control is stable.

[0054] In some embodiments, one or more active error amplifiers can be configured to amplify one or more ripples of the combination of signals carried by the feedback path. Figure 6 A system 600 for improving the DC accuracy of a ripple regulator is shown. Figure 2A-2B The use of the ripple enhancement techniques shown in , 3A-3B and 4A-4B enables the DC accuracy of the ripple regulator to be improved using a simple amplifier configuration. Figure 6In the ripple-based controller, an error amplifier (Gm) as well as a compensation capacitor (Cea) and a compensation resistor (Rea) can be placed between the feedback path and the ripple-based controller to improve DC regulation. The ripple enhancer can include Figure 2A-2B , 3A-3B or 4A-4B. The input to the controller can be changed to V B and V ERR , where V B The error amplifier output voltage V ERR Located within a certain (e.g., convenient) range. REF Can be provided to the error amplifier instead of to the controller. The amplifier (Gm) in the system 600, 610 can be used as: (1) a high DC gain voltage error amplifier for accurate DC regulation; (2) an amplifier for the ripple voltage from the ripple enhancer. The ripple enhancer can be used to generate (e.g., tens of millivolts) ripple to synchronize with the inductor current. The amplifier can increase the ripple (e.g., to hundreds of millivolts) so that the ripple can be more easily handled by the ripple-based controller.

[0055] The selection of the values ​​of the resistor (Res) and capacitor (Ces) is simple because the error amplifier (Gm) and the ripple enhancer are decoupled in the system 600. The values ​​of the resistor (Res) and capacitor (Ces) can be selected to create a zero well below the switching frequency of the regulator. The parasitic capacitance at the output of the error amplifier (Gm) may need to be kept to a minimum to allow the system 600 to ignore the parasitic pole effect on the ripple shape.

[0056] To improve the COT ripple regulator, for the first stage, constant switching frequency operation at CCM can be achieved by making the on-time proportional to the inverse of the input voltage and making the on-time proportional to the output voltage. However, second-order effects (e.g., regulator efficiency, comparator delay, driver delay) may still affect the switching frequency. For multi-MHz high-frequency operation, these second-order effects may cause more than 20% switching frequency variation.

[0057] Figure 7 An example system 700 for reducing switching frequency variation is shown. In system 700, the switching frequency can be reduced by changing (1) the current mirror ratio K1 (I2 = K1 * I1), (2) the capacitance value C, and (3) the threshold value (V TH ) to change the on-time of the switch. By making I1 and I2 I proportional to the input voltage (V I ) is inversely proportional to V. For the first stage, the switching frequency may not increase with V I By making the threshold voltage (V TH ) and V O or VREF proportional to V O or V REF (V O The target divided by the feedback ratio). For the first stage, the switching frequency can be unchanged with Vo.

[0058] Based on the system 700, the on-time can be calculated as:

[0059]

[0060] This results in the switching frequency being calculated as:

[0061]

[0062] In the above equation, Td can represent the total delay of the comparator and the driver, and η can represent the regulator efficiency. If Td is close to 0 and η is close to 1, Fsw can be close to a constant and has no effect on the input voltage (V I ) and output voltage (V O ) are not sensitive.

[0063] For some applications, the CCM switching frequency accuracy may be critical and a PLL loop can be added to eliminate the second-order effects of switching frequency variations. Figure 7 As shown, the PLL can compare the phase between the pwm signal and the precise clock (generated inside the chip or outside). The output of the PLL can be an n-bit digital signal. The n-bit digital signal can be used to dynamically generate / trim the on-time. Figure 8-10 Shown is the method for implementing Figure 7 Example circuits 800, 900, 1000 of an on-time generator in FIG. Figure 8-10 The circuit shown in can be used to dynamically generate the on-time in real time. Figure 8 The current mirror ratio K1 is trimmed as shown, and the Fig. 9 trim the capacitor size as shown or by Fig.10 Trim K2(V O or V REF Relative to V TH The dynamic trimming is performed by multiplying Fig.10 In FIG. 4 , four bits of control S<3:0> are provided as an example. Different numbers of bits may be used depending on the specific requirements of the switching frequency accuracy.

[0064] Fig.11 Shown is the method for implementing Figure 7An example block diagram 1100 of a PLL in a phase-locked loop. The phase-locked loop may include a sequential phase detector 1102, a state machine 1104, and an n-bit bidirectional counter 1106. The sequential phase detector 1102 may be configured to detect a phase difference between a pwm signal and a precision clock. The outputs (pu and pd signals) of the sequential phase detector 1102 may reflect the phase difference between the pwm signal and the precision clock. For example, if the frequency of the pwm signal is much higher than the precision clock, the pu signal may be mostly '1' and the pd signal may be mostly '0'. If the pwm signal and the precision clock have the same frequency, the time of the pu signal may be evenly distributed between '1' and '0', and the time of the pd signal may be evenly distributed as '1' and '0'. If the frequency of the pwm signal is much lower than the precision clock, the pu signal may be mostly '0' and the pd signal may be mostly '1'.

[0065] The state machine 1104 can be used to generate three control signals "up", "down" and "stop" based on the "pu" and "pd" signals and other system control signals to control the n-bit bidirectional counter 1106. For example, the other system control signal can be "DCM", and when the chip is operating in DCM, the PLL loop can be stopped. The output of the n-bit bidirectional counter 1106 (e.g., S <n:0>) can directly control the parameters in the on-time generator. The output of the state machine 1104 can control the n-bit bidirectional counter 1106 to increase the count, decrease the count or stop counting. The proposed PLL can be implemented digitally and may have no DC current consumption.

[0066] Fig.12 An example ripple regulator architecture 1200 for providing robust smart COT control is shown. The ripple regulator architecture 1200 may include Figure 2A-2C , 3A-3C, 4A-4C, 6, 7, 8, 9, 10, 11. Fig.12 In the example, the ripple enhancer can be configured to enhance / create a voltage waveform that is synchronized with the inductor current waveform and has a ripple amplitude (e.g., tens of millivolts). A simple error amplifier (Gm) can be configured to further amplify the ripple (e.g., to about hundreds of millivolts). The error amplifier also provides good DC regulation. The output of the error amplifier can be provided to a pwm comparator (CM1) to generate a trigger pulse to the on-time generator. The trigger pulse can also be generated by CM0, which converts V FB0 (Ripple-free enhanced output voltage feedback) with V REF Make a comparison.

[0067] The on-time generator can generate a O ) and is proportional to the input voltage (V I ) inversely proportional to the on-time, so that the switching frequency at CCM is constant in the first stage. The on-time pulse, zcd signal (shows the switch node (e.g., Figure 1A The signal of the zero-crossing event of the node 120 in FIG. 1 is CM0, which is V O The output of the "_low" and fault signals (e.g., ocp, ovp) can be provided to the logic block. The logic block can generate high-side and low-side control signals, which are provided to the drivers (for opening / closing the top / bottom switches). The logic block can also generate a signal HIQ to control the quiescent current of the analog block. In architecture 1200, the only blocks that must be turned on at all times during operation are the backup comparator CM0 and the bandgap reference ( Fig.12 When HIQ='0', all other components may be turned off. A simple method of generating a HIQ signal includes using the rising edge of a pwm signal. Each rising edge of a pwm signal may trigger a HIQ pulse (eg, a 10 μs HIQ pulse).

[0068] Figure 2A-2B Any of the ripple enhancers shown in FIGS. 3A-3B and 4A-4B may be used in architecture 1200 . Figure 8 , 9 Any of the on-time generators shown in FIG. 10 may be used in architecture 1200. For some applications, the use of a PLL may be optional. The PLL may be configured as follows: Fig.11 In some implementations, the architecture 1200 with constant off-time control and / or other ripple-based control schemes may be employed.

[0069] Fig.13 A method 1300 for providing intelligent constant on-time control is shown. The operations of method 1300 presented below are intended to be illustrative. In some embodiments, completion of method 1300 may utilize one or more additional operations not described and / or may not require one or more operations discussed. In some embodiments, two or more operations may occur substantially simultaneously.

[0070] Method 1300 may be implemented at a system, the system comprising a first switch coupled to a power supply input; a second switch coupled to the first switch; a switch node between the first switch and the second switch, the switch node being configured to be connected to an inductor and a power supply output; and a feedback path coupled to (1) the switch node and (2) the power supply output, the feedback path implementing feedback of signals from (1) the switch node and (2) the power supply output. Method 1300 may be implemented at a system, the system comprising a first switch coupled to a power supply input; a second switch coupled to the first switch; a switch node between the first switch and the second switch, the switch node being configured to be connected to an inductor and a power supply output; and a feedback path coupled to (1) a synthesis node and (2) the power supply output, the feedback path implementing feedback of signals from (1) the synthesis node and (2) the power supply output.

[0071] At operation 1310 , a combination of signals carried by feedback paths may be received.

[0072] At operation 1320 , a voltage at the output of the power supply may be controlled based on a combination of the signals carried by the feedback paths.

[0073] In some embodiments, the operation and structure of the system can be the same or similar to one or more of the systems shown in Figures 1, 2A-2B, 3A-3B, 4A-4B, 6, 12.

[0074] For ease of description, spatially relative terms such as "below", "under", "lower", "above", "up", "left", "right", etc. are used to explain the position of one element relative to a second element. These terms are intended to encompass different orientations of the device in addition to the different orientations shown in the figures. In addition, terms such as "first", "second", etc. are also used to describe various elements, regions, parts, etc., and are not intended to be limiting. The same terms refer to the same elements throughout the specification.

[0075] As used herein, the terms "having", "containing", "including", "comprising", and the like are open-ended terms that indicate the presence of stated elements or features, but do not exclude other elements or features. Unless the context clearly indicates otherwise, the articles "a", "an", and "the" are intended to include the plural as well as the singular.

[0076] Although the present invention has been disclosed in the context of certain embodiments and examples, it will be appreciated by those skilled in the art that the present invention extends beyond the specifically disclosed embodiments to other alternative embodiments and / or uses of the present invention and to obvious modifications and equivalents thereof. Therefore, the scope of the present invention disclosed herein should not be limited to the specifically disclosed embodiments described above.

[0077] In addition, those skilled in the art will recognize the interchangeability of various features from different embodiments. In addition to the variations described herein, those skilled in the art can mix and match other known equivalents of each feature to construct similar systems and techniques based on the principles of the invention.

[0078] It should be understood that not all objects or advantages may be achieved according to any particular embodiment of the present invention. Thus, for example, those skilled in the art will recognize that the present invention may be embodied or performed in a manner that achieves or optimizes one advantage or a group of advantages as taught herein without necessarily achieving other objects or advantages that may be taught or suggested herein.

Claims

1. A system for providing intelligent constant on-time control, comprising: a first switch coupled to the power input terminal node, wherein the first switch operates according to a first control signal; a second switch coupled to the first switch, wherein the second switch operates according to a second control signal; a switch node between the first switch and the second switch, the switch node being connected to a power supply output node via an inductor; An inductor current simulator comprising: a first current source configured to provide a first current, wherein the first current is proportional to a product of a constant and a voltage at the power input node, a second current source configured to provide a second current, wherein the second current is proportional to a product of the constant and a voltage at the power supply output node, a synthesis node coupled between the first current source and the second current source, and A controller configured to provide the first control signal and the second control signal based on a control voltage including an AC component of the voltage at the synthesis node and a DC component of the voltage at the power output node but not including the DC component of the voltage at the synthesis node and the AC component of the voltage at the power output node.

2. The system according to claim 1, wherein: The inductor current simulator further comprises: A third switch is coupled between the first current source and the synthesis node, wherein the third switch operates according to the first control signal.

3. The system according to claim 1, wherein: The controller controls the on-time of the first switch by digitally changing a capacitance value, a current mirror ratio, or a threshold voltage of the system via a phase-locked loop.

4. The system according to claim 3, wherein: The phase locked loop includes a sequential phase detector, a state machine and an n-bit bidirectional counter.

5. The system of claim 1, further comprising a capacitor coupled in parallel with the second current source.

6. The system of claim 1, further comprising a capacitor coupled between the synthesis node and the controller.

7. The system of claim 1, further comprising a first resistor coupled between the power supply output node and the synthesis node.

8. The system of claim 7, further comprising a second resistor coupled between the synthesis node and ground.

9. The system of claim 1, further comprising a resistor coupled between the inductor and the power supply output node.

10. The system of claim 1, further comprising a resistor coupled between the synthesis node and a bias voltage source.

11. The system of claim 1 , further comprising: a first diode coupled in parallel with the first switch; as well as A second diode is coupled in parallel with the second switch.

12. The system of claim 1, further comprising: a resistor coupled to the power supply output node; as well as A capacitor is coupled between the resistor and ground.

13. A method for providing intelligent constant on-time control for a system, the system comprising: a first switch coupled to the power input terminal node; a second switch coupled to the first switch; a switch node between the first switch and the second switch, the switch node being connected to a power supply output node via an inductor; A feedback path coupled to (1) the synthesis node and (2) the power supply output terminal, the feedback path implementing feedback of signals from (1) the synthesis node and (2) the power supply output terminal; as well as a controller coupled to the feedback path, the controller configured to provide a first control signal and a second control signal based on a control voltage including an AC component of the voltage at the synthesis node and a DC component of the voltage at the power supply output node and excluding the DC component of the voltage at the synthesis node and the AC component of the voltage at the power supply output node; The method comprises: generating a first current with a first current source, wherein the first current source is coupled to a synthesis node, and wherein the first current is proportional to a product of a constant and a voltage at the power input node; Providing a second current to the synthesis node using a second current source, wherein the second current is proportional to the product of the constant and the voltage at the power output node; providing the first control signal and the second control signal based on a control voltage including the AC component of the voltage at the synthesis node and the DC component of the voltage at the power supply output terminal node and excluding the DC component of the voltage at the synthesis node and the AC component of the voltage at the power supply output terminal node; controlling the first switch using the first control signal; and The second switch is controlled by the second control signal.

14. The method according to claim 13, wherein: The system includes a third switch coupled between the first current source and the synthesis node; and The method also includes operating the third switch according to the first control signal. 15 . The method of claim 13 , further comprising controlling the on-time of the first switch by digitally changing a capacitance value, a current mirror ratio, or a threshold voltage of a phase-locked loop.

16. The method according to claim 15, wherein: The phase locked loop includes a sequential phase detector, a state machine and an n-bit bidirectional counter.

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