Bitstream processing method

Abstract

The present disclosure provides a bitstream processing method. The bitstream processing method of the present invention includes processing a bitstream to provide processed bits; and transmitting the processed bits to a station through a combination of a plurality of resource units assigned to the station, including: parsing the bitstream into a combination of a plurality of resource units; and if there are remaining bits after parsing, allocating the remaining bits to one or more resource units instead of all resource units in the combination of the plurality of resource units. The bitstream processing method of the present invention can improve system performance.

Description

Background Art

[0002] Unless otherwise indicated herein, the methods described in this section are not prior art to the present invention and are not admitted to be prior art by inclusion in this section.

[0003] In a next-generation EHT system (e.g., a wireless local area network (WLAN) system) according to the upcoming Institute of Electrical and Electronics Engineers (IEEE) 802.11be standard, an aggregated RU (interchangeably referred to herein as a multi-RU) including a plurality of RUs may be allocated to a single station (STA) to improve spectral efficiency. However, in some RU aggregation scenarios, after filling bits for a smaller-sized RU (e.g., RU484, which represents an RU of 484 tones), there may be some remaining bits for a larger RU (e.g., RU996, which represents an RU of 996 tones). Therefore, a solution is needed to handle the remaining bit processing in such a case.

Summary of the Invention

[0004] These and other objects of the present invention will no doubt become apparent to those of ordinary skill in the art after reading the following detailed description of the preferred embodiments illustrated in the various charts and figures.

[0005] According to an embodiment of the present invention, there is provided a bitstream processing method, including processing a bitstream to provide a processed bit; and transmitting the processed bit to a station through a combination of a plurality of resource units allocated to the station, including: parsing the bitstream into a combination of a plurality of resource units; and if there are remaining bits after parsing, allocating the remaining bits to one or more resource units instead of all resource units in the combination of the plurality of resource units.

[0006] According to another embodiment of the present invention, there is provided a bitstream processing method, including: processing a bitstream to provide a processed bit; and transmitting the processed bit to the station through a combination of a plurality of resource units allocated to the STA, wherein the combination of the plurality of resource units includes at least one smaller resource unit and at least one larger resource unit, and each of the at least one larger resource units has more tones than the at least one smaller resource unit, and wherein, the processing of the bitstream includes: parsing the bitstream into the combination of the plurality of resource units in a proportional cyclic manner; and if there are remaining bits after parsing in the proportional cyclic manner, allocating the remaining bits to the at least one larger resource unit.

[0007] Other aspects and features of the present invention will become apparent to those skilled in the art by reading the following description of the specific embodiments.

Brief Description of the Drawings

[0008] Various embodiments of the present disclosure presented as examples will be described in detail with reference to the following drawings, wherein:

[0009] Figure 1 is a schematic diagram of an example network environment in which various solutions according to the present disclosure can be implemented.

[0010] Figure 2 is a diagram according to an example design of the present disclosure.

[0011] Figure 3 is a diagram according to an example scenario of the present disclosure.

[0012] Figure 4 is a diagram according to an example scenario of the present disclosure.

[0013] Figure 5 is a diagram according to an example scenario of the present disclosure.

[0014] Figure 6 is a diagram according to an example scenario of the present disclosure.

[0015] Figure 7 shows an example system with example devices according to an embodiment of the present disclosure.

[0016] Figure 8 shows an example process according to an embodiment of the present disclosure.

[0017] Figure 9 shows an example process according to an embodiment of the present disclosure.

Detailed Embodiments

[0018] In the specification and claims, certain terms are used to refer to particular components. Those skilled in the art will appreciate that manufacturers may use different names to refer to the same component. The specification and claims do not use differences in name as a way to distinguish components, but rather use differences in function as the basis for distinction. The term "comprising" used throughout the specification and claims is an open-ended term and should be interpreted as "including but not limited to". Additionally, the term "coupled" herein includes any direct and indirect means of electrical connection. Thus, if the text describes a first device as being coupled to a second device, it means that the first device can be directly electrically connected to the second device, or indirectly electrically connected to the second device through other devices or connection means.

[0019] It will be readily understood that, as generally described and illustrated in the figures herein, the components of the present invention can be arranged and designed in a variety of different configurations. Thus, as shown in the figures, the following more detailed description of the embodiments of the systems and methods of the present invention is not intended to limit the scope of the claimed invention, but is merely representative of selected embodiments of the present invention.

[0020] Implementations according to the present disclosure relate to various techniques, methods, concepts, and / or solutions related to residual bit processing for proportional cyclic RU parsing in an EHT system. According to the present disclosure, many possible solutions can be implemented individually or in combination. That is, although these possible solutions may be described separately below, two or more of these possible solutions can be implemented in one or another combination.

[0021] It is noted that although the descriptions provided herein may be in the context of certain wireless access technologies, networks, and network topologies (such as Wi-Fi), the concepts, solutions, and any (multiple) variants / derivatives proposed can be implemented in and by other types of radio access technologies, networks, and network topologies, such as but not limited to Bluetooth, ZigBee, fifth generation (5G) / new radio (NR), long term evolution (LTE), advanced LTE, advanced LTE Pro, Internet of Things (IoT), industrial Internet of Things (IIoT), and narrowband Internet of Things (NB-IoT). Therefore, the scope of the present disclosure is not limited to the examples described herein.

[0022] Figure 1 An example network environment 100 is shown in which various solutions and concepts according to the present disclosure can be implemented. Figure 2 Figure 6 An example of the implementation of various proposed solutions in the network environment 100 according to the present disclosure is shown. Refer to Figure 1 Figure 6 The following description of various proposed solutions is provided.

[0023] As Figure 1 shown, the network environment 100 may include at least one STA 110 communicating wirelessly with STA 120. Each of STA 110 and STA 120 may be a non-access point (non-AP) STA, or either of STA 110 and STA 120 may act as an AP. In some cases, STA 110 and STA 120 may be associated with a basic service set (BSS) according to one or more IEEE 802.11 standards (e.g., IEEE 802.11be and future developed standards). Each of STA 110 and STA 120 may be configured to communicate with each other using residual bit processing according to the various proposed solutions described below for proportional cyclic RU parsing in an EHT system.

[0024] Figure 2 An example design 200 according to the present disclosure is shown. Generally, the basic operations of multi-RU transmission may include the following referenceFigure 2 Many of the described operations. For example, data for a STA (e.g., STA 110 or STA 120) for transmission on multiple RUs using one physical layer (PHY) service data unit (PSDU) can be provided by a media access control layer (MAC) 210. Information bits of multiple RUs can be jointly encoded by a joint encoder 220 to provide an encoded bit sequence to a stream parser 230, which can perform stream parsing to split or otherwise parse an input encoded bit stream into different spatial streams. Then, depending on the bandwidth and / or RU allocation and the interleaving / tone mapping scheme, a bit-level RU and segmentation (RU / segment) parser 240 can operate at the bit level for each stream to allocate, distribute, or parse the encoded bits on each of the multiple RUs for modulation and tone mapping / interleaving for transmission on the allocated RUs.

[0025] Under the proposed scheme according to the present disclosure, regarding proportional cyclic RU parsing, a parameter s = max{1, N bpscs / 2} (referred to herein as the "s-bit") can be defined, where N bpscs represents the number of encoded bits per subcarrier per spatial stream. Thus, the value of the s-bit may depend on the modulation type used, since N bpscsDepending on the modulation type used (e.g., for Quadrature Phase Shift Keying (QPSK), Nbpscs = 2; for 16 - Quadrature Amplitude Modulation (QAM), Nbpscs = 4). Thus, the coded bits can be parsed into multiple RUs in a proportional polling manner, where the parser ratio depends on the size (or number of tones) of each RU in the RU aggregation. For example, the parser ratio can be defined in the format of m0:m1:m2… (or 1s:2s:3s…), and each of m0, m1, and m2 can be in s - bit units. The operation of the proportional round - robin parser is as follows: First, the parser can parse m0 s - bits into the first RU (RU1), then parse m1 s - bits into the second RU (RU2), …, and the parsing is achieved by alternately (alternatively) allocating the coded bits to each RU in the multiple RUs. For some multi - RU combinations, if there are remaining bits after alternately allocating the coded bits to each RU at the ratio of m0:m1:… (or 1s:2s:…), the residual (remaining) bits can be allocated to each relatively larger - sized RU. Additionally, the residual / remaining bits can also be allocated to the larger RUs (when the number of larger RUs is equal to or greater than 2) at the ratio of m1:m2:m3 (or 2:2:2) (in s - bit units if the larger RUs have the same size) to further improve system performance. Otherwise, the residual / remaining bits can be allocated to each larger RU sequentially or evenly as described below.

[0026] Figure 3 FIG. 300 shows an example scenario according to the present disclosure. In Figure 3 , a set of example combinations of RUs and corresponding parameters are shown in a table. For example, for each example combination of multiple RUs, a corresponding parameter can be the total number of tones or data sub - carriers (N sd ). Another corresponding parameter can be the ratio between the RUs in the combination, expressed as Ns d，0 :Ns d，1 :Ns d，2 :… approximated as m0:m1:m2:…, where mi is an integer in s - bit units and 0 ≤ i ≤ the number of RUs in the combination - 1. Thus, in the present disclosure, each expression of the ratio (e.g., m0:...:mn) can be replaced by an alternative expression of 1s:...:ns, where n > 1. Another corresponding parameter can be the number of remaining (or residual) bits (per symbol) if any, after parsing the coded bit stream into a combination of multiple RUs in a cyclic manner.

[0027] Referring to Figure 3As shown, for some combinations of RUs, there may be remaining bits after cyclic parsing, while for some other combinations of RUs, there may be no remaining bits after cyclic parsing. In each of those combinations of multiple RUs with remaining bits, there may be at least one smaller RU and at least one larger RU in terms of the number of tones. For example, in the listed example combinations of multiple RUs, the following combinations may have remaining bits after cyclic parsing: the combination of a smaller RU (RU484) with 484 tones plus a larger RU (RU996) with 996 tones, the combination of an aggregated RU as the smaller RU (one RU (RU242) with 242 tones and one RU (RU484) with 484 tones) and a larger RU (RU996) with 996 tones, the combination of a smaller RU (RU484) with 484 tones plus two larger RUs (RU996) with 996 tones each, the combination of a smaller RU (RU484) with 484 tones plus three larger RUs (RU996) with 996 tones each, and the combination of a smaller RU (RU242) with 242 tones plus a larger RU (RU996) with 996 tones.

[0028] Under the proposed scheme according to the present disclosure, as Figure 4 shown, for combinations of multiple RUs with remaining bits after cyclic parsing, the remaining bits can be assigned to at least one larger RU of the multiple combined RUs. For example, under the first method, the remaining bits can be proportionally distributed among the larger RUs (such as RU996) of the combination of multiple RUs in the ratio of m 1 :m 2 :… over the last predefined number of tones (e.g., 44 tones). Under the second method, as Figure 5 shown, the remaining bits can be sequentially distributed over the last predefined number of tones (e.g., 44 tones) on each larger RU (such as RU996) of the combination of multiple RUs. Under the third method, as Figure 6 shown, the remaining bits can be evenly distributed over each larger RU (e.g., RU996) of the combination of multiple RUs.

[0029] Figure 4 Example scenario 400 according to the present disclosure is shown. In scenario 400, a bit stream (e.g., the encoded bits of input data) can be cyclically parsed in a proportional manner into combinations of multiple RUs having at least one smaller RU and at least one larger RU. Then, in the case where there are remaining bits left from the parsing in a proportional cyclic manner, the remaining bits can be assigned to at least one larger RU in the combination of multiple RUs. For example, in Figure 4In the example shown, the combination of multiple RUs may include one smaller RU (e.g., RU484) and two larger RUs (e.g., the first RU996 and the second RU996), and m 0 : m 1 : m 2 The ratio of is 448:996:996, or 1:2:2. Thus, initially, the bitstream can be parsed into a combination of multiple RUs of RU484, the first RU996, and the second RU996 in a proportional cyclic manner with a ratio of 1:2:2. Thereafter, under the proposed scheme according to the present disclosure, the remaining bits can be distributed over the last 44 tones between the first RU996 and the second RU996.

[0030] Figure 5 FIG. 500 shows an example scenario according to the present disclosure. In scenario 500, a bitstream (e.g., the encoded bits of input data) can be parsed into a combination of multiple RUs having at least one smaller RU and at least one larger RU in a proportional cyclic manner. Then, in the case of remaining bits after parsing in a proportional cyclic manner, the remaining bits can be assigned to at least one larger RU in the combination of multiple RUs. For example, in Figure 5 the example shown, the combination of multiple RUs may include one smaller RU (e.g., RU484) and two larger RUs (e.g., the first RU996 and the second RU996), where m 0 : m 1 : m 2 The ratio of is 448:996:996 or 1:2:2. Thus, initially, the bitstream can be parsed into a combination of multiple RUs of RU484, the first RU996, and the second RU996 in a proportional cyclic manner with a ratio of 1:2:2. Thereafter, under the proposed scheme according to the present disclosure, the remaining bits can be distributed over the last 44 tones on each of the first RU996 and the second RU996.

[0031] Figure 6 FIG. 600 shows an example scenario according to the present disclosure. In scenario 600, a bitstream (e.g., the encoded bits of input data) can be parsed into a combination of multiple RUs having at least one smaller RU and at least one larger RU in a proportional cyclic manner. Then, in the case of remaining bits after parsing in a proportional cyclic manner, the remaining bits can be assigned to at least one larger RU in the combination of multiple RUs. For example, in Figure 6 the example shown, the combination of multiple RUs may include one smaller RU (e.g., RU484) and two larger RUs (e.g., the first RU996 and the second RU996), where m 0 : m 1 : m 2The ratio is 448:996:996 or 1:2:2. Thus, under the proposed solution according to the present disclosure, for each Nth iteration (N>1) of the bitstream for the combination of multiple RUs parsed into RU484, the first RU996, and the second RU996, the bitstream is allocated in a ratio of 1:2:2. In the first RU996 and the second RU996 in the combination of multiple RUs in a proportional cycling manner, one or more additional m 1 s bits can be allocated to the first RU996, and one or more additional m 2 s bits can be allocated to the second RU996.

[0032] Figure 7 FIG. shows an example system 700 having at least an example device 710 and an example device 720 according to an embodiment of the present disclosure. Each of the device 710 and the device 720 can perform various functions to implement the solutions, techniques, processes, and methods described herein related to the remaining bit processing for proportional cycling RU parsing in an EHT system, including the various solutions, concepts, ideas, systems, and methods described above regarding the various proposed designs, and the following processes. For example, the device 710 can be implemented in the STA110, while the device 720 can be implemented in the STA 120, and vice versa.

[0033] Each of the device 710 and the device 720 can be part of an electronic device, which can be a STA or an AP, such as a portable or mobile device, a wearable device, a wireless communication device, or a computing device. When implemented in a STA, each of the device 710 and the device 720 can be implemented in a smart phone, a smart watch, a personal digital assistant, a digital camera, or a computing device such as a tablet computer, a laptop computer, or a notebook computer. Each of the device 710 and the device 720 can also be part of a machine-type device, which can be an IoT device, a home device, a wired communication device, or a computing device such as an immobile or fixed device. For example, each of the device 710 and the device 720 can be implemented in a smart thermostat, a smart refrigerator, a smart door lock, a wireless speaker, or a home control center. When implemented in a network device or as a network device, the device 710 and / or the device 720 can be implemented in a network node, such as an AP in a WLAN.

[0034] In some embodiments, each of apparatus 710 and apparatus 720 may be implemented in the form of one or more integrated circuit (IC) chips, such as but not limited to, one or more single-core processors, one or more multi-core processors, one or more reduced instruction set computing (RISC) processors, or one or more complex instruction set computing (CISC) processors. In the various scenarios above, each of apparatus 710 and apparatus 720 may be implemented in or as a STA or an AP. Each of apparatus 710 and apparatus 720 may include Figure 7 at least some of those components shown in Figure 7 . For example, the processors in Figure 7 are respectively such as processor 712 and processor 722. Each of apparatus 710 and apparatus 720 may further include one or more other components (such as, internal power supplies, display devices, and / or user interface devices) that are not relevant to the proposed solutions of the present disclosure, and thus, for the sake of simplicity and conciseness, such components of apparatus 710 and apparatus 720 are neither shown nor described in Figure 7 .

[0035] In one aspect, each of processor 712 and processor 722 may be implemented in the form of one or more single-core processors, one or more multi-core processors, one or more RISC processors, or one or more CISC processors. That is, even though the singular term "processor" is used herein to refer to processor 712 and processor 722, according to the disclosure of the present invention, each of processor 712 and processor 722 may include multiple processors in some embodiments and may include a single processor in other embodiments. In another aspect, each of processor 712 and processor 722 may be implemented in the form of hardware (and optionally, firmware) having electronic components, which include, for example but not limited to, one or more transistors, one or more diodes, one or more capacitors, one or more resistors, one or more inductors, one or more memristors, and / or one or more varactor diodes, which are configured and arranged to achieve a specific purpose according to the present disclosure. In other words, in at least some embodiments, each of processor 712 and processor 722 is a dedicated machine specifically designed, arranged, and configured to perform specific tasks, including those tasks related to the remaining bit processing for the proportional cyclic RU resolution in the EHT system according to various embodiments of the present disclosure.

[0036] In some embodiments, device 710 may further include a transceiver 716 coupled to processor 712. Transceiver 716 may include a transmitter capable of wirelessly transmitting data and a receiver capable of wirelessly receiving data. In some embodiments, device 720 may further include a transceiver 726 coupled to processor 722. Transceiver 726 may include a transmitter capable of wirelessly transmitting data and a receiver capable of wirelessly receiving data. It is noted that although transceivers 716 and 726 are respectively illustrated as being external to and separate from processors 712 and 722, in some embodiments, transceiver 716 may be a system-on-chip (SoC) and be a component of processor 712, and transceiver 726 may be an SoC and be a component of processor 722.

[0037] In some embodiments, device 710 may further include a memory 714 coupled to processor 712 and accessible by and storing data therein. In some embodiments, device 720 may further include a memory 724 coupled to processor 722 and accessible by and storing data therein. Each of memories 714 and 724 may include a type of random access memory (RAM), such as dynamic RAM (DRAM), static RAM (SRAM), thyristor RAM (T-RAM), and / or zero-capacitor RAM (Z-RAM). Additionally or alternatively, each of memories 714 and 724 may include a type of read-only memory (ROM), such as mask ROM, programmable ROM (PROM), erasable programmable ROM (EPROM), and / or electrically erasable programmable ROM (EEPROM). Alternatively or additionally, each of memories 714 and 724 may include a type of non-volatile random access memory (NVRAM), such as flash memory, solid-state memory, ferroelectric RAM (FeRAM), magnetoresistive RAM (MRAM), and / or phase change memory.

[0038] Each of devices 710 and 720 may be a communication entity capable of communicating with each other using various proposed solutions according to the present disclosure. For illustrative purposes and not limitation, a description of the functions of device 710 (such as STA 110) and device 720 (such as STA 120) is provided below. It is noted that although a detailed description of the capabilities, functions, and / or technical features of device 710 is provided below, the same may be equally applicable to device 720, although its detailed description is not provided merely for the sake of brevity. It is also noted that although example implementations of the following description are provided in the context of a WLAN, the same implementations may be implemented in other types of networks.

[0039] Under a proposed solution related to the remaining bit processing for proportional cyclic RU parsing in an EHT system according to the present disclosure, apparatus 710 is implemented in or as STA 110 in a network environment, while apparatus 720 is implemented in or as STA 120 in a network environment. The processor 712 of apparatus 710 may encode data for a STA (e.g., STA 120) to provide a bitstream. Additionally, the processor 712 may process the bitstream to provide processed bits. For example, the processor 712 may parse the bitstream into a combination of multiple RUs assigned to a STA, and in the case of remaining bits in the parsing, the processor 712 may assign the remaining bits to one or more RUs, but not all RUs in the RU combination. Further, the processor 712 may wirelessly transmit the processed bits to the STA via transceiver 716 through the combination of multiple RUs.

[0040] In some embodiments, when parsing the bitstream into a combination of multiple RUs, the processor 712 may parse the bitstream into a combination of multiple RUs in a proportional cyclic manner.

[0041] In some implementations, the combination of multiple RUs may include at least one smaller RU and at least one larger RU, and each of the at least one larger RUs has more tones than the at least one smaller RU. In such a case, when assigning the remaining bits to one or more RUs rather than all RUs in the combination of multiple RUs, the processor 712 may assign the remaining bits to at least one larger RU.

[0042] In some implementations, when assigning the remaining bits to at least one larger RU, the processor 712 may proportionally distribute the remaining bits over the last predetermined number of tones on each of the at least one larger RUs. For example, the processor 712 may proportionally distribute the remaining bits over the last 44 tones on each of the at least one larger RUs.

[0043] In some embodiments, the combination of multiple RUs may include a smaller RU of 484 tones and a larger RU of 996 tones. In such a case, in units of s bits, the proportional ratio of the multiple RUs may be 1:2, and alternatively represented as 1s:2s, and the remaining remaining bits are assigned to the larger RU of 996 tones.

[0044] In some embodiments, the combination of multiple RUs may include a smaller RU of 484 tones and two larger RUs of 996 tones. In this case, in units of s bits, the proportional ratio of the multiple RUs may be 1:2:2, and may also be represented as 1s:2s:2s, and the remaining remaining bits are assigned to the two larger RUs of 996 tones in a 2:2 ratio in units of s bits (or represented as 2s:2s).

[0045] In some embodiments, the combination of multiple RUs may include one smaller RU of 484 tones and three larger RUs of 996 tones. In this case, the ratio of the multiple RUs can be 1:2:2:2 in units of s bits, or can be expressed as 1s:2s:2s:2s, and the remaining remaining bits are allocated to the three larger RUs of 996 tones in a ratio of 2:2:2 (or expressed as 2s:2s:2s) in units of s bits.

[0046] In some embodiments, the combination of multiple RUs may include one aggregated RU and one larger RU of 996 tones, and the aggregated RU includes one smaller RU of 242 tones and one smaller RU of 484 tones. In such a case, in units of s bits, the ratio of the multiple RUs can be 3:4, or alternatively expressed as 3s:4s, and the remaining remaining bits are allocated to the large RU of 996 tones.

[0047] In some implementations, the combination of multiple RUs may include one smaller RU of 242 tones and one larger RU of 996 tones. In this case, in units of s bits, the ratio of the multiple RUs can be 1:4 and can alternatively be expressed as 1s:4s.

[0048] Under a scheme related to the processing of remaining bits for proportional cyclic RU parsing in an EHT system according to the present disclosure, device 710 is implemented in STA 110 or as STA 110 in network environment 100, device 720 is implemented in STA 120 or as STA 120 in network environment 110. The processor 712 of device 710 may encode data for a STA (e.g., STA120) to provide a bit stream. Additionally, processor 712 may process the bit stream to provide a processed bit. For example, processor 712 may parse the bit stream in a proportional cyclic manner into a combination of multiple RUs allocated to the STA, and may include at least one smaller RU and at least one larger RU, each RU of the at least one larger RU having more tones than the at least one smaller RU. Further, in the case where remaining bits remain from the parsing in a proportional cyclic manner, processor 712 may allocate the remaining bits to one or more RUs rather than all of the RUs in the combination of multiple RUs. Additionally, processor 712 may wirelessly transmit the processed bit to the STA via the combination of multiple RUs through transceiver 716.

[0049] In some embodiments, when allocating the remaining bits to at least one larger RU, processor 712 may proportionally allocate the remaining bits to the last 44 tones on each of the at least one larger RUs.

[0050] In some implementations, when allocating the remaining bits to at least one larger RU, the processor 712 may sequentially allocate the remaining bits to the last 44 tones on each of the at least one larger RUs.

[0051] In some implementations, when allocating the remaining bits to at least one larger RU, the processor 712 may evenly allocate the remaining bits to each of the at least one larger RUs. For example, when evenly distributing the remaining bits to each of the at least one larger RUs, for every N iterations of parsing the bitstream into a combination of multiple RUs in a proportional cycling manner, the processor 712 may allocate the remaining bits to each RU in the at least one larger RU, where N is an integer equal to or greater than 1.

[0052] In some embodiments, the combination of multiple RUs may include a smaller RU of 484 tones and a larger RU of 996 tones. In such a case, the proportional ratio of the multiple RUs may be 1:2 (in s bits), and alternatively represented as 1s:2s, and the remaining remaining bits are allocated to the larger RU of 996 tones.

[0053] In some embodiments, the combination of multiple RUs may include a smaller RU of 484 tones and two larger RUs of 996 tones. In this case, the proportional ratio of the multiple RUs may be 1:2:2 (in s bits), or may be represented as 1s:2s:2s, and the remaining remaining bits are allocated to the two larger RUs of 996 tones in a ratio of 2:2 (in s bits) (or represented as 2s:2s).

[0054] In some embodiments, the combination of multiple RUs may include a smaller RU of 484 tones and three larger RUs of 996 tones. In this case, the proportional ratio of the multiple RUs may be 1:2:2:2 in s bits, or may be represented as 1s:2s:2s:2s, and the remaining remaining bits are allocated to the three larger RUs of 996 tones in a ratio of 2:2:2 (in s bits) (or represented as 2s:2s:2s).

[0055] In some implementations, the combination of multiple RUs may include an aggregated RU and a larger RU of 996 tones, and the aggregated RU includes a smaller RU of 242 tones and a smaller RU of 484 tones. In such a case, the proportional ratio of the multiple RUs may be 3:4 in s bits, or alternatively represented as 3s:4s, and the remaining remaining bits are allocated to the larger RU of 996 tones.

[0056] In some embodiments, the combination of multiple RUs may include a smaller RU of 242 tones and a larger RU of 996 tones. In this case, the ratio of the multiple RUs can be 1:4 in terms of s bits and can alternatively be expressed as 1s:4s.

[0057] Figure 8 An example process 800 in accordance with an embodiment of the present disclosure is shown. Process 800 may represent an aspect of implementing the various proposed designs, concepts, schemes, systems, and methods described above. More specifically, process 800 may represent an aspect of the proposed concepts and schemes related to residual bit processing for proportional cyclic RU parsing in an EHT system according to the present disclosure. Process 800 may include one or more operations, actions, or functions shown in blocks 810, 820, and 830 and one or more of sub-blocks 822 and 824. Although shown as discrete blocks, depending on the desired implementation, the various blocks of process 800 may be divided into more blocks, combined into fewer blocks, or eliminated. Additionally, the blocks / sub-blocks of process 800 may be executed in the Figure 8 order shown or in other orders. Further, one or more blocks / sub-blocks of process 800 may be executed repeatedly or iteratively. Process 800 may be implemented by or implemented in device 710 and device 720 or any variant thereof. For illustrative purposes only and without limitation, process 800 is described below in the context of device 710 implemented in or as STA 110 and device 720 implemented in or as STA 120 in a wireless network (e.g., WLAN) according to a network environment 100 compliant with one or more IEEE 802.11 standards. Process 800 may begin at block 810.

[0058] At 810, process 800 may involve the processor 712 of device 710 (e.g., STA 110) encoding data for a STA (e.g., STA 120) to provide a bit stream. Process 800 may proceed from 810 to 820.

[0059] At 820, process 800 may include the processor 712 processing the bit stream by performing the operations represented by 822 and 824 to provide processed bits. Process 800 may proceed from 820 to 830.

[0060] At 830, process 800 may include the processor 712 sending the processed bits to the STA via transceiver 716 through a combination of multiple RUs assigned to the STA.

[0061] At 822, process 800 may include the processor 712 parsing the bit stream into a combination of multiple RUs. Process 800 may proceed from 822 to 824.

[0062] At 824, in the case of remaining bits after parsing, process 800 may involve processor 712 allocating the remaining bits to one or more RUs rather than all of the RUs in a combination of multiple RUs.

[0063] In some implementations, when parsing a bitstream into a combination of multiple RUs, process 800 may include processor 712 parsing the bitstream into a combination of multiple RUs in a proportional cycling manner.

[0064] In some embodiments, a combination of multiple RUs may include at least one smaller RU and at least one larger RU, and each of the at least one larger RUs has more tones than the at least one smaller RU. In such a case, when allocating the remaining bits to one or more RUs rather than all of the RUs in a combination of multiple RUs, process 800 may involve processor 712 allocating the remaining bits to at least one larger RU.

[0065] In some implementations, in allocating the remaining bits to at least one larger RU, process 800 may include processor 712 proportionally allocating the remaining bits over the last predetermined number of tones on each of the at least one larger RUs. For example, process 800 may include processor 712 proportionally allocating the remaining bits over the last 44 tones on each of the at least one larger RUs.

[0066] In some embodiments, a combination of multiple RUs may include a smaller RU of 484 tones and a larger RU of 996 tones. In such a case, the ratio of the multiple RUs may be 1:2 in terms of s bits and may alternatively be expressed as 1s:2s, and the remaining remaining bits are allocated to the larger RU of 996 tones.

[0067] In some embodiments, a combination of multiple RUs may include a smaller RU of 484 tones and two larger RUs of 996 tones. In this case, the ratio of the multiple RUs may be 1:2:2 in terms of s bits and may also be expressed as 1s:2s:2s, and the remaining remaining bits are allocated to the two larger RUs of 996 tones in a ratio of 2:2 (in terms of s bits) or expressed as 2s:2s.

[0068] In some embodiments, a combination of multiple RUs may include a smaller RU of 484 tones and three larger RUs of 996 tones. In this case, the ratio of the multiple RUs may be 1:2:2:2 in terms of s bits and may also be expressed as 1s:2s:2s:2s, and the remaining remaining bits are allocated to the three larger RUs of 996 tones in a ratio of 2:2:2 (in terms of s bits) or expressed as 2s:2s:2s.

[0069] In some implementations, the combination of multiple RUs may include an aggregated RU and a larger RU of 996 tones, and the aggregated RU includes a smaller RU of 242 tones and a smaller RU of 484 tones. In such a case, the ratio of the multiple RUs may be 3:4 in units of s bits, or alternatively expressed as 3s:4s, and the remaining bits are allocated to the large RU of 996 tones.

[0070] In some embodiments, the combination of multiple RUs may include a smaller RU of 242 tones and a larger RU of 996 tones. In this case, the ratio of the multiple RUs may be 1:4 in units of s bits and may alternatively be expressed as 1s:4s.

[0071] Figure 9 An example process 900 in accordance with an embodiment of the present disclosure is shown. Process 900 may represent one aspect of implementing the various proposed designs, concepts, schemes, systems, and methods described above. More specifically, process 900 may represent one aspect of the proposed concepts and schemes related to the residual bit processing for proportional cyclic RU parsing in an EHT system in accordance with the present disclosure. Process 900 may include one or more operations, actions, or functions shown in blocks 910, 920, and 930 and sub-blocks 922 and 924. Although shown as discrete blocks, the various blocks of process 900 may be divided, combined into fewer blocks, or eliminated according to the desired implementation. Additionally, the blocks / sub-blocks of process 900 may be executed in the Figure 9 order shown or in other orders. Further, one or more blocks / sub-blocks of process 900 may be executed repeatedly or iteratively. Process 900 may be implemented or realized in or by device 710 and device 720 or any variant thereof. For illustrative purposes only and without limiting the scope, process 900 is described below in the context of device 710 implemented or realized as STA 110 and device 720 implemented or realized as STA 120 in a wireless network (e.g., WLAN) according to a network environment 100 that complies with one or more IEEE 802.11 standards. Process 900 may begin at block 910.

[0072] At 910, process 900 may involve the processor 712 of device 710 (e.g., STA 110) encoding data for a STA (e.g., STA 120) to provide a bit stream. Processing 900 may proceed from 910 to 920.

[0073] At 920, process 900 may involve the processor 712 processing the bit stream by performing the operations represented by 922 and 924 to provide a processed bit. Process 900 may proceed from 920 to 930.

[0074] At 930, process 900 may include the processor 712 transmitting processed bits to the STA through the transceiver 716 through a combination of multiple RUs assigned to the STA, where the combination of multiple RUs may include at least one smaller RU and at least one larger RU, and each of the at least one larger RUs has more tones than the at least one smaller RU.

[0075] At 922, process 900 may include the processor 712 parsing the bit stream into a combination of multiple RUs in a proportional round-robin manner. Process 900 may proceed from 922 to 924.

[0076] At 924, in the case of remaining bits remaining from the parsing in a proportional round-robin manner, process 900 may involve the processor 712 allocating the remaining bits to one or more RUs rather than all of the RUs in the combination of multiple RUs.

[0077] In some implementations, in allocating the remaining bits to at least one larger RU, process 900 may include the processor 712 proportionally allocating the remaining bits over the last 44 tones of each of the at least one larger RUs.

[0078] In some embodiments, in allocating the remaining bits to at least one larger RU, process 900 may include the processor 712 sequentially allocating the remaining bits over the last 44 tones of each of the at least one larger RUs.

[0079] In some embodiments, in allocating the remaining bits to at least one larger RU, process 900 may include the processor 712 evenly allocating the remaining bits over each of the at least one larger RUs. For example, when evenly allocating the remaining bits over each of the at least one larger RUs, process 900 may involve the processor 712. For each N iterations of parsing the bit stream into a combination of multiple RUs in a proportional round-robin manner, the processor 712 may allocate the remaining bits to each of the at least one larger RUs, where N is an integer equal to or greater than 1.

[0080] In some implementations, the combination of multiple RUs may include a smaller RU of 484 tones and a larger RU of 996 tones. In such a case, the proportional ratio of the multiple RUs may be 1:2 in units of s bits and may alternatively be expressed as 1s:2s, and the remaining remaining bits are allocated to the larger RU of 996 tones.

[0081] In some embodiments, the combination of multiple RUs may include one smaller RU of 484 tones and two larger RUs of 996 tones. In this case, the ratio of the multiple RUs can be 1:2:2 in terms of s bits, or expressed as 1s:2s:2s, and the remaining bits are allocated to the two larger RUs of 996 tones in a ratio of 2:2 (in terms of s bits) or expressed as 2s:2s.

[0082] In some implementations, the combination of multiple RUs may include one smaller RU of 484 tones and three larger RUs of 996 tones. In this case, the ratio of the multiple RUs can be 1:2:2:2 in terms of s bits, or expressed as 1s:2s:2s:2s, and the remaining bits are allocated to the two larger RUs of 996 tones in a ratio of 2:2:2 (in terms of s bits) or expressed as 2s:2s:2s.

[0083] In some embodiments, the combination of multiple RUs may include one aggregated RU and one larger RU of 996 tones, and the aggregated RU includes one smaller RU of 242 tones and one smaller RU of 484 tones. In such a case, the ratio of the multiple RUs can be 3:4 in terms of s bits, or alternatively expressed as 3s:4s, and the remaining bits are allocated to the larger RU of 996 tones.

[0084] In some embodiments, the combination of multiple RUs may include one smaller RU of 242 tones and one larger RU of 996 tones. In this case, the ratio of the multiple RUs can be 1:4 in terms of s bits and can alternatively be expressed as 1s:4s.

[0085] The subject matter described herein sometimes shows different components contained within or connected to other different components. It should be understood that the architectures so depicted are merely exemplary, and in fact, many other architectures that achieve the same functions can be implemented. In a conceptual sense, any arrangement of components that achieve the same function is effectively "associated" so as to achieve the desired function. Thus, any two components combined herein to obtain a particular function can be considered "associated" with each other to achieve the desired function, regardless of the architecture or intermediate components. Similarly, any two such associated components can also be considered "operably connected" or "operably coupled" to each other to achieve the desired function, and any two components that can be so associated can also be considered "operably couplable" to each other to achieve the desired function. Specific examples of "operably couplable" include, but are not limited to: components that can be physically coupled and / or physically interact with each other, and / or components that can wirelessly interact and / or wirelessly interact with each other, and / or components that logically interact and / or can logically interact with each other.

[0086] In addition, regarding the use of basically any plural and / or singular terms herein, as long as it is appropriate for the context and / or application, those with ordinary knowledge in the relevant technical field can transform the plural into the singular and / or the singular into the plural. For the sake of clarity, various singular / plural permutations can be explicitly set forth herein.

[0087] Those of ordinary skill in the art will understand that, generally, the terms used in the text, particularly the terms used in the appended claims (e.g., the subject matter in the appended claims), are generally intended to be "open" terms (e.g., the term "comprising" should be interpreted as "comprising but not limited to", the term "having" should be interpreted as "having at least", the term "including" should be interpreted as "including but not limited to", etc.). Those of ordinary skill in the art will also understand that if an intention is to specify the number of the claimed subject matter, such intention will be explicitly stated in the claims. In the absence of such a statement, there is no such intention. For example, for the purpose of helping understanding, the appended claims may include the use of introductory phrases such as "at least one" and "one or more" to introduce the claimed subject matter. However, the use of such phrases should not be construed as limiting any claim that introduces a claimed subject matter with the indefinite article "a" or "an" to an invention that only includes one such claimed subject matter, even if the same claim includes an introductory phrase such as "one or more" or "at least one" and an indefinite article such as "a" or "an" (e.g., "a" and / or "an" should generally be interpreted as meaning "at least one" or "one or more"); the same applies to the case of introducing a claimed subject matter with a definite article. Additionally, even if the specific number of the introduced claimed subject matter is explicitly stated, those of ordinary skill in the art will also recognize that such a statement should generally be interpreted as meaning at least the stated number (e.g., a statement of "only two subjects" without other modifiers generally means at least two subjects, or two or more subjects). Furthermore, in the case of using idiomatic expressions such as "at least one of A, B, and C, etc.", generally such a structure is intended to have the meaning of the idiomatic expression as understood by those of ordinary skill in the art (e.g., "a system having at least one of A, B, and C" will include but not be limited to a system having A alone, B alone, C alone, A and B together, A and C together, B and C together, and / or A, B, and C together, etc.). In the case of using idiomatic expressions such as "at least one of A, B, or C, etc.", generally such a structure is intended to have the meaning of the idiomatic expression as understood by those of ordinary skill in the art (e.g., "a system having at least one of A, B, or C" will include but not be limited to a system having A alone, B alone, C alone, A and B together, A and C together, B and C together, and / or A, B, and C together, etc.).Those of ordinary skill in the art will further understand that, whether in the specification, the claims, or the drawings, almost any disjunctive word and / or phrase that represents two or more alternative terms should be understood to contemplate the possibility of including one of the terms, any one of the terms, or all two of the terms. For example, the phrase "A or B" should be understood to include the possibilities of "A", "B", or "A and B".

[0088] From the foregoing, it can be understood that the various embodiments of the present disclosure have been described herein for purposes of illustration, and various modifications can be made without departing from the scope and spirit of the present disclosure. Accordingly, the various embodiments disclosed herein are not intended to be limiting, and the true scope and spirit are indicated by the appended claims.

Claims

1. A bitstream processing method, comprising: processing a bitstream to provide processed bits; and sending the processed bits to a station through a combination of a plurality of resource units assigned to the station, and wherein the processing of the bitstream includes: parsing the bitstream into a combination of the plurality of resource units in a proportional cyclic manner; and processing the bitstream to provide processed bits further includes: if there are remaining bits after parsing in the proportional cyclic manner, allocating the remaining bits to larger resource units, wherein the combination of the plurality of resource units includes at least one smaller resource unit and at least one larger resource unit, and each of the at least one larger resource units has more tones than the at least one smaller resource unit, and wherein allocating the remaining bits to larger resource units includes evenly distributing the remaining bits on each of the larger resource units.

2. The bitstream processing method according to claim 1, wherein allocating the remaining bits to the at least one larger resource unit includes: allocating the remaining bits proportionally on the last 44 tones of each of the at least one larger resource units.

3. The bitstream processing method according to claim 1, wherein allocating the remaining bits to the at least one larger resource unit includes: sequentially allocating the remaining bits on the last 44 tones of each of the at least one larger resource units.

4. The bitstream processing method according to claim 1, wherein evenly distributing the remaining bits on each of the at least one larger resource units includes: for each N iterations of parsing the bitstream into a combination of the plurality of resource units in the proportional cyclic manner, allocating the remaining bits to each resource unit of the at least one larger resource units, where N is an integer equal to or greater than 1.

5. The bitstream processing method according to claim 1, wherein the combination of the plurality of resource units includes a smaller resource unit of 484 tones and a larger resource unit of 996 tones, and wherein the ratio of the plurality of resource units is 1:2, and the remaining remaining bits are allocated to the larger resource unit of 996 tones.

6. The bitstream processing method according to claim 1, wherein the combination of the plurality of resource units includes a smaller resource unit of 484 tones and two larger resource units of 996 tones, and wherein the ratio of the plurality of resource units is 1:2:2, and the remaining remaining bits are allocated to the two larger resource units of 996 tones in a ratio of 2:

2.

7. The bitstream processing method according to claim 1, wherein the combination of the plurality of resource units includes a smaller resource unit of 484 tones and three larger resource units of 996 tones, and wherein the ratio of the plurality of resource units is 1:2:2:2, and the remaining remaining bits are allocated to the three larger resource units of 996 tones in a ratio of 2:2:

2.

8. The bitstream processing method according to claim 1, wherein The combination of the multiple resource units includes an aggregated resource unit and a larger resource unit of 996 tones, and the aggregated resource unit contains a smaller resource unit of 242 tones and a smaller resource unit of 484 tones. Among them, the ratio of the multiple resource units is 3:4, and the remaining bits are allocated to the larger resource unit of 996 tones.

9. The bitstream processing method according to claim 1, wherein, the combination of the multiple resource units includes a smaller resource unit of 242 tones and a larger resource unit of 996 tones, and among them, the ratio of the multiple resource units is 1:4.

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