Lookup circuit for secure and non-secure storage

Abstract

An apparatus is provided that includes an input circuit that receives a request that includes an input address in an input domain. An output circuit provides an output address. The output address includes a secure physical address to a secure storage circuit and a non-secure physical address to a non-secure storage circuit. A lookup circuit stores a plurality of mappings including at least one mapping between the input address and the secure physical address and at least one mapping between the input address and the non-secure physical address.

Description

TECHNICAL FIELD

[0001] The present disclosure relates to data processing. More specifically, the present disclosure relates to data storage. BACKGROUND

[0002] In some systems, it can be desirable to operate in a plurality of different modes and to allocate memory for each mode. For example, software executing in a first mode of operation can be restricted to accessing memory regions associated with the first mode of operation. Meanwhile, software executing in a second mode of operation can be allowed to access memory regions associated with the first mode of operation as well as memory regions associated with the second mode of operation. The first and second modes of operation can for example be a non-secure mode of operation and a secure mode of operation respectively. SUMMARY

[0003] In at least one example embodiment, there is an apparatus comprising: input circuitry to receive a request, the request comprising an input address in an input domain; output circuitry to provide an output address, wherein the output address comprises a secure physical address to secure storage circuitry and a non-secure physical address to non-secure storage circuitry; and lookup circuitry to store a plurality of entries, an entry indicating a respective one of the output addresses for each of the input addresses, wherein at least one of the entries is related to one of the secure physical addresses and at least one of the entries is related to one of the non-secure physical addresses.

[0004] In at least one example embodiment, there is a method comprising: receiving a request, the request comprising an input address in an input domain; providing an output address, wherein the output address comprises a secure physical address to secure storage circuitry and a non-secure physical address to non-secure storage circuitry; and storing a plurality of entries, an entry indicating a respective one of the output addresses for each of the input addresses, wherein at least one of the entries is related to one of the secure physical addresses and at least one of the entries is related to one of the non-secure physical addresses.

[0005] In at least one example embodiment, there is an apparatus comprising: means for receiving a request, the request comprising an input address in an input domain; means for providing an output address, wherein the output address comprises a secure physical address to secure storage circuitry and a non-secure physical address to non-secure storage circuitry; and means for storing a plurality of entries, an entry indicating a respective one of the output addresses for each of the input addresses, wherein at least one of the entries is related to one of the secure physical addresses and at least one of the entries is related to one of the non-secure physical addresses. Attached Figure Description

[0006] The present technology will be further described by way of example only, with reference to embodiments shown in the accompanying drawings, wherein:

[0007] Figure 1 A system according to some embodiments is shown;

[0008] Figure 2 An example of a second-stage circuit according to some embodiments is shown;

[0009] Figure 3 Several examples of possible settings that can be set in the configuration register according to some embodiments are shown;

[0010] Figure 4 A flowchart illustrating a decision-making process according to some embodiments is shown; and

[0011] Figure 5 Methods according to some embodiments are shown. Detailed Implementation

[0012] Before discussing embodiments with reference to the accompanying drawings, the following description of the embodiments and associated advantages are provided.

[0013] At least some embodiments provide an apparatus comprising: an input circuit for receiving a request including an input address in an input field; an output circuit for providing an output address, wherein the output address includes a secure physical address to a secure storage circuit and a non-secure physical address to a non-secure storage circuit; and a lookup circuit for storing a plurality of entries, each entry indicating a corresponding one of the output addresses for each of the input addresses, wherein at least one of the entries is associated with one of the secure physical addresses and at least one of the entries is associated with one of the non-secure physical addresses.

[0014] In the above embodiments, an access request (e.g., a read or write) is received by the device to access the storage circuitry. The storage circuitry is separated into secure storage circuitry and non-secure storage circuitry, where the secure storage circuitry stores data for software executing in a secure mode of operation, and the non-secure storage circuitry stores data for software executing in a non-secure mode of operation. In some embodiments, the software executing in the secure mode of operation is able to access data in either storage circuitry, but the software executing in the non-secure mode of operation is prohibited from accessing data in the secure storage circuitry (e.g., can access the non-secure storage circuitry, but cannot access the secure storage circuitry). The output address is a physical address, and thus corresponds to a particular location in the secure storage circuitry or the non-secure storage circuitry, and the input address is in an input domain. For example, the input domain itself can be a domain of physical addresses if no change to the address is required. Note, however, that even in this case where no change between the input address and the output address, the term "translation" is used. The domain can also be a virtual domain (or a partial physical domain) in which the physical address is different from the input address. A lookup circuit can be used to indicate the corresponding output address for the input address. In some cases, the input address and the output address can be the same. Regardless, the lookup circuit contains entries for both secure addresses and non-secure addresses.

[0015] In some embodiments, the device is a memory protection unit. A memory protection unit (MPU) provides a protection function for the storage circuitry, preventing programs from accessing memory that is not allowed to be accessed. This can be done by defining a plurality of memory regions, each of which can be associated with particular access attributes, and each of which can be indicated as belonging to secure storage circuitry or non-secure storage circuitry. In some of these embodiments, the translation procedure performed by the MPU does not change the input address (and thus, the input address and the output address are the same) - rather than changing the address, the request is directed to the appropriate storage circuitry.

[0016] In some embodiments, the input address is an intermediate physical address; and the entries include a mapping from the input address to a secure physical address and a mapping from the input address to a non-secure physical address. This can be used for a multi-stage translation, where in a first stage a virtual address (VA) is translated to an intermediate physical address (IPA), and then in a second stage the device is used to translate the IPA to a physical address (PA). Note again that the VA and the IPA, or the IPA and the PA, or even the VA, the IPA, and the PA can all be the same. One case in which the IPA can be used is when a hypervisor is provided. Without knowledge of the hypervisor, an operating system can assume that a particular address is a physical address, as the operating system can see an abstract view of the system that has been provided by the hypervisor. In reality, however, a second level of translation can be required to translate this (intermediate physical) address to an actual physical address.

[0017] In some embodiments, the lookup circuit comprises for each of the entries a security indicator, which is used to indicate whether the entry is a secure physical address or whether the entry is a non-secure physical address. The security indicator may, for example, take the form of a single bit in the lookup circuit to indicate whether the entry relates to a non-secure address or a secure address.

[0018] In some embodiments, the apparatus comprises a protection circuit for controlling access to the secure storage circuit and the non-secure storage circuit in dependence on the security indicator. Based on the indicator, the lookup circuit can determine from where data should be retrieved. In particular, if the entry indicates that the address is a secure physical address, data should be retrieved from the secure storage circuit, whereas if the address is a non-secure physical address, data should be retrieved from the non-secure storage circuit.

[0019] In some embodiments, each of the requests comprises a request type field, which is used to indicate whether the input address in the request is associated with one of the secure physical addresses or one of the non-secure physical addresses. Thus, the request type field indicates whether the issuer of the request (e.g. an operating system) believes that the request relates to an address in the secure storage apparatus or the non-secure storage apparatus.

[0020] In some embodiments, the protection circuit is adapted to control access to the secure storage circuit and the non-secure storage circuit in dependence on the security indicator and the request type field. The security indicator and the request type field can differ from each other. For example, the request type field can indicate that a request is being made to the non-secure storage apparatus, whereas data is actually stored in the secure storage apparatus. For example, data can be stored in an "unexpected" location in order to enable communication between programs. For this, both programs will operate in the same domain (e.g. secure or non-secure) as cross-domain communication can be prohibited for security purposes.

[0021] In some embodiments, the protection circuit allows the request to proceed when the request type field and the security indicator correspond. In these embodiments, the request will be allowed to proceed when the indications provided by the security indicator and the request type field both indicate the use of the same domain (e.g. when they match). No further action is required as the domain indicated by the request type field matches the domain of the security indicator and thus data is stored in the intended domain.

[0022] For example, in some embodiments, the protection circuit forwards the request to the non-secure storage circuit when the request type field indicates that the input address is associated with a non-secure storage circuit and the security indicator indicates that the input address is associated with a non-secure storage circuit. Similarly, in some embodiments, the protection circuit forwards the request to the secure storage circuit when the request type field indicates that the input address is associated with a secure storage circuit and the security indicator indicates that the input address is associated with a secure storage circuit.

[0023] In some embodiments, the apparatus comprises storage circuitry to store one or more settings to control the behaviour of the protection circuit in the event of a mismatch between the request type field and the security indicator to perform one or more error actions. For example, the storage circuitry can take the form of a flip-flop which indicates whether a particular action will occur in the event of a mismatch. For example, the flip-flop can store a single bit of a register along with other bits which indicate whether other actions are to be performed instead, or which of several actions is to be performed.

[0024] In some embodiments, the protection circuit performs an error action when the request type field indicates that the input address is associated with a secure storage circuit and the security indicator indicates that the input address is associated with a non-secure storage circuit; and performs an error action when the request type field indicates that the input address is associated with a non-secure storage circuit and the security indicator indicates that the input address is associated with a secure storage circuit. Thus, the error action is performed in response to a mismatch between the security indicator and the request type field.

[0025] The error action has a number of possibilities, each of which can be used alone or in any combination.

[0026] In some embodiments, the error action comprises forwarding the request to the storage circuit of the lowest security indicated by the request type field and the security indicator. For example, this can be the storage circuit of the lowest privilege and / or can be the circuit with the lowest protection associated with it. In the case where the storage circuits define domains of "secure" and "non-secure", this would be the non-secure domain. By directing the request to the storage circuit of the lowest security, the likelihood of security being compromised is less.

[0027] Alternatively, in some embodiments, the error action comprises forwarding the request to the storage circuit of the highest security indicated by the request type field and the security indicator.

[0028] In some embodiments, the error action includes generating a fault. For example, in some embodiments, the fault corresponds to an invalid page fault. In this way, existing techniques for handling memory access errors can be employed, e.g., an operating system or hypervisor responds to the fault by aborting or ending execution of the software that issued the invalid access request. The operating system or hypervisor can also perform different actions depending on the nature or privilege of the software that issued the request.

[0029] In some embodiments, the request includes an override field that is used to indicate whether the protection circuit should be overridden.

[0030] In some embodiments, the override field is adapted to indicate whether the request should be forwarded to a secure storage circuit or a non-secure circuit, independent of the security indicator. In this way, it is possible to cause the request to proceed and / or be directed to a particular storage circuit, independent of the underlying protection mechanism, regardless of the typical behavior of the protection circuit.

[0031] Some specific embodiments will now be described with reference to the accompanying drawings.

[0032] Figure 1 A system 100 is shown in which software is executed in a number of different privilege modes and execution levels. In particular, the system 100 includes a secure domain (S) and a non-secure domain (NS). Applications operating in the secure domain are able to access data reserved for both the secure and non-secure domains. However, software executing in the non-secure domain is only able to access memory reserved for the non-secure domain and not memory reserved for the secure domain. Thus, at any time, the apparatus can be executing software in the secure domain in a valid secure mode of operation or software in the non-secure domain in a valid non-secure mode of operation.

[0033] In addition to these modes of execution, there are a number of different levels of execution - one for each mode of execution. There is a lowest application level 105, 110, an operating system level 115, 120 and a hypervisor level 125, 130. Above this is a secure monitor level 135, which encompasses both the secure and non-secure domains.

[0034] Applications execute at the lowest privilege level 105, 110 and are managed by the operating system. The operating system executes at the operating system level 115, 120 and is in turn managed by the hypervisor. The hypervisor executes at the hypervisor level 125, 130, which is in turn managed by the secure monitor, which is responsible for switching between secure and non-secure modes of operation.

[0035] Due to the division between the modes of execution, the operating system, operating in its non-secure domain 120, is only able to manage applications operating in its non-secure domain 110 and not applications operating in its secure domain 105.

[0036] The system 100 can use a plurality of different operating systems. These can in turn be managed by hypervisors. Again, a hypervisor is provided for the secure domain 125, which manages the operating system in the secure domain 115, and a hypervisor is provided for the non-secure domain 130, which manages the operating system within the non-secure domain 120. A secure monitor 135 is provided, which operates at the highest execution level.

[0037] During execution of one of the applications, an access request can be issued for a virtual address (VA). The virtual address is issued by the relevant operating system to the first stage translation circuitry 140, which can take the form of a translation lookaside buffer (TLB) or an EL0 managed memory protection unit (MPU). The TLB provides a first stage translation from the virtual address (VA) to a physical address (PA) or an intermediate physical address (IPA). The intermediate physical address can be used in order to enable execution of a plurality of different operating systems, since the operating systems are provided with an abstract view of the system by the appropriate hypervisor 125, 130.

[0038] Subsequently, a second stage of address translation is performed by the second stage translation circuitry 145. This produces a PA based on the input. This can involve a further translation from the IPA, for example, and this can be provided by a TLB, for example. Alternatively, both the input and the output can be PAs, and a memory protection operation can be performed in order to control access to appropriate regions of memory. This service will take the form of a memory protection unit (MPU). In either case, only a single second stage circuitry 145 is provided. Thus, the PA output by the second stage circuitry 145 can be related to either the secure memory 155 provided for the secure domain application 105, operating system 115, hypervisor 125, or the non-secure memory 155 provided for the non-secure domain application 110, operating system 120 and hypervisor 130.

[0039] The address output by the first stage translation circuitry 140 can be an intermediate physical address or a physical address. In particular, although a second stage of the translation procedure is performed, this second translation stage need not involve a change or translation of the address. That is, there can be no translation of the address, or the translation is performed entirely by the first stage translation circuitry 140, which outputs a physical address. Subsequently, further operations can be performed on this physical address by the MPU 145, for example, such as determining whether access to the physical address is permitted. In other embodiments, the intermediate physical address output by the first stage translation circuitry 140 must be further translated in order to obtain a physical address.

[0040] As explained previously, the term "translation" is used herein even when both stages use an MPU. The skilled person will understand that "translation" in this context does not require a transformation of the address. For example, such a "translation" procedure can comprise performing checks, attribute allocation and calculation of a new address, where the translation circuit (e.g. in the form of an MPU) will output an address calculated to be the same as the input address. Thus, although a change of address can occur after the first stage or after the second stage, there is no obligation for a change of address to occur at any time. Such behaviour would correspond to an MMU for example, which performs a full address translation, where the associated page table entry contains an IPA having the same value as the associated VA (in the case of a first stage translation).

[0041] Figure 2 An example of a second stage circuit 145 in the form of a memory protection unit (MPU) is shown. The MPU 145 comprises an input circuit 200 which receives a request for an access location and a memory. As discussed previously, the address provided to the input circuit 200 can be an IPA or a PA. Since the Figure 2 The embodiment shown is an MPU, so the address provided to the input circuit 200 is a PA. The access request received by the input circuit 200 also includes a flag (NS) to indicate whether the access request is secure (0) or non-secure (1). In addition, a supercontrol (SA, NSA) is provided which indicates whether the access request is to be forced to a particular memory circuit. In this case, this value indicates that no supercontrol is provided, since both SA (force secure to non-secure) and NSA (force non-secure to secure) are zero.

[0042] The access request is passed to a protection circuit 205 to control access to secure circuit 150 and non-secure circuit 155. The control is performed based on a storage circuit 220 which contains a plurality of regions of memory which have been identified with parameters for these particular regions. In addition, the protection circuit also references a configuration register 210 which controls the behaviour of the protection circuit 205. The relative Figure 3 An example of the configuration register 210 is shown. In this example, the input address provided (0xF433C1ADE) lies within a region having a base address of 0xF433C1ABB which has a size of 384 bytes. Note that the MPU is able to define regions which are not a power of two in size, providing flexibility in defining the size of a region. Thus, the access request hits this region. As discussed previously, the region is identified with a set of parameters. In this case, the parameters are a base address (0xF433C1ABB) and a size (384 bytes). In addition, the region is identified as being secure (0) and non-secure (1) in this example. Figure 2As shown, the storage circuit 220 defining the region lists the parameters as 0xF4A. The details of these parameters are not relevant to the present disclosure. However, such parameters can be used to further control access to the memory region, for example by restricting whether different programs can read or write to the memory region in question. In any event, the flag "NS" is provided as a security indicator to indicate whether the memory region is associated with the secure storage circuit 150 or the non-secure storage circuit 155. In this case, the value on the region of the storage circuit 220 that has been hit has a value of "1" for the flag "NS". Thus, the memory region is associated with the non-secure storage circuit 155. The protection circuit notes that the security indicator matches the request type field "NS" and thus allows the request to proceed. Thus, in this case the output address matching the input address is output by the output circuit 230 to the non-secure storage circuit 155. In contrast Figure 4 The behaviour of the protection circuit in relation to the configuration register 210, the request type field "NS", the override fields "SA" and "NSA" and the security indicator "NS" is shown in more detail.

[0043] Thus, it will be appreciated that the second stage circuit 145 is able to provide a single storage circuit 220 that provides access to both the secure storage circuit 150 and the non-secure storage circuit 155. Thus, only a single MPU 145 need be provided in order to control access to both the secure storage circuit 150 and the non-secure circuit 155.

[0044] Figure 3A number of examples of possible settings that can be stored in configuration register 210 are shown, which can be used to control the behavior of protection circuit 205. In particular, configuration register 210 can be used to control the number of error actions that occur when there is a mismatch between the request type field and the security indicator "NS". In this example, the error actions indicate whether a fault should be raised, the type of fault that should be raised, and how the request should be directed in the case of a mismatch. The "raise fault" error action has two possible values. Either a fault is raised or no fault is raised. Thus, this can be represented by a single bit. The "fault type" indicates the type of fault that should be raised in the case that a fault is raised. In this example, this can include the invalid page fault previously proposed by the system to indicate that the requested page is invalid, or a "security mismatch" fault to indicate a mismatch between the request type field and the security indicator. Again, since this configuration value has only two options, a single bit can be used to represent it. Clearly, if the raising of a fault is not defined by the "raise fault" configuration value, the "fault type" configuration value will be ignored. The "direction" error action indicates the direction to which the request should be directed. There are three allowed values in this example. If the direction is indicated as "none", the request is not forwarded. If the direction is indicated as "lowest", the request is forwarded to the lowest security storage circuit, which in this example is non-secure storage circuit 155. Alternatively, if the direction is indicated as most secure, the request is directed to the most secure storage circuit, which in this case would be secure storage circuit 150. These three values can be represented by two bits. Thus, a total of four bits can be used to indicate whether a fault should be raised, the type of fault that should be raised, and how the request should be handled in the case of a mismatch. Other possible error actions will be clear to those skilled in the art.

[0045] Figure 4A flowchart 400 is shown which illustrates the decision procedure that can be performed by the protection circuit 205 when determining whether a memory region hit in the storage circuit 220 should be accessed. At step 405, an access request is received. The access request includes an address (INPUT. ADDR) and an indication of whether the access request is secure (0) or non-secure (1) (INPUT. NS). At step 410, it is then determined whether the region of memory is secure, i.e. whether REGION[INPUT. ADDR]. NS is 1. If not, then at step 415 it is determined whether the access request is secure. If so, then at step 450 it has been determined that the memory region is secure and the access request is secure. It is then determined at step 450 whether the request should be forced non-secure (i.e. whether the SA flag is 1). If not, then at step 455 the request proceeds as secure (OUTPUT. NS = 0). If so, then at step 445 the request proceeds as non-secure (OUTPUT. NS = 1). Returning to step 415, if the access request is non-secure, then at step 425 it has been determined that the memory region is secure but the access request is non-secure. It is then determined at step 425 whether NSCHECK is set. In the case where there is a mismatch between the memory region being secure and the request being secure (as is the case at step 425), then this results in a fault. Thus, if NSCHECK is set, then at step 435 a fault is generated. The type of fault can be specified by the configuration value "fault type" shown. Otherwise, at step 440 the transaction defaults to the lowest security mode (i.e. non-secure). However, step 440 allows this to be overridden or forced. In particular, at step 440 it is determined whether NSA is set to force a non-secure transaction to be a secure transaction. If not, then at step 445 the transaction is output as non-secure (OUTPUT. NS = 1). If so, then at step 455 the transaction is output as secure as discussed previously. Figure 3 The type of fault can be specified by the configuration value "fault type" shown. Otherwise, at step 440 the transaction defaults to the lowest security mode (i.e. non-secure). However, step 440 allows this to be overridden or forced. In particular, at step 440 it is determined whether NSA is set to force a non-secure transaction to be a secure transaction. If not, then at step 445 the transaction is output as non-secure (OUTPUT. NS = 1). If so, then at step 455 the transaction is output as secure as discussed previously.

[0046] Returning to step 410, if the region of memory is non-secure, then at step 420 it is determined whether the access request is non-secure (i.e. whether INPUT. NS is 1). If so, then there is a match between the memory region and the transaction type (both are non-secure) and the procedure continues to step 440 as discussed previously where overrides are considered. Otherwise, the procedure continues to step 430 which represents a mismatch between the memory region being accessed and the transaction type. Thus, step 430 determines whether NSCHECK is enabled. If so, then at step 435 this results in a fault being generated as discussed previously. If not, then the transaction proceeds at the lowest security level (i.e. non-secure) and step 440 determines whether the transaction should be forced to be secure (i.e. whether NSA is 0) as discussed previously.

[0047] Thus, it is explained how the protection circuit 205 determines which memory circuit 150, 155 to access, depending on which memory region in the hit storage circuit 220, the security indicator associated with that region (REGION[INPUT.ADDR].NS), the request type field (INPUT.NS) indicating whether the input address is associated with a secure or non-secure physical address, the override flags "SA" and "NSA", and the configuration region 210 (NSCHECK) indicating what is to happen in case of a mismatch between the request type field and the security indicator.

[0048] In this particular example, the "direction" configuration value is set to "lowest". Thus, when there is a mismatch in the memory region type and the request type of steps 425 and 430, the transaction is by default non-secure if no fault is generated. However, it will be appreciated that in other embodiments, the transaction can be by default secure (causing the program to go from steps 425 and 430 to step 450 if no exception is raised), or the decision of steps 425 and 430 can be removed altogether, and a fault can always be generated at step 435 and the transaction discarded when there is a mismatch at steps 415 and 420.

[0049] Figure 5 A method according to some embodiments is shown. The method is shown in the form of a flowchart 500. At step 510, entries are stored in a storage circuit, the entries indicating for an input address a corresponding output address. This can provide a translation between the input address and the output address or the input address and the output address can be the same (e.g. in the case of an MPU). At least one of the entries corresponds to a secure physical address in a secure storage circuit and at least one entry corresponds to a non-secure physical address in a non-secure storage circuit. At step 520, a request is received, the request comprising an input address in an input field. Depending on the nature of the apparatus, the input field can for example be an intermediate physical address field or can be a physical address field. At step 530, an output address is provided in dependence on the input address. The output address comprises a secure physical address to a secure storage circuit and a non-secure physical address to a non-secure storage circuit.

[0050] Thus, it is explained how an apparatus can be provided that controls access to both a secure storage circuit and a non-secure storage circuit as part of an access procedure.

[0051] In this application, the word "configured" is used to mean that an element of an apparatus has the capability to carry out a defined operation. In this context, a "configuration" means an arrangement or manner of interconnection of hardware or software. For example, an apparatus can have dedicated hardware which provides the defined operation, or a processor or other processing device can be programmed to perform the function. "Configured" does not imply that the apparatus element needs to be changed in any way in order to provide the defined operation.

[0052] While the illustrative embodiments have been described with reference to the accompanying drawings detailed description, it is to be understood that the application is not limited to those precise embodiments, and that various changes, additions and modifications can be made to the embodiments without departing from the scope of the application as defined by the appended claims. For example, features of one claim can be combined with features of another claim while not departing from the scope of the application.

Claims

1. An apparatus comprising: An input circuit for receiving a request, the request including an input address in an input field, wherein the input address includes a physical address; Output circuitry is used to provide output addresses, wherein the output addresses include secure physical addresses to secure storage circuits and insecure physical addresses to insecure storage circuits. Each of the requests includes a request type field, which indicates whether the input address in the request is associated with a secure physical address among the secure physical addresses or a non-secure physical address among the non-secure physical addresses; A lookup circuit is used to store a plurality of entries, each entry indicating a corresponding output address among the output addresses for each of the input addresses, wherein at least one entry is associated with a secure physical address among the secure physical addresses, and at least one entry is associated with a non-secure physical address among the non-secure physical addresses, wherein each entry includes a security indicator for indicating whether the entry is a secure physical address or whether the entry is a non-secure physical address; A protection circuit is configured to control access to the secure storage circuit and the insecure storage circuit based on the security indicator; and A storage circuit is provided to store one or more settings to control the behavior of the protection circuit by executing one or more error actions when the request type field differs from the security indicator. The device in question is a memory protection unit; in: When the request type field indicates that the input address is associated with the secure storage circuit and the security indicator indicates that the input address is associated with the insecure storage circuit, the protection circuit performs the error action; and The protection circuit performs the error action when the request type field indicates that the input address is associated with the non-secure storage circuit and the security indicator indicates that the input address is associated with the secure storage circuit.

2. The apparatus according to claim 1, wherein: The input address is an intermediate physical address; and The entry includes a mapping from the input address to the secure physical address and a mapping from the input address to the insecure physical address.

3. The apparatus according to claim 1, wherein: The protection circuit is adapted to control access to the secure storage circuit and the insecure storage circuit based on the security indicator and the request type field.

4. The apparatus according to claim 1, wherein: When the request type field corresponds to the security indicator, the protection circuit allows the request to continue.

5. The apparatus according to claim 1, wherein: When the request type field indicates that the input address is associated with the insecure storage circuit and the security indicator indicates that the input address is associated with the insecure storage circuit, the protection circuit forwards the request to the insecure storage circuit.

6. The apparatus according to claim 1, wherein: When the request type field indicates that the input address is associated with the secure storage circuit and the security indicator indicates that the input address is associated with the secure storage circuit, the protection circuit forwards the request to the secure storage circuit.

7. The apparatus according to claim 1, wherein: The error action includes forwarding the request to the lowest security storage circuit indicated by the request type field and the security indicator.

8. The apparatus according to claim 1, wherein: The error action includes forwarding the request to the highest security storage circuit indicated by the request type field and the security indicator.

9. The apparatus according to claim 1, wherein: The erroneous action includes generating a fault.

10. The apparatus according to claim 9, wherein: The fault corresponds to an invalid page fault.

11. The apparatus according to claim 1, comprising: The request includes an over-control field, which indicates whether the protection circuit should be over-controlled.

12. The apparatus according to claim 11, wherein: The overriding field is adapted to indicate whether the request should be forwarded to the secure storage circuit or the insecure storage circuit, and is independent of the security indicator.

13. A method for protecting a memory cell, comprising: Receive a request, the request including an input address in an input field, wherein the input address includes a physical address; Provide output addresses, wherein the output addresses include secure physical addresses to secure storage circuits and insecure physical addresses to insecure storage circuits. Each of the requests includes a request type field, which indicates whether the input address in the request is associated with a secure physical address among the secure physical addresses or a non-secure physical address among the non-secure physical addresses; Multiple entries are stored, each entry indicating a corresponding output address among the output addresses for each of the input addresses, wherein at least one entry is associated with a secure physical address among the secure physical addresses, and at least one entry is associated with a non-secure physical address among the non-secure physical addresses, wherein each entry includes a security indicator for indicating whether the entry is a secure physical address or a non-secure physical address; Access to the secure storage circuit and the non-secure storage circuit is controlled according to the security indicator; and Store one or more settings to perform one or more error actions when the request type field differs from the security indicator; in: When the request type field indicates that the input address is associated with the secure storage circuit and the security indicator indicates that the input address is associated with the insecure storage circuit, the protection circuit performs the error action; and The protection circuit performs the error action when the request type field indicates that the input address is associated with the non-secure storage circuit and the security indicator indicates that the input address is associated with the secure storage circuit.

14. An apparatus comprising: A component for receiving a request, the request including an input address in an input field, wherein the input address includes a physical address; A component for providing output addresses, wherein the output addresses include secure physical addresses to secure storage circuits and insecure physical addresses to insecure storage circuits. Each of the requests includes a request type field, which indicates whether the input address in the request is associated with a secure physical address among the secure physical addresses or a non-secure physical address among the non-secure physical addresses; A component for storing multiple entries, each entry indicating a corresponding output address among the output addresses for each of the input addresses, wherein at least one entry is associated with a secure physical address among the secure physical addresses, and at least one entry is associated with a non-secure physical address among the non-secure physical addresses, wherein each entry includes a security indicator for indicating whether the entry is a secure physical address or a non-secure physical address; A control component for controlling access to the secure storage circuit and the non-secure storage circuit according to the security indicator; and A storage component is used to store one or more settings to control the behavior of the control component by executing one or more error actions when the request type field differs from the security indicator. The device in question is a memory protection unit; in: When the request type field indicates that the input address is associated with the secure storage circuit and the security indicator indicates that the input address is associated with the insecure storage circuit, the control member performs the error action; and The control element performs the error action when the request type field indicates that the input address is associated with the insecure storage circuit and the security indicator indicates that the input address is associated with the secure storage circuit.

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