Power management components for memory subsystem voltage regulation

Abstract

A memory subsystem includes a power management component comprising a plurality of regulators configured to supply respective operating voltages to components of the memory subsystem. The power management component is configured to adjust a regulator voltage level provided to a particular component until a change in the operating state of the particular component is detected. The power management component is further configured to determine a value for the regulator voltage level upon detecting the change in the operating state of the particular component.

Description

Technical Field

[0001] Embodiments of the present disclosure relate generally to memory subsystems, and more particularly, to a power management component for memory subsystem voltage regulation. Background Art

[0002] The memory subsystem may be a storage system, such as a solid-state drive (SSD), and may include one or more memory components that store data. The memory components may be, for example, non-volatile memory components and volatile memory components. Typically, a host system may utilize the memory subsystem to store data in the memory components and retrieve data from the memory components. Summary of the Invention

[0003] In one aspect, the present disclosure relates to a memory subsystem for regulator voltage level measurement, comprising: a power management component comprising a plurality of regulators configured to supply corresponding operating voltages to components of the memory subsystem; wherein the power management component is configured to: adjust the regulator voltage level provided to a specific component until a change in the operating state of the specific component is detected; and determine the value of the regulator voltage level when the change in the operating state of the specific component is detected.

[0004] On the other hand, the present disclosure relates to a method for regulator voltage level measurement, which includes: providing an operating voltage from a power management component of a memory subsystem to a specific component of the memory subsystem via a regulator of the power management component; adjusting the voltage level of the operating voltage output by the regulator; detecting the occurrence of an operating state change of the specific component due to the adjustment of the voltage level; and determining the voltage level of the operating voltage when the operating state change of the specific component is detected.

[0005] In another aspect, the present disclosure relates to a power management component for regulator voltage level measurement, comprising: a plurality of regulators configured to supply respective operating voltages to components of a memory subsystem; feedback circuitry coupled to the plurality of regulators and a control component, the feedback circuitry configured to: compare a voltage level of a regulator output voltage provided to a particular component with a first threshold voltage level; and provide a feedback signal indicative of a result of the comparison to the control component; and wherein the control component is configured to: adjust the voltage level of the regulator output voltage to a plurality of different voltage levels such that the first threshold voltage level is compared with the plurality of different voltage levels of the regulator output voltage until a change in an operating state of the particular component is detected; after detecting the change in operating state, adjust the first threshold voltage level to a second threshold voltage level; adjust the voltage level of the regulator output voltage to the plurality of different voltage levels such that the second threshold voltage level is compared with the plurality of different voltage levels of the regulator output voltage until the change in operating state of the particular component is detected; and determine, based on the first and second threshold voltage levels, an operating voltage level at which the change in operating state of the particular component is detected. BRIEF DESCRIPTION OF THE DRAWINGS

[0006] The present disclosure will be more fully understood from the detailed description given below and from the accompanying drawings of various embodiments of the present disclosure.

[0007] Figure 1 An example computing environment including a memory subsystem according to some embodiments of the present disclosure is described.

[0008] Figures 2A to 2B Example power management components according to some embodiments of the present disclosure are described.

[0009] Figure 3 is a flow chart corresponding to an example method of determining an operating voltage level for a regulator, according to some embodiments of the present disclosure.

[0010] Figure 4 is a block diagram of an example computer system in which embodiments of the present disclosure may operate. DETAILED DESCRIPTION

[0011] Aspects of the present disclosure relate to a power management component for monitoring an operating voltage of a regulator. A memory subsystem is also referred to hereinafter as a "memory device." An example of a memory subsystem is a storage system, such as a solid-state drive (SSD). In some embodiments, the memory subsystem is a hybrid memory / storage subsystem. Typically, a host system may utilize a memory subsystem that includes one or more memory components. The host system may provide data to be stored at the memory subsystem and may request retrieval of data from the memory subsystem.

[0012] A memory subsystem (e.g., an SSD) may include power management components, such as a power management integrated circuit (PMIC). The power management components may include various regulators that provide output voltages (e.g., regulator voltages) to power various system components (e.g., control circuitry, input / output (I / O) circuitry, array core circuitry, peripheral components, etc.). These regulators may include buck regulators, boost regulators, buck-boost regulators, and / or low dropout (LDO) regulators, among other regulator types. The regulator output voltages may correspond to various voltage rails of the memory subsystem, such as I / O rails, supply rails, reference rails, etc. As used herein, voltage rail (or rail voltage) may be used to refer to the output voltage of a voltage regulator configured for a specific load. Some common voltage rails may include 1V, 2.5V, 3.3V, and 5V; however, embodiments of the present disclosure are not limited to specific rail voltage values.

[0013] In various instances, it may be beneficial to measure (e.g., test) the voltage level actually output by the regulator of a power management component. Such measurements may be used, for example, in conjunction with evaluating the power management component and / or the various memory subsystem components powered thereby. For example, determining the marginal operating range of a component powered by a PMIC regulator may be beneficial. Due to the dependence of supply rail voltage on multiple system components, it may be difficult to test the internal supply rail voltage of a power management component via circuitry external to the power management component, such as an in-circuit test (ICT) system, without utilizing direct probing. Such ICT systems are utilized by various conventional systems.

[0014] Aspects of the present disclosure address the shortcomings of previous approaches by using circuitry within a power management component (e.g., a PMIC) to stimulate and measure regulator voltage levels. Such internal measurements can be used, for example, to determine the marginal operating voltage range of the regulator and / or components coupled thereto. In several examples, the PMIC regulator output voltage provided to a memory subsystem component can be adjusted until the component experiences an operating state change. The operating state change can, for example, be a change from a first state (e.g., an active state) to a brownout state. A brownout condition (e.g., a brownout state) refers to a state in which the supply voltage provided to a powered component drops below a level at which the component can operate effectively. As further described herein, the regulator voltage level can be adjusted and / or monitored via circuitry within the PMIC. For example, feedback circuitry, an analog-to-digital converter (ADC), pulse width modulation circuitry, etc. can be used to adjust and monitor the regulator output voltage level. For example, the internally measured regulator output voltage level of a component experiencing a brownout condition can be used to determine the marginal operating range of the component and / or determine whether the component is defective.

[0015] Figure 1 An example computing environment 100 including a memory subsystem 104 according to some embodiments of the present disclosure is described. A host system 102 may be a computing device, such as a desktop computer, a laptop computer, a network server, a mobile device, or any other such computing device that includes memory and processing devices. Host system 102 may include or be coupled to memory subsystem 104 so that host system 102 can read data from or write data to memory subsystem 104. Host system 102 may be coupled to memory subsystem 104 via a physical host interface. As used herein, "coupled to" generally refers to a connection between components, which may be an indirect communication connection or a direct communication connection (e.g., without intervening components), whether wired or wireless, including, for example, electrical, optical, magnetic, or other connections. Examples of physical host interfaces include, but are not limited to, a Serial Advanced Technology Attachment (SATA) interface, a Peripheral Component Interconnect Express (PCIe) interface, a Universal Serial Bus (USB) interface, Fibre Channel, Serial Attached SCSI (SAS), and the like. A physical host interface may be used to transmit data between host system 102 and memory subsystem 104. The host system 102 may further utilize an NVM Express (NVMe) interface to access the memory components 118-1 to 118-N when the memory subsystem 104 is coupled to the host system 102 via a PCIe interface. A physical host interface may provide an interface for passing control, address, data, and other signals between the memory subsystem 104 and the host system 102.

[0016] The host system 102 may include a memory subsystem detector 103. The host system 102 may be configured to determine, via the memory subsystem detector 103, an operational state of the memory subsystem 104 based on, for example, the absence of a signal to be received from the memory subsystem 104. In one example, the host system 102 may be configured to determine, via the memory subsystem detector 103, that the memory subsystem 104 has been physically decoupled from the host system 102. In another example, the host system 102 may be configured to determine, via the memory subsystem detector 103, to place the memory subsystem 104 in a different state other than the active state (e.g., non-operational) when the memory subsystem 104 is physically coupled to the host system 102. The memory subsystem 104 may be placed in a different state when the memory subsystem 104 and / or at least a portion of the components of the memory subsystem 104 experience a brownout.

[0017] Memory subsystem 104 may include media, such as memory components 118-1 through 118-N. Memory components 118-1 through 118-N may be volatile memory components, non-volatile memory components, or a combination thereof. In some embodiments, memory subsystem 104 is a storage system. An example of a storage system is an SSD. In some embodiments, memory subsystem 104 is a hybrid memory / storage subsystem. Typically, computing environment 100 may include a host system 102 that utilizes memory subsystem 104. For example, host system 102 may write data to and read data from memory subsystem 104.

[0018] Memory components 118-1 to 118-N may include various combinations of different types of nonvolatile memory components and / or volatile memory components. An example of a nonvolatile memory component includes NAND-type flash memory. Each of memory components 118-1 to 118-N may include one or more memory cell arrays, such as single-level cells (SLC) or multi-level cells (MLC) (e.g., triple-level cells (TLC) or quad-level cells (QLC)). In some embodiments, a particular memory component may include both an SLC portion and an MLC portion of a memory cell. Each of the memory cells may store one or more data bits (e.g., a data block) used by the host system 102. Although nonvolatile memory components (e.g., NAND-type flash memory) are described, memory components 118-1 to 118-N may be based on various memory technologies and / or array architectures. In some embodiments, the memory components 118-1 to 118-N may be, but are not limited to, random access memory (RAM), read-only memory (ROM), dynamic random access memory (DRAM), synchronous dynamic random access memory (SDRAM), phase change memory (PCM), magnetic random access memory (MRAM), NOR (NOR) flash memory, electrically erasable programmable read-only memory (EEPROM), and may be arranged in a planar array, a cross-point array, a three-dimensional cross-point array, etc.

[0019] The memory system controller 106 can communicate with the memory components 118-1 to 118-N to perform operations such as reading, writing, or erasing data at the memory components 118-1 to 118-N, as well as other such operations. The memory system controller 106 may include hardware, such as one or more integrated circuits and / or discrete components, buffer memory, or a combination thereof. The memory system controller 106 may be a microcontroller, dedicated logic circuitry (e.g., a field programmable gate array (FPGA), an application-specific integrated circuit (ASIC), etc.), or other suitable processor. The memory system controller 106 may include a processing device (e.g., a processor 114) configured to execute instructions stored in the local memory 116. The local memory 116 of the memory system controller 106 includes embedded memory configured to store instructions for executing various processes, operations, logic flows, and routines that control the operation of the memory subsystem 104, including handling communications between the memory subsystem 104 and the host system 102. In some embodiments, the local memory 116 may include memory registers that store memory pointers, fetched data, etc. Local memory 116 may also include read-only memory (ROM) for storing microcode.

[0020] The memory system controller 106 may further include power monitoring circuitry 107. The memory system controller 106 may be configured to determine the respective operating states of the components of the memory subsystem 104 to which the regulator voltage is provided via the power monitoring circuitry 107. The power monitoring circuitry 107 may be similar to the power monitoring circuitry 111 integrated within the control component 110. For example, if the power monitoring circuitry 111 cannot be properly utilized, the power monitoring circuitry 107 may operate in place of the power monitoring circuitry 111 of the control component 110.

[0021] Although Figure 1 The example memory subsystem 104 in FIG has been described as including a memory system controller 106, but in another embodiment of the present disclosure, the memory subsystem 104 may not include a memory system controller 106, but may rely on external control (e.g., provided by an external host, or by a processor or controller separate from the memory subsystem).

[0022] Typically, the memory system controller 106 may receive commands or operations from the host system 102 and may convert the commands or operations into instructions or appropriate commands to achieve the desired access to the memory components 118-1 to 118-N. The memory system controller 106 may be responsible for other operations associated with the memory components 118-1 to 118-N, such as wear leveling operations, garbage collection operations, error detection and error correction code (ECC) operations, encryption operations, cache operations, and address translation between logical block addresses and physical block addresses. The memory system controller 106 may further include host interface circuitry for communicating with the host system 102 via a physical host interface (not shown). The host interface circuitry may convert commands received from the host system into command instructions to access the memory components 118-1 to 118-N and convert responses associated with the memory components 118-1 to 118-N into information for the host system 102.

[0023] The memory subsystem 104 may also include additional circuitry or components not illustrated. For example, the memory components 118-1 through 118-N may include control circuitry, address circuitry (e.g., row and column decoding circuitry), and / or input / output (I / O) circuitry through which the memory components 118-1 through 118-N can communicate with the memory system controller 106 and / or the host system 102. As an example, in some embodiments, the address circuitry may receive an address from the memory system controller 106 and decode the address to access the memory components 118-1 through 118-N.

[0024] Memory subsystem 104 includes a power management component 108. In some embodiments, power management component 108 and / or the functionality of power management component 108 is part of host system 102, an application, or an operating system. In various embodiments, power management component 108 is a power management integrated circuit (PMIC).

[0025] The power management component 108 may include a control component 110, a feedback circuit system 109, and regulators 112-1 to 112-M. The regulators 112-1 to 112-M are operable to generate and output voltages (e.g., rail voltages) that can be provided as operating voltages to various components within the memory subsystem 104. The voltages may be based on the input voltage (V in ) generates regulator voltages for regulators 112-1 through 112-M. The input voltage may be supplied to power management component 108 via connector / interface 113 and may be further purposefully adjusted to change the respective regulator voltages before being supplied to the respective regulators 112-1 through 112-M, as further described herein.

[0026] Regulator voltages generated from regulators 112-1 through 112-M may be provided to various components of the memory subsystem 104. As described herein, the regulator voltages may correspond to various voltage rails of the memory subsystem, such as I / O rails, supply rails, reference rails, etc., that are provided to power various system components, such as the memory system controller 106 and components therein, memory components 118-1 through 118-M, control circuitry, input / output (I / O) circuitry, array core circuitry, peripheral components, etc. For example, the regulator voltages of regulators 112-1 through 112-M may correspond to respective supply voltage rails used in an SSD.

[0027] Feedback circuitry 109 may be coupled to regulators 112-1 through 112-M and control component 110. In some embodiments, feedback circuitry 109 may be configured to receive regulator voltages of regulators 112-1 through 112-M as respective inputs and provide feedback signals to control component 110. Feedback circuitry 109 may include comparators and / or analog-to-digital converters (ADCs), such as in conjunction with Figures 2A to 2B In response to receiving the feedback signal from the feedback circuitry 109 , the control component 110 may determine the values ​​of the respective regulator voltage levels of the regulators 112 - 1 through 112 -M.

[0028] The control component 110 may include a voltage regulation component 120 and a power monitoring circuit system 111. Using the power monitoring circuit system 111, the control component 110 may be configured to detect a change in the operating state of the corresponding component. The change in operating state may correspond to when the corresponding component experiences a brownout. As an example, the power monitoring circuit system 111 may monitor power status signals provided by various subsystem components powered by the PMIC 108. Such power status signals may be, for example, power good / reset signals. Using the voltage regulation component 120, the control component may be configured to adjust the regulator voltage provided to the corresponding component of the memory subsystem 104. In one example, the voltage regulation component 120 may be configured to adjust the voltage of the regulator provided to the corresponding component of the memory subsystem 104 by adjusting the input voltage (V in ) to adjust the regulator voltage.

[0029] Control component 110 can cooperatively utilize power monitoring circuitry 111, voltage regulation component 120, and feedback signals received from feedback circuitry 109. In one example, control component 110 can adjust the regulator voltage level provided to a particular component until a change in the operating state of the particular component is detected. In another example, control component 110 can determine the value of the regulator voltage level when a change in the operating state of the particular component is detected.

[0030] As described herein, undervoltage in a particular component may also cause undervoltage in other components of the memory subsystem 104. For example, undervoltage in one of the memory components 118-1 through 118-N may further cause undervoltage in the power management component 108 and / or the entire memory subsystem 104. Thus, functionality for detecting operating states and / or changes in operating states of components of the memory subsystem 104 may be implemented across various components of the computing system 100. For example, the host system 102 may include a memory subsystem detector 103 that may detect the operating state of the memory subsystem 104, and the memory system controller 106 may include a power monitoring circuitry 107 that may perform similar functionality as that performed by the power monitoring circuitry 111 within the power management component 108. The memory subsystem detector 103 and / or the power monitoring circuitry 111 may communicate with the power management component 108 via various communication protocols, signals, and / or circuits, such as an inter-integrated circuit (I2C), general-purpose input / output (GPIO) signals, and / or a universal asynchronous receiver / transmitter (UART).

[0031] Figures 2A to 2B An example power management component 208 is illustrated according to some embodiments of the present disclosure. Figures 2A to 2B The examples illustrated in include various types of feedback circuitry similar to feedback circuitry 109. The feedback circuitry may be used to measure a regulator output voltage level internal to the PMIC.

[0032] Figure 2A An example of a power management component 208 including a plurality of comparators 225-1 through 225-N according to some embodiments of the present disclosure is illustrated. The power management component 208 may include a power management circuit (PMIC). The PMIC may include a control component 210 and a voltage converter 224. The voltage converter 224 may include regulators 212-1 through 212-N and feedback circuitry, such as illustrated as comparators 225-1 through 225-N. The regulators 212-1 through 212-N and the comparators 225-1 through 225-N may be collectively referred to as regulators 212 and comparators 225, respectively.

[0033] The PMIC can be powered by an input voltage, which can be further adjusted by a voltage adjustment component 220 within the control component 210. The regulator 212 can be configured to generate corresponding regulator voltages 228-1 to 228-M (e.g., collectively referred to as regulator voltages 228) based on the adjusted input voltage. However, embodiments are not limited thereto. In one example, a regulator (e.g., a buck-boost converter) can adjust the regulator voltage level by adjusting pulse width modulation without changing the input voltage. In another example, the regulator voltage level of a particular regulator (e.g., a low dropout (LDO) regulator) can be adjusted by modifying the position of the load line that adjusts the regulator voltage through the load.

[0034] The generated regulator voltage 228 can be provided as an operating voltage to corresponding components of the memory subsystem, such as the memory system controller 106, the processor 114, the local memory 116, and the memory components 118-1 to 118-N and / or various circuitry associated therewith (e.g., I / O circuitry, address circuitry, control circuitry, etc.). The regulator 212 can include an LDO regulator, a buck-boost converter, a buck regulator, a boost regulator, or a combination thereof, but embodiments are not limited thereto.

[0035] As an example, an LDO regulator can be a linear voltage regulator that operates with a very small input-output differential voltage and can regulate the output voltage of a buck-boost converter to output one of the regulator voltages 228. Multiple LDO regulators can be provided based on the regulator voltages 228 used in the memory subsystem.

[0036] The buck-boost converter can detect the input voltage and can operate in buck mode when the input voltage is higher than the output voltage from the buck-boost converter. When the detected input voltage is lower than the output voltage from the buck-boost converter, the buck-boost converter can operate in boost mode. The buck-boost converter can help to achieve a constant voltage output.

[0037] A buck regulator may be a voltage-step-down direct current (DC) / DC converter that generates a predetermined output voltage by reducing an input voltage. A buck regulator may use a switching device that switches on and off within a specific cycle and may have a structure in which an input power supply (e.g., input voltage) is connected to a circuit when the switch is on and disconnected from the circuit when the switch is off. A buck regulator may output a DC voltage by averaging a pulse-shaped voltage that is periodically connected to and disconnected from the circuit through an inductor-capacitor (LC) filter. A buck regulator may use the following principle: an output voltage is generated by averaging a pulse voltage by periodically reducing the DC voltage so that the output voltage of the buck regulator has a voltage lower than the input voltage of the buck regulator.

[0038] A boost regulator can be a voltage-step-up DC / DC converter. In a boost regulator, when the switch is on, the input voltage is connected to the two terminals of an inductor, creating a charging current. When the switch is off, the charging current is delivered to the load. Therefore, the current flowing through the output terminals of the boost regulator can be less than the current flowing through the input terminals of the boost regulator. Because there are no losses due to the operating principle of the boost regulator, the output voltage of the boost regulator can be higher than the input voltage of the boost regulator, based on the relationship "input current * input voltage = output current * output voltage."

[0039] Each comparator 225 may be configured to receive a regulator voltage (eg, one of the regulator voltages 228 ) from a corresponding one of the regulators 212 and compare the received regulator voltage to a reference voltage V REF1 to V REFN For example, the comparator 225-1 can compare the regulator voltage 228-1 with the reference voltage V REF1 The reference voltage is a programmable value, so that for example the reference voltage V REF1 to V REFN The threshold adjustment component 222 can be programmed to different values ​​by the control component 210. As an example, the threshold adjustment component 222 can adjust the reference voltage level in a number of specific increments / decrements. REF1 to V REFN to determine a corresponding regulator voltage level (the value of the corresponding regulator voltage 228 ), as further described herein.

[0040] In some embodiments, at least two of the comparators 225 may have different corresponding reference voltages associated therewith. For example, the reference voltage V REF1 The voltage level can be different from the reference voltage V REFN Thus, at least some of the regulator voltages 228 may be compared to different threshold voltage levels.

[0041] The results of the comparison can be provided to the control component 210 in the form of signals (e.g., signals 227-1 to 227-N). The signals 227-1 to 227-N that can be provided by the comparator 225 can be binary in nature and can indicate whether the corresponding monitored output voltage is greater than a threshold voltage level. For example, the signals can represent binary logic values ​​(e.g., logic "1" or "0"), where one binary value indicates that the regulator voltage is greater than the reference voltage and the other binary value indicates that the regulator voltage is not greater than the reference voltage.

[0042] The control component 210 may include a power monitoring circuit system 211, a voltage adjustment component 220, a threshold adjustment component 222, and a voltage determination component 223. As described herein, the control component 210 may determine the operating state and / or operating state change of a component of a memory subsystem (e.g., memory subsystem 104) via the power monitoring circuit system 211. In one example, the control component 210 may monitor a power state signal of a component of the memory subsystem via the power monitoring circuit system 211. The power state signal may indicate whether the corresponding component is in an active state (e.g., operating) or an inactive state (e.g., voltage is too low). By monitoring the power state signal, the power monitoring circuit system 211 may determine when the operating state of the corresponding component has changed. The actual output voltage level of the regulator when this operating state change occurs may be measured in various ways, including (but not limited to) using, for example, Figure 2A The comparator 225 described in and / or as Figure 2B ADC 229 as described in .

[0043] The control component 210 can adjust the threshold (e.g., reference voltage level) of the comparator 225 to different (e.g., programmable) values ​​(e.g., via signal 226) via the threshold adjustment component 222. The control component 210 can determine the regulator voltage level based on the feedback signals 227-1 to 227-N received from the comparator 225 via the voltage determination component 223.

[0044] The control component 210 can utilize various components of the control component 210 in a collaborative manner to determine the value of the operating voltage level when a change in the operating state of the corresponding component is detected. For example, when the regulator voltage level and the corresponding threshold voltage level provided to the corresponding component are adjusted by the voltage adjustment component 220 and the threshold adjustment component 222, respectively, the voltage determination component 223 can collect information from the power monitoring circuit system 211 and the feedback circuit system 109. Based on the collected information, the voltage determination component 223 can determine the regulator voltage level and further determine the operating voltage level based on the regulator voltage level, as further described below.

[0045] Table 1 illustrates an example of determining an operating voltage level by adjusting a regulator voltage and adjusting (e.g., rastering) a corresponding comparator threshold voltage level. As an example, whenever a corresponding regulator voltage is adjusted, a predetermined threshold voltage level (e.g., 2.5V) of a comparator (e.g., comparator 225-1) may be compared to a corresponding regulator output voltage, as shown in Table 1 below:

[0046] Table 1

[0047]

[0048]

[0049] It should be noted that “V OUT ” indicates the regulator output voltage, “V TH ” indicates the corresponding threshold voltage of the comparator, “+” indicates that the regulator voltage is greater than the corresponding threshold voltage, and “-” indicates that the regulator voltage is less than the corresponding threshold voltage. In this example, during the first round of iterations, the regulator voltage is iteratively adjusted and compared with the threshold voltage of 2.5V (see the column “V TH =2.5”). As shown in the example of Table 1, for the first, second and third iterations, V OUT Greater than V TH (As indicated by a "+"). At V TH = 2.5V, during the fourth and fifth iterations, determine V OUT Less than V TH (As indicated by the "-"). Therefore, it is determined that a V OUT The operational state of the component to which it is provided changes.

[0050] In this example, for the second iteration, V TH From 2.5V to 2.3V. During the second iteration (e.g., column “V TH = 2.3”), adjust V in a similar way to the first round OUT And with 2.3V V TH As shown in Table 1, for the first, second, third and fourth iterations, V OUT Greater than V TH (As indicated by "+"). However, for the fifth iteration, when V OUT When adjusted to 2.1V, as determined by the feedback signal V OUT Less than V TH Since different feedback signals are obtained during the fourth iteration of the two rounds of iteration, the V used during the fourth iterations of the first and second rounds can be used to calculate the feedback signal. THDetermine the operating voltage level at which a change in operating state has occurred. In one example, the operating voltage level that has placed the corresponding component in a brownout state can be determined based on a range, for example, from 2.3V to 2.5V. Thus, in this example, the voltage level range can be determined to be from 2.5V to 3.3V (within the voltage level range within which the corresponding component can operate without a change in operating state (e.g., not being placed in a brownout state)), which is determined based on the upper limit (e.g., 2.5V) of a previously determined range (e.g., 2.3V to 2.5V). As used herein, an operating voltage level range within which the corresponding component can operate without a change in operating state (e.g., not being placed in a brownout state) may be referred to as an operating voltage range. In another example, the operating voltage level can be determined based on a specific numerical value (e.g., rather than a range) by interpolating between threshold voltage levels previously used for comparison (e.g., 2.5V to 2.3V). For example, interpolation performed between 2.5V and 2.3V can determine the operating voltage to be 2.4V. Thus, in this example, the operating voltage range of the monitored component may be determined to be from 2.4 V to 3.3 V, which is determined based on the operating voltage level being 2.4 V. After determining the operating voltage range, the power management component 208 may report the operating voltage range and / or the operating voltage level to the memory system controller 106 and / or the host system 102 (e.g., in conjunction with power system testing).

[0051] In some embodiments, a more accurate marginal operating voltage level may be determined by performing additional comparator VT adjustments, as shown in Table 2 below:

[0052] Table 2

[0053] Iteration <![CDATA[V OUT ]]> <![CDATA[V TH =2.5]]> <![CDATA[V TH =2.3]]> <![CDATA[V TH =2.45]]> <![CDATA[V TH =2.35]]> 1 3.3 + + + + 2 3 + + + + 3 2.7 + + + + 4 2.4 - + - + 5 2.1 - - - -

[0054] For example, continuing the above example, one may calculate the value of V for the adjusted (eg, incremented) V TH Perform the third iteration. In this example, V TH The increment is by a certain amount (eg, 0.15V) that is less than the V TH Similarly, in the fourth iteration, V may be adjusted (eg, decremented) TH By a specific amount that is less than 0.15 V. In this example, the operating voltage level may be determined to be from 2.45 V to 3.3 V, which is determined based on an upper limit (eg, 2.45 V) of a previously determined range (eg, 2.35 V to 2.45 V).

[0055] Figure 2BAn example of a power management component 208 including an analog-to-digital converter (ADC) 229 is illustrated in accordance with some embodiments of the present disclosure. The ADC 229 can be coupled to the regulators 212 of the voltage converter 224 and the control component 210. The ADC 229 can be configured to receive a regulator voltage from a respective regulator 212 as an input analog signal and convert the regulator voltage into a respective digital signal, for example, by monitoring the output voltage at a particular rate (e.g., sampling the output voltage). The digital signal obtained from sampling the regulator voltage of the regulator 212 can indicate the regulator output voltage level of the regulator 212, as shown in Table 3 below:

[0056] Table 3

[0057] Iteration <![CDATA[V OUT ]]> Sampled digital value 1 3.3 3.3 2 3 3 3 2.7 2.7 4 2.4 2.4 5 2.1 2.1

[0058] Thus, the control component 210 can report the sampled value directly to the memory system controller 106 and / or the host system 102 by interpolating between the threshold voltage levels previously used for comparison, without having to determine the operating voltage range and / or determine the operating voltage level. Therefore, the power management component 208 including the ADC 229 as feedback circuitry may not include the voltage determination component 223.

[0059] Figure 3 is a flow chart of an example method for determining an operating voltage level according to some embodiments of the present disclosure. Method 330 may be performed by processing logic, which may include hardware (e.g., a processing device, circuitry, dedicated logic, programmable logic, microcode, integrated circuit systems, etc.), software (e.g., instructions executed by a processing device), or a combination thereof. In some embodiments, method 330 may be performed by a power management component, such as Figure 1 The power management component 108 or Figure 2A or Figure 2B 208 of the power management component. Although shown in a particular sequence or order, the order of the processes of method 330 may be modified unless otherwise specified. Therefore, the illustrated embodiments should be understood as examples only, and the illustrated procedures may be performed in a different order, and some processes may be performed in parallel. In addition, one or more processes may be omitted in various embodiments. Therefore, not all processes are required in every embodiment. Other process flows are also possible.

[0060] At block 331, an operating voltage is provided from the power management component to a specific component via a regulator of the power management component of the memory subsystem. At block 333, a voltage level of the operating voltage output by the regulator is adjusted. The voltage level can be adjusted in an incremental or decremental manner. In one example, the voltage level of the operating voltage can be decreased (e.g., decremented) from a first voltage level until a first operating state change is detected. In another example, the voltage level of the operating voltage can be increased (e.g., incremented) to a level above the first voltage level until a second operating state change is detected. The first operating state change can differ from the second operating state change in that, for example, the first operating state change can include a change from an active state to an undervoltage state, while the second operating state change can include a change from an undervoltage state to an active state.

[0061] Detection of a change in operating state can occur in various ways. For example, a system controller (e.g., system controller 106) can monitor a power status pin of a component that receives a regulator output voltage (e.g., a power rail). In response to the power status pin indicating a particular state of the component (e.g., a bad power state due to an undervoltage condition), the system controller can provide a signal to a PMIC (e.g., 108, 208) indicating a change in operating state. The PMIC can measure the regulator voltage when a change in operating state occurs, as discussed above, and the measured regulator voltage can be reported to a host (e.g., 102) directly or via a memory system controller (e.g., 106).

[0062] At block 335, the occurrence of a change in the operating state of a particular component due to the adjustment of the voltage level is detected. The change in operating state may include, for example, a change from a particular state to an undervoltage state. The voltage level may be adjusted by the voltage adjustment component 220, such as in conjunction with Figure 1 and as described in Figure 2.

[0063] At block 337, the voltage level of the operating voltage at which the change in the operating state of the particular component is detected may be determined. The voltage level may be determined via circuitry within the power management component (e.g., voltage determination component 223), such as in conjunction with Figure 1 2. As described above, in several embodiments, the value of the regulator output voltage level when a state change of a particular component occurs can be determined by rastering the threshold voltage of a comparator (e.g., feedback circuitry within the PMIC) and / or by using an ADC within the PMIC.

[0064] In some embodiments, the operating voltage range may be determined based on previously determined voltage levels. For example, the operating voltage range may be defined as the voltage level of the operating voltage initially output by the regulator to the voltage level of the operating voltage when the operating state change is detected.

[0065] Embodiments of the present disclosure may provide benefits such as detecting manufacturing defects and / or estimating the durability of a regulator. For example, to identify defective regulators, regulators may be tested at the manufacturing level (e.g., before the regulators are available to customers) to determine which regulators provide relatively low levels of operating voltage (which indicates a defect). In another example, by determining the operating voltage level that places the corresponding component in a brownout state, it is possible to estimate the time it will take for the operating voltage level to eventually drop below a specific level (e.g., how many years it will take before the voltage is brownout due to aging of the regulator), as this will decrease as the regulator ages.

[0066] Figure 4 An example machine illustrating a computer system 400 within which a set of instructions for causing the machine to perform any one or more of the methodologies discussed herein may be executed. In some embodiments, the computer system 400 may correspond to a host system (e.g., Figure 1 102) that includes, is coupled to, or utilizes a memory subsystem (e.g., Figure 1 In some embodiments, the machine may be connected (e.g., via a network) to other machines in a LAN, an intranet, an extranet, and / or the Internet. The machine may operate in the capacity of a server or a client user machine in a client-server network environment, as a peer in a peer-to-peer (or distributed) network environment, or as a server or a client user machine in a cloud computing infrastructure or environment.

[0067] The machine may be a personal computer (PC), a tablet PC, a set-top box (STB), a personal digital assistant (PDA), a cellular phone, a network appliance, a server, a network router, a switch or a bridge, or any machine capable of executing a set of instructions (sequential or otherwise) that specify actions to be performed by the machine. Further, while a single machine is illustrated, the term "machine" shall also be taken to include any collection of machines that individually or collectively execute a set (or multiple sets) of instructions to perform any one or more of the methodologies discussed herein.

[0068] The example computer system 400 includes a processing device 463, a main memory 465, a static memory 467, and a data storage system 478 that communicate with each other via a bus 491. In some embodiments, the main memory 465 can be read-only memory (ROM), flash memory, dynamic random access memory (DRAM) (such as synchronous DRAM (SDRAM) or Rambus DRAM (RDRAM)), and other possibilities. In some embodiments, the static memory 467 can be flash memory, static random access memory (SRAM), and other possibilities. The data storage system 478 can correspond to Figure 1Memory subsystem 104.

[0069] The processing device 463 represents one or more general-purpose processing devices, such as a microprocessor, a central processing unit, or the like. More specifically, the processing device may be a complex instruction set computing (CISC) microprocessor, a reduced instruction set computing (RISC) microprocessor, a very long instruction word (VLIW) microprocessor, or a processor that implements other instruction sets or a combination of instruction sets. The processing device 463 may also be one or more special-purpose processing devices, such as an application-specific integrated circuit (ASIC), a field-programmable gate array (FPGA), a digital signal processor (DSP), a network processor, or the like. The processing device 463 is configured to execute instructions 487 for performing the operations and steps discussed herein. The computer system 400 may further include a network interface device 468 for communicating over a network 480.

[0070] The data storage system 478 may include a machine-readable storage medium 484 (also referred to as a computer-readable medium) on which one or more sets of instructions 487 or software embodying any one or more of the methodologies or functions described herein are stored. The instructions 487 may also reside, in whole or in part, within the main memory 465 and / or the processing device 463 during execution by the computer system 400, with the main memory 465 and the processing device 463 also constituting machine-readable storage media. The machine-readable storage medium 484, the data storage system 478, and / or the main memory 465 may correspond to Figure 1 Memory subsystem 104.

[0071] In one embodiment, instructions 487 include instructions for implementing functionality corresponding to power monitoring 462, threshold adjustment 464, and voltage determination 466, which correspond to Figure 1 and the power monitoring circuitry 107 and / or 111, the threshold adjustment component 222, and the voltage determination component 105 and / or 223 of FIG. 2 . Although the machine-readable storage medium 484 is shown as a single medium in the example embodiment, the term "machine-readable storage medium" should be understood to include a single medium or multiple media that store one or more sets of instructions. The term "machine-readable storage medium" should also be understood to include any medium capable of storing or encoding a set of instructions for execution by a machine and causing the machine to perform any one or more of the methods of the present disclosure. Thus, the term "machine-readable storage medium" should be understood to include, but not be limited to, solid-state memory, optical media, and magnetic media.

[0072] As used herein, "a," "an," or "several" may refer to one or more things, and "plurality" may refer to one or more such things. For example, a memory device may refer to one or more memory devices, and a plurality of memory devices may refer to two or more memory devices. Additionally, as used herein, particularly with respect to reference numerals in the drawings, the designator "N" indicates that a number of the particular feature so designated may be included in several embodiments of the present disclosure.

[0073] The figures herein follow a numbering convention in which the first digit or digits correspond to the figure number and the remaining digits identify the element or component in the figure. Similar elements or components between different figures may be identified by using similar digits. For example, 111 in Figure 1 2 may refer to element “ 11 ” and similar elements are referred to as 211 in FIG. 2 .

[0074] Some portions of the foregoing detailed description have been presented in terms of algorithms and symbolic representations of operations on data bits within a computer memory. These algorithmic descriptions and representations are the means used by those skilled in the data processing arts to most effectively convey the substance of their work to others skilled in the art. An algorithm is here, and generally, conceived to be a self-consistent sequence of operations leading to a desired result. The operations are those requiring physical manipulations of physical quantities. Typically, but not necessarily, these quantities take the form of electrical or magnetic signals capable of being stored, combined, compared, and otherwise manipulated. It has proven convenient at times, primarily for reasons of common usage, to refer to these signals as bits, values, elements, symbols, characters, terms, numbers, or the like.

[0075] It should be borne in mind, however, that all of these and similar terms are to be associated with the appropriate physical quantities and are merely convenient labels applied to these quantities. The present disclosure may involve the actions and processes of computer systems or similar electronic computing devices that manipulate and transform data represented as physical (electronic) quantities within the computer system's registers and memories into other data similarly represented as physical quantities within the computer system's memories or registers or other such information storage systems.

[0076] The present disclosure also relates to an apparatus for performing the operations described herein. This apparatus may be specially constructed for the intended purpose, or it may comprise a general-purpose computer selectively activated or reconfigured by a computer program stored in the computer. This computer program may be stored on a computer-readable storage medium, such as, but not limited to, any type of magnetic disk, including floppy disks, optical disks, CD-ROMs and magneto-optical disks, read-only memory (ROM), random access memory (RAM), EPROM, EEPROM, magnetic or optical cards, or any type of medium suitable for storing electronic instructions, each coupled to a computer system bus.

[0077] The algorithms and displays presented herein are not inherently related to any particular computer or other device. Various general-purpose systems may be used with programs according to the teachings herein, or it may prove convenient to construct more specialized equipment to perform the methods. The structures of a variety of these systems will appear as set forth in the description below. Additionally, the present disclosure is not described with reference to any particular programming language. It will be appreciated that a variety of programming languages ​​may be used to implement the teachings of the present disclosure as described herein.

[0078] The present disclosure may be provided as a computer program product or software, which may include a machine-readable medium having stored thereon instructions that can be used to program a computer system (or other electronic device) to perform a program according to the present disclosure. A machine-readable medium includes any mechanism for storing information in a form readable by a machine (e.g., a computer). In some embodiments, a machine-readable (e.g., computer-readable) medium includes a machine (e.g., computer) readable storage medium, such as a read-only memory ("ROM"), a random access memory ("RAM"), a magnetic disk storage medium, an optical storage medium, a flash memory component, or the like.

[0079] In the foregoing specification, embodiments of the present disclosure have been described with reference to specific example embodiments thereof. It will be apparent that various modifications may be made thereto without departing from the broader spirit and scope of the embodiments of the present disclosure as set forth in the appended claims. Accordingly, the specification and drawings are to be regarded in an illustrative rather than a restrictive sense.

Claims

1. A memory subsystem (104) for regulator voltage level measurement, comprising: Power management component (108; 208 ), which includes a plurality of regulators ( 112 - 1 , . . . , 112 -M; 212-1, ..., 212-N), the plurality of regulators being configured to supply respective operating voltages to components of the memory subsystem; The power management component is configured to: adjusting a regulator voltage level provided to a specific component (118-1, ..., 118-N) to a plurality of different voltage levels in an incremental or decremental manner until a change in an operating state of the specific component is detected; and A value of the regulator voltage level when the change in the operating state of the particular component is detected is determined based on a comparison of the plurality of different voltage levels with a first threshold voltage level and a second threshold voltage level. 2 . The memory subsystem of claim 1 , wherein the change in the operating state of the particular component comprises a change from a first state to an undervoltage state.

3. The memory subsystem of claim 1 , wherein the power management component is configured to determine the value of the regulator voltage level upon detecting the change in the operating state of the particular component by using at least one of: a comparator (225-1, ..., 225-N) within the power management component, the comparator having a programmable threshold level; or An analog-to-digital converter (230) is internal to the power management component.

4. The memory subsystem of claim 3 , wherein the power management component is further configured to determine the value of the regulator voltage level when the change in the operating state of the particular component is detected by adjusting the programmable threshold level of the comparator in specific increments.

5. The memory subsystem of claim 1, wherein the power management component is configured to detect the operating state change by monitoring a state of a power state signal of the particular component.

6. The memory subsystem of claim 1, wherein the power management component is configured to detect the operating state change by detecting a communication failure of the particular component.

7. The memory subsystem of claim 6 , wherein the power management component is coupled to a controller (106) configured to control a number of specific components (118-1, ..., 118-N), wherein the specific component is one of the number of memory components, and the controller is configured to detect the communication failure of the specific component.

8. The memory subsystem of any one of claims 1 to 7, wherein the power management component is further configured to determine an operating voltage range for the particular component based on the value of the regulator voltage level when a change in the operating state of the particular component is detected.

9. The memory subsystem of any one of claims 1 to 7, wherein the power management component is further configured to determine the value of the regulator voltage level when the change in the operating state of the particular component is detected via a test circuit external to the memory subsystem without directly probing the regulator voltage level provided to the particular component.

10. The memory subsystem of any one of claims 1 to 7, wherein the memory subsystem comprises a solid-state drive (SSD), and wherein the power management component comprises a power management integrated circuit (PMIC).

11. A method for regulator voltage level measurement, comprising: via a regulator (112-1, ..., 112-M; 112-M) of a power management component (108; 208) of a memory subsystem (104); 212-1, ..., 212-N) providing operating voltages from the power management component to specific components (118-1, ..., 118-N) of the memory subsystem; adjusting a voltage level of the operating voltage output by the regulator to a plurality of different voltage levels in an incremental manner or in a decremental manner until a change in the operating state of the specific component due to the adjustment of the voltage level is detected; and The voltage level of the operating voltage when the change in the operating state of the specific component is detected is determined based on a comparison of the plurality of different voltage levels with a first threshold voltage level and a second threshold voltage level.

12. The method of claim 11, further comprising determining, via circuitry within the power management component, the voltage level of the operating voltage upon detecting the change in the operating state of the particular component.

13. The method of claim 11, further comprising adjusting the voltage level of the operating voltage output by the regulator via pulse width modulation.

14. The method of claim 11, wherein the operating state change comprises a change from a first state to a brownout state, and wherein the method includes adjusting the voltage level of the operating voltage output by the regulator until the particular component reaches the brownout state.

15. The method of any one of claims 11 to 14, wherein adjusting the voltage level of the operating voltage output by the regulator comprises: reducing the voltage level of the operating voltage output by the regulator from a first voltage level until a first operating state change is detected; and The voltage level of the operating voltage output by the regulator is increased to a voltage level higher than the first voltage level until a second operating state change is detected.

16. The method according to any one of claims 11 to 14, further comprising determining an operating voltage range of the specific component based on a voltage level of the operating voltage initially output by the regulator and the voltage level of the operating voltage when the operating state change of the specific component is detected.

17. A power management component (108; 208), which includes: a plurality of regulators (112-1, ..., 112-M; 212-1, ..., 212-N) configured to supply respective operating voltages to components of the memory subsystem (104); Feedback circuitry (109) coupled to the plurality of regulators and control components (110; 210), the feedback circuitry being configured to: comparing a voltage level of a regulator output voltage provided to a particular component (118-1, ..., 118-N) to a first threshold voltage level; and providing a feedback signal (227-1, ..., 227-N) indicative of a result of the comparison to the control component; and wherein the control component is configured to: adjusting the voltage level of the regulator output voltage to a plurality of different voltage levels in an incremental manner or a decremental manner, such that the first threshold voltage level is compared with the plurality of different voltage levels of the regulator output voltage until a change in the operating state of the particular component is detected; adjusting the first threshold voltage level to a second threshold voltage level after detecting the change in the operating state; adjusting the voltage level of the regulator output voltage to the plurality of different voltage levels in an incremental manner or a decremental manner such that the second threshold voltage level is compared with the plurality of different voltage levels of the regulator output voltage until the change in the operating state of the specific component is detected; and An operating voltage level at which the operating state change of the specific component is detected is determined based on the first threshold voltage level and the second threshold voltage level.

18. The power management component of claim 17, wherein the control component is configured to determine the operating voltage level using interpolation based on the first threshold voltage level and the second threshold voltage level.

19. The power management component according to any one of claims 17 to 18, wherein: a first feedback signal (227-1, ..., 227-N) indicative of a result of the comparison between the first threshold voltage level and a particular one of the plurality of different voltage levels of the regulator output voltage comprising a signal having a first state; and A second feedback signal (227-1, ..., 227-N) indicative of the result of the comparison between the second threshold voltage level and the particular one of the plurality of different voltage levels of the regulator output voltage comprises a signal having a second state.

20. The power management assembly of claim 19, wherein: The first state indicates that the first threshold voltage level is greater than the particular one of the plurality of different voltage levels of the regulator output voltage; and The second state indicates that the second threshold voltage level is less than the particular one of the plurality of different voltage levels of the regulator output voltage.

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