Hermetic packaging for power semiconductors

Abstract

The present invention discloses an airtight high current electronic package, which includes a package body and a substrate airtightly coupled to the package body. A semiconductor device is thermally mounted to the substrate and has a high current output. A high current input / output (I / O) terminal is bonded to the high current output of the semiconductor device by a strip terminal as an integral high current heat sink terminal. The high current I / O terminal passes through a hole formed in the side wall of the package body. A ceramic seal surrounds the high current I / O terminal and has a first surface airtightly bonded to the outer surface of the side wall of the package body. A metal airtight sealing gasket surrounds the high current I / O terminal and is bonded to the second surface of the ceramic seal, and is bonded to a portion of the high current I / O terminal that passes through the metal airtight sealing gasket.

Description

Background Art

[0001] At present, there are packages for power semiconductors. Unfortunately, such packages are not designed for high-power applications. Many existing high-power devices are relatively large and heavy and are not easy to attach to radiators. Certain applications (such as space program power components) require high current capacity and must be hermetically sealed. Existing packages are also fragile to a certain extent, allowing the seal around the component to cause fracture, thereby compromising the hermetic seal of the package. Many existing power systems are too heavy, too large or too inefficient to meet future space mission requirements, and some power systems cannot operate in extreme environments.

[0002] Current space-qualified metal oxide semiconductor field effect transistors (MOSFETs), diodes, and capacitors are only capable of operating at -55°C to +150°C, at up to 180V, and are built into channels with a capacity of <10kW, with multiple MOSFET transistors per channel. Such components are not certified for the high temperatures (300°C) required to minimize the mass of heat rejection heat sinks that deep space science and human exploration missions will encounter.

[0003] Both science and human exploration missions require radiation-hardened, extreme temperature components and interconnects. The drive capabilities specified for NASA missions are centered around extreme temperature, radiation-hardened, high voltage (1,200V) components. Electric propulsion applications require a significant increase in voltage tolerance (to >1,200V).

[0004] Therefore, improvements are needed for applications such as NASA's deep space missions involving electric propulsion. The current operating temperature range (i.e. -55°C to +150°C) is so narrow that extensive thermal management is required, increasing the power and specific mass of the propulsion system. High voltage capacity is required to manage the current of high power electric thrusters. The deep space radiation environment will rapidly degrade current components.

[0005] Among the requirements for semiconductor packages suitable for environments such as space are high current handling capability of hundreds of amperes, hermetic seals that meet JANS (MIL-PRF-19500) grade requirements, low inductance, low impedance, high thermal conductivity, high flexibility in heat sink capabilities (including multiple points of thermally conductive contact), high isolation voltage capability for space applications (high altitude and near perfect vacuum environment), lightweight relative to standard commercial copper-based packages, ability to meet JANS space-grade HiRel screening and long-term reliability testing, ability to support electronic devices in high radiation / harsh environments, physical durability to withstand the harsh conditions experienced in launch vehicles, and scalability and size flexibility to accommodate different electronic technology devices (such as silicon, silicon carbide and gallium nitride), but not limited to these.

[0006] Figure 1 A top cross-sectional view of a current high power semiconductor package with a hermetic seal used in a typical JANS space-grade package is shown. Figure 2 It is intercepted by line 2-2 Figure 1 an enlarged side cross-sectional view of a portion of a prior art semiconductor package, and Figure 3 yes Figure 2 An enlarged side cross-sectional view of a portion of a prior art semiconductor package illustrating a typical hermetic seal failure mode. Figures 1 to 3 The design type shown is limited by the size of the high current leads (typically 0.060" maximum diameter) and the lead material (typically copper core Its electrical resistivity is about 10-15 times higher than that of copper).

[0007] Figure 1 Package body 10, shown in cross-section in FIG. 1 , is formed of a material such as Kovar, Alloy 42, Alloy 46, or Alloy 52. ​​Metallized substrate 12 is thermally and mechanically bonded to the inner surface of base plate 14, which is formed of a material such as copper-tungsten alloy, molybdenum, Cu / Mo / Cu composite material, or AlSiC and brazed to package body 10. Semiconductor die 16 is thermally bonded to the inner surface of metallized substrate 12. Figures 1 to 3 In the case of the power MOSFET shown, semiconductor die 16 has its drain connection on the bottom side of semiconductor die 16, which is electrically connected to metallized substrate 12. Bond wire 18 is connected between bond pad 20 on die 16 and high current I / O drain terminal 22. The source of the MOSFET is connected to a first end of bond wire 26 at bond pad 24, and a second end of bond wire 26 is connected to high current I / O source terminal 28. The gate of the MOSFET at bond pad 30 on die 16 is connected to a first end of bond wire 32, and a second end of bond wire 32 is connected to I / O gate terminal 34.

[0008] Each of the high current I / O terminals 22 and 28 and the gate terminal 34 communicates with the outside of the package body 10 through a ceramic hermetic seal 36 formed in a hole in the package body 10. The hole in which the high current I / O source terminal 28 is disposed is Figure 2 The cover 40 is identified by reference numeral 38. The cover 40 is seam welded to the package body 10 to hermetically seal the package body.

[0009] Figure 1 and Figure 2The depicted design is a rigid design, and the ceramic hermetic seal 36 is susceptible to cracking during high stress and / or high temperature cycling conditions and other harsh environments typically experienced in space applications. The loss of hermeticity through typical ceramic cracking modes is caused by the mismatch of the coefficient of thermal expansion (CTE) with the package sidewalls. Mechanical stresses (depicted by arrows 42) that may be applied between the sidewalls of the package body 10 and the high current drain and source I / O terminals 22 and 28 and the I / O gate terminal 34 are easily transferred to the ceramic sealing material 36, causing it to crack, thereby causing, for example, Figure 3 The airtight failure depicted in the figure is Figure 2 An enlarged side cross-sectional view of a prior art semiconductor package illustrating a typical hermetic seal failure mode. Summary of the invention

[0010] According to the present invention, a semiconductor package has a thin profile, low mass, and is designed to accommodate a high-power semiconductor device. According to one aspect of the present invention, a semiconductor package has a capability of supplying 200A.

[0011] The semiconductor package has multiple levels of cooling points including the internal terminals of the enclosed semiconductor device and the package base. This aspect of the invention is particularly useful when the device is deployed in space since all cooling is accomplished by conduction.

[0012] According to one aspect of the present invention, a hermetic electronic package is formed in a package body. A substrate is hermetically coupled to a first end of the package body. A cover is seam welded to the package body at a second end opposite to the first end to form a hermetic seal with the package body. The substrate is thermally coupled to the substrate and has a plurality of metallized regions. The semiconductor device is electrically mounted to the substrate and has a first high current input / output terminal and a second high current terminal. The first high current terminal is electrically bonded to a first metallized region on the substrate, and the second high current terminal is electrically bonded to a second metallized region on the substrate through a plurality of bonding wires. The first high current input / output (I / O) terminal passes through a hole formed in a side wall of the package body and is electrically bonded to the first metallized region on the substrate through a first strip terminal as an integral high current heat sink terminal. The second high current input / output (I / O) terminal passes through a hole formed in a side wall of the package body and is electrically bonded to the second metallized region on the substrate through a first strip terminal as an integral high current heat sink terminal. Each of the first high current I / O terminal and the second high current I / O terminal is surrounded by a ceramic seal having a first surface and a second surface, the first surface being hermetically bonded to an outer surface of a side wall of the package body, and surrounded by a metal hermetic sealing gasket hermetically bonded to the second surface of each ceramic seal and hermetically bonded to the high current I / O terminal it surrounds.

[0013] According to one aspect of the present invention, the package body is formed of one of Kovar, Alloy 42, Alloy 46, and Alloy 52.

[0014] According to one aspect of the present invention, the ceramic seal is formed of one of aluminum oxide and silicon nitride.

[0015] According to one aspect of the invention, a CuAg braze is used to braze the ceramic seal to the package sidewall.

[0016] According to one aspect of the present invention, the high current I / O terminal is formed of one of copper, copper zirconium, and beryllium copper (BeCu).

[0017] According to one aspect of the invention, the high current I / O terminals are used as integral heat sink terminals.

[0018] According to one aspect of the present invention, the metal hermetic sealing gasket is formed of one of Kovar, Alloy 42, Alloy 46, and Alloy 52.

[0019] According to one aspect of the present invention, a metal hermetic sealing gasket is hermetically bonded to the second surface of the ceramic seal and a portion of the high current I / O terminal and the gate I / O terminal using a CuAg braze.

[0020] According to one aspect of the present invention, a hermetic electronic package is formed in a package body. A substrate is hermetically coupled to a first end of the package body. A cover seam is welded to the package body to form a hermetic seal with the package body. A substrate having a first metallization region, a second metallization region, and a third metallization region is thermally coupled to the substrate. A MOSFET semiconductor device has a drain, a source, and a gate, the drain being electrically and thermally mounted to a first metallization region on the substrate, the source being electrically bonded to a second metallization region on the substrate by a plurality of bonding wires, and the gate being bonded to a third metallization region on the substrate by at least one bonding wire. A high current input / output (I / O) terminal is electrically bonded to the first metallization region on the substrate by a first strip terminal as an integral high current heat sink terminal, and passes through a first hole formed in a side wall of the package body. A source high current I / O terminal is electrically bonded to a second metallization region on the substrate by a second strip terminal as an integral high current heat sink terminal, and the source high current I / O terminal passes through a second hole formed in a side wall of the package body. A gate I / O terminal is electrically bonded to a third metallization region on the substrate by a gate bonding wire. Each of the first high current I / O terminal and the second high current I / O terminal and the gate I / O terminal is surrounded by a ceramic seal having a first surface and a second surface, the first surface being hermetically bonded to an outer surface of a side wall of the package body, and is surrounded by a metal hermetic sealing gasket hermetically bonded to the second surface of each ceramic seal and hermetically bonded to the high current I / O terminal it surrounds.

[0021] According to one aspect of the present invention, a method for manufacturing an airtight electronic package includes: providing a package body; airtightly coupling a package substrate to the package body; thermally coupling a substrate to the substrate, the substrate having first, second, and third metallization areas; thermally mounting a semiconductor device to the substrate, the semiconductor device having at least one high current output electrically bonded to the first metallization area of ​​the substrate; bonding at least one high current input / output (I / O) terminal to the first metallization area of ​​the substrate through a strip terminal as an integral high current heat sink terminal, the at least one high current I / O terminal passing through a hole formed in a side wall of the package body; airtightly bonding a ceramic seal surrounding the at least one high current I / O terminal to an outer surface of the side wall of the package body; airtightly bonding a metal airtight sealing gasket surrounding the at least one high current I / O terminal to the ceramic seal and to a portion of the at least one high current I / O terminal passing through the metal airtight sealing gasket; and seam welding a cover to the package body at a second end opposite to the first end to form an airtight seal with the package body.

[0022] According to one aspect of the invention, hermetically bonding the ceramic seal surrounding the at least one high current I / O terminal to the outer surface of the sidewall of the package body comprises brazing an inner surface of the ceramic seal to the outer surface of the sidewall of the package body.

[0023] According to one aspect of the present invention, the metal hermetic sealing gasket surrounding the at least one high current I / O terminal is hermetically bonded to the outer surface of the ceramic seal and to the portion of the at least one high current I / O terminal passing through the metal hermetic sealing gasket, including brazing the metal hermetic sealing gasket to the outer surface of the ceramic seal and to the portion of the at least one high current I / O terminal passing through the metal hermetic sealing gasket. The semiconductor device is thermally mounted to the substrate and has a high current output. The high current input / output (I / O) terminal is bonded to the high current output of the semiconductor device by a conductive tape as an integral high current heat sink terminal. The high current I / O terminal passes through a hole formed in the side wall of the package body. The ceramic seal surrounds the high current I / O terminal and has a first surface that is hermetically bonded to the outer surface of the side wall of the package body. The metal hermetic sealing gasket surrounds the high current I / O terminal and is bonded to the second surface of the ceramic seal, and is bonded to a portion of the high current I / O terminal passing through the metal hermetic sealing gasket.

[0024] According to one aspect of the present invention, the hermetic electronic package further comprises a cover seam welded to the package body to hermetically seal it.

[0025] According to one aspect of the present invention, the package body is formed of one of Kovar, Alloy 42, Alloy 46, and Alloy 52.

[0026] According to one aspect of the present invention, the ceramic seal is formed of one of aluminum oxide and silicon nitride.

[0027] According to one aspect of the invention, a CuAg braze is used to braze the ceramic seal to the package sidewall.

[0028] According to one aspect of the present invention, the high current I / O terminal is formed of one of copper, copper zirconium, and beryllium copper (BeCu).

[0029] According to one aspect of the invention, the high current I / O terminals are used as integral heat sink terminals.

[0030] According to one aspect of the present invention, the metal hermetic sealing gasket is formed of one of Kovar, Alloy 42, Alloy 46, and Alloy 52.

[0031] According to one aspect of the present invention, a CuAg braze is used to hermetically bond a metal hermetic sealing gasket to the second surface of the ceramic seal and a portion of the at least one high current I / O terminal that passes through the metal hermetic sealing gasket. BRIEF DESCRIPTION OF THE DRAWINGS

[0032] The invention will be explained in more detail below with reference to embodiments and the accompanying drawings, in which:

[0033] Figure 1 is a top cross-sectional view of a representative prior art semiconductor package;

[0034] Figure 2 is through Figure 1 The line 2-2 is intercepted Figure 1 An enlarged side cross-sectional view of a portion of a prior art semiconductor package;

[0035] Figure 3 yes Figure 2 An enlarged side cross-sectional view of a prior art semiconductor package illustrating a typical hermetic seal failure mode;

[0036] Figure 4 is a top cross-sectional view of a representative semiconductor package according to the present invention;

[0037] Figure 5 is through Figure 4 The line 5-5 is intercepted Figure 4 an enlarged side cross-sectional view of a portion of a semiconductor package;

[0038] Figure 6is a flow chart showing a method for manufacturing a semiconductor package of the present invention according to one aspect of the present invention; and

[0039] Figure 7 is a flow chart illustrating an illustrative method for soldering a hermetic seal to an outer wall of a package body and I / O terminals. DETAILED DESCRIPTION

[0040] Those skilled in the art will recognize that the following description is illustrative only and not limiting in any way. Other embodiments will be readily apparent to those skilled in the art.

[0041] See also Figure 4 and Figure 5 , a top cross-sectional view shows a representative semiconductor package 50 according to the present invention, and an enlarged side cross-sectional view shows Figure 4 The line 5-5 is intercepted Figure 4 part of a semiconductor package. Figure 4 and Figure 5 The semiconductor package 50 includes Figure 1 and Figure 2 Some of the same components of the prior art semiconductor package depicted. These components will be Figure 4 and Figure 5 Used for identification Figure 1 and Figure 2 The same reference numerals are used to identify corresponding elements in the drawings.

[0042] Figure 4 and Figure 5 The semiconductor package 50 includes Figure 4 , which is formed of a material such as Kovar, Alloy 42, Alloy 46, or Alloy 52. ​​The metallized substrate 12 is thermally and mechanically bonded by pre-welding it to the inner surface of a substrate 14, which is formed of a material such as copper tungsten alloy, molybdenum, Cu / Mo / Cu composite material, or AlSiC, and the substrate 14 is brazed to the package body 10 to hermetically bond and seal it to the substrate. Figure 4 and Figure 5 In the case of the power MOSFET shown, semiconductor die 16 has its drain connection on the bottom side of the die, which is electrically connected to metallized substrate 12 by soldering its preform to metallized substrate 12. In one illustrative, non-limiting embodiment of the invention, 95Pb / 5In solder may be employed.

[0043] In the case where the MOSFET device formed on the semiconductor die 16 is to be placed in the package 12, the metallization on the metallized substrate 12 is formed into three conductive regions 52, 54 and 56, which serve as connection locations for the source terminal, the drain terminal and the gate terminal of the MOSFET device formed on the semiconductor die 16, respectively. The drain of the MOSFET device is electrically connected to the bottom side of the semiconductor die 16, which is bonded to the conductive region 54 of the metallized substrate 12 to provide both electrical and thermal connections between the semiconductor die 16 and the metallized substrate 12. The source of the MOSFET device is electrically connected to the top side of the semiconductor die 16 and is electrically connected to the conductive region 52 of the metallized substrate 12 by a plurality of bond lines (indicated by the oval dashed lines 58), which are stitched between the conductive region 52 of the metallized substrate 12 and the source connection point on the top side of the semiconductor die 16 to provide the current carrying capacity required of the high power MOSFET device formed on the semiconductor die 16.

[0044] The gate of the MOSFET device is a geometrically distributed gate as is known in the art, and is shown connected to a conductive region 56 of the metallized substrate 12 by a bond wire (indicated by an oval dashed line 60).

[0045] The source and drain connections from the conductive regions 52 and 54 of the metallized substrate 12 are connected to the high current I / O terminals 22 and 28, respectively, through the strap terminal conductors 62 and 64. The strap terminal conductors 62 and 64 also serve as thermal conductors that provide integral high current heat sink terminals to help transfer heat from the high power MOSFET device to the exterior of the package 50 and may be formed of materials such as copper, or copper zirconium and beryllium copper (BeCu).

[0046] Conductive region 56 of metallized substrate 12 is connected to gate I / O terminal 66 via bond wire 68. Kelvin sense line 70 is connected to Kelvin current sense I / O terminal 72.

[0047] Each of the high current I / O terminals 22 and 28 and the gate and Kelvin current sense I / O terminals 66 and 72 communicates with the outside of the package body 10 through a hermetic seal 74 bonded to the outer wall of the package body 10. The hole in which the high current I / O terminal 22 is provided is Figure 4 and Figure 5 The hole in which the high current I / O terminal 28 is disposed is identified by the reference numeral 38a. Figure 4 The hole in which the gate and Kelvin current sensing I / O terminals 66 and 72 are located is marked by the reference numeral 38b. Figure 4 They are identified by reference numerals 38c and 38d, respectively. Figure 5The lid 40 is shown seam welded to the package body 10 to bond and hermetically seal it to the package body 10 .

[0048] The hermetic seal 74 through which the high current I / O terminals 22 and 28 and the gate and Kelvin current sensing I / O terminals 66 and 72 pass is designed to match the high coefficient of thermal expansion (CTE) of the I / O terminals and the internal terminals with the CTE of the package body 10, and is a multi-part structure. The ceramic seal 76 forming a part of the hermetic seal 74 through which the terminals 22, 28, 66 and 72 pass is formed of a material such as alumina or silicon nitride, and the first surface of the ceramic seal 76 is each attached to the outer wall of the package body 10 by a hermetic sealing joint in the form of a high temperature brazing member 78 of a material such as CuAg. A metal hermetic sealing gasket 80 formed of a material such as Kovar, alloy 60, alloy 46 or alloy 52 is attached to the second surface of the ceramic seal 76 and to the I / O terminals passing therethrough by a hermetic sealing joint 82 in the form of a high temperature brazing member of a material such as CuAg. Due to the smaller diameters of the I / O terminals 66 and 72 , the greatest thermal stress occurs in the high temperature braze 78 between the ceramic seal 76 and the outer wall of the package body 10 in the smaller I / O terminals 66 and 72 .

[0049] In one example of the present invention, where the high current I / O terminals 22 and 28 are formed to have a diameter of 0.125″, the ceramic seal 76 may have a diameter of approximately 0.380″ and a thickness of approximately 0.050″, the thickness of the high temperature brazing joint 78 may be approximately 0.010″, and the metal hermetic sealing gasket 80 may have a diameter of approximately 0.250″ and a thickness of approximately 0.020″. In one example of the present invention, where the signal I / O terminals 22 and 28 are formed to have a diameter of 0.040″, the ceramic seal 76 may have a diameter of approximately 0.200″ and a thickness of approximately 0.050″, the thickness of the high temperature brazing joint 78 may be approximately 0.010″, and the metal hermetic sealing gasket 80 may have a diameter of approximately 0.150″ and a thickness of approximately 021″.

[0050] See now Figure 6 , a flow chart shows an exemplary method 90 for manufacturing a semiconductor package of the present invention according to one aspect of the present invention. The method starts at reference numeral 92 .

[0051] At 94, the substrate is brazed to the package body. At 96, the various I / O terminals are positioned in their respective holes in the wall of the package body. At 98, the hermetic seal is brazed to the outer wall of the package body and to the I / O terminals. All of the above processes can be performed at a package manufacturing facility.

[0052] At reference numeral 100, a metallized substrate is bonded to a package substrate by a process such as preform soldering. At reference numeral 102, a semiconductor die is bonded to a metallized substrate by a process such as preform soldering.

[0053] At reference numeral 104, the top bond wires are bonded to the connection pads on the top surface of the semiconductor die and to the corresponding areas of the metallized substrate. At reference numeral 106, the I / O terminals are bonded to the metallized substrate. At reference numeral 108, the lid seam is welded to the package body to hermetically seal the package. The method ends at reference numeral 110.

[0054] See now Figure 7 , the flowchart shows the Figure 6 1. A schematic method 120 of the process shown at reference numeral 98 of the present invention. The method begins at reference numeral 122. At reference numeral 124, a ceramic seal is positioned around the I / O terminals. At reference numeral 126, the ceramic seal is brazed to the outer wall of the package body. At reference numeral 128, a metal hermetic sealing gasket is positioned above the ceramic seal and around the I / O terminals. At reference numeral 130, a metal hermetic sealing gasket is brazed to the I / O terminals and the ceramic seal. The method ends at reference numeral 132.

[0055] Although the embodiments and applications of the present invention have been shown and described, it will be apparent to those skilled in the art that more modifications than those described above may be made without departing from the inventive concept herein. Therefore, the present invention is not to be restricted except in the spirit of the appended claims.

Claims

1. A hermetic electronic package comprising: Encapsulation body; a packaging substrate, the packaging substrate being hermetically coupled to the first end of the packaging body; a cover seam welded to the package body at a second end opposite the first end to form an airtight seal with the package body; a substrate thermally coupled to the package substrate, the substrate having a plurality of metallization regions; a semiconductor device electrically mounted to the substrate, the semiconductor device having a first high current terminal electrically bonded to a first metallization region on the substrate and a second high current terminal electrically bonded to a second metallization region on the substrate via a plurality of bond wires; a first high current I / O terminal electrically bonded to the first metallization region on the substrate via a first strap terminal as an integral high current heat sink terminal, the first high current I / O terminal passing through a first hole formed in the package body; a second high current I / O terminal electrically bonded to the second metallization region on the substrate via a second strap terminal as an integral high current heat sink terminal, the second high current I / O terminal passing through a second hole formed in the package body; Each of the first high current I / O terminal and the second high current I / O terminal is surrounded by a corresponding ceramic seal having a first surface and a second surface, wherein the first surface is hermetically bonded to the outer surface of the package body, and the second surface is hermetically bonded to a corresponding hermetic sealing gasket and the high current I / O terminal surrounded by it. 2 . The hermetic electronic package of claim 1 , wherein the ceramic seal is formed from one of aluminum oxide and silicon nitride.

3. The hermetic electronic package of claim 1, wherein the ceramic seal is brazed to the package body using a CuAg braze. 4 . The hermetic electronic package of claim 1 , wherein the first high current I / O terminal and the second high current I / O terminal are formed of one of copper, copper zirconium, and beryllium copper (BeCu).

5. The hermetic electronic package of claim 1, wherein the first high current I / O terminal and the second high current I / O terminal function as integral heat sink terminals. 6 . The hermetic electronic package of claim 1 , wherein the metal hermetic sealing gasket is formed from one of Kovar, Alloy 42, Alloy 46, and Alloy 52.

7. The hermetic electronic package of claim 1, wherein the metal hermetic sealing gaskets are each hermetically bonded to the second surface of the respective ceramic seal and a portion of the high current I / O terminal therearound using a CuAg braze.

8. A hermetic electronic package comprising: Encapsulation body; a packaging substrate, the packaging substrate being hermetically coupled to the first end of the packaging body; a cover seam welded to the package body at a second end opposite the first end to form an airtight seal with the package body; a substrate thermally coupled to the package substrate, the substrate having a first metallization region, a second metallization region, and a third metallization region; a MOSFET semiconductor device having a drain terminal, a source terminal, and a gate terminal, the drain terminal being electrically and thermally mounted to the first metallization region on the substrate, the source terminal being electrically bonded to the second metallization region on the substrate by a plurality of first bond wires, and the gate terminal being bonded to the third metallization region on the substrate by at least one second bond wire; a drain high current input / output (I / O) terminal electrically bonded to the first metallization region by a first strap terminal as an integral high current heat sink terminal, the drain high current I / O terminal passing through a first aperture formed in the package body; a source high current I / O terminal electrically bonded to the second metallization region via a second strap terminal as an integral high current heat sink terminal, the source high current I / O terminal passing through a second hole formed in the package body; as well as a gate I / O terminal electrically bonded to the third metallization region on the substrate via a gate bonding wire, Each of the drain high current I / O terminal, the source high current I / O terminal and the gate I / O terminal is surrounded by a corresponding ceramic seal and a corresponding metal airtight sealing gasket, a first surface of each ceramic seal is airtightly bonded to the outer surface of the package body, and a second surface of each ceramic seal is airtightly bonded to the corresponding metal airtight sealing gasket, and each metal airtight sealing gasket is airtightly bonded to the one of the drain high current I / O terminal, the source high current I / O terminal and the gate I / O terminal that it surrounds. 9 . The hermetic electronic package of claim 1 , wherein the package body is formed from one of Kovar, Alloy 42, Alloy 46, and Alloy 52.

10. The hermetic electronic package of claim 8, wherein the ceramic seal is formed of one of aluminum oxide and silicon nitride, and is brazed to the package body using a CuAg braze.

11. The hermetic electronic package of claim 8, wherein the drain high current I / O terminal and the source high current I / O terminal are formed of one of copper, copper zirconium, and beryllium copper (BeCu). 12 . The hermetic electronic package of claim 8 , wherein the metal hermetic sealing gasket is formed of one of Kovar, Alloy 42, Alloy 46, and Alloy 52.

13. The hermetic electronic package of claim 8, wherein the metal hermetic sealing gaskets are each hermetically bonded to the second surface of the corresponding ceramic seal and to a portion of the corresponding drain high current I / O terminal, the source high current I / O terminal, or the gate I / O terminal using a CuAg braze.

14. A method of manufacturing a hermetic electronic package, comprising: Providing a packaging body; hermetically coupling a package substrate to a first end portion of the package body; thermally coupling a substrate to the packaging substrate; mounting a semiconductor device to the substrate, the semiconductor device having at least one high current output electrically bonded to a first metallization region of the substrate; bonding at least one high current input / output (I / O) terminal to the first metallization region of the substrate via a strap terminal that is an integral high current heat sink terminal, the at least one high current I / O terminal passing through a corresponding hole formed in the package body; hermetically bonding a ceramic seal surrounding the at least one high current I / O terminal to an outer surface of the package body by brazing a first surface of the ceramic seal to the outer surface of the package body; hermetically bonding a metallic hermetic sealing gasket surrounding the at least one high current I / O terminal to the second surface of the ceramic seal and to a portion of the at least one high current I / O terminal; as well as A lid is seam welded to the package body at a second end opposite the first end to form a hermetic seal with the package body.

15. The method of claim 14, wherein mounting the semiconductor device to the substrate comprises bonding a drain terminal of the semiconductor device to a first metallization region of the substrate and bonding a source terminal of the semiconductor device to a second metallization region of the substrate, bonding at least one high current I / O terminal comprises bonding a drain high current I / O terminal to the first metallization area of ​​the substrate through a first strap terminal, and bonding a source high current I / O terminal to the second metallization area of ​​the substrate through a second strap terminal, the drain high current I / O terminal and the source high current I / O terminal passing through corresponding holes formed in the package body, hermetically bonding the ceramic seal includes hermetically bonding a first ceramic seal surrounding the drain high current I / O terminal and a second ceramic seal surrounding the source high current I / O terminal to an outer surface of the package body, and Hermetically bonding a metal hermetic sealing gasket includes hermetic bonding a first metal hermetic sealing gasket to the first ceramic seal and a portion of the drain high current I / O terminal, and hermetic bonding a second metal hermetic sealing gasket to the second ceramic seal and a portion of the source high current I / O terminal.

16. The method of claim 14, wherein respective ones of the first and second bond wires are stitched between the source terminal and a source connection point on the second metallization region.

Images