Stacked semiconductor device and method for manufacturing the stacked semiconductor device

Abstract

A stacked semiconductor device and a method for manufacturing the stacked semiconductor device are provided. The stacked semiconductor device includes: a plurality of semiconductor chips stacked to overlap each other; a plurality of through electrodes respectively penetrating the semiconductor chips, the plurality of through electrodes being coupled to each other; and a plurality of gaps respectively buried in the through electrodes.

Description

Technical Field

[0001] The present disclosure generally relates to a stacked semiconductor device and a method for manufacturing the stacked semiconductor device, and more particularly, to a stacked semiconductor device including a through electrode and a method for manufacturing the stacked semiconductor device. Background Art

[0002] In a stacked semiconductor device, semiconductor chips overlap each other so that the integration of the semiconductor device can be improved. The semiconductor chips overlapping each other can be electrically connected to each other through through electrodes. The through electrodes can reduce the length of the interconnection structure between the semiconductor chips overlapping each other, thereby providing a semiconductor device with improved data transmission speed. Summary of the invention

[0003] According to one aspect of the present disclosure, a stacked semiconductor device can be provided, which includes: a plurality of semiconductor chips stacked to overlap each other; a plurality of through electrodes respectively penetrating the semiconductor chips, wherein the plurality of through electrodes are combined with each other; and a plurality of gaps respectively buried in the through electrodes.

[0004] According to another aspect of the present disclosure, a method for manufacturing a stacked semiconductor device may be provided, the method comprising the following steps: forming a first semiconductor chip penetrated by a first through-electrode buried with a first void; forming a second semiconductor chip penetrated by a second through-electrode buried with a second void; aligning the first semiconductor chip on the second semiconductor chip; and bonding the first through-electrode to the second through-electrode. BRIEF DESCRIPTION OF THE DRAWINGS

[0005] In the accompanying drawings, dimensions may be exaggerated for clarity of illustration. It will be understood that when an element is referred to as being "between" two elements, it can be the only element between the two elements, or one or more intervening elements may also be present. Like reference numerals refer to like elements throughout.

[0006] Figure 1 is a cross-sectional view schematically showing a stacked semiconductor device according to an embodiment of the present disclosure.

[0007] Figure 2 It is shown Figure 1 An enlarged cross-sectional view of region A is shown.

[0008] Figure 3 is a block diagram illustrating a memory system according to an embodiment of the present disclosure.

[0009] Figure 4 is a cross-sectional view showing a stacked memory device according to an embodiment of the present disclosure.

[0010] Figure 5 is a diagram illustrating a memory system according to an embodiment of the present disclosure.

[0011] Figure 6 is a block diagram illustrating a memory system according to an embodiment of the present disclosure.

[0012] Figure 7 is a block diagram illustrating a computing system according to an embodiment of the present disclosure.

[0013] Figure 8 is a diagram illustrating a CMOS image sensor according to an embodiment of the present disclosure.

[0014] Fig. 9A , Fig. 9B , Fig. 9C , Fig.9D , Fig.9E , Fig.9F , Figure 9G , Figure 9H , Fig.9I , Figure 9J , Fig. 10A and Fig. 10B is a cross-sectional view showing a method for manufacturing a stacked semiconductor device according to an embodiment of the present disclosure. DETAILED DESCRIPTION

[0015] In order to describe the embodiments of the concepts according to the present disclosure, the specific structural or functional descriptions disclosed herein are only illustrative. The embodiments of the concepts according to the present disclosure can be implemented in various forms and should not be interpreted as being limited to the embodiments set forth herein.

[0016] Hereinafter, the terms "first" and "second" are used to distinguish one component from another component. For example, without departing from the scope of the concept according to the present disclosure, a first component may be referred to as a second component, and similarly, a second component may be referred to as a first component.

[0017] Embodiments provide a stacked semiconductor device capable of improving stability of a bonding structure and a method of manufacturing the stacked semiconductor device.

[0018] Figure 1 1 is a cross-sectional view schematically showing a stacked semiconductor device 10 according to an embodiment of the present disclosure. Figure 1 It is a cross-sectional view taken along a through via region where the through electrodes TE1 to TEn of the stacked semiconductor device 10 are provided.

[0019] Reference Figure 1The stacked semiconductor device 10 may include a plurality of semiconductor chips C1 to Cn (n is a natural number of 2 or more). The semiconductor chips C1 to Cn may be stacked to overlap each other. The semiconductor chips C1 to Cn may be penetrated by through electrodes TE1 to TEn.

[0020] The number and arrangement of the through electrodes penetrating each of the semiconductor chips C1 to Cn may be various. The through electrodes TE1 to TEn penetrating different semiconductor chips C1 to Cn, respectively, may be arranged in a line. A bonding medium such as a bump may be provided between the through electrodes to achieve electrical connection between the through electrodes. In an embodiment of the present disclosure, the through electrodes TE1 to TEn arranged in a line may be directly bonded to each other without any medium such as a bump to be electrically connected to each other. The through electrodes TE1 to TEn connected to each other may be used as a data transmission path.

[0021] The semiconductor chips C1 to Cn may be chips of the same type or chips of different types. In an embodiment, each of the semiconductor chips C1 to Cn may be a memory chip. In another embodiment, at least one of the semiconductor chips C1 to Cn may correspond to a logic chip, and the others may correspond to memory chips. In another embodiment, at least one of the semiconductor chips C1 to Cn may correspond to a logic chip, and the others may correspond to pixel chips.

[0022] Each of the through electrodes TE1 to TEn may include a buffer portion BP and a vertical portion VP extending from the buffer portion BP. The vertical portion VP of the upper through electrode and the buffer portion of the lower through electrode are coupled to each other so that the through electrodes TE1 to TEn are electrically connected to each other.

[0023] Hereinafter, a semiconductor chip (e.g., C2) disposed at a relatively upper portion among the semiconductor chips C1 to Cn is designated as a first semiconductor chip, and a semiconductor chip (e.g., C3) disposed at a relatively lower portion among the semiconductor chips C1 to Cn is designated as a second semiconductor chip. In addition, a through-electrode (e.g., TE2) disposed at a relatively upper portion among the through-electrodes TE1 to TEn is represented by a first through-electrode, and a through-electrode (e.g., TE3) disposed at a relatively lower portion among the through-electrodes TE1 to TEn is represented by a second through-electrode.

[0024] Figure 2 It is shown Figure 1 An enlarged cross-sectional view of region A is shown. Figure 1 The buffer portion BP of the through-electrodes TE1 to TEn described may include a first buffer portion BPa of the first through-electrode TE2 and a second buffer portion BPb of the second through-electrode TE3, referring to Figure 1The described vertical portion VP of the through electrodes TE1 to TEn may include a first vertical portion VPa of the first through electrode TE2 and a second vertical portion VPb of the second through electrode TE3 .

[0025] Reference Figure 2 , each of the first semiconductor chip C2 and the second semiconductor chip C3 may include a substrate 110a or 110b, a first insulating structure 120a or 120b, a conductive pad 130a or 130b, and a second insulating structure 140a or 140b.

[0026] Each of the substrates 110a and 110b of the first semiconductor chip C2 and the second semiconductor chip C3 may have a first surface SU1a or SU1b and a second surface SU2a or SU2b opposite to the first surface SU1a or SU1b. The first insulating structures 120a and 120b of the first semiconductor chip C2 and the second semiconductor chip C3 may be formed on the first surfaces SU1a and SU1b of the substrates 110a and 110b, respectively. The conductive pads 130a of the first semiconductor chip C2 may face the first surface SU1a of the substrate 110a with the first insulating structure 120a interposed therebetween, and the conductive pads 130b of the second semiconductor chip C3 may face the first surface SU1b of the substrate 110b with the first insulating structure 120b interposed therebetween. The second insulating structures 140a and 140b of the first and second semiconductor chips C2 and C3 may be formed to cover a surface of the first insulating structure 120a where the conductive pads 130a are disposed and a surface of the first insulating structure 120b where the conductive pads 130b are disposed, respectively.

[0027] The substrate 110b of the second semiconductor chip C3 may be bonded to the second insulating structure 140a of the first semiconductor chip C2. Each of the first through-electrode TE2 and the second through-electrode TE3 may fill the buffer hole and the via hole corresponding thereto. In other words, the first through-electrode TE2 may fill the first buffer hole BHa and the first via hole VHa, and the second through-electrode TE3 may fill the second buffer hole BHb and the second via hole VHb.

[0028] The first buffer hole BHa may extend from the first surface SU1a toward the second surface SU2a to penetrate the substrate 110a of the first semiconductor chip C2. The first via hole VHa may extend from the first buffer hole BHa and may penetrate the first insulating structure 120a, the conductive pad 130a, and the second insulating structure 140a of the first semiconductor chip C2. The first buffer portion BPa of the first through electrode TE2 may be disposed in the first buffer hole BHa. The first vertical portion VPa of the first through electrode TE2 may extend from the first buffer portion BPa and fill the first via hole VHa.

[0029] The second buffer hole BHb may extend from the first surface SU1b toward the second surface SU2b to penetrate the substrate 110b of the second semiconductor chip C3. The second via hole VHb may extend from the second buffer hole BHb and may penetrate the first insulating structure 120b, the conductive pad 130b, and the second insulating structure 140b of the second semiconductor chip C3. The second buffer portion BPb of the second through electrode TE3 may be disposed in the second buffer hole BHb. The second vertical portion VPb of the second through electrode TE3 may extend from the second buffer portion BPb and fill the second via hole VHb.

[0030] The substrates 110a and 110b of the first semiconductor chip C2 and the second semiconductor chip C3 may be insulated from the first through electrode TE2 and the second through electrode TE3 by the sidewall insulation patterns 151a and 151b. The sidewall insulation pattern 151a may extend between the buffer portion BPa and the substrate 110a and between the vertical portion VPa and the first insulation structure 120a. The sidewall insulation pattern 151b may extend between the buffer portion BPb and the substrate 110b and between the vertical portion VPb and the first insulation structure 120b. The first vertical portion VPa of the first through electrode TE2 and the second vertical portion VPb of the second through electrode TE3 may contact the conductive pads 130a and 130b, respectively. In an embodiment, the first vertical portion VPa of the first through electrode TE2 may protrude further than the sidewall insulation pattern 151a to contact the conductive pad 130a and the second insulation structure 140a, and the second vertical portion VPb of the second through electrode TE3 may protrude further than the sidewall insulation pattern 151b to contact the conductive pad 130b and the second insulation structure 140b.

[0031] The voids may be buried in the first through electrode TE2 and the second through electrode TE3, respectively. The voids may include air gaps. The voids may include a first void 159a buried in the first through electrode TE2 and a second void 159b buried in the second through electrode TE3. The first vertical portion VPa may be disposed between the first void 159a and the second void 159b.

[0032] The first void 159a may be disposed in the first buffer hole BHa and surrounded by the first buffer portion BPa of the first through electrode TE2. That is, the first void 159a may be sealed in the first buffer hole BHa by the first buffer portion BPa.

[0033] The second void 159b may be disposed in the second buffer hole BHb and surrounded by the second buffer portion BPb of the second through electrode TE3. That is, the second void 159b may be sealed in the second buffer hole BHb by the second buffer portion BPb.

[0034] Each of the first buffer hole BHa and the second buffer hole BHb may have a width wider than that of each of the first via hole VHa and the second via hole VHb. Figure 1 The width WB of the buffer portion BP shown may be defined as being greater than the width WA of the vertical portion VP. In addition, the first void 159a and the second void 159b may be formed in the first buffer hole BHa and the second buffer hole BHb. In an embodiment, each of the first buffer hole BHa and the second buffer hole BHb may have a curved sidewall extending in a stacking direction in which the first through electrode TE2 and the second through electrode TE3 are stacked, and each of the first via hole VHa and the second via hole VHb may have a flat sidewall extending in the stacking direction.

[0035] The second buffer portion BPb may include a recessed portion RP recessed toward the inside of the second gap 159b by pressure generated in the coupling between the second buffer portion BPb and the first vertical portion VPa.

[0036] Each of the substrates 110 a and 110 b may be a semiconductor substrate made of silicon, germanium, gallium arsenide, or the like.

[0037] Each of the first insulating structures 120 a and 120 b may extend to cover an integrated circuit formed in a main region (not shown in the drawings), and include a plurality of insulating layers.

[0038] Each of the conductive pads 130a and 130b may be connected to an integrated circuit disposed in a main region of a semiconductor chip corresponding thereto. The conductive pads 130a and 130b may be formed of various conductive materials. In an implementation, the conductive pads 130a and 130b may include aluminum.

[0039] The second insulating structures 140a and 140b may include various insulating materials. In an implementation, the second insulating structures 140a and 140b may include a silicon oxide layer.

[0040] Each of the first through electrode TE2 and the second through electrode TE3 may include a barrier layer 153a or 153b and a metal layer 155a or 155b. Each of the barrier layers 153a and 153b may be formed as a single layer made of titanium, titanium nitride, tantalum, tantalum nitride, tungsten, tungsten nitride, nickel, nickel nitride, etc., or as a double layer including titanium and titanium nitride. Each of the metal layers 155a and 155b may include various metals that can be combined by low-temperature plasma annealing. In an embodiment, each of the metal layers 155a and 155b may include a metal that can be combined at a temperature of 300°C or less. In an embodiment, each of the metal layers 155a and 155b may include copper.

[0041] The metal layers 155a and 155b of the first through electrode TE2 and the second through electrode TE3 may be combined with each other. The metal layers 155a and 155b may surround the voids 159a and 159b, respectively. In other words, the first void 150a may be buried in the metal layer 155a, and the second void 159b may be buried in the metal layer 155b.

[0042] Barrier layers 153a and 153b may be formed on the sidewalls of metal layers 155a and 155b, respectively. That is, barrier layers 153a and 153b may be disposed between metal layer 155a and sidewall insulation pattern 151a and between metal layer 155b and sidewall insulation pattern 151b, respectively. Barrier layer 153a may extend between metal layer 155a and conductive pad 130a and between metal layer 155a and second insulation structure 140a. Barrier layer 153b may extend between metal layer 155b and conductive pad 130b and between metal layer 155b and second insulation structure 140b.

[0043] According to the above-described embodiment of the present disclosure, each through electrode may include a contact surface in contact with the conductive pad, a first bonding surface adjacent to the second surface of the substrate, and a second bonding surface adjacent to the surface of the second insulating structure. For example, the first through electrode TE2 may include a contact surface CS in contact with the conductive pad 130a, a first bonding surface BS1 adjacent to the second surface SU2a of the substrate 110a, and a second bonding surface BS2 adjacent to the surface of the second insulating structure 140a. The second bonding surface BS2 may be set as the contact surface CS. The surface of the second insulating structure 140a may be in contact with the second surface SU2b of the adjacent substrate 110b.

[0044] Figure 3 is a block diagram showing a memory system 300 according to an embodiment of the present disclosure.

[0045] Reference Figure 3 , the memory system 300 may be applied to an electronic device such as a computer, a digital camera, or a smart phone to process data.

[0046] The memory system 300 may include a memory controller 310 and a stacked memory device 320 .

[0047] According to an access request from the host HOST, the memory controller 310 may transmit data to the stacked memory device 320 or provide a control signal to the stacked memory device 320. The memory controller 310 may detect errors in data read from the stacked memory device 320 and correct the detected errors.

[0048] The stacked memory device 320 may include two or more memory chips 330_1 to 330_n stacked on each other. Each of the memory chips 330_1 to 330_n may include a volatile memory device or a non-volatile memory device. For example, each of the memory chips 330_1 to 330_n may include a dynamic random access memory (DRAM), a read-only memory (ROM), a mask ROM (MROM), a programmable ROM (PROM), an erasable programmable ROM (EPROM), an electrically erasable programmable ROM (EEPROM), a NAND flash memory, a NOR flash memory, a phase change random access memory (PRAM), a magnetic RAM (MRAM), a resistive RAM (RRAM), a ferroelectric RAM (FRAM), etc.

[0049] The memory chips 330_1 to 330_n can be referred to as Figure 1 and Figure 2 The described through electrodes are coupled to each other.

[0050] Figure 4 is a cross-sectional view showing a stacked memory device 400 according to an embodiment of the present disclosure.

[0051] The stacked memory device 400 may include a memory cell array region AR1, a peripheral circuit region AR2, and a through-hole region AR3. The memory cell array region AR1 and the peripheral circuit region AR2 may be included in the main region of the stacked memory device 400. The through-hole region AR3 may be a region providing a data transmission path and having through electrodes 457a and 457b coupled to each other disposed therein.

[0052] The stacked memory device 400 may include a first memory chip MCa and a second memory chip MCb overlapping each other. Each of the first memory chip MCa and the second memory chip MCb may include a semiconductor substrate 410a or 410b, a first insulating structure 420a or 420b formed on a surface of the semiconductor substrate 410a or 410b, and a second insulating structure 440a or 440b formed on a surface of the first insulating structure 420a or 420b.

[0053] Various impurities for a well structure and a channel may be doped in the semiconductor substrates 410a and 410b. Isolation layers 411a and 411b may be buried in the semiconductor substrates 410a and 410b.

[0054] Memory cells and lines connected to the memory cells may be buried in each of the first insulating structures 420a and 420b in the memory cell array region AR1. Figure 4, the case where the memory cell includes a DRAM cell structure is illustrated, but the present disclosure is not limited thereto. The conductive pads 431a and 431b may be buried in the second insulating structures 440a and 440b in the memory cell array region AR1, respectively. The conductive pads 431a and 431b formed in the memory cell array region AR1 may be connected to the memory cell via lines buried in the first insulating structures 420a and 420b.

[0055] A peripheral circuit for controlling the operation of the memory cell and a line connected to the peripheral circuit may be buried in each of the first insulating structures 420a and 420b in the peripheral circuit region AR2. According to a control signal input from the outside (e.g., a storage controller), the peripheral circuit may input data to the memory cell or read data from the memory cell. Conductive pads 433a and 433b may be buried in second insulating structures 440a and 440b in the peripheral circuit region AR2, respectively. Each of the conductive pads 433a and 433b formed in the peripheral circuit region AR2 may be connected to the corresponding peripheral circuit via a line buried in the corresponding first insulating structure 420a or 420b.

[0056] The first insulating structures 420a and 420b and the second insulating structures 440a and 440b described above may extend to the through-hole region AR3. Through-electrodes 457a and 457b used as a path for the stacked memory device 400 to exchange data or signals with the outside of the stacked memory device 400 (e.g., a storage controller) may be formed in the through-hole region AR3. The through-electrodes 457a and 457b may be insulated from the substrates 410a and 410b by sidewall insulating patterns 451a and 451b, respectively, and electrically connected to the conductive pads 430a and 430b provided in the peripheral circuit region AR2, respectively.

[0057] The through electrodes 457a and 457b can be Figure 2 The same structure as described above is formed for each of the first through-electrode TE2 and the second through-electrode TE3 .

[0058] Figure 5 is a diagram illustrating a memory system 500 according to an embodiment of the present disclosure.

[0059] Reference Figure 5 , the memory system 500 may include a high bandwidth memory device (HBM) 520 and a processor 530 mounted on an interposer 510 .

[0060] The HBM 520 may be connected to the processor 530 through the interposer 510. The HBM 520 may include an interface chip 521 disposed on the interposer 510 and a memory chip 523 stacked on the interface chip 521. The memory chip 523 and the interface chip 521 may be connected to the processor 530 through the interposer 510. Figure 1 The through-electrodes described above are electrically connected to each other. The through-electrodes penetrating the memory chip 523 and the interface chip 521 may include a through-electrode as shown in FIG. Figure 2 Description of the gap.

[0061] The interface chip 521 may provide an interface for communication between the processor 530 and the memory chip 523 .

[0062] The processor 530 may include a memory controller for controlling each HBM 520. For example, the processor 530 may include a graphics processing unit (GPU) or a central processing unit (CPU) having built-in memory control.

[0063] Figure 6 is a block diagram illustrating a memory system 600 according to an embodiment of the present disclosure.

[0064] Reference Figure 6 , the memory system 600 may include a memory controller 610 and a stacked memory device 620 .

[0065] The storage controller 610 can control the stacked memory device 620, and includes a static random access memory (SRAM) 611, a central processing unit (CPU) 612, a host interface 613, an error correction block 614, and a memory interface 615. The SRAM 611 can be used as a working memory of the CPU 612. The CPU 612 can perform an overall control operation for data exchange of the storage controller 610. The host interface 613 is provided with a data exchange protocol of a host Host connected to the memory system 600. The error correction block 614 detects errors included in data read from the stacked memory device 620, and corrects the detected errors. The memory interface 615 performs an interface with the stacked memory device 620. The storage controller 610 may also include a read-only memory (ROM) storing code data and the like for interfacing with the host Host.

[0066] The stacked memory device 620 may include a plurality of memory packages 621_1 to 621_m. Each of the memory packages 621_1 to 621_m may be formed in a structure in which a plurality of memory chips 623 are stacked. The memory chips 623 may be formed by referring to Figure 1 The through-electrodes described above are electrically connected to each other. Each through-electrode penetrating the memory chip 623 may include a through-electrode as shown in FIG. Figure 2 Description of the gap.

[0067] A plurality of channels CH1 to CHm may be provided to the memory controller 610 and the stacked memory device 620. A memory package corresponding to each of the channels CH1 to CHm may be electrically connected to the channel. Each of the channels CH1 to CHm may be electrically connected to a memory package corresponding thereto through a through electrode penetrating the memory chip 623.

[0068] The above-mentioned memory system 600 may be a memory card or a solid state drive (SSD) in which a stacked memory device 620 and a memory controller 610 are connected to each other. For example, when the memory system 600 is an SSD, the memory controller 610 may communicate with the outside (e.g., a host) through one of various interface protocols such as a universal serial bus (USB) protocol, a multimedia card (MMC) protocol, a peripheral component interconnect (PCI) protocol, a high-speed PCI (PCI-E) protocol, an advanced technology attachment (ATA) protocol, a serial ATA (SATA) protocol, a parallel ATA (PATA) protocol, a small computer mini interface (SCSI) protocol, an enhanced mini disk interface (ESDI) protocol, and an integrated drive electronics (IDE) protocol.

[0069] Figure 7 is a block diagram illustrating a computing system according to an embodiment of the present disclosure.

[0070] Reference Figure 7 , the computing system 700 may include a CPU 720 electrically connected to a system bus 760, a random access memory (RAM) 730, a user interface 740, a modem 750, and a memory system 710. When the computing system 700 is a mobile device, a battery for supplying an operating voltage to the computing system 700 may also be included, and an application chipset, an image processor, a mobile DRAM, and the like may also be included.

[0071] The memory system 710 may include a memory controller 711 and a memory device 712. The memory device 712 may be connected to a memory controller 711 and a memory device 712. Figure 6 The stacked memory device 620 described above is configured in the same manner. The memory controller 711 may be configured in the same manner as described above. Figure 6 The described storage controller 610 is configured identically.

[0072] Figure 8 is a diagram illustrating a CMOS image sensor (CIS) 800 according to an embodiment of the present disclosure.

[0073] Reference Figure 8 , the CIS 800 may include a logic chip 810 and a pixel chip 820 stacked on the logic chip 810 .

[0074] The logic chip 810 may include a logic circuit for processing a pixel signal from the pixel chip 820. The logic circuit may include a row driver, a correlated double sampler (CDS), an analog-to-digital converter (ADC), a timing controller, and the like.

[0075] The pixel chip 820 may include a pixel array. The pixel array may generate an electrical pixel signal by converting incident light. The pixel array may include a plurality of unit pixels arranged in a matrix form. The pixel array may be driven by a driving signal provided from the logic chip 810.

[0076] The logic chip 810 and the pixel chip 820 may be penetrated by the through-electrodes combined with each other and electrically connected to each other through the through-electrodes. The through-electrodes penetrating the logic chip 810 and the pixel chip 820 may be connected to the reference Figure 2 The described first through-electrode TE2 and second through-electrode TE3 are identically configured.

[0077] Fig. 9A , Fig. 9B , Fig. 9C , Fig.9D , Fig.9E , Fig.9F , Figure 9G , Figure 9H , Fig.9I , Figure 9J , Fig. 10A and Fig. 10B is a cross-sectional view showing a method for manufacturing a stacked semiconductor device according to an embodiment of the present disclosure. Fig. 9A , Fig. 9B , Fig. 9C , Fig.9D , Fig.9E , Fig.9F , Figure 9G , Figure 9H , Fig.9I , Figure 9J , Fig. 10A and Fig. 10B This is a cross-sectional view taken along a through-hole region of a stacked semiconductor device.

[0078] FIG. 9A to FIG. 9J It is a cross-sectional view showing an embodiment of a method for manufacturing a semiconductor chip.

[0079] Reference Fig. 9A , a first insulating structure 920 may be formed on a first surface 910S1 of a preliminary substrate 910A having a first surface 910S1 and a second surface 910S2 opposite to the first surface 910S1. Although not shown in the drawings, elements and lines for at least one of a memory cell array, a pixel array, a peripheral circuit, and a logic circuit of a semiconductor chip may be formed in a main region (not shown) of the preliminary substrate 910A.

[0080] The preliminary substrate 910A may be a semiconductor substrate made of silicon, germanium, gallium arsenide, etc. Various impurities for a well structure, a channel region, etc. may be doped in the preliminary substrate 910A.

[0081] The first insulating structure 920 may extend to cover a main region (not shown) of the preliminary substrate 910A. The first insulating structure 920 may include two or more insulating layers stacked on the preliminary substrate 910A.

[0082] Subsequently, a conductive pad 930 may be formed on the first insulating structure 920. Subsequently, a second insulating structure 940 may be formed on the first insulating structure 920. The second insulating structure 940 may be formed to cover the conductive pad 930.

[0083] Subsequently, a mask pattern 941 may be formed on the second insulating structure 940. The mask pattern 941 may be patterned to have an opening overlapping the conductive pad 930 using a photolithography process.

[0084] The via hole 943 may be formed by sequentially etching the second insulating structure 940, the conductive pad 930, and the first insulating structure 920 through an etching process using the above-described mask pattern 941 as an etching barrier. The via hole 943 may be formed to expose the preliminary substrate 910A. The via hole 943 may be formed to a depth at which the via hole 943 does not penetrate the preliminary substrate 910A. In an embodiment, the via hole 943 may be formed to a depth corresponding to the thickness of the stacked structure including the second insulating structure 940, the conductive pad 930, and the first insulating structure 920. The width of the via hole 943 may be formed to be narrower than the width of the conductive pad 930.

[0085] Reference Fig. 9B After forming the via hole 943, the Fig. 9A The mask pattern 941 is shown. Subsequently, a protective layer 945 may be formed on the sidewalls of the via hole 943. The protective layer 945 may be formed of a material having an etching selectivity relative to the preliminary substrate 910A. In an embodiment, the protective layer 945 may include an oxide. The protective layer 945 may be etched so that the preliminary substrate 910A may be exposed through the bottom surface of the via hole 943.

[0086] Reference Fig. 9C , the buffer hole 947 may be formed by etching the preliminary substrate 910A through the via hole 943. While the preliminary substrate 910A is being etched, the first insulating structure 920, the conductive pad 930, and the second insulating structure 940 may be formed by Fig. 9B The protective layer 945 shown protects the PCB. After the buffer hole 947 is formed, the protective layer 945 can be removed.

[0087] The etching process for forming the buffer hole 947 may be performed by an isotropic etching process. Therefore, in the direction in which the preliminary substrate 910A and the first insulating structure 920 are stacked, the sidewall of the buffer hole 947 may have a greater curvature than the sidewall of the via hole 943. In an embodiment, the buffer hole 947 may be formed in a circular shape or an elliptical shape.

[0088] The buffer hole 947 may extend from the via hole 943 to the inside of the preliminary substrate 910A. The bottom surface of the buffer hole 947 may be spaced apart from the second surface 910S2 of the preliminary substrate 910A. In other words, the buffer hole 947 may be formed to a depth that the buffer hole 947 does not completely penetrate the preliminary substrate 910A.

[0089] Reference Fig.9D , an insulating layer 951L may be formed on a surface of each of the buffer hole 947 and the via hole 943. The insulating layer 951L may extend onto the sidewalls of the first insulating structure 920 that define the sidewalls of the via hole 943, the sidewalls of the conductive pad 930, and the sidewalls of the second insulating structure 940, and onto the top surface of the second insulating structure 940. The insulating layer 951L may include an oxide layer.

[0090] Reference Fig.9E , a sacrificial material 952 may be formed on the insulating layer 951L. The sacrificial material 952 may be formed by a spin coating process to fill Fig.9D The buffer hole 947 and the via hole 943 are shown. Subsequently, the sacrificial material 952 can be removed to make Fig.9D The upper end of the via hole 943 is shown to be open. Hereinafter, the upper end of the via hole 943 that is open when a portion of the sacrificial material 952 is removed is defined as an opening OP.

[0091] The etching process of the sacrificial material 952 for forming the opening OP may include an etching process such as an etch-back process. The sacrificial material 952 may be formed of a material having an etching selectivity with respect to the second insulating structure 940 and the conductive pad 930. In an embodiment, the sacrificial material 952 may include carbon, a photoresist, or an organic compound.

[0092] The opening OP may extend to a level where a sidewall of the conductive pad 930 is disposed. In an implementation, a top surface of the sacrificial material 952 defining a bottom surface of the opening OP may correspond to a level where a top surface of the insulating structure 920 is disposed.

[0093] Reference Fig.9F , by etching Fig.9E The exposed portion of the insulating layer 951L is shown to form a sidewall insulating layer 951. The sidewall insulating layer 951 may remain in a state where the sidewall insulating layer 951 extends from the surface of the buffer hole 947 to the sidewall of the first insulating structure 920.

[0094] Reference Figure 9G , by selectively removing Fig.9F The sacrificial material 952 is shown to expose the sidewall insulating layer 951. Subsequently, a barrier layer 953L and a metal layer 955L may be sequentially formed on the sidewall insulating layer 951.

[0095] The barrier layer 953L may extend from the sidewall insulating layer 951 onto the sidewall of the conductive pad 930. The barrier layer 953L may be connected to the conductive pad 930 exposed on the sidewall insulating layer 951. The barrier layer 953L may be formed as a single layer including titanium, titanium nitride, tantalum, tantalum nitride, tungsten nitride, nickel, nickel boride, etc., or as a double layer including titanium and titanium nitride.

[0096] The metal layer 955L may be formed by a deposition process such as electroplating. In an embodiment, the metal layer 955L may include copper. The metal layer 955L may be formed on the barrier layer 953L to fill the buffer hole 947 and the via hole 943. The void 959 may be buried in the buffer hole 947 formed to a depth deeper than the depth of the via hole 943. When the width of the buffer hole 947 is formed to be wider than the width of the via hole 943, the void 959 may be easily buried in the buffer hole 947. The metal layer 955L may completely fill the via hole 943 so that the void 959 may be sealed in the buffer hole 947.

[0097] Reference Figure 9H , which can be removed by planarization process Figure 9G A portion of each of the metal layer 955L and the barrier layer 953L is shown such that a top surface of the second insulating structure 940 is exposed.

[0098] Reference Fig.9I , available from Figure 9H The second surface 910S2 of the preliminary substrate 910A shown removes a portion of the preliminary substrate 910A so that the end of the sidewall insulating layer 951 is exposed. Therefore, the thickness of the preliminary substrate 910A can be reduced. Hereinafter, the preliminary substrate with the reduced thickness is defined as a combined substrate 910B. The end of the sidewall insulating layer 951 can be exposed in a state where the end protrudes further than the combined substrate 910B.

[0099] Reference Figure 9J , can be removed Fig.9I The exposed portion of the sidewall insulating layer 951 is shown. Thus, a sidewall insulating pattern 951P serving as a target may be formed.

[0100] Subsequently, a barrier pattern 953P may be formed by removing a portion of the barrier layer to expose the metal layer 955. The barrier pattern 953P and the metal layer 955 may constitute a through electrode 957. The exposed portion of the metal layer 955 may constitute a protrusion PP protruding further than the bonding substrate 910B.

[0101] By reference FIG. 9A to FIG. 9J The through electrode 957 formed by the described process may include a buffer portion P1 filling the buffer hole 947 in the bonding substrate 910B and a vertical portion P2 extending from the buffer portion P1. The vertical portion P2 may be formed on the sidewall insulation pattern 951P to fill the via hole 943 penetrating the first insulation structure 920, the conductive pad 930, and the second insulation structure 940 and contact the conductive pad 930.

[0102] Fig. 10A and Fig. 10B 9 is a cross-sectional view showing a process of bonding the first semiconductor chip 970 and the second semiconductor chip 980. The bonding process between the first semiconductor chip 970 and the second semiconductor chip 980 may be performed by a bonding process between wafers, by a bonding process between dies, or by a bonding process between a wafer and a die.

[0103] Reference Fig. 10A , can be respectively obtained by referring to FIG. 9A to FIG. 9J The first through electrode 957a and the second through electrode 957b manufactured by the described process penetrate the first semiconductor chip 970 and the second semiconductor chip 989. The first void 959a may be buried in the first through electrode 957a, and the second void 959b may be buried in the second through electrode 957b.

[0104] According to reference FIG. 9A to FIG. 9J According to the process described, the first through electrode 957a may include a first buffer portion P1a and a first vertical portion P2a extending from the first buffer portion P1a. The first buffer portion P1a may be disposed in a first buffer hole 947a penetrating the first bonding substrate 910Ba of the first semiconductor chip 970 and surround the first gap 959a. The first vertical portion P2a may extend to penetrate the first insulating structure 920a, the first conductive pad 930a, and the second insulating structure 940a of the first semiconductor chip 970. The sidewall of the first buffer portion P1a facing the first bonding substrate 910Ba and the sidewall of the first vertical portion P2a facing the first insulating structure 920a may be surrounded by a first sidewall insulating pattern 951Pa. The first vertical portion P2a may protrude farther than the first sidewall insulating pattern 951Pa and contact the first conductive pad 930a of the first semiconductor chip 970.

[0105] According to reference FIG. 9A to FIG. 9JAccording to the process described, the second through electrode 957b may include a second buffer portion P1b and a second vertical portion P2b extending from the second buffer portion P1b. The second buffer portion P1b may be disposed in a second buffer hole 947b penetrating the second bonding substrate 910Bb of the second semiconductor chip 980 and surround the second gap 959b. The second vertical portion P2b may extend to penetrate the first insulating structure 920b, the second conductive pad 930b, and the second insulating structure 940b of the second semiconductor chip 980. The side wall of the second buffer portion P1b facing the second bonding substrate 910Bb and the side wall of the second vertical portion P2b facing the first insulating structure 920b may be surrounded by a second sidewall insulating pattern 951Pb. The second vertical portion P2b may protrude further than the second sidewall insulating pattern 951Pb and contact the second conductive pad 930b of the second semiconductor chip 980.

[0106] The first buffer portion P1a may protrude further than the first bonding substrate 910Ba, and the second buffer portion P1b may protrude further than the second bonding substrate 910Bb.

[0107] The first semiconductor chip 970 may be aligned on the second semiconductor chip 980 such that the first vertical portion P2 a and the second buffer portion P1 b face each other.

[0108] Reference Fig. 10B , the first through electrode 957a of the first semiconductor chip 970 may be bonded to the second through electrode 957b of the second semiconductor chip 980. The first through electrode 957a and the second through electrode 957b may be bonded to each other by bonding the first vertical portion P2a to the second buffer portion P1b.

[0109] The bonding process may include a plasma annealing process. The plasma annealing process may be performed at a low temperature of 300° C. or less. During the plasma annealing process, the first through electrode 957 a and the second through electrode 957 b may be bonded to each other through coherence between metal layers of the first through electrode 957 a and the second through electrode 957 b.

[0110] The metal layer of each of the first through electrode 957a and the second through electrode 957b may thermally expand due to the heat generated during the above-mentioned bonding process, and a repulsive force may occur between the first through electrode 957a and the second through electrode 957b. By the repulsive force generated between the first through electrode 957a and the second through electrode 957b and the coherence between the metal layers of the first through electrode 957a and the second through electrode 957b, the protrusion of the second through electrode 957b may be extended toward Fig. 10A The second gap 959b is shown as being recessed. Fig. 10A The shape of the second gap 959b shown may be as follows Fig. 10BThe first void 959a is deformed during the bonding process shown and remains as a recessed void 959b' having a greater curvature deviation than the first void 959a. In an embodiment, the recessed void 959b' may have a concave portion and a convex portion.

[0111] As described above, according to the embodiments of the present disclosure, the repulsive force generated between the metal layers at the bonding interface during the bonding process can be offset by the buffering effect of the void, and thus the stability of the bonding structure between the semiconductor chips can be improved.

[0112] Although a structure in which the first semiconductor chip 970 and the second semiconductor chip 980 are coupled to each other is exemplified above, the number of semiconductor chips coupled to each other in the present disclosure is not limited thereto.

[0113] According to the present disclosure, repulsive force between through electrodes caused by thermal expansion of the through electrodes during a bonding process can be offset by gaps formed in the through electrodes. Therefore, stability of the bonding structure can be improved.

[0114] CROSS-REFERENCE TO RELATED APPLICATIONS

[0115] This application claims the benefit of Korean Patent Application No. 10-2020-0030963, filed on March 12, 2020, in the Korean Intellectual Property Office, the entire disclosure of which is incorporated herein by reference.

Claims

1. A stacked semiconductor device, comprising: a plurality of semiconductor chips, the plurality of semiconductor chips being stacked to overlap each other; A plurality of through electrodes, each of which penetrates the semiconductor chip, wherein the plurality of through electrodes are directly connected to each other; as well as A plurality of voids are respectively buried in the through electrodes.

2. The stacked semiconductor device according to claim 1, wherein: Each of the semiconductor chips comprises: a substrate having a first surface and a second surface opposite to the first surface; a first insulating structure, the first insulating structure being on the first surface of the substrate; a conductive pad facing the first surface of the substrate, with the first insulating structure interposed between the conductive pad and the first surface of the substrate; and A second insulating structure covers a surface of the first insulating structure where the conductive pad is disposed.

3. The stacked semiconductor device according to claim 2, wherein: Each of the through electrodes comprises: a contact surface, the contact surface being in contact with the conductive pad; a first bonding surface adjacent to the second surface of the substrate; and A second bonding surface is adjacent to a surface of the second insulating structure.

4. The stacked semiconductor device according to claim 1, wherein: The through electrode comprises: a plurality of metal layers, each of the plurality of metal layers surrounding the gap, wherein the plurality of metal layers are combined with each other; and A plurality of barrier layers are respectively formed on the sidewalls of the metal layer.

5. The stacked semiconductor device according to claim 1, wherein: At least one of the plurality of voids is deformed.

6. The stacked semiconductor device according to claim 1, wherein: At least one of the plurality of voids is a recessed void.

7. A stacked semiconductor device, comprising: a plurality of semiconductor chips, the plurality of semiconductor chips being stacked to overlap each other; a plurality of through electrodes, each of which penetrates the semiconductor chip, wherein the plurality of through electrodes are combined with each other; and a plurality of gaps, wherein the plurality of gaps are respectively buried in the through electrodes, Wherein, each of the semiconductor chips comprises: a substrate having a first surface and a second surface opposite to the first surface; a first insulating structure, the first insulating structure being on the first surface of the substrate; a conductive pad facing the first surface of the substrate, with the first insulating structure interposed between the conductive pad and the first surface of the substrate; and a second insulating structure, the second insulating structure covering a surface of the first insulating structure on which the conductive pad is disposed, Wherein, each of the through electrodes comprises: a buffer portion disposed in a buffer hole extending from the first surface toward the second surface of the substrate to penetrate the substrate; and A vertical portion fills a via hole extending from the buffer hole to penetrate the first insulating structure, the conductive pad, and the second insulating structure.

8. The stacked semiconductor device according to claim 7, further comprising a sidewall insulation pattern extending between the first insulation structure and the vertical portion and between the buffer portion and the substrate, in, The vertical portion protrudes farther than the sidewall insulation pattern to contact the conductive pad and the second insulation structure.

9. The stacked semiconductor device according to claim 7, wherein: Each of the voids is buried in the buffer hole and is surrounded by the buffer portion.

10. The stacked semiconductor device according to claim 7, wherein: The through electrodes are electrically connected to each other through a structure in which the vertical portion of the upper through electrode and the buffer portion of the lower through electrode are coupled to each other.

11. The stacked semiconductor device according to claim 7, wherein: The buffer hole has a curved side wall extending in a stacking direction of the plurality of through electrodes, and The via hole has a flat side wall extending in the stacking direction.

12. The stacked semiconductor device according to claim 7, wherein: The buffer hole has a width wider than a width of the via hole.

13. A method for manufacturing a stacked semiconductor device, the method comprising the steps of: forming a first semiconductor chip penetrated by a first through-electrode in which a first gap is buried; forming a second semiconductor chip penetrated by a second through-electrode in which a second gap is buried; aligning the first semiconductor chip on the second semiconductor chip; as well as The first through-electrode is directly coupled to the second through-electrode.

14. The method according to claim 13, wherein: The combining of the first through-electrode and the second through-electrode includes a plasma annealing process.

15. The method according to claim 13, wherein: When the first through-electrode is bonded to the second through-electrode, a shape of the second gap is deformed.

16. The method according to claim 13, wherein: Each of the step of forming the first semiconductor chip and the step of forming the second semiconductor chip includes the following steps: forming a first insulating structure on the first surface of a substrate having a first surface and a second surface opposite to the first surface; forming a conductive pad on the first insulating structure; forming a second insulating structure on the first insulating structure to cover the conductive pad; forming a via hole penetrating the second insulating structure, the conductive pad, and the first insulating structure to expose the substrate; forming a buffer hole extending from the via hole to the interior of the substrate; forming a sidewall insulating layer from the surface of the buffer hole to the sidewall of the first insulating structure; forming a barrier layer connected to the conductive pad on the sidewall insulating layer; forming a metal layer on the barrier layer to fill the buffer hole and the via hole; planarizing the barrier layer and the metal layer to expose the second insulating structure; removing a portion of the substrate from the second surface of the substrate to reduce the thickness of the substrate and expose ends of the sidewall insulating layer; and The end portions of the sidewall insulating layer and a portion of the barrier layer are removed to expose the metal layer.

17. The method according to claim 16, wherein: The metal layer has a protrusion that protrudes farther than the substrate having a reduced thickness.

18. The method according to claim 16, wherein: Each of the first void and the second void is buried in the buffer hole.

19. The method according to claim 16, wherein: Each of the first through-electrode and the second through-electrode includes a buffer portion filling the buffer hole and a vertical portion filling the via hole and contacting the conductive pad, The coupling of the first through-electrode and the second through-electrode is performed by coupling the vertical portion of the first through-electrode to the buffer portion of the second through-electrode.

20. A method for manufacturing a stacked semiconductor device, the method comprising the steps of: forming a first semiconductor chip penetrated by a first through-electrode in which a first gap is buried; forming a second semiconductor chip penetrated by a second through-electrode in which a second gap is buried; aligning the first semiconductor chip on the second semiconductor chip; as well as coupling the first through-electrode to the second through-electrode, The first through-electrode includes a first buffer portion and a first vertical portion, the first buffer portion penetrates the first substrate of the first semiconductor chip and surrounds the first gap, and the first vertical portion extends from the first buffer portion and is connected to the first conductive pad of the first semiconductor chip. The second through-electrode includes a second buffer portion and a second vertical portion, the second buffer portion penetrates the second substrate of the second semiconductor chip and surrounds the second gap, and the second vertical portion extends from the second buffer portion and is connected to the second conductive pad of the second semiconductor chip.

21. The method according to claim 20, wherein: The first buffer portion is formed to protrude further than the first substrate, and The second buffer portion is formed to protrude further than the second substrate.

22. The method according to claim 21, wherein: When the first through electrode is coupled to the second through electrode, the protrusion of the second buffer portion is recessed toward the inside of the second gap.

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